target/mips/tcg/exception.c

   1 /*
   2  *  MIPS Exceptions processing helpers for QEMU.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "internal.h"
  24 #include "exec/helper-proto.h"
  25 #include "exec/exec-all.h"
  26
  27 target_ulong exception_resume_pc(CPUMIPSState *env)
  28 {
  29     target_ulong bad_pc;
  30     target_ulong isa_mode;
  31
  32     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
  33     bad_pc = env->active_tc.PC | isa_mode;
  34     if (env->hflags & MIPS_HFLAG_BMASK) {
  35         /*
  36          * If the exception was raised from a delay slot, come back to
  37          * the jump.
  38          */
  39         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
  40     }
  41
  42     return bad_pc;
  43 }
  44
  45 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  46                                 int error_code)
  47 {
  48     do_raise_exception_err(env, exception, error_code, 0);
  49 }
  50
  51 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  52 {
  53     do_raise_exception(env, exception, GETPC());
  54 }
  55
  56 void helper_raise_exception_debug(CPUMIPSState *env)
  57 {
  58     do_raise_exception(env, EXCP_DEBUG, 0);
  59 }
  60
  61 static void raise_exception(CPUMIPSState *env, uint32_t exception)
  62 {
  63     do_raise_exception(env, exception, 0);
  64 }
  65
  66 void helper_wait(CPUMIPSState *env)
  67 {
  68     CPUState *cs = env_cpu(env);
  69
  70     cs->halted = 1;
  71     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
  72     /*
  73      * Last instruction in the block, PC was updated before
  74      * - no need to recover PC and icount.
  75      */
  76     raise_exception(env, EXCP_HLT);
  77 }
  78
  79 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
  80 {
  81     MIPSCPU *cpu = MIPS_CPU(cs);
  82     CPUMIPSState *env = &cpu->env;
  83
  84     env->active_tc.PC = tb->pc;
  85     env->hflags &= ~MIPS_HFLAG_BMASK;
  86     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  87 }
  88
  89 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  90 {
  91     if (interrupt_request & CPU_INTERRUPT_HARD) {
  92         MIPSCPU *cpu = MIPS_CPU(cs);
  93         CPUMIPSState *env = &cpu->env;
  94
  95         if (cpu_mips_hw_interrupts_enabled(env) &&
  96             cpu_mips_hw_interrupts_pending(env)) {
  97             /* Raise it */
  98             cs->exception_index = EXCP_EXT_INTERRUPT;
  99             env->error_code = 0;
 100             mips_cpu_do_interrupt(cs);
 101             return true;
 102         }
 103     }
 104     return false;
 105 }
 106
 107 static const char * const excp_names[EXCP_LAST + 1] = {
 108     [EXCP_RESET] = "reset",
 109     [EXCP_SRESET] = "soft reset",
 110     [EXCP_DSS] = "debug single step",
 111     [EXCP_DINT] = "debug interrupt",
 112     [EXCP_NMI] = "non-maskable interrupt",
 113     [EXCP_MCHECK] = "machine check",
 114     [EXCP_EXT_INTERRUPT] = "interrupt",
 115     [EXCP_DFWATCH] = "deferred watchpoint",
 116     [EXCP_DIB] = "debug instruction breakpoint",
 117     [EXCP_IWATCH] = "instruction fetch watchpoint",
 118     [EXCP_AdEL] = "address error load",
 119     [EXCP_AdES] = "address error store",
 120     [EXCP_TLBF] = "TLB refill",
 121     [EXCP_IBE] = "instruction bus error",
 122     [EXCP_DBp] = "debug breakpoint",
 123     [EXCP_SYSCALL] = "syscall",
 124     [EXCP_BREAK] = "break",
 125     [EXCP_CpU] = "coprocessor unusable",
 126     [EXCP_RI] = "reserved instruction",
 127     [EXCP_OVERFLOW] = "arithmetic overflow",
 128     [EXCP_TRAP] = "trap",
 129     [EXCP_FPE] = "floating point",
 130     [EXCP_DDBS] = "debug data break store",
 131     [EXCP_DWATCH] = "data watchpoint",
 132     [EXCP_LTLBL] = "TLB modify",
 133     [EXCP_TLBL] = "TLB load",
 134     [EXCP_TLBS] = "TLB store",
 135     [EXCP_DBE] = "data bus error",
 136     [EXCP_DDBL] = "debug data break load",
 137     [EXCP_THREAD] = "thread",
 138     [EXCP_MDMX] = "MDMX",
 139     [EXCP_C2E] = "precise coprocessor 2",
 140     [EXCP_CACHE] = "cache error",
 141     [EXCP_TLBXI] = "TLB execute-inhibit",
 142     [EXCP_TLBRI] = "TLB read-inhibit",
 143     [EXCP_MSADIS] = "MSA disabled",
 144     [EXCP_MSAFPE] = "MSA floating point",
 145 };
 146
 147 const char *mips_exception_name(int32_t exception)
 148 {
 149     if (exception < 0 || exception > EXCP_LAST) {
 150         return "unknown";
 151     }
 152     return excp_names[exception];
 153 }
 154
 155 void do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
 156                             int error_code, uintptr_t pc)
 157 {
 158     CPUState *cs = env_cpu(env);
 159
 160     qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
 161                   __func__, exception, mips_exception_name(exception),
 162                   error_code);
 163     cs->exception_index = exception;
 164     env->error_code = error_code;
 165
 166     cpu_loop_exit_restore(cs, pc);
 167 }