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target/mips: Add simple user-mode mips_cpu_tlb_fill()
[qemu/ar7.git] / target / mips / tlb_helper.c
blobafc019c80dd1a4053d543b6aa60d5897f975ce33
1 /*
2 * MIPS TLB (Translation lookaside buffer) helpers.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27
28 enum {
29 TLBRET_XI = -6,
30 TLBRET_RI = -5,
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39
40 /* no MMU emulation */
41 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
42 target_ulong address, MMUAccessType access_type)
43 {
44 *physical = address;
45 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
46 return TLBRET_MATCH;
47 }
48
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
51 target_ulong address, MMUAccessType access_type)
52 {
53 if (address <= (int32_t)0x7FFFFFFFUL) {
54 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
55 *physical = address + 0x40000000UL;
56 } else {
57 *physical = address;
58 }
59 } else if (address <= (int32_t)0xBFFFFFFFUL) {
60 *physical = address & 0x1FFFFFFF;
61 } else {
62 *physical = address;
63 }
64
65 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
66 return TLBRET_MATCH;
67 }
68
69 /* MIPS32/MIPS64 R4000-style MMU emulation */
70 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
71 target_ulong address, MMUAccessType access_type)
72 {
73 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
74 uint32_t MMID = env->CP0_MemoryMapID;
75 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
76 uint32_t tlb_mmid;
77 int i;
78
79 MMID = mi ? MMID : (uint32_t) ASID;
80
81 for (i = 0; i < env->tlb->tlb_in_use; i++) {
82 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
83 /* 1k pages are not supported. */
84 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
85 target_ulong tag = address & ~mask;
86 target_ulong VPN = tlb->VPN & ~mask;
87 #if defined(TARGET_MIPS64)
88 tag &= env->SEGMask;
89 #endif
90
91 /* Check ASID/MMID, virtual page number & size */
92 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
93 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) {
94 /* TLB match */
95 int n = !!(address & mask & ~(mask >> 1));
96 /* Check access rights */
97 if (!(n ? tlb->V1 : tlb->V0)) {
98 return TLBRET_INVALID;
99 }
100 if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
101 return TLBRET_XI;
102 }
103 if (access_type == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
104 return TLBRET_RI;
105 }
106 if (access_type != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
107 *physical = tlb->PFN[n] | (address & (mask >> 1));
108 *prot = PAGE_READ;
109 if (n ? tlb->D1 : tlb->D0) {
110 *prot |= PAGE_WRITE;
111 }
112 if (!(n ? tlb->XI1 : tlb->XI0)) {
113 *prot |= PAGE_EXEC;
114 }
115 return TLBRET_MATCH;
116 }
117 return TLBRET_DIRTY;
118 }
119 }
120 return TLBRET_NOMATCH;
121 }
122
123 static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
124 {
125 env->tlb->nb_tlb = 1;
126 env->tlb->map_address = &no_mmu_map_address;
127 }
128
129 static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
130 {
131 env->tlb->nb_tlb = 1;
132 env->tlb->map_address = &fixed_mmu_map_address;
133 }
134
135 static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
136 {
137 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
138 env->tlb->map_address = &r4k_map_address;
139 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
140 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
141 env->tlb->helper_tlbp = r4k_helper_tlbp;
142 env->tlb->helper_tlbr = r4k_helper_tlbr;
143 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
144 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
145 }
146
147 void mmu_init(CPUMIPSState *env, const mips_def_t *def)
148 {
149 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
150
151 switch (def->mmu_type) {
152 case MMU_TYPE_NONE:
153 no_mmu_init(env, def);
154 break;
155 case MMU_TYPE_R4000:
156 r4k_mmu_init(env, def);
157 break;
158 case MMU_TYPE_FMT:
159 fixed_mmu_init(env, def);
160 break;
161 case MMU_TYPE_R3000:
162 case MMU_TYPE_R6000:
163 case MMU_TYPE_R8000:
164 default:
165 cpu_abort(env_cpu(env), "MMU type not supported\n");
166 }
167 }
168
169 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
170 {
171 /*
172 * Interpret access control mode and mmu_idx.
173 * AdE? TLB?
174 * AM K S U E K S U E
175 * UK 0 0 1 1 0 0 - - 0
176 * MK 1 0 1 1 0 1 - - !eu
177 * MSK 2 0 0 1 0 1 1 - !eu
178 * MUSK 3 0 0 0 0 1 1 1 !eu
179 * MUSUK 4 0 0 0 0 0 1 1 0
180 * USK 5 0 0 1 0 0 0 - 0
181 * - 6 - - - - - - - -
182 * UUSK 7 0 0 0 0 0 0 0 0
183 */
184 int32_t adetlb_mask;
185
186 switch (mmu_idx) {
187 case 3: /* ERL */
188 /* If EU is set, always unmapped */
189 if (eu) {
190 return 0;
191 }
192 /* fall through */
193 case MIPS_HFLAG_KM:
194 /* Never AdE, TLB mapped if AM={1,2,3} */
195 adetlb_mask = 0x70000000;
196 goto check_tlb;
197
198 case MIPS_HFLAG_SM:
199 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
200 adetlb_mask = 0xc0380000;
201 goto check_ade;
202
203 case MIPS_HFLAG_UM:
204 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
205 adetlb_mask = 0xe4180000;
206 /* fall through */
207 check_ade:
208 /* does this AM cause AdE in current execution mode */
209 if ((adetlb_mask << am) < 0) {
210 return TLBRET_BADADDR;
211 }
212 adetlb_mask <<= 8;
213 /* fall through */
214 check_tlb:
215 /* is this AM mapped in current execution mode */
216 return ((adetlb_mask << am) < 0);
217 default:
218 assert(0);
219 return TLBRET_BADADDR;
220 };
221 }
222
223 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
224 int *prot, target_ulong real_address,
225 MMUAccessType access_type, int mmu_idx,
226 unsigned int am, bool eu,
227 target_ulong segmask,
228 hwaddr physical_base)
229 {
230 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
231
232 if (mapped < 0) {
233 /* is_seg_am_mapped can report TLBRET_BADADDR */
234 return mapped;
235 } else if (mapped) {
236 /* The segment is TLB mapped */
237 return env->tlb->map_address(env, physical, prot, real_address,
238 access_type);
239 } else {
240 /* The segment is unmapped */
241 *physical = physical_base | (real_address & segmask);
242 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
243 return TLBRET_MATCH;
244 }
245 }
246
247 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
248 int *prot, target_ulong real_address,
249 MMUAccessType access_type, int mmu_idx,
250 uint16_t segctl, target_ulong segmask)
251 {
252 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
253 bool eu = (segctl >> CP0SC_EU) & 1;
254 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
255
256 return get_seg_physical_address(env, physical, prot, real_address,
257 access_type, mmu_idx, am, eu, segmask,
258 pa & ~(hwaddr)segmask);
259 }
260
261 static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
262 int *prot, target_ulong real_address,
263 MMUAccessType access_type, int mmu_idx)
264 {
265 /* User mode can only access useg/xuseg */
266 #if defined(TARGET_MIPS64)
267 int user_mode = mmu_idx == MIPS_HFLAG_UM;
268 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
269 int kernel_mode = !user_mode && !supervisor_mode;
270 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
271 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
272 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
273 #endif
274 int ret = TLBRET_MATCH;
275 /* effective address (modified for KVM T&E kernel segments) */
276 target_ulong address = real_address;
277
278 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
279 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
280 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
281 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
282 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
283
284 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
285 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
286
287 if (mips_um_ksegs_enabled()) {
288 /* KVM T&E adds guest kernel segments in useg */
289 if (real_address >= KVM_KSEG0_BASE) {
290 if (real_address < KVM_KSEG2_BASE) {
291 /* kseg0 */
292 address += KSEG0_BASE - KVM_KSEG0_BASE;
293 } else if (real_address <= USEG_LIMIT) {
294 /* kseg2/3 */
295 address += KSEG2_BASE - KVM_KSEG2_BASE;
296 }
297 }
298 }
299
300 if (address <= USEG_LIMIT) {
301 /* useg */
302 uint16_t segctl;
303
304 if (address >= 0x40000000UL) {
305 segctl = env->CP0_SegCtl2;
306 } else {
307 segctl = env->CP0_SegCtl2 >> 16;
308 }
309 ret = get_segctl_physical_address(env, physical, prot,
310 real_address, access_type,
311 mmu_idx, segctl, 0x3FFFFFFF);
312 #if defined(TARGET_MIPS64)
313 } else if (address < 0x4000000000000000ULL) {
314 /* xuseg */
315 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
316 ret = env->tlb->map_address(env, physical, prot,
317 real_address, access_type);
318 } else {
319 ret = TLBRET_BADADDR;
320 }
321 } else if (address < 0x8000000000000000ULL) {
322 /* xsseg */
323 if ((supervisor_mode || kernel_mode) &&
324 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
325 ret = env->tlb->map_address(env, physical, prot,
326 real_address, access_type);
327 } else {
328 ret = TLBRET_BADADDR;
329 }
330 } else if (address < 0xC000000000000000ULL) {
331 /* xkphys */
332 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
333 /* KX/SX/UX bit to check for each xkphys EVA access mode */
334 static const uint8_t am_ksux[8] = {
335 [CP0SC_AM_UK] = (1u << CP0St_KX),
336 [CP0SC_AM_MK] = (1u << CP0St_KX),
337 [CP0SC_AM_MSK] = (1u << CP0St_SX),
338 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
339 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
340 [CP0SC_AM_USK] = (1u << CP0St_SX),
341 [6] = (1u << CP0St_KX),
342 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
343 };
344 unsigned int am = CP0SC_AM_UK;
345 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
346
347 if (xr & (1 << ((address >> 59) & 0x7))) {
348 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
349 }
350 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
351 if (env->CP0_Status & am_ksux[am]) {
352 ret = get_seg_physical_address(env, physical, prot,
353 real_address, access_type,
354 mmu_idx, am, false, env->PAMask,
355 0);
356 } else {
357 ret = TLBRET_BADADDR;
358 }
359 } else {
360 ret = TLBRET_BADADDR;
361 }
362 } else if (address < 0xFFFFFFFF80000000ULL) {
363 /* xkseg */
364 if (kernel_mode && KX &&
365 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
366 ret = env->tlb->map_address(env, physical, prot,
367 real_address, access_type);
368 } else {
369 ret = TLBRET_BADADDR;
370 }
371 #endif
372 } else if (address < KSEG1_BASE) {
373 /* kseg0 */
374 ret = get_segctl_physical_address(env, physical, prot, real_address,
375 access_type, mmu_idx,
376 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
377 } else if (address < KSEG2_BASE) {
378 /* kseg1 */
379 ret = get_segctl_physical_address(env, physical, prot, real_address,
380 access_type, mmu_idx,
381 env->CP0_SegCtl1, 0x1FFFFFFF);
382 } else if (address < KSEG3_BASE) {
383 /* sseg (kseg2) */
384 ret = get_segctl_physical_address(env, physical, prot, real_address,
385 access_type, mmu_idx,
386 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
387 } else {
388 /*
389 * kseg3
390 * XXX: debug segment is not emulated
391 */
392 ret = get_segctl_physical_address(env, physical, prot, real_address,
393 access_type, mmu_idx,
394 env->CP0_SegCtl0, 0x1FFFFFFF);
395 }
396 return ret;
397 }
398
399 void cpu_mips_tlb_flush(CPUMIPSState *env)
400 {
401 /* Flush qemu's TLB and discard all shadowed entries. */
402 tlb_flush(env_cpu(env));
403 env->tlb->tlb_in_use = env->tlb->nb_tlb;
404 }
405
406 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
407 MMUAccessType access_type, int tlb_error)
408 {
409 CPUState *cs = env_cpu(env);
410 int exception = 0, error_code = 0;
411
412 if (access_type == MMU_INST_FETCH) {
413 error_code |= EXCP_INST_NOTAVAIL;
414 }
415
416 switch (tlb_error) {
417 default:
418 case TLBRET_BADADDR:
419 /* Reference to kernel address from user mode or supervisor mode */
420 /* Reference to supervisor address from user mode */
421 if (access_type == MMU_DATA_STORE) {
422 exception = EXCP_AdES;
423 } else {
424 exception = EXCP_AdEL;
425 }
426 break;
427 case TLBRET_NOMATCH:
428 /* No TLB match for a mapped address */
429 if (access_type == MMU_DATA_STORE) {
430 exception = EXCP_TLBS;
431 } else {
432 exception = EXCP_TLBL;
433 }
434 error_code |= EXCP_TLB_NOMATCH;
435 break;
436 case TLBRET_INVALID:
437 /* TLB match with no valid bit */
438 if (access_type == MMU_DATA_STORE) {
439 exception = EXCP_TLBS;
440 } else {
441 exception = EXCP_TLBL;
442 }
443 break;
444 case TLBRET_DIRTY:
445 /* TLB match but 'D' bit is cleared */
446 exception = EXCP_LTLBL;
447 break;
448 case TLBRET_XI:
449 /* Execute-Inhibit Exception */
450 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
451 exception = EXCP_TLBXI;
452 } else {
453 exception = EXCP_TLBL;
454 }
455 break;
456 case TLBRET_RI:
457 /* Read-Inhibit Exception */
458 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
459 exception = EXCP_TLBRI;
460 } else {
461 exception = EXCP_TLBL;
462 }
463 break;
464 }
465 /* Raise exception */
466 if (!(env->hflags & MIPS_HFLAG_DM)) {
467 env->CP0_BadVAddr = address;
468 }
469 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
470 ((address >> 9) & 0x007ffff0);
471 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
472 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
473 (address & (TARGET_PAGE_MASK << 1));
474 #if defined(TARGET_MIPS64)
475 env->CP0_EntryHi &= env->SEGMask;
476 env->CP0_XContext =
477 (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
478 (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
479 (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
480 #endif
481 cs->exception_index = exception;
482 env->error_code = error_code;
483 }
484
485 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
486 {
487 MIPSCPU *cpu = MIPS_CPU(cs);
488 CPUMIPSState *env = &cpu->env;
489 hwaddr phys_addr;
490 int prot;
491
492 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
493 cpu_mmu_index(env, false)) != 0) {
494 return -1;
495 }
496 return phys_addr;
497 }
498
499 #if !defined(TARGET_MIPS64)
500
501 /*
502 * Perform hardware page table walk
503 *
504 * Memory accesses are performed using the KERNEL privilege level.
505 * Synchronous exceptions detected on memory accesses cause a silent exit
506 * from page table walking, resulting in a TLB or XTLB Refill exception.
507 *
508 * Implementations are not required to support page table walk memory
509 * accesses from mapped memory regions. When an unsupported access is
510 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
511 * exception.
512 *
513 * Note that if an exception is caused by AddressTranslation or LoadMemory
514 * functions, the exception is not taken, a silent exit is taken,
515 * resulting in a TLB or XTLB Refill exception.
516 */
517
518 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
519 uint64_t *pte)
520 {
521 if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
522 return false;
523 }
524 if (entry_size == 64) {
525 *pte = cpu_ldq_code(env, vaddr);
526 } else {
527 *pte = cpu_ldl_code(env, vaddr);
528 }
529 return true;
530 }
531
532 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
533 int entry_size, int ptei)
534 {
535 uint64_t result = entry;
536 uint64_t rixi;
537 if (ptei > entry_size) {
538 ptei -= 32;
539 }
540 result >>= (ptei - 2);
541 rixi = result & 3;
542 result >>= 2;
543 result |= rixi << CP0EnLo_XI;
544 return result;
545 }
546
547 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
548 int directory_index, bool *huge_page, bool *hgpg_directory_hit,
549 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
550 {
551 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
552 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
553 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
554 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
555 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
556 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
557 int directory_shift = (ptew > 1) ? -1 :
558 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
559 int leaf_shift = (ptew > 1) ? -1 :
560 (ptew == 1) ? native_shift + 1 : native_shift;
561 uint32_t direntry_size = 1 << (directory_shift + 3);
562 uint32_t leafentry_size = 1 << (leaf_shift + 3);
563 uint64_t entry;
564 uint64_t paddr;
565 int prot;
566 uint64_t lsb = 0;
567 uint64_t w = 0;
568
569 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
570 cpu_mmu_index(env, false)) !=
571 TLBRET_MATCH) {
572 /* wrong base address */
573 return 0;
574 }
575 if (!get_pte(env, *vaddr, direntry_size, &entry)) {
576 return 0;
577 }
578
579 if ((entry & (1 << psn)) && hugepg) {
580 *huge_page = true;
581 *hgpg_directory_hit = true;
582 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
583 w = directory_index - 1;
584 if (directory_index & 0x1) {
585 /* Generate adjacent page from same PTE for odd TLB page */
586 lsb = (1 << w) >> 6;
587 *pw_entrylo0 = entry & ~lsb; /* even page */
588 *pw_entrylo1 = entry | lsb; /* odd page */
589 } else if (dph) {
590 int oddpagebit = 1 << leaf_shift;
591 uint64_t vaddr2 = *vaddr ^ oddpagebit;
592 if (*vaddr & oddpagebit) {
593 *pw_entrylo1 = entry;
594 } else {
595 *pw_entrylo0 = entry;
596 }
597 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
598 cpu_mmu_index(env, false)) !=
599 TLBRET_MATCH) {
600 return 0;
601 }
602 if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
603 return 0;
604 }
605 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
606 if (*vaddr & oddpagebit) {
607 *pw_entrylo0 = entry;
608 } else {
609 *pw_entrylo1 = entry;
610 }
611 } else {
612 return 0;
613 }
614 return 1;
615 } else {
616 *vaddr = entry;
617 return 2;
618 }
619 }
620
621 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
622 int mmu_idx)
623 {
624 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
625 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
626 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
627 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
628 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
629
630 /* Initial values */
631 bool huge_page = false;
632 bool hgpg_bdhit = false;
633 bool hgpg_gdhit = false;
634 bool hgpg_udhit = false;
635 bool hgpg_mdhit = false;
636
637 int32_t pw_pagemask = 0;
638 target_ulong pw_entryhi = 0;
639 uint64_t pw_entrylo0 = 0;
640 uint64_t pw_entrylo1 = 0;
641
642 /* Native pointer size */
643 /*For the 32-bit architectures, this bit is fixed to 0.*/
644 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
645
646 /* Indices from PWField */
647 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
648 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
649 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
650 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
651 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
652
653 /* Indices computed from faulting address */
654 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
655 int uindex = (address >> pf_udw) & ((1 << udw) - 1);
656 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
657 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
658
659 /* Other HTW configs */
660 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
661
662 /* HTW Shift values (depend on entry size) */
663 int directory_shift = (ptew > 1) ? -1 :
664 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
665 int leaf_shift = (ptew > 1) ? -1 :
666 (ptew == 1) ? native_shift + 1 : native_shift;
667
668 /* Offsets into tables */
669 int goffset = gindex << directory_shift;
670 int uoffset = uindex << directory_shift;
671 int moffset = mindex << directory_shift;
672 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
673 int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
674
675 uint32_t leafentry_size = 1 << (leaf_shift + 3);
676
677 /* Starting address - Page Table Base */
678 uint64_t vaddr = env->CP0_PWBase;
679
680 uint64_t dir_entry;
681 uint64_t paddr;
682 int prot;
683 int m;
684
685 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
686 /* walker is unimplemented */
687 return false;
688 }
689 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
690 /* walker is disabled */
691 return false;
692 }
693 if (!(gdw > 0 || udw > 0 || mdw > 0)) {
694 /* no structure to walk */
695 return false;
696 }
697 if ((directory_shift == -1) || (leaf_shift == -1)) {
698 return false;
699 }
700
701 /* Global Directory */
702 if (gdw > 0) {
703 vaddr |= goffset;
704 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
705 &pw_entrylo0, &pw_entrylo1))
706 {
707 case 0:
708 return false;
709 case 1:
710 goto refill;
711 case 2:
712 default:
713 break;
714 }
715 }
716
717 /* Upper directory */
718 if (udw > 0) {
719 vaddr |= uoffset;
720 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
721 &pw_entrylo0, &pw_entrylo1))
722 {
723 case 0:
724 return false;
725 case 1:
726 goto refill;
727 case 2:
728 default:
729 break;
730 }
731 }
732
733 /* Middle directory */
734 if (mdw > 0) {
735 vaddr |= moffset;
736 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
737 &pw_entrylo0, &pw_entrylo1))
738 {
739 case 0:
740 return false;
741 case 1:
742 goto refill;
743 case 2:
744 default:
745 break;
746 }
747 }
748
749 /* Leaf Level Page Table - First half of PTE pair */
750 vaddr |= ptoffset0;
751 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
752 cpu_mmu_index(env, false)) !=
753 TLBRET_MATCH) {
754 return false;
755 }
756 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
757 return false;
758 }
759 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
760 pw_entrylo0 = dir_entry;
761
762 /* Leaf Level Page Table - Second half of PTE pair */
763 vaddr |= ptoffset1;
764 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
765 cpu_mmu_index(env, false)) !=
766 TLBRET_MATCH) {
767 return false;
768 }
769 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
770 return false;
771 }
772 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
773 pw_entrylo1 = dir_entry;
774
775 refill:
776
777 m = (1 << pf_ptw) - 1;
778
779 if (huge_page) {
780 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
781 hgpg_mdhit)
782 {
783 case 4:
784 m = (1 << pf_gdw) - 1;
785 if (pf_gdw & 1) {
786 m >>= 1;
787 }
788 break;
789 case 2:
790 m = (1 << pf_udw) - 1;
791 if (pf_udw & 1) {
792 m >>= 1;
793 }
794 break;
795 case 1:
796 m = (1 << pf_mdw) - 1;
797 if (pf_mdw & 1) {
798 m >>= 1;
799 }
800 break;
801 }
802 }
803 pw_pagemask = m >> TARGET_PAGE_BITS_MIN;
804 update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask);
805 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
806 {
807 target_ulong tmp_entryhi = env->CP0_EntryHi;
808 int32_t tmp_pagemask = env->CP0_PageMask;
809 uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
810 uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
811
812 env->CP0_EntryHi = pw_entryhi;
813 env->CP0_PageMask = pw_pagemask;
814 env->CP0_EntryLo0 = pw_entrylo0;
815 env->CP0_EntryLo1 = pw_entrylo1;
816
817 /*
818 * The hardware page walker inserts a page into the TLB in a manner
819 * identical to a TLBWR instruction as executed by the software refill
820 * handler.
821 */
822 r4k_helper_tlbwr(env);
823
824 env->CP0_EntryHi = tmp_entryhi;
825 env->CP0_PageMask = tmp_pagemask;
826 env->CP0_EntryLo0 = tmp_entrylo0;
827 env->CP0_EntryLo1 = tmp_entrylo1;
828 }
829 return true;
830 }
831 #endif
832
833 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
834 MMUAccessType access_type, int mmu_idx,
835 bool probe, uintptr_t retaddr)
836 {
837 MIPSCPU *cpu = MIPS_CPU(cs);
838 CPUMIPSState *env = &cpu->env;
839 hwaddr physical;
840 int prot;
841 int ret = TLBRET_BADADDR;
842
843 /* data access */
844 /* XXX: put correct access by using cpu_restore_state() correctly */
845 ret = get_physical_address(env, &physical, &prot, address,
846 access_type, mmu_idx);
847 switch (ret) {
848 case TLBRET_MATCH:
849 qemu_log_mask(CPU_LOG_MMU,
850 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
851 " prot %d\n", __func__, address, physical, prot);
852 break;
853 default:
854 qemu_log_mask(CPU_LOG_MMU,
855 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
856 ret);
857 break;
858 }
859 if (ret == TLBRET_MATCH) {
860 tlb_set_page(cs, address & TARGET_PAGE_MASK,
861 physical & TARGET_PAGE_MASK, prot,
862 mmu_idx, TARGET_PAGE_SIZE);
863 return true;
864 }
865 #if !defined(TARGET_MIPS64)
866 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
867 /*
868 * Memory reads during hardware page table walking are performed
869 * as if they were kernel-mode load instructions.
870 */
871 int mode = (env->hflags & MIPS_HFLAG_KSU);
872 bool ret_walker;
873 env->hflags &= ~MIPS_HFLAG_KSU;
874 ret_walker = page_table_walk_refill(env, address, mmu_idx);
875 env->hflags |= mode;
876 if (ret_walker) {
877 ret = get_physical_address(env, &physical, &prot, address,
878 access_type, mmu_idx);
879 if (ret == TLBRET_MATCH) {
880 tlb_set_page(cs, address & TARGET_PAGE_MASK,
881 physical & TARGET_PAGE_MASK, prot,
882 mmu_idx, TARGET_PAGE_SIZE);
883 return true;
884 }
885 }
886 }
887 #endif
888 if (probe) {
889 return false;
890 }
891
892 raise_mmu_exception(env, address, access_type, ret);
893 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
894 }
895
896 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
897 MMUAccessType access_type, uintptr_t retaddr)
898 {
899 hwaddr physical;
900 int prot;
901 int ret = 0;
902 CPUState *cs = env_cpu(env);
903
904 /* data access */
905 ret = get_physical_address(env, &physical, &prot, address, access_type,
906 cpu_mmu_index(env, false));
907 if (ret == TLBRET_MATCH) {
908 return physical;
909 }
910
911 raise_mmu_exception(env, address, access_type, ret);
912 cpu_loop_exit_restore(cs, retaddr);
913 }
914
915 static void set_hflags_for_handler(CPUMIPSState *env)
916 {
917 /* Exception handlers are entered in 32-bit mode. */
918 env->hflags &= ~(MIPS_HFLAG_M16);
919 /* ...except that microMIPS lets you choose. */
920 if (env->insn_flags & ASE_MICROMIPS) {
921 env->hflags |= (!!(env->CP0_Config3 &
922 (1 << CP0C3_ISA_ON_EXC))
923 << MIPS_HFLAG_M16_SHIFT);
924 }
925 }
926
927 static inline void set_badinstr_registers(CPUMIPSState *env)
928 {
929 if (env->insn_flags & ISA_NANOMIPS32) {
930 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
931 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
932 if ((instr & 0x10000000) == 0) {
933 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
934 }
935 env->CP0_BadInstr = instr;
936
937 if ((instr & 0xFC000000) == 0x60000000) {
938 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
939 env->CP0_BadInstrX = instr;
940 }
941 }
942 return;
943 }
944
945 if (env->hflags & MIPS_HFLAG_M16) {
946 /* TODO: add BadInstr support for microMIPS */
947 return;
948 }
949 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
950 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
951 }
952 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
953 (env->hflags & MIPS_HFLAG_BMASK)) {
954 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
955 }
956 }
957
958 void mips_cpu_do_interrupt(CPUState *cs)
959 {
960 MIPSCPU *cpu = MIPS_CPU(cs);
961 CPUMIPSState *env = &cpu->env;
962 bool update_badinstr = 0;
963 target_ulong offset;
964 int cause = -1;
965
966 if (qemu_loglevel_mask(CPU_LOG_INT)
967 && cs->exception_index != EXCP_EXT_INTERRUPT) {
968 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
969 " %s exception\n",
970 __func__, env->active_tc.PC, env->CP0_EPC,
971 mips_exception_name(cs->exception_index));
972 }
973 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
974 (env->hflags & MIPS_HFLAG_DM)) {
975 cs->exception_index = EXCP_DINT;
976 }
977 offset = 0x180;
978 switch (cs->exception_index) {
979 case EXCP_DSS:
980 env->CP0_Debug |= 1 << CP0DB_DSS;
981 /*
982 * Debug single step cannot be raised inside a delay slot and
983 * resume will always occur on the next instruction
984 * (but we assume the pc has always been updated during
985 * code translation).
986 */
987 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
988 goto enter_debug_mode;
989 case EXCP_DINT:
990 env->CP0_Debug |= 1 << CP0DB_DINT;
991 goto set_DEPC;
992 case EXCP_DIB:
993 env->CP0_Debug |= 1 << CP0DB_DIB;
994 goto set_DEPC;
995 case EXCP_DBp:
996 env->CP0_Debug |= 1 << CP0DB_DBp;
997 /* Setup DExcCode - SDBBP instruction */
998 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
999 (9 << CP0DB_DEC);
1000 goto set_DEPC;
1001 case EXCP_DDBS:
1002 env->CP0_Debug |= 1 << CP0DB_DDBS;
1003 goto set_DEPC;
1004 case EXCP_DDBL:
1005 env->CP0_Debug |= 1 << CP0DB_DDBL;
1006 set_DEPC:
1007 env->CP0_DEPC = exception_resume_pc(env);
1008 env->hflags &= ~MIPS_HFLAG_BMASK;
1009 enter_debug_mode:
1010 if (env->insn_flags & ISA_MIPS3) {
1011 env->hflags |= MIPS_HFLAG_64;
1012 if (!(env->insn_flags & ISA_MIPS_R6) ||
1013 env->CP0_Status & (1 << CP0St_KX)) {
1014 env->hflags &= ~MIPS_HFLAG_AWRAP;
1015 }
1016 }
1017 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
1018 env->hflags &= ~(MIPS_HFLAG_KSU);
1019 /* EJTAG probe trap enable is not implemented... */
1020 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1021 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1022 }
1023 env->active_tc.PC = env->exception_base + 0x480;
1024 set_hflags_for_handler(env);
1025 break;
1026 case EXCP_RESET:
1027 cpu_reset(CPU(cpu));
1028 break;
1029 case EXCP_SRESET:
1030 env->CP0_Status |= (1 << CP0St_SR);
1031 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
1032 goto set_error_EPC;
1033 case EXCP_NMI:
1034 env->CP0_Status |= (1 << CP0St_NMI);
1035 set_error_EPC:
1036 env->CP0_ErrorEPC = exception_resume_pc(env);
1037 env->hflags &= ~MIPS_HFLAG_BMASK;
1038 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
1039 if (env->insn_flags & ISA_MIPS3) {
1040 env->hflags |= MIPS_HFLAG_64;
1041 if (!(env->insn_flags & ISA_MIPS_R6) ||
1042 env->CP0_Status & (1 << CP0St_KX)) {
1043 env->hflags &= ~MIPS_HFLAG_AWRAP;
1044 }
1045 }
1046 env->hflags |= MIPS_HFLAG_CP0;
1047 env->hflags &= ~(MIPS_HFLAG_KSU);
1048 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1049 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1050 }
1051 env->active_tc.PC = env->exception_base;
1052 set_hflags_for_handler(env);
1053 break;
1054 case EXCP_EXT_INTERRUPT:
1055 cause = 0;
1056 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
1057 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
1058
1059 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
1060 offset = 0x200;
1061 } else {
1062 uint32_t vector = 0;
1063 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
1064
1065 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
1066 /*
1067 * For VEIC mode, the external interrupt controller feeds
1068 * the vector through the CP0Cause IP lines.
1069 */
1070 vector = pending;
1071 } else {
1072 /*
1073 * Vectored Interrupts
1074 * Mask with Status.IM7-IM0 to get enabled interrupts.
1075 */
1076 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
1077 /* Find the highest-priority interrupt. */
1078 while (pending >>= 1) {
1079 vector++;
1080 }
1081 }
1082 offset = 0x200 + (vector * (spacing << 5));
1083 }
1084 }
1085 goto set_EPC;
1086 case EXCP_LTLBL:
1087 cause = 1;
1088 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1089 goto set_EPC;
1090 case EXCP_TLBL:
1091 cause = 2;
1092 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1093 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1094 !(env->CP0_Status & (1 << CP0St_EXL))) {
1095 #if defined(TARGET_MIPS64)
1096 int R = env->CP0_BadVAddr >> 62;
1097 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1098 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1099
1100 if ((R != 0 || UX) && (R != 3 || KX) &&
1101 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1102 offset = 0x080;
1103 } else {
1104 #endif
1105 offset = 0x000;
1106 #if defined(TARGET_MIPS64)
1107 }
1108 #endif
1109 }
1110 goto set_EPC;
1111 case EXCP_TLBS:
1112 cause = 3;
1113 update_badinstr = 1;
1114 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1115 !(env->CP0_Status & (1 << CP0St_EXL))) {
1116 #if defined(TARGET_MIPS64)
1117 int R = env->CP0_BadVAddr >> 62;
1118 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1119 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1120
1121 if ((R != 0 || UX) && (R != 3 || KX) &&
1122 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1123 offset = 0x080;
1124 } else {
1125 #endif
1126 offset = 0x000;
1127 #if defined(TARGET_MIPS64)
1128 }
1129 #endif
1130 }
1131 goto set_EPC;
1132 case EXCP_AdEL:
1133 cause = 4;
1134 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1135 goto set_EPC;
1136 case EXCP_AdES:
1137 cause = 5;
1138 update_badinstr = 1;
1139 goto set_EPC;
1140 case EXCP_IBE:
1141 cause = 6;
1142 goto set_EPC;
1143 case EXCP_DBE:
1144 cause = 7;
1145 goto set_EPC;
1146 case EXCP_SYSCALL:
1147 cause = 8;
1148 update_badinstr = 1;
1149 goto set_EPC;
1150 case EXCP_BREAK:
1151 cause = 9;
1152 update_badinstr = 1;
1153 goto set_EPC;
1154 case EXCP_RI:
1155 cause = 10;
1156 update_badinstr = 1;
1157 goto set_EPC;
1158 case EXCP_CpU:
1159 cause = 11;
1160 update_badinstr = 1;
1161 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
1162 (env->error_code << CP0Ca_CE);
1163 goto set_EPC;
1164 case EXCP_OVERFLOW:
1165 cause = 12;
1166 update_badinstr = 1;
1167 goto set_EPC;
1168 case EXCP_TRAP:
1169 cause = 13;
1170 update_badinstr = 1;
1171 goto set_EPC;
1172 case EXCP_MSAFPE:
1173 cause = 14;
1174 update_badinstr = 1;
1175 goto set_EPC;
1176 case EXCP_FPE:
1177 cause = 15;
1178 update_badinstr = 1;
1179 goto set_EPC;
1180 case EXCP_C2E:
1181 cause = 18;
1182 goto set_EPC;
1183 case EXCP_TLBRI:
1184 cause = 19;
1185 update_badinstr = 1;
1186 goto set_EPC;
1187 case EXCP_TLBXI:
1188 cause = 20;
1189 goto set_EPC;
1190 case EXCP_MSADIS:
1191 cause = 21;
1192 update_badinstr = 1;
1193 goto set_EPC;
1194 case EXCP_MDMX:
1195 cause = 22;
1196 goto set_EPC;
1197 case EXCP_DWATCH:
1198 cause = 23;
1199 /* XXX: TODO: manage deferred watch exceptions */
1200 goto set_EPC;
1201 case EXCP_MCHECK:
1202 cause = 24;
1203 goto set_EPC;
1204 case EXCP_THREAD:
1205 cause = 25;
1206 goto set_EPC;
1207 case EXCP_DSPDIS:
1208 cause = 26;
1209 goto set_EPC;
1210 case EXCP_CACHE:
1211 cause = 30;
1212 offset = 0x100;
1213 set_EPC:
1214 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1215 env->CP0_EPC = exception_resume_pc(env);
1216 if (update_badinstr) {
1217 set_badinstr_registers(env);
1218 }
1219 if (env->hflags & MIPS_HFLAG_BMASK) {
1220 env->CP0_Cause |= (1U << CP0Ca_BD);
1221 } else {
1222 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1223 }
1224 env->CP0_Status |= (1 << CP0St_EXL);
1225 if (env->insn_flags & ISA_MIPS3) {
1226 env->hflags |= MIPS_HFLAG_64;
1227 if (!(env->insn_flags & ISA_MIPS_R6) ||
1228 env->CP0_Status & (1 << CP0St_KX)) {
1229 env->hflags &= ~MIPS_HFLAG_AWRAP;
1230 }
1231 }
1232 env->hflags |= MIPS_HFLAG_CP0;
1233 env->hflags &= ~(MIPS_HFLAG_KSU);
1234 }
1235 env->hflags &= ~MIPS_HFLAG_BMASK;
1236 if (env->CP0_Status & (1 << CP0St_BEV)) {
1237 env->active_tc.PC = env->exception_base + 0x200;
1238 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
1239 env->CP0_Config5 & (1 << CP0C5_CV))) {
1240 /* Force KSeg1 for cache errors */
1241 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
1242 } else {
1243 env->active_tc.PC = env->CP0_EBase & ~0xfff;
1244 }
1245
1246 env->active_tc.PC += offset;
1247 set_hflags_for_handler(env);
1248 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
1249 (cause << CP0Ca_EC);
1250 break;
1251 default:
1252 abort();
1253 }
1254 if (qemu_loglevel_mask(CPU_LOG_INT)
1255 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1256 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1257 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1258 __func__, env->active_tc.PC, env->CP0_EPC, cause,
1259 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
1260 env->CP0_DEPC);
1261 }
1262 cs->exception_index = EXCP_NONE;
1263 }
1264
1265 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
1266 {
1267 CPUState *cs = env_cpu(env);
1268 r4k_tlb_t *tlb;
1269 target_ulong addr;
1270 target_ulong end;
1271 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1272 uint32_t MMID = env->CP0_MemoryMapID;
1273 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
1274 uint32_t tlb_mmid;
1275 target_ulong mask;
1276
1277 MMID = mi ? MMID : (uint32_t) ASID;
1278
1279 tlb = &env->tlb->mmu.r4k.tlb[idx];
1280 /*
1281 * The qemu TLB is flushed when the ASID/MMID changes, so no need to
1282 * flush these entries again.
1283 */
1284 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
1285 if (tlb->G == 0 && tlb_mmid != MMID) {
1286 return;
1287 }
1288
1289 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1290 /*
1291 * For tlbwr, we can shadow the discarded entry into
1292 * a new (fake) TLB entry, as long as the guest can not
1293 * tell that it's there.
1294 */
1295 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1296 env->tlb->tlb_in_use++;
1297 return;
1298 }
1299
1300 /* 1k pages are not supported. */
1301 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1302 if (tlb->V0) {
1303 addr = tlb->VPN & ~mask;
1304 #if defined(TARGET_MIPS64)
1305 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1306 addr |= 0x3FFFFF0000000000ULL;
1307 }
1308 #endif
1309 end = addr | (mask >> 1);
1310 while (addr < end) {
1311 tlb_flush_page(cs, addr);
1312 addr += TARGET_PAGE_SIZE;
1313 }
1314 }
1315 if (tlb->V1) {
1316 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1317 #if defined(TARGET_MIPS64)
1318 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1319 addr |= 0x3FFFFF0000000000ULL;
1320 }
1321 #endif
1322 end = addr | mask;
1323 while (addr - 1 < end) {
1324 tlb_flush_page(cs, addr);
1325 addr += TARGET_PAGE_SIZE;
1326 }
1327 }
1328 }
1329 #endif /* !CONFIG_USER_ONLY */
AR7 emulation for QEMU