target/arm: Restrict v7A TCG cpus to TCG accel
[qemu/ar7.git] / tcg / riscv / tcg-target-con-str.h
blob8d8afaee53c921aed19b79997d6af22ddcb20c3d
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define RISC-V target-specific operand constraints.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * Define constraint letters for register sets:
9 * REGS(letter, register_mask)
11 REGS('r', ALL_GENERAL_REGS)
12 REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
15 * Define constraint letters for constants:
16 * CONST(letter, TCG_CT_CONST_* bit set)
18 CONST('I', TCG_CT_CONST_S12)
19 CONST('N', TCG_CT_CONST_N12)
20 CONST('M', TCG_CT_CONST_M12)
21 CONST('Z', TCG_CT_CONST_ZERO)