target/arm: Restrict v7A TCG cpus to TCG accel
[qemu/ar7.git] / tcg / mips / tcg-target-con-set.h
blobfe3e868a2f0df8f4b896b8cf3c72165fbe1d2a5a
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define MIPS target-specific constraint sets.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
9 * Each operand should be a sequence of constraint letters as defined by
10 * tcg-target-con-str.h; the constraint combination is inclusive or.
12 C_O0_I1(r)
13 C_O0_I2(rZ, r)
14 C_O0_I2(rZ, rZ)
15 C_O0_I2(SZ, S)
16 C_O0_I3(SZ, S, S)
17 C_O0_I3(SZ, SZ, S)
18 C_O0_I4(rZ, rZ, rZ, rZ)
19 C_O0_I4(SZ, SZ, S, S)
20 C_O1_I1(r, L)
21 C_O1_I1(r, r)
22 C_O1_I2(r, 0, rZ)
23 C_O1_I2(r, L, L)
24 C_O1_I2(r, r, ri)
25 C_O1_I2(r, r, rI)
26 C_O1_I2(r, r, rIK)
27 C_O1_I2(r, r, rJ)
28 C_O1_I2(r, r, rWZ)
29 C_O1_I2(r, rZ, rN)
30 C_O1_I2(r, rZ, rZ)
31 C_O1_I4(r, rZ, rZ, rZ, 0)
32 C_O1_I4(r, rZ, rZ, rZ, rZ)
33 C_O2_I1(r, r, L)
34 C_O2_I2(r, r, L, L)
35 C_O2_I2(r, r, r, r)
36 C_O2_I4(r, r, rZ, rZ, rN, rN)