4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "disas/disas.h"
26 #include "qemu-common.h"
28 #include "qemu/bitops.h"
29 #include "exec/cpu_ldst.h"
30 #include "exec/translator.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 #include "exec/gen-icount.h"
36 #include "trace-tcg.h"
39 /* is_jmp field values */
40 #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */
41 #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */
43 typedef struct DisasContext
{
44 DisasContextBase base
;
47 uint32_t delayed_branch
;
49 /* If not -1, jmp_pc contains this value and so is a direct jump. */
50 target_ulong jmp_pc_imm
;
53 /* Include the auto-generated decoder. */
54 #include "decode.inc.c"
57 static TCGv cpu_R
[32];
60 static TCGv jmp_pc
; /* l.jr/l.jalr temp pc */
62 static TCGv cpu_sr_f
; /* bf/bnf, F flag taken */
63 static TCGv cpu_sr_cy
; /* carry (unsigned overflow) */
64 static TCGv cpu_sr_ov
; /* signed overflow */
65 static TCGv cpu_lock_addr
;
66 static TCGv cpu_lock_value
;
67 static TCGv_i32 fpcsr
;
68 static TCGv_i64 cpu_mac
; /* MACHI:MACLO */
69 static TCGv_i32 cpu_dflag
;
71 void openrisc_translate_init(void)
73 static const char * const regnames
[] = {
74 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
75 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
76 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
77 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
81 cpu_sr
= tcg_global_mem_new(cpu_env
,
82 offsetof(CPUOpenRISCState
, sr
), "sr");
83 cpu_dflag
= tcg_global_mem_new_i32(cpu_env
,
84 offsetof(CPUOpenRISCState
, dflag
),
86 cpu_pc
= tcg_global_mem_new(cpu_env
,
87 offsetof(CPUOpenRISCState
, pc
), "pc");
88 cpu_ppc
= tcg_global_mem_new(cpu_env
,
89 offsetof(CPUOpenRISCState
, ppc
), "ppc");
90 jmp_pc
= tcg_global_mem_new(cpu_env
,
91 offsetof(CPUOpenRISCState
, jmp_pc
), "jmp_pc");
92 cpu_sr_f
= tcg_global_mem_new(cpu_env
,
93 offsetof(CPUOpenRISCState
, sr_f
), "sr_f");
94 cpu_sr_cy
= tcg_global_mem_new(cpu_env
,
95 offsetof(CPUOpenRISCState
, sr_cy
), "sr_cy");
96 cpu_sr_ov
= tcg_global_mem_new(cpu_env
,
97 offsetof(CPUOpenRISCState
, sr_ov
), "sr_ov");
98 cpu_lock_addr
= tcg_global_mem_new(cpu_env
,
99 offsetof(CPUOpenRISCState
, lock_addr
),
101 cpu_lock_value
= tcg_global_mem_new(cpu_env
,
102 offsetof(CPUOpenRISCState
, lock_value
),
104 fpcsr
= tcg_global_mem_new_i32(cpu_env
,
105 offsetof(CPUOpenRISCState
, fpcsr
),
107 cpu_mac
= tcg_global_mem_new_i64(cpu_env
,
108 offsetof(CPUOpenRISCState
, mac
),
110 for (i
= 0; i
< 32; i
++) {
111 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUOpenRISCState
,
119 static void gen_exception(DisasContext
*dc
, unsigned int excp
)
121 TCGv_i32 tmp
= tcg_const_i32(excp
);
122 gen_helper_exception(cpu_env
, tmp
);
123 tcg_temp_free_i32(tmp
);
126 static void gen_illegal_exception(DisasContext
*dc
)
128 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
129 gen_exception(dc
, EXCP_ILLEGAL
);
130 dc
->base
.is_jmp
= DISAS_NORETURN
;
133 /* not used yet, open it when we need or64. */
134 /*#ifdef TARGET_OPENRISC64
135 static void check_ob64s(DisasContext *dc)
137 if (!(dc->flags & CPUCFGR_OB64S)) {
138 gen_illegal_exception(dc);
142 static void check_of64s(DisasContext *dc)
144 if (!(dc->flags & CPUCFGR_OF64S)) {
145 gen_illegal_exception(dc);
149 static void check_ov64s(DisasContext *dc)
151 if (!(dc->flags & CPUCFGR_OV64S)) {
152 gen_illegal_exception(dc);
157 /* We're about to write to REG. On the off-chance that the user is
158 writing to R0, re-instate the architectural register. */
159 #define check_r0_write(reg) \
161 if (unlikely(reg == 0)) { \
166 static void gen_ove_cy(DisasContext
*dc
)
168 if (dc
->tb_flags
& SR_OVE
) {
169 gen_helper_ove_cy(cpu_env
);
173 static void gen_ove_ov(DisasContext
*dc
)
175 if (dc
->tb_flags
& SR_OVE
) {
176 gen_helper_ove_ov(cpu_env
);
180 static void gen_ove_cyov(DisasContext
*dc
)
182 if (dc
->tb_flags
& SR_OVE
) {
183 gen_helper_ove_cyov(cpu_env
);
187 static void gen_add(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
189 TCGv t0
= tcg_const_tl(0);
190 TCGv res
= tcg_temp_new();
192 tcg_gen_add2_tl(res
, cpu_sr_cy
, srca
, t0
, srcb
, t0
);
193 tcg_gen_xor_tl(cpu_sr_ov
, srca
, srcb
);
194 tcg_gen_xor_tl(t0
, res
, srcb
);
195 tcg_gen_andc_tl(cpu_sr_ov
, t0
, cpu_sr_ov
);
198 tcg_gen_mov_tl(dest
, res
);
204 static void gen_addc(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
206 TCGv t0
= tcg_const_tl(0);
207 TCGv res
= tcg_temp_new();
209 tcg_gen_add2_tl(res
, cpu_sr_cy
, srca
, t0
, cpu_sr_cy
, t0
);
210 tcg_gen_add2_tl(res
, cpu_sr_cy
, res
, cpu_sr_cy
, srcb
, t0
);
211 tcg_gen_xor_tl(cpu_sr_ov
, srca
, srcb
);
212 tcg_gen_xor_tl(t0
, res
, srcb
);
213 tcg_gen_andc_tl(cpu_sr_ov
, t0
, cpu_sr_ov
);
216 tcg_gen_mov_tl(dest
, res
);
222 static void gen_sub(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
224 TCGv res
= tcg_temp_new();
226 tcg_gen_sub_tl(res
, srca
, srcb
);
227 tcg_gen_xor_tl(cpu_sr_cy
, srca
, srcb
);
228 tcg_gen_xor_tl(cpu_sr_ov
, res
, srcb
);
229 tcg_gen_and_tl(cpu_sr_ov
, cpu_sr_ov
, cpu_sr_cy
);
230 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_sr_cy
, srca
, srcb
);
232 tcg_gen_mov_tl(dest
, res
);
238 static void gen_mul(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
240 TCGv t0
= tcg_temp_new();
242 tcg_gen_muls2_tl(dest
, cpu_sr_ov
, srca
, srcb
);
243 tcg_gen_sari_tl(t0
, dest
, TARGET_LONG_BITS
- 1);
244 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_sr_ov
, cpu_sr_ov
, t0
);
247 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
251 static void gen_mulu(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
253 tcg_gen_muls2_tl(dest
, cpu_sr_cy
, srca
, srcb
);
254 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_sr_cy
, cpu_sr_cy
, 0);
259 static void gen_div(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
261 TCGv t0
= tcg_temp_new();
263 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_ov
, srcb
, 0);
264 /* The result of divide-by-zero is undefined.
265 Supress the host-side exception by dividing by 1. */
266 tcg_gen_or_tl(t0
, srcb
, cpu_sr_ov
);
267 tcg_gen_div_tl(dest
, srca
, t0
);
270 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
274 static void gen_divu(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
276 TCGv t0
= tcg_temp_new();
278 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_cy
, srcb
, 0);
279 /* The result of divide-by-zero is undefined.
280 Supress the host-side exception by dividing by 1. */
281 tcg_gen_or_tl(t0
, srcb
, cpu_sr_cy
);
282 tcg_gen_divu_tl(dest
, srca
, t0
);
288 static void gen_muld(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
290 TCGv_i64 t1
= tcg_temp_new_i64();
291 TCGv_i64 t2
= tcg_temp_new_i64();
293 tcg_gen_ext_tl_i64(t1
, srca
);
294 tcg_gen_ext_tl_i64(t2
, srcb
);
295 if (TARGET_LONG_BITS
== 32) {
296 tcg_gen_mul_i64(cpu_mac
, t1
, t2
);
297 tcg_gen_movi_tl(cpu_sr_ov
, 0);
299 TCGv_i64 high
= tcg_temp_new_i64();
301 tcg_gen_muls2_i64(cpu_mac
, high
, t1
, t2
);
302 tcg_gen_sari_i64(t1
, cpu_mac
, 63);
303 tcg_gen_setcond_i64(TCG_COND_NE
, t1
, t1
, high
);
304 tcg_temp_free_i64(high
);
305 tcg_gen_trunc_i64_tl(cpu_sr_ov
, t1
);
306 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
310 tcg_temp_free_i64(t1
);
311 tcg_temp_free_i64(t2
);
314 static void gen_muldu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
316 TCGv_i64 t1
= tcg_temp_new_i64();
317 TCGv_i64 t2
= tcg_temp_new_i64();
319 tcg_gen_extu_tl_i64(t1
, srca
);
320 tcg_gen_extu_tl_i64(t2
, srcb
);
321 if (TARGET_LONG_BITS
== 32) {
322 tcg_gen_mul_i64(cpu_mac
, t1
, t2
);
323 tcg_gen_movi_tl(cpu_sr_cy
, 0);
325 TCGv_i64 high
= tcg_temp_new_i64();
327 tcg_gen_mulu2_i64(cpu_mac
, high
, t1
, t2
);
328 tcg_gen_setcondi_i64(TCG_COND_NE
, high
, high
, 0);
329 tcg_gen_trunc_i64_tl(cpu_sr_cy
, high
);
330 tcg_temp_free_i64(high
);
334 tcg_temp_free_i64(t1
);
335 tcg_temp_free_i64(t2
);
338 static void gen_mac(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
340 TCGv_i64 t1
= tcg_temp_new_i64();
341 TCGv_i64 t2
= tcg_temp_new_i64();
343 tcg_gen_ext_tl_i64(t1
, srca
);
344 tcg_gen_ext_tl_i64(t2
, srcb
);
345 tcg_gen_mul_i64(t1
, t1
, t2
);
347 /* Note that overflow is only computed during addition stage. */
348 tcg_gen_xor_i64(t2
, cpu_mac
, t1
);
349 tcg_gen_add_i64(cpu_mac
, cpu_mac
, t1
);
350 tcg_gen_xor_i64(t1
, t1
, cpu_mac
);
351 tcg_gen_andc_i64(t1
, t1
, t2
);
352 tcg_temp_free_i64(t2
);
354 #if TARGET_LONG_BITS == 32
355 tcg_gen_extrh_i64_i32(cpu_sr_ov
, t1
);
357 tcg_gen_mov_i64(cpu_sr_ov
, t1
);
359 tcg_temp_free_i64(t1
);
364 static void gen_macu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
366 TCGv_i64 t1
= tcg_temp_new_i64();
367 TCGv_i64 t2
= tcg_temp_new_i64();
369 tcg_gen_extu_tl_i64(t1
, srca
);
370 tcg_gen_extu_tl_i64(t2
, srcb
);
371 tcg_gen_mul_i64(t1
, t1
, t2
);
372 tcg_temp_free_i64(t2
);
374 /* Note that overflow is only computed during addition stage. */
375 tcg_gen_add_i64(cpu_mac
, cpu_mac
, t1
);
376 tcg_gen_setcond_i64(TCG_COND_LTU
, t1
, cpu_mac
, t1
);
377 tcg_gen_trunc_i64_tl(cpu_sr_cy
, t1
);
378 tcg_temp_free_i64(t1
);
383 static void gen_msb(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
385 TCGv_i64 t1
= tcg_temp_new_i64();
386 TCGv_i64 t2
= tcg_temp_new_i64();
388 tcg_gen_ext_tl_i64(t1
, srca
);
389 tcg_gen_ext_tl_i64(t2
, srcb
);
390 tcg_gen_mul_i64(t1
, t1
, t2
);
392 /* Note that overflow is only computed during subtraction stage. */
393 tcg_gen_xor_i64(t2
, cpu_mac
, t1
);
394 tcg_gen_sub_i64(cpu_mac
, cpu_mac
, t1
);
395 tcg_gen_xor_i64(t1
, t1
, cpu_mac
);
396 tcg_gen_and_i64(t1
, t1
, t2
);
397 tcg_temp_free_i64(t2
);
399 #if TARGET_LONG_BITS == 32
400 tcg_gen_extrh_i64_i32(cpu_sr_ov
, t1
);
402 tcg_gen_mov_i64(cpu_sr_ov
, t1
);
404 tcg_temp_free_i64(t1
);
409 static void gen_msbu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
411 TCGv_i64 t1
= tcg_temp_new_i64();
412 TCGv_i64 t2
= tcg_temp_new_i64();
414 tcg_gen_extu_tl_i64(t1
, srca
);
415 tcg_gen_extu_tl_i64(t2
, srcb
);
416 tcg_gen_mul_i64(t1
, t1
, t2
);
418 /* Note that overflow is only computed during subtraction stage. */
419 tcg_gen_setcond_i64(TCG_COND_LTU
, t2
, cpu_mac
, t1
);
420 tcg_gen_sub_i64(cpu_mac
, cpu_mac
, t1
);
421 tcg_gen_trunc_i64_tl(cpu_sr_cy
, t2
);
422 tcg_temp_free_i64(t2
);
423 tcg_temp_free_i64(t1
);
428 static bool trans_l_add(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
430 check_r0_write(a
->d
);
431 gen_add(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
435 static bool trans_l_addc(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
437 check_r0_write(a
->d
);
438 gen_addc(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
442 static bool trans_l_sub(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
444 check_r0_write(a
->d
);
445 gen_sub(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
449 static bool trans_l_and(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
451 check_r0_write(a
->d
);
452 tcg_gen_and_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
456 static bool trans_l_or(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
458 check_r0_write(a
->d
);
459 tcg_gen_or_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
463 static bool trans_l_xor(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
465 check_r0_write(a
->d
);
466 tcg_gen_xor_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
470 static bool trans_l_sll(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
472 check_r0_write(a
->d
);
473 tcg_gen_shl_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
477 static bool trans_l_srl(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
479 check_r0_write(a
->d
);
480 tcg_gen_shr_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
484 static bool trans_l_sra(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
486 check_r0_write(a
->d
);
487 tcg_gen_sar_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
491 static bool trans_l_ror(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
493 check_r0_write(a
->d
);
494 tcg_gen_rotr_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
498 static bool trans_l_exths(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
500 check_r0_write(a
->d
);
501 tcg_gen_ext16s_tl(cpu_R
[a
->d
], cpu_R
[a
->a
]);
505 static bool trans_l_extbs(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
507 check_r0_write(a
->d
);
508 tcg_gen_ext8s_tl(cpu_R
[a
->d
], cpu_R
[a
->a
]);
512 static bool trans_l_exthz(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
514 check_r0_write(a
->d
);
515 tcg_gen_ext16u_tl(cpu_R
[a
->d
], cpu_R
[a
->a
]);
519 static bool trans_l_extbz(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
521 check_r0_write(a
->d
);
522 tcg_gen_ext8u_tl(cpu_R
[a
->d
], cpu_R
[a
->a
]);
526 static bool trans_l_cmov(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
530 check_r0_write(a
->d
);
531 zero
= tcg_const_tl(0);
532 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_R
[a
->d
], cpu_sr_f
, zero
,
533 cpu_R
[a
->a
], cpu_R
[a
->b
]);
538 static bool trans_l_ff1(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
540 check_r0_write(a
->d
);
541 tcg_gen_ctzi_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], -1);
542 tcg_gen_addi_tl(cpu_R
[a
->d
], cpu_R
[a
->d
], 1);
546 static bool trans_l_fl1(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
548 check_r0_write(a
->d
);
549 tcg_gen_clzi_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], TARGET_LONG_BITS
);
550 tcg_gen_subfi_tl(cpu_R
[a
->d
], TARGET_LONG_BITS
, cpu_R
[a
->d
]);
554 static bool trans_l_mul(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
556 check_r0_write(a
->d
);
557 gen_mul(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
561 static bool trans_l_mulu(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
563 check_r0_write(a
->d
);
564 gen_mulu(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
568 static bool trans_l_div(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
570 check_r0_write(a
->d
);
571 gen_div(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
575 static bool trans_l_divu(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
577 check_r0_write(a
->d
);
578 gen_divu(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], cpu_R
[a
->b
]);
582 static bool trans_l_muld(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
584 gen_muld(dc
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
588 static bool trans_l_muldu(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
590 gen_muldu(dc
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
594 static bool trans_l_j(DisasContext
*dc
, arg_l_j
*a
, uint32_t insn
)
596 target_ulong tmp_pc
= dc
->base
.pc_next
+ a
->n
* 4;
598 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
599 dc
->jmp_pc_imm
= tmp_pc
;
600 dc
->delayed_branch
= 2;
604 static bool trans_l_jal(DisasContext
*dc
, arg_l_jal
*a
, uint32_t insn
)
606 target_ulong tmp_pc
= dc
->base
.pc_next
+ a
->n
* 4;
607 target_ulong ret_pc
= dc
->base
.pc_next
+ 8;
609 tcg_gen_movi_tl(cpu_R
[9], ret_pc
);
610 /* Optimize jal being used to load the PC for PIC. */
611 if (tmp_pc
!= ret_pc
) {
612 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
613 dc
->jmp_pc_imm
= tmp_pc
;
614 dc
->delayed_branch
= 2;
619 static void do_bf(DisasContext
*dc
, arg_l_bf
*a
, TCGCond cond
)
621 target_ulong tmp_pc
= dc
->base
.pc_next
+ a
->n
* 4;
622 TCGv t_next
= tcg_const_tl(dc
->base
.pc_next
+ 8);
623 TCGv t_true
= tcg_const_tl(tmp_pc
);
624 TCGv t_zero
= tcg_const_tl(0);
626 tcg_gen_movcond_tl(cond
, jmp_pc
, cpu_sr_f
, t_zero
, t_true
, t_next
);
628 tcg_temp_free(t_next
);
629 tcg_temp_free(t_true
);
630 tcg_temp_free(t_zero
);
631 dc
->delayed_branch
= 2;
634 static bool trans_l_bf(DisasContext
*dc
, arg_l_bf
*a
, uint32_t insn
)
636 do_bf(dc
, a
, TCG_COND_NE
);
640 static bool trans_l_bnf(DisasContext
*dc
, arg_l_bf
*a
, uint32_t insn
)
642 do_bf(dc
, a
, TCG_COND_EQ
);
646 static bool trans_l_jr(DisasContext
*dc
, arg_l_jr
*a
, uint32_t insn
)
648 tcg_gen_mov_tl(jmp_pc
, cpu_R
[a
->b
]);
649 dc
->delayed_branch
= 2;
653 static bool trans_l_jalr(DisasContext
*dc
, arg_l_jalr
*a
, uint32_t insn
)
655 tcg_gen_mov_tl(jmp_pc
, cpu_R
[a
->b
]);
656 tcg_gen_movi_tl(cpu_R
[9], dc
->base
.pc_next
+ 8);
657 dc
->delayed_branch
= 2;
661 static bool trans_l_lwa(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
665 check_r0_write(a
->d
);
667 tcg_gen_addi_tl(ea
, cpu_R
[a
->a
], a
->i
);
668 tcg_gen_qemu_ld_tl(cpu_R
[a
->d
], ea
, dc
->mem_idx
, MO_TEUL
);
669 tcg_gen_mov_tl(cpu_lock_addr
, ea
);
670 tcg_gen_mov_tl(cpu_lock_value
, cpu_R
[a
->d
]);
675 static void do_load(DisasContext
*dc
, arg_load
*a
, TCGMemOp mop
)
679 check_r0_write(a
->d
);
681 tcg_gen_addi_tl(ea
, cpu_R
[a
->a
], a
->i
);
682 tcg_gen_qemu_ld_tl(cpu_R
[a
->d
], ea
, dc
->mem_idx
, mop
);
686 static bool trans_l_lwz(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
688 do_load(dc
, a
, MO_TEUL
);
692 static bool trans_l_lws(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
694 do_load(dc
, a
, MO_TESL
);
698 static bool trans_l_lbz(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
700 do_load(dc
, a
, MO_UB
);
704 static bool trans_l_lbs(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
706 do_load(dc
, a
, MO_SB
);
710 static bool trans_l_lhz(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
712 do_load(dc
, a
, MO_TEUW
);
716 static bool trans_l_lhs(DisasContext
*dc
, arg_load
*a
, uint32_t insn
)
718 do_load(dc
, a
, MO_TESW
);
722 static bool trans_l_swa(DisasContext
*dc
, arg_store
*a
, uint32_t insn
)
725 TCGLabel
*lab_fail
, *lab_done
;
728 tcg_gen_addi_tl(ea
, cpu_R
[a
->a
], a
->i
);
730 /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned
731 to cpu_R[0]. Since l.swa is quite often immediately followed by a
732 branch, don't bother reallocating; finish the TB using the "real" R0.
733 This also takes care of RB input across the branch. */
736 lab_fail
= gen_new_label();
737 lab_done
= gen_new_label();
738 tcg_gen_brcond_tl(TCG_COND_NE
, ea
, cpu_lock_addr
, lab_fail
);
741 val
= tcg_temp_new();
742 tcg_gen_atomic_cmpxchg_tl(val
, cpu_lock_addr
, cpu_lock_value
,
743 cpu_R
[a
->b
], dc
->mem_idx
, MO_TEUL
);
744 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_sr_f
, val
, cpu_lock_value
);
747 tcg_gen_br(lab_done
);
749 gen_set_label(lab_fail
);
750 tcg_gen_movi_tl(cpu_sr_f
, 0);
752 gen_set_label(lab_done
);
753 tcg_gen_movi_tl(cpu_lock_addr
, -1);
757 static void do_store(DisasContext
*dc
, arg_store
*a
, TCGMemOp mop
)
759 TCGv t0
= tcg_temp_new();
760 tcg_gen_addi_tl(t0
, cpu_R
[a
->a
], a
->i
);
761 tcg_gen_qemu_st_tl(cpu_R
[a
->b
], t0
, dc
->mem_idx
, mop
);
765 static bool trans_l_sw(DisasContext
*dc
, arg_store
*a
, uint32_t insn
)
767 do_store(dc
, a
, MO_TEUL
);
771 static bool trans_l_sb(DisasContext
*dc
, arg_store
*a
, uint32_t insn
)
773 do_store(dc
, a
, MO_UB
);
777 static bool trans_l_sh(DisasContext
*dc
, arg_store
*a
, uint32_t insn
)
779 do_store(dc
, a
, MO_TEUW
);
783 static bool trans_l_nop(DisasContext
*dc
, arg_l_nop
*a
, uint32_t insn
)
788 static bool trans_l_addi(DisasContext
*dc
, arg_rri
*a
, uint32_t insn
)
792 check_r0_write(a
->d
);
793 t0
= tcg_const_tl(a
->i
);
794 gen_add(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], t0
);
799 static bool trans_l_addic(DisasContext
*dc
, arg_rri
*a
, uint32_t insn
)
803 check_r0_write(a
->d
);
804 t0
= tcg_const_tl(a
->i
);
805 gen_addc(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], t0
);
810 static bool trans_l_muli(DisasContext
*dc
, arg_rri
*a
, uint32_t insn
)
814 check_r0_write(a
->d
);
815 t0
= tcg_const_tl(a
->i
);
816 gen_mul(dc
, cpu_R
[a
->d
], cpu_R
[a
->a
], t0
);
821 static bool trans_l_maci(DisasContext
*dc
, arg_l_maci
*a
, uint32_t insn
)
825 t0
= tcg_const_tl(a
->i
);
826 gen_mac(dc
, cpu_R
[a
->a
], t0
);
831 static bool trans_l_andi(DisasContext
*dc
, arg_rrk
*a
, uint32_t insn
)
833 check_r0_write(a
->d
);
834 tcg_gen_andi_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->k
);
838 static bool trans_l_ori(DisasContext
*dc
, arg_rrk
*a
, uint32_t insn
)
840 check_r0_write(a
->d
);
841 tcg_gen_ori_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->k
);
845 static bool trans_l_xori(DisasContext
*dc
, arg_rri
*a
, uint32_t insn
)
847 check_r0_write(a
->d
);
848 tcg_gen_xori_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->i
);
852 static bool trans_l_mfspr(DisasContext
*dc
, arg_l_mfspr
*a
, uint32_t insn
)
854 check_r0_write(a
->d
);
856 #ifdef CONFIG_USER_ONLY
857 gen_illegal_exception(dc
);
859 if (dc
->mem_idx
== MMU_USER_IDX
) {
860 gen_illegal_exception(dc
);
862 TCGv_i32 ti
= tcg_const_i32(a
->k
);
863 gen_helper_mfspr(cpu_R
[a
->d
], cpu_env
, cpu_R
[a
->d
], cpu_R
[a
->a
], ti
);
864 tcg_temp_free_i32(ti
);
870 static bool trans_l_mtspr(DisasContext
*dc
, arg_l_mtspr
*a
, uint32_t insn
)
872 #ifdef CONFIG_USER_ONLY
873 gen_illegal_exception(dc
);
875 if (dc
->mem_idx
== MMU_USER_IDX
) {
876 gen_illegal_exception(dc
);
878 TCGv_i32 ti
= tcg_const_i32(a
->k
);
879 gen_helper_mtspr(cpu_env
, cpu_R
[a
->a
], cpu_R
[a
->b
], ti
);
880 tcg_temp_free_i32(ti
);
886 static bool trans_l_mac(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
888 gen_mac(dc
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
892 static bool trans_l_msb(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
894 gen_msb(dc
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
898 static bool trans_l_macu(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
900 gen_macu(dc
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
904 static bool trans_l_msbu(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
906 gen_msbu(dc
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
910 static bool trans_l_slli(DisasContext
*dc
, arg_dal
*a
, uint32_t insn
)
912 check_r0_write(a
->d
);
913 tcg_gen_shli_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->l
& (TARGET_LONG_BITS
- 1));
917 static bool trans_l_srli(DisasContext
*dc
, arg_dal
*a
, uint32_t insn
)
919 check_r0_write(a
->d
);
920 tcg_gen_shri_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->l
& (TARGET_LONG_BITS
- 1));
924 static bool trans_l_srai(DisasContext
*dc
, arg_dal
*a
, uint32_t insn
)
926 check_r0_write(a
->d
);
927 tcg_gen_sari_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->l
& (TARGET_LONG_BITS
- 1));
931 static bool trans_l_rori(DisasContext
*dc
, arg_dal
*a
, uint32_t insn
)
933 check_r0_write(a
->d
);
934 tcg_gen_rotri_tl(cpu_R
[a
->d
], cpu_R
[a
->a
], a
->l
& (TARGET_LONG_BITS
- 1));
938 static bool trans_l_movhi(DisasContext
*dc
, arg_l_movhi
*a
, uint32_t insn
)
940 check_r0_write(a
->d
);
941 tcg_gen_movi_tl(cpu_R
[a
->d
], a
->k
<< 16);
945 static bool trans_l_macrc(DisasContext
*dc
, arg_l_macrc
*a
, uint32_t insn
)
947 check_r0_write(a
->d
);
948 tcg_gen_trunc_i64_tl(cpu_R
[a
->d
], cpu_mac
);
949 tcg_gen_movi_i64(cpu_mac
, 0);
953 static bool trans_l_sfeq(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
955 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
959 static bool trans_l_sfne(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
961 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
965 static bool trans_l_sfgtu(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
967 tcg_gen_setcond_tl(TCG_COND_GTU
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
971 static bool trans_l_sfgeu(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
973 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
977 static bool trans_l_sfltu(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
979 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
983 static bool trans_l_sfleu(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
985 tcg_gen_setcond_tl(TCG_COND_LEU
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
989 static bool trans_l_sfgts(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
991 tcg_gen_setcond_tl(TCG_COND_GT
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
995 static bool trans_l_sfges(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
997 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
1001 static bool trans_l_sflts(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
1003 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
1007 static bool trans_l_sfles(DisasContext
*dc
, arg_ab
*a
, TCGCond cond
)
1009 tcg_gen_setcond_tl(TCG_COND_LE
, cpu_sr_f
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
1013 static bool trans_l_sfeqi(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1015 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1019 static bool trans_l_sfnei(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1021 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1025 static bool trans_l_sfgtui(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1027 tcg_gen_setcondi_tl(TCG_COND_GTU
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1031 static bool trans_l_sfgeui(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1033 tcg_gen_setcondi_tl(TCG_COND_GEU
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1037 static bool trans_l_sfltui(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1039 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1043 static bool trans_l_sfleui(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1045 tcg_gen_setcondi_tl(TCG_COND_LEU
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1049 static bool trans_l_sfgtsi(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1051 tcg_gen_setcondi_tl(TCG_COND_GT
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1055 static bool trans_l_sfgesi(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1057 tcg_gen_setcondi_tl(TCG_COND_GE
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1061 static bool trans_l_sfltsi(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1063 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1067 static bool trans_l_sflesi(DisasContext
*dc
, arg_ai
*a
, TCGCond cond
)
1069 tcg_gen_setcondi_tl(TCG_COND_LE
, cpu_sr_f
, cpu_R
[a
->a
], a
->i
);
1073 static bool trans_l_sys(DisasContext
*dc
, arg_l_sys
*a
, uint32_t insn
)
1075 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1076 gen_exception(dc
, EXCP_SYSCALL
);
1077 dc
->base
.is_jmp
= DISAS_NORETURN
;
1081 static bool trans_l_trap(DisasContext
*dc
, arg_l_trap
*a
, uint32_t insn
)
1083 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1084 gen_exception(dc
, EXCP_TRAP
);
1085 dc
->base
.is_jmp
= DISAS_NORETURN
;
1089 static bool trans_l_msync(DisasContext
*dc
, arg_l_msync
*a
, uint32_t insn
)
1091 tcg_gen_mb(TCG_MO_ALL
);
1095 static bool trans_l_psync(DisasContext
*dc
, arg_l_psync
*a
, uint32_t insn
)
1100 static bool trans_l_csync(DisasContext
*dc
, arg_l_csync
*a
, uint32_t insn
)
1105 static bool trans_l_rfe(DisasContext
*dc
, arg_l_rfe
*a
, uint32_t insn
)
1107 #ifdef CONFIG_USER_ONLY
1108 gen_illegal_exception(dc
);
1110 if (dc
->mem_idx
== MMU_USER_IDX
) {
1111 gen_illegal_exception(dc
);
1113 gen_helper_rfe(cpu_env
);
1114 dc
->base
.is_jmp
= DISAS_EXIT
;
1120 static void do_fp2(DisasContext
*dc
, arg_da
*a
,
1121 void (*fn
)(TCGv
, TCGv_env
, TCGv
))
1123 check_r0_write(a
->d
);
1124 fn(cpu_R
[a
->d
], cpu_env
, cpu_R
[a
->a
]);
1125 gen_helper_update_fpcsr(cpu_env
);
1128 static void do_fp3(DisasContext
*dc
, arg_dab
*a
,
1129 void (*fn
)(TCGv
, TCGv_env
, TCGv
, TCGv
))
1131 check_r0_write(a
->d
);
1132 fn(cpu_R
[a
->d
], cpu_env
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
1133 gen_helper_update_fpcsr(cpu_env
);
1136 static void do_fpcmp(DisasContext
*dc
, arg_ab
*a
,
1137 void (*fn
)(TCGv
, TCGv_env
, TCGv
, TCGv
),
1138 bool inv
, bool swap
)
1141 fn(cpu_sr_f
, cpu_env
, cpu_R
[a
->b
], cpu_R
[a
->a
]);
1143 fn(cpu_sr_f
, cpu_env
, cpu_R
[a
->a
], cpu_R
[a
->b
]);
1146 tcg_gen_xori_tl(cpu_sr_f
, cpu_sr_f
, 1);
1148 gen_helper_update_fpcsr(cpu_env
);
1151 static bool trans_lf_add_s(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
1153 do_fp3(dc
, a
, gen_helper_float_add_s
);
1157 static bool trans_lf_sub_s(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
1159 do_fp3(dc
, a
, gen_helper_float_sub_s
);
1163 static bool trans_lf_mul_s(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
1165 do_fp3(dc
, a
, gen_helper_float_mul_s
);
1169 static bool trans_lf_div_s(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
1171 do_fp3(dc
, a
, gen_helper_float_div_s
);
1175 static bool trans_lf_rem_s(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
1177 do_fp3(dc
, a
, gen_helper_float_rem_s
);
1181 static bool trans_lf_itof_s(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
1183 do_fp2(dc
, a
, gen_helper_itofs
);
1187 static bool trans_lf_ftoi_s(DisasContext
*dc
, arg_da
*a
, uint32_t insn
)
1189 do_fp2(dc
, a
, gen_helper_ftois
);
1193 static bool trans_lf_madd_s(DisasContext
*dc
, arg_dab
*a
, uint32_t insn
)
1195 check_r0_write(a
->d
);
1196 gen_helper_float_madd_s(cpu_R
[a
->d
], cpu_env
, cpu_R
[a
->d
],
1197 cpu_R
[a
->a
], cpu_R
[a
->b
]);
1198 gen_helper_update_fpcsr(cpu_env
);
1202 static bool trans_lf_sfeq_s(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
1204 do_fpcmp(dc
, a
, gen_helper_float_eq_s
, false, false);
1208 static bool trans_lf_sfne_s(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
1210 do_fpcmp(dc
, a
, gen_helper_float_eq_s
, true, false);
1214 static bool trans_lf_sfgt_s(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
1216 do_fpcmp(dc
, a
, gen_helper_float_lt_s
, false, true);
1220 static bool trans_lf_sfge_s(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
1222 do_fpcmp(dc
, a
, gen_helper_float_le_s
, false, true);
1226 static bool trans_lf_sflt_s(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
1228 do_fpcmp(dc
, a
, gen_helper_float_lt_s
, false, false);
1232 static bool trans_lf_sfle_s(DisasContext
*dc
, arg_ab
*a
, uint32_t insn
)
1234 do_fpcmp(dc
, a
, gen_helper_float_le_s
, false, false);
1238 static void openrisc_tr_init_disas_context(DisasContextBase
*dcb
, CPUState
*cs
)
1240 DisasContext
*dc
= container_of(dcb
, DisasContext
, base
);
1241 CPUOpenRISCState
*env
= cs
->env_ptr
;
1244 dc
->mem_idx
= cpu_mmu_index(env
, false);
1245 dc
->tb_flags
= dc
->base
.tb
->flags
;
1246 dc
->delayed_branch
= (dc
->tb_flags
& TB_FLAGS_DFLAG
) != 0;
1247 dc
->jmp_pc_imm
= -1;
1249 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
1250 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
1253 static void openrisc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
1255 DisasContext
*dc
= container_of(db
, DisasContext
, base
);
1257 /* Allow the TCG optimizer to see that R0 == 0,
1258 when it's true, which is the common case. */
1259 if (dc
->tb_flags
& TB_FLAGS_R0_0
) {
1260 cpu_R
[0] = tcg_const_tl(0);
1266 static void openrisc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
1268 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1270 tcg_gen_insn_start(dc
->base
.pc_next
, (dc
->delayed_branch
? 1 : 0)
1271 | (dc
->base
.num_insns
> 1 ? 2 : 0));
1274 static bool openrisc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
1275 const CPUBreakpoint
*bp
)
1277 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1279 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1280 gen_exception(dc
, EXCP_DEBUG
);
1281 dc
->base
.is_jmp
= DISAS_NORETURN
;
1282 /* The address covered by the breakpoint must be included in
1283 [tb->pc, tb->pc + tb->size) in order to for it to be
1284 properly cleared -- thus we increment the PC here so that
1285 the logic setting tb->size below does the right thing. */
1286 dc
->base
.pc_next
+= 4;
1290 static void openrisc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
1292 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1293 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1294 uint32_t insn
= cpu_ldl_code(&cpu
->env
, dc
->base
.pc_next
);
1296 if (!decode(dc
, insn
)) {
1297 gen_illegal_exception(dc
);
1299 dc
->base
.pc_next
+= 4;
1301 /* When exiting the delay slot normally, exit via jmp_pc.
1302 * For DISAS_NORETURN, we have raised an exception and already exited.
1303 * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing
1304 * in the manual saying this is illegal, but it surely it should.
1305 * At least or1ksim overrides pcnext and ignores the branch.
1307 if (dc
->delayed_branch
1308 && --dc
->delayed_branch
== 0
1309 && dc
->base
.is_jmp
== DISAS_NEXT
) {
1310 dc
->base
.is_jmp
= DISAS_JUMP
;
1314 static void openrisc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
1316 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1317 target_ulong jmp_dest
;
1319 /* If we have already exited the TB, nothing following has effect. */
1320 if (dc
->base
.is_jmp
== DISAS_NORETURN
) {
1324 /* Adjust the delayed branch state for the next TB. */
1325 if ((dc
->tb_flags
& TB_FLAGS_DFLAG
? 1 : 0) != (dc
->delayed_branch
!= 0)) {
1326 tcg_gen_movi_i32(cpu_dflag
, dc
->delayed_branch
!= 0);
1329 /* For DISAS_TOO_MANY, jump to the next insn. */
1330 jmp_dest
= dc
->base
.pc_next
;
1331 tcg_gen_movi_tl(cpu_ppc
, jmp_dest
- 4);
1333 switch (dc
->base
.is_jmp
) {
1335 jmp_dest
= dc
->jmp_pc_imm
;
1336 if (jmp_dest
== -1) {
1337 /* The jump destination is indirect/computed; use jmp_pc. */
1338 tcg_gen_mov_tl(cpu_pc
, jmp_pc
);
1339 tcg_gen_discard_tl(jmp_pc
);
1340 if (unlikely(dc
->base
.singlestep_enabled
)) {
1341 gen_exception(dc
, EXCP_DEBUG
);
1343 tcg_gen_lookup_and_goto_ptr();
1347 /* The jump destination is direct; use jmp_pc_imm.
1348 However, we will have stored into jmp_pc as well;
1349 we know now that it wasn't needed. */
1350 tcg_gen_discard_tl(jmp_pc
);
1353 case DISAS_TOO_MANY
:
1354 if (unlikely(dc
->base
.singlestep_enabled
)) {
1355 tcg_gen_movi_tl(cpu_pc
, jmp_dest
);
1356 gen_exception(dc
, EXCP_DEBUG
);
1357 } else if ((dc
->base
.pc_first
^ jmp_dest
) & TARGET_PAGE_MASK
) {
1358 tcg_gen_movi_tl(cpu_pc
, jmp_dest
);
1359 tcg_gen_lookup_and_goto_ptr();
1362 tcg_gen_movi_tl(cpu_pc
, jmp_dest
);
1363 tcg_gen_exit_tb(dc
->base
.tb
, 0);
1368 if (unlikely(dc
->base
.singlestep_enabled
)) {
1369 gen_exception(dc
, EXCP_DEBUG
);
1371 tcg_gen_exit_tb(NULL
, 0);
1375 g_assert_not_reached();
1379 static void openrisc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
1381 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
1383 qemu_log("IN: %s\n", lookup_symbol(s
->base
.pc_first
));
1384 log_target_disas(cs
, s
->base
.pc_first
, s
->base
.tb
->size
);
1387 static const TranslatorOps openrisc_tr_ops
= {
1388 .init_disas_context
= openrisc_tr_init_disas_context
,
1389 .tb_start
= openrisc_tr_tb_start
,
1390 .insn_start
= openrisc_tr_insn_start
,
1391 .breakpoint_check
= openrisc_tr_breakpoint_check
,
1392 .translate_insn
= openrisc_tr_translate_insn
,
1393 .tb_stop
= openrisc_tr_tb_stop
,
1394 .disas_log
= openrisc_tr_disas_log
,
1397 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
1401 translator_loop(&openrisc_tr_ops
, &ctx
.base
, cs
, tb
);
1404 void openrisc_cpu_dump_state(CPUState
*cs
, FILE *f
,
1405 fprintf_function cpu_fprintf
,
1408 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1409 CPUOpenRISCState
*env
= &cpu
->env
;
1412 cpu_fprintf(f
, "PC=%08x\n", env
->pc
);
1413 for (i
= 0; i
< 32; ++i
) {
1414 cpu_fprintf(f
, "R%02d=%08x%c", i
, cpu_get_gpr(env
, i
),
1415 (i
% 4) == 3 ? '\n' : ' ');
1419 void restore_state_to_opc(CPUOpenRISCState
*env
, TranslationBlock
*tb
,
1423 env
->dflag
= data
[1] & 1;
1425 env
->ppc
= env
->pc
- 4;