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intel_iommu: switching the rest DPRINTF to trace
[qemu/ar7.git] / target / mips / op_helper.c
blobe5f3ea40420eb070ea362eeb776a2dc63f2d796b
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "qemu/host-utils.h"
23 #include "exec/helper-proto.h"
24 #include "exec/exec-all.h"
25 #include "exec/cpu_ldst.h"
26 #include "sysemu/kvm.h"
27
28 /*****************************************************************************/
29 /* Exceptions processing helpers */
30
31 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
32 int error_code)
33 {
34 do_raise_exception_err(env, exception, error_code, 0);
35 }
36
37 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
38 {
39 do_raise_exception(env, exception, GETPC());
40 }
41
42 void helper_raise_exception_debug(CPUMIPSState *env)
43 {
44 do_raise_exception(env, EXCP_DEBUG, 0);
45 }
46
47 static void raise_exception(CPUMIPSState *env, uint32_t exception)
48 {
49 do_raise_exception(env, exception, 0);
50 }
51
52 #if defined(CONFIG_USER_ONLY)
53 #define HELPER_LD(name, insn, type) \
54 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
55 int mem_idx, uintptr_t retaddr) \
56 { \
57 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
58 }
59 #else
60 #define HELPER_LD(name, insn, type) \
61 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
62 int mem_idx, uintptr_t retaddr) \
63 { \
64 switch (mem_idx) \
65 { \
66 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
67 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
68 default: \
69 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
70 } \
71 }
72 #endif
73 HELPER_LD(lw, ldl, int32_t)
74 #if defined(TARGET_MIPS64)
75 HELPER_LD(ld, ldq, int64_t)
76 #endif
77 #undef HELPER_LD
78
79 #if defined(CONFIG_USER_ONLY)
80 #define HELPER_ST(name, insn, type) \
81 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
82 type val, int mem_idx, uintptr_t retaddr) \
83 { \
84 cpu_##insn##_data_ra(env, addr, val, retaddr); \
85 }
86 #else
87 #define HELPER_ST(name, insn, type) \
88 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
89 type val, int mem_idx, uintptr_t retaddr) \
90 { \
91 switch (mem_idx) \
92 { \
93 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
94 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
95 default: \
96 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
97 } \
98 }
99 #endif
100 HELPER_ST(sb, stb, uint8_t)
101 HELPER_ST(sw, stl, uint32_t)
102 #if defined(TARGET_MIPS64)
103 HELPER_ST(sd, stq, uint64_t)
104 #endif
105 #undef HELPER_ST
106
107 /* 64 bits arithmetic for 32 bits hosts */
108 static inline uint64_t get_HILO(CPUMIPSState *env)
109 {
110 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
111 }
112
113 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
114 {
115 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
116 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
117 }
118
119 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
120 {
121 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
122 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
123 return tmp;
124 }
125
126 /* Multiplication variants of the vr54xx. */
127 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
128 target_ulong arg2)
129 {
130 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
131 (int64_t)(int32_t)arg2));
132 }
133
134 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
135 target_ulong arg2)
136 {
137 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
138 (uint64_t)(uint32_t)arg2);
139 }
140
141 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
142 target_ulong arg2)
143 {
144 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
145 (int64_t)(int32_t)arg2);
146 }
147
148 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
149 target_ulong arg2)
150 {
151 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
152 (int64_t)(int32_t)arg2);
153 }
154
155 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
156 target_ulong arg2)
157 {
158 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
159 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
160 }
161
162 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
163 target_ulong arg2)
164 {
165 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
166 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
167 }
168
169 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
170 target_ulong arg2)
171 {
172 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
173 (int64_t)(int32_t)arg2);
174 }
175
176 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
177 target_ulong arg2)
178 {
179 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
180 (int64_t)(int32_t)arg2);
181 }
182
183 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
184 target_ulong arg2)
185 {
186 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
187 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
188 }
189
190 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
191 target_ulong arg2)
192 {
193 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
194 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
195 }
196
197 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
198 target_ulong arg2)
199 {
200 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
201 }
202
203 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
204 target_ulong arg2)
205 {
206 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
207 (uint64_t)(uint32_t)arg2);
208 }
209
210 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
211 target_ulong arg2)
212 {
213 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
214 (int64_t)(int32_t)arg2);
215 }
216
217 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
218 target_ulong arg2)
219 {
220 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
221 (uint64_t)(uint32_t)arg2);
222 }
223
224 static inline target_ulong bitswap(target_ulong v)
225 {
226 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
227 ((v & (target_ulong)0x5555555555555555ULL) << 1);
228 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
229 ((v & (target_ulong)0x3333333333333333ULL) << 2);
230 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
231 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
232 return v;
233 }
234
235 #ifdef TARGET_MIPS64
236 target_ulong helper_dbitswap(target_ulong rt)
237 {
238 return bitswap(rt);
239 }
240 #endif
241
242 target_ulong helper_bitswap(target_ulong rt)
243 {
244 return (int32_t)bitswap(rt);
245 }
246
247 #ifndef CONFIG_USER_ONLY
248
249 static inline hwaddr do_translate_address(CPUMIPSState *env,
250 target_ulong address,
251 int rw, uintptr_t retaddr)
252 {
253 hwaddr lladdr;
254 CPUState *cs = CPU(mips_env_get_cpu(env));
255
256 lladdr = cpu_mips_translate_address(env, address, rw);
257
258 if (lladdr == -1LL) {
259 cpu_loop_exit_restore(cs, retaddr);
260 } else {
261 return lladdr;
262 }
263 }
264
265 #define HELPER_LD_ATOMIC(name, insn, almask) \
266 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
267 { \
268 if (arg & almask) { \
269 env->CP0_BadVAddr = arg; \
270 do_raise_exception(env, EXCP_AdEL, GETPC()); \
271 } \
272 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
273 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
274 return env->llval; \
275 }
276 HELPER_LD_ATOMIC(ll, lw, 0x3)
277 #ifdef TARGET_MIPS64
278 HELPER_LD_ATOMIC(lld, ld, 0x7)
279 #endif
280 #undef HELPER_LD_ATOMIC
281
282 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
283 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
284 target_ulong arg2, int mem_idx) \
285 { \
286 target_long tmp; \
287 \
288 if (arg2 & almask) { \
289 env->CP0_BadVAddr = arg2; \
290 do_raise_exception(env, EXCP_AdES, GETPC()); \
291 } \
292 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
293 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
294 if (tmp == env->llval) { \
295 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
296 return 1; \
297 } \
298 } \
299 return 0; \
300 }
301 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
302 #ifdef TARGET_MIPS64
303 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
304 #endif
305 #undef HELPER_ST_ATOMIC
306 #endif
307
308 #ifdef TARGET_WORDS_BIGENDIAN
309 #define GET_LMASK(v) ((v) & 3)
310 #define GET_OFFSET(addr, offset) (addr + (offset))
311 #else
312 #define GET_LMASK(v) (((v) & 3) ^ 3)
313 #define GET_OFFSET(addr, offset) (addr - (offset))
314 #endif
315
316 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
317 int mem_idx)
318 {
319 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
320
321 if (GET_LMASK(arg2) <= 2) {
322 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
323 GETPC());
324 }
325
326 if (GET_LMASK(arg2) <= 1) {
327 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
328 GETPC());
329 }
330
331 if (GET_LMASK(arg2) == 0) {
332 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
333 GETPC());
334 }
335 }
336
337 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
338 int mem_idx)
339 {
340 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
341
342 if (GET_LMASK(arg2) >= 1) {
343 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
344 GETPC());
345 }
346
347 if (GET_LMASK(arg2) >= 2) {
348 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
349 GETPC());
350 }
351
352 if (GET_LMASK(arg2) == 3) {
353 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
354 GETPC());
355 }
356 }
357
358 #if defined(TARGET_MIPS64)
359 /* "half" load and stores. We must do the memory access inline,
360 or fault handling won't work. */
361
362 #ifdef TARGET_WORDS_BIGENDIAN
363 #define GET_LMASK64(v) ((v) & 7)
364 #else
365 #define GET_LMASK64(v) (((v) & 7) ^ 7)
366 #endif
367
368 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
369 int mem_idx)
370 {
371 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
372
373 if (GET_LMASK64(arg2) <= 6) {
374 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
375 GETPC());
376 }
377
378 if (GET_LMASK64(arg2) <= 5) {
379 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
380 GETPC());
381 }
382
383 if (GET_LMASK64(arg2) <= 4) {
384 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
385 GETPC());
386 }
387
388 if (GET_LMASK64(arg2) <= 3) {
389 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
390 GETPC());
391 }
392
393 if (GET_LMASK64(arg2) <= 2) {
394 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
395 GETPC());
396 }
397
398 if (GET_LMASK64(arg2) <= 1) {
399 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
400 GETPC());
401 }
402
403 if (GET_LMASK64(arg2) <= 0) {
404 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
405 GETPC());
406 }
407 }
408
409 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
410 int mem_idx)
411 {
412 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
413
414 if (GET_LMASK64(arg2) >= 1) {
415 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
416 GETPC());
417 }
418
419 if (GET_LMASK64(arg2) >= 2) {
420 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
421 GETPC());
422 }
423
424 if (GET_LMASK64(arg2) >= 3) {
425 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
426 GETPC());
427 }
428
429 if (GET_LMASK64(arg2) >= 4) {
430 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
431 GETPC());
432 }
433
434 if (GET_LMASK64(arg2) >= 5) {
435 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
436 GETPC());
437 }
438
439 if (GET_LMASK64(arg2) >= 6) {
440 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
441 GETPC());
442 }
443
444 if (GET_LMASK64(arg2) == 7) {
445 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
446 GETPC());
447 }
448 }
449 #endif /* TARGET_MIPS64 */
450
451 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
452
453 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
454 uint32_t mem_idx)
455 {
456 target_ulong base_reglist = reglist & 0xf;
457 target_ulong do_r31 = reglist & 0x10;
458
459 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
460 target_ulong i;
461
462 for (i = 0; i < base_reglist; i++) {
463 env->active_tc.gpr[multiple_regs[i]] =
464 (target_long)do_lw(env, addr, mem_idx, GETPC());
465 addr += 4;
466 }
467 }
468
469 if (do_r31) {
470 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
471 GETPC());
472 }
473 }
474
475 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
476 uint32_t mem_idx)
477 {
478 target_ulong base_reglist = reglist & 0xf;
479 target_ulong do_r31 = reglist & 0x10;
480
481 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
482 target_ulong i;
483
484 for (i = 0; i < base_reglist; i++) {
485 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
486 GETPC());
487 addr += 4;
488 }
489 }
490
491 if (do_r31) {
492 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
493 }
494 }
495
496 #if defined(TARGET_MIPS64)
497 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
498 uint32_t mem_idx)
499 {
500 target_ulong base_reglist = reglist & 0xf;
501 target_ulong do_r31 = reglist & 0x10;
502
503 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
504 target_ulong i;
505
506 for (i = 0; i < base_reglist; i++) {
507 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
508 GETPC());
509 addr += 8;
510 }
511 }
512
513 if (do_r31) {
514 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
515 }
516 }
517
518 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
519 uint32_t mem_idx)
520 {
521 target_ulong base_reglist = reglist & 0xf;
522 target_ulong do_r31 = reglist & 0x10;
523
524 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
525 target_ulong i;
526
527 for (i = 0; i < base_reglist; i++) {
528 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
529 GETPC());
530 addr += 8;
531 }
532 }
533
534 if (do_r31) {
535 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
536 }
537 }
538 #endif
539
540 #ifndef CONFIG_USER_ONLY
541 /* SMP helpers. */
542 static bool mips_vpe_is_wfi(MIPSCPU *c)
543 {
544 CPUState *cpu = CPU(c);
545 CPUMIPSState *env = &c->env;
546
547 /* If the VPE is halted but otherwise active, it means it's waiting for
548 an interrupt. */
549 return cpu->halted && mips_vpe_active(env);
550 }
551
552 static bool mips_vp_is_wfi(MIPSCPU *c)
553 {
554 CPUState *cpu = CPU(c);
555 CPUMIPSState *env = &c->env;
556
557 return cpu->halted && mips_vp_active(env);
558 }
559
560 static inline void mips_vpe_wake(MIPSCPU *c)
561 {
562 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
563 because there might be other conditions that state that c should
564 be sleeping. */
565 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
566 }
567
568 static inline void mips_vpe_sleep(MIPSCPU *cpu)
569 {
570 CPUState *cs = CPU(cpu);
571
572 /* The VPE was shut off, really go to bed.
573 Reset any old _WAKE requests. */
574 cs->halted = 1;
575 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
576 }
577
578 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
579 {
580 CPUMIPSState *c = &cpu->env;
581
582 /* FIXME: TC reschedule. */
583 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
584 mips_vpe_wake(cpu);
585 }
586 }
587
588 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
589 {
590 CPUMIPSState *c = &cpu->env;
591
592 /* FIXME: TC reschedule. */
593 if (!mips_vpe_active(c)) {
594 mips_vpe_sleep(cpu);
595 }
596 }
597
598 /**
599 * mips_cpu_map_tc:
600 * @env: CPU from which mapping is performed.
601 * @tc: Should point to an int with the value of the global TC index.
602 *
603 * This function will transform @tc into a local index within the
604 * returned #CPUMIPSState.
605 */
606 /* FIXME: This code assumes that all VPEs have the same number of TCs,
607 which depends on runtime setup. Can probably be fixed by
608 walking the list of CPUMIPSStates. */
609 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
610 {
611 MIPSCPU *cpu;
612 CPUState *cs;
613 CPUState *other_cs;
614 int vpe_idx;
615 int tc_idx = *tc;
616
617 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
618 /* Not allowed to address other CPUs. */
619 *tc = env->current_tc;
620 return env;
621 }
622
623 cs = CPU(mips_env_get_cpu(env));
624 vpe_idx = tc_idx / cs->nr_threads;
625 *tc = tc_idx % cs->nr_threads;
626 other_cs = qemu_get_cpu(vpe_idx);
627 if (other_cs == NULL) {
628 return env;
629 }
630 cpu = MIPS_CPU(other_cs);
631 return &cpu->env;
632 }
633
634 /* The per VPE CP0_Status register shares some fields with the per TC
635 CP0_TCStatus registers. These fields are wired to the same registers,
636 so changes to either of them should be reflected on both registers.
637
638 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
639
640 These helper call synchronizes the regs for a given cpu. */
641
642 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
643 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
644 int tc); */
645
646 /* Called for updates to CP0_TCStatus. */
647 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
648 target_ulong v)
649 {
650 uint32_t status;
651 uint32_t tcu, tmx, tasid, tksu;
652 uint32_t mask = ((1U << CP0St_CU3)
653 | (1 << CP0St_CU2)
654 | (1 << CP0St_CU1)
655 | (1 << CP0St_CU0)
656 | (1 << CP0St_MX)
657 | (3 << CP0St_KSU));
658
659 tcu = (v >> CP0TCSt_TCU0) & 0xf;
660 tmx = (v >> CP0TCSt_TMX) & 0x1;
661 tasid = v & cpu->CP0_EntryHi_ASID_mask;
662 tksu = (v >> CP0TCSt_TKSU) & 0x3;
663
664 status = tcu << CP0St_CU0;
665 status |= tmx << CP0St_MX;
666 status |= tksu << CP0St_KSU;
667
668 cpu->CP0_Status &= ~mask;
669 cpu->CP0_Status |= status;
670
671 /* Sync the TASID with EntryHi. */
672 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
673 cpu->CP0_EntryHi |= tasid;
674
675 compute_hflags(cpu);
676 }
677
678 /* Called for updates to CP0_EntryHi. */
679 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
680 {
681 int32_t *tcst;
682 uint32_t asid, v = cpu->CP0_EntryHi;
683
684 asid = v & cpu->CP0_EntryHi_ASID_mask;
685
686 if (tc == cpu->current_tc) {
687 tcst = &cpu->active_tc.CP0_TCStatus;
688 } else {
689 tcst = &cpu->tcs[tc].CP0_TCStatus;
690 }
691
692 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
693 *tcst |= asid;
694 }
695
696 /* CP0 helpers */
697 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
698 {
699 return env->mvp->CP0_MVPControl;
700 }
701
702 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
703 {
704 return env->mvp->CP0_MVPConf0;
705 }
706
707 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
708 {
709 return env->mvp->CP0_MVPConf1;
710 }
711
712 target_ulong helper_mfc0_random(CPUMIPSState *env)
713 {
714 return (int32_t)cpu_mips_get_random(env);
715 }
716
717 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
718 {
719 return env->active_tc.CP0_TCStatus;
720 }
721
722 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
723 {
724 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
725 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
726
727 if (other_tc == other->current_tc)
728 return other->active_tc.CP0_TCStatus;
729 else
730 return other->tcs[other_tc].CP0_TCStatus;
731 }
732
733 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
734 {
735 return env->active_tc.CP0_TCBind;
736 }
737
738 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
739 {
740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
741 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
742
743 if (other_tc == other->current_tc)
744 return other->active_tc.CP0_TCBind;
745 else
746 return other->tcs[other_tc].CP0_TCBind;
747 }
748
749 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
750 {
751 return env->active_tc.PC;
752 }
753
754 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
755 {
756 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
757 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
758
759 if (other_tc == other->current_tc)
760 return other->active_tc.PC;
761 else
762 return other->tcs[other_tc].PC;
763 }
764
765 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
766 {
767 return env->active_tc.CP0_TCHalt;
768 }
769
770 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
771 {
772 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
773 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
774
775 if (other_tc == other->current_tc)
776 return other->active_tc.CP0_TCHalt;
777 else
778 return other->tcs[other_tc].CP0_TCHalt;
779 }
780
781 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
782 {
783 return env->active_tc.CP0_TCContext;
784 }
785
786 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
787 {
788 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
789 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
790
791 if (other_tc == other->current_tc)
792 return other->active_tc.CP0_TCContext;
793 else
794 return other->tcs[other_tc].CP0_TCContext;
795 }
796
797 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
798 {
799 return env->active_tc.CP0_TCSchedule;
800 }
801
802 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
803 {
804 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
805 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
806
807 if (other_tc == other->current_tc)
808 return other->active_tc.CP0_TCSchedule;
809 else
810 return other->tcs[other_tc].CP0_TCSchedule;
811 }
812
813 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
814 {
815 return env->active_tc.CP0_TCScheFBack;
816 }
817
818 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
819 {
820 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
821 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
822
823 if (other_tc == other->current_tc)
824 return other->active_tc.CP0_TCScheFBack;
825 else
826 return other->tcs[other_tc].CP0_TCScheFBack;
827 }
828
829 target_ulong helper_mfc0_count(CPUMIPSState *env)
830 {
831 int32_t count;
832 qemu_mutex_lock_iothread();
833 count = (int32_t) cpu_mips_get_count(env);
834 qemu_mutex_unlock_iothread();
835 return count;
836 }
837
838 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
839 {
840 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
841 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
842
843 return other->CP0_EntryHi;
844 }
845
846 target_ulong helper_mftc0_cause(CPUMIPSState *env)
847 {
848 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
849 int32_t tccause;
850 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
851
852 if (other_tc == other->current_tc) {
853 tccause = other->CP0_Cause;
854 } else {
855 tccause = other->CP0_Cause;
856 }
857
858 return tccause;
859 }
860
861 target_ulong helper_mftc0_status(CPUMIPSState *env)
862 {
863 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
864 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
865
866 return other->CP0_Status;
867 }
868
869 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
870 {
871 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
872 }
873
874 target_ulong helper_mfc0_maar(CPUMIPSState *env)
875 {
876 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
877 }
878
879 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
880 {
881 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
882 }
883
884 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
885 {
886 return (int32_t)env->CP0_WatchLo[sel];
887 }
888
889 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
890 {
891 return env->CP0_WatchHi[sel];
892 }
893
894 target_ulong helper_mfc0_debug(CPUMIPSState *env)
895 {
896 target_ulong t0 = env->CP0_Debug;
897 if (env->hflags & MIPS_HFLAG_DM)
898 t0 |= 1 << CP0DB_DM;
899
900 return t0;
901 }
902
903 target_ulong helper_mftc0_debug(CPUMIPSState *env)
904 {
905 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
906 int32_t tcstatus;
907 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
908
909 if (other_tc == other->current_tc)
910 tcstatus = other->active_tc.CP0_Debug_tcstatus;
911 else
912 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
913
914 /* XXX: Might be wrong, check with EJTAG spec. */
915 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
916 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
917 }
918
919 #if defined(TARGET_MIPS64)
920 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
921 {
922 return env->active_tc.PC;
923 }
924
925 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
926 {
927 return env->active_tc.CP0_TCHalt;
928 }
929
930 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
931 {
932 return env->active_tc.CP0_TCContext;
933 }
934
935 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
936 {
937 return env->active_tc.CP0_TCSchedule;
938 }
939
940 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
941 {
942 return env->active_tc.CP0_TCScheFBack;
943 }
944
945 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
946 {
947 return env->lladdr >> env->CP0_LLAddr_shift;
948 }
949
950 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
951 {
952 return env->CP0_MAAR[env->CP0_MAARI];
953 }
954
955 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
956 {
957 return env->CP0_WatchLo[sel];
958 }
959 #endif /* TARGET_MIPS64 */
960
961 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
962 {
963 uint32_t index_p = env->CP0_Index & 0x80000000;
964 uint32_t tlb_index = arg1 & 0x7fffffff;
965 if (tlb_index < env->tlb->nb_tlb) {
966 if (env->insn_flags & ISA_MIPS32R6) {
967 index_p |= arg1 & 0x80000000;
968 }
969 env->CP0_Index = index_p | tlb_index;
970 }
971 }
972
973 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
974 {
975 uint32_t mask = 0;
976 uint32_t newval;
977
978 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
979 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
980 (1 << CP0MVPCo_EVP);
981 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
982 mask |= (1 << CP0MVPCo_STLB);
983 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
984
985 // TODO: Enable/disable shared TLB, enable/disable VPEs.
986
987 env->mvp->CP0_MVPControl = newval;
988 }
989
990 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
991 {
992 uint32_t mask;
993 uint32_t newval;
994
995 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
996 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
997 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
998
999 /* Yield scheduler intercept not implemented. */
1000 /* Gating storage scheduler intercept not implemented. */
1001
1002 // TODO: Enable/disable TCs.
1003
1004 env->CP0_VPEControl = newval;
1005 }
1006
1007 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1008 {
1009 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1010 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011 uint32_t mask;
1012 uint32_t newval;
1013
1014 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1015 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1016 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1017
1018 /* TODO: Enable/disable TCs. */
1019
1020 other->CP0_VPEControl = newval;
1021 }
1022
1023 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1024 {
1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1026 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1027 /* FIXME: Mask away return zero on read bits. */
1028 return other->CP0_VPEControl;
1029 }
1030
1031 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1032 {
1033 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1034 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1035
1036 return other->CP0_VPEConf0;
1037 }
1038
1039 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1040 {
1041 uint32_t mask = 0;
1042 uint32_t newval;
1043
1044 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1045 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1046 mask |= (0xff << CP0VPEC0_XTC);
1047 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1048 }
1049 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1050
1051 // TODO: TC exclusive handling due to ERL/EXL.
1052
1053 env->CP0_VPEConf0 = newval;
1054 }
1055
1056 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1057 {
1058 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1059 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1060 uint32_t mask = 0;
1061 uint32_t newval;
1062
1063 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1064 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1065
1066 /* TODO: TC exclusive handling due to ERL/EXL. */
1067 other->CP0_VPEConf0 = newval;
1068 }
1069
1070 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1071 {
1072 uint32_t mask = 0;
1073 uint32_t newval;
1074
1075 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1076 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1077 (0xff << CP0VPEC1_NCP1);
1078 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1079
1080 /* UDI not implemented. */
1081 /* CP2 not implemented. */
1082
1083 // TODO: Handle FPU (CP1) binding.
1084
1085 env->CP0_VPEConf1 = newval;
1086 }
1087
1088 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1089 {
1090 /* Yield qualifier inputs not implemented. */
1091 env->CP0_YQMask = 0x00000000;
1092 }
1093
1094 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1095 {
1096 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1097 }
1098
1099 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1100
1101 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1102 {
1103 /* 1k pages not implemented */
1104 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1105 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1106 | (rxi << (CP0EnLo_XI - 30));
1107 }
1108
1109 #if defined(TARGET_MIPS64)
1110 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1111
1112 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1113 {
1114 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1115 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1116 }
1117 #endif
1118
1119 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1120 {
1121 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1122 uint32_t newval;
1123
1124 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1125
1126 env->active_tc.CP0_TCStatus = newval;
1127 sync_c0_tcstatus(env, env->current_tc, newval);
1128 }
1129
1130 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1131 {
1132 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1133 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1134
1135 if (other_tc == other->current_tc)
1136 other->active_tc.CP0_TCStatus = arg1;
1137 else
1138 other->tcs[other_tc].CP0_TCStatus = arg1;
1139 sync_c0_tcstatus(other, other_tc, arg1);
1140 }
1141
1142 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1143 {
1144 uint32_t mask = (1 << CP0TCBd_TBE);
1145 uint32_t newval;
1146
1147 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1148 mask |= (1 << CP0TCBd_CurVPE);
1149 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1150 env->active_tc.CP0_TCBind = newval;
1151 }
1152
1153 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1154 {
1155 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1156 uint32_t mask = (1 << CP0TCBd_TBE);
1157 uint32_t newval;
1158 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1159
1160 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1161 mask |= (1 << CP0TCBd_CurVPE);
1162 if (other_tc == other->current_tc) {
1163 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1164 other->active_tc.CP0_TCBind = newval;
1165 } else {
1166 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1167 other->tcs[other_tc].CP0_TCBind = newval;
1168 }
1169 }
1170
1171 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1172 {
1173 env->active_tc.PC = arg1;
1174 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1175 env->lladdr = 0ULL;
1176 /* MIPS16 not implemented. */
1177 }
1178
1179 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1180 {
1181 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1182 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1183
1184 if (other_tc == other->current_tc) {
1185 other->active_tc.PC = arg1;
1186 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1187 other->lladdr = 0ULL;
1188 /* MIPS16 not implemented. */
1189 } else {
1190 other->tcs[other_tc].PC = arg1;
1191 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1192 other->lladdr = 0ULL;
1193 /* MIPS16 not implemented. */
1194 }
1195 }
1196
1197 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1198 {
1199 MIPSCPU *cpu = mips_env_get_cpu(env);
1200
1201 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1202
1203 // TODO: Halt TC / Restart (if allocated+active) TC.
1204 if (env->active_tc.CP0_TCHalt & 1) {
1205 mips_tc_sleep(cpu, env->current_tc);
1206 } else {
1207 mips_tc_wake(cpu, env->current_tc);
1208 }
1209 }
1210
1211 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1212 {
1213 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1214 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1215 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1216
1217 // TODO: Halt TC / Restart (if allocated+active) TC.
1218
1219 if (other_tc == other->current_tc)
1220 other->active_tc.CP0_TCHalt = arg1;
1221 else
1222 other->tcs[other_tc].CP0_TCHalt = arg1;
1223
1224 if (arg1 & 1) {
1225 mips_tc_sleep(other_cpu, other_tc);
1226 } else {
1227 mips_tc_wake(other_cpu, other_tc);
1228 }
1229 }
1230
1231 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1232 {
1233 env->active_tc.CP0_TCContext = arg1;
1234 }
1235
1236 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1237 {
1238 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1239 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1240
1241 if (other_tc == other->current_tc)
1242 other->active_tc.CP0_TCContext = arg1;
1243 else
1244 other->tcs[other_tc].CP0_TCContext = arg1;
1245 }
1246
1247 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1248 {
1249 env->active_tc.CP0_TCSchedule = arg1;
1250 }
1251
1252 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1253 {
1254 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1255 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1256
1257 if (other_tc == other->current_tc)
1258 other->active_tc.CP0_TCSchedule = arg1;
1259 else
1260 other->tcs[other_tc].CP0_TCSchedule = arg1;
1261 }
1262
1263 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1264 {
1265 env->active_tc.CP0_TCScheFBack = arg1;
1266 }
1267
1268 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1269 {
1270 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1271 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1272
1273 if (other_tc == other->current_tc)
1274 other->active_tc.CP0_TCScheFBack = arg1;
1275 else
1276 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1277 }
1278
1279 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1280 {
1281 /* 1k pages not implemented */
1282 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1283 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1284 | (rxi << (CP0EnLo_XI - 30));
1285 }
1286
1287 #if defined(TARGET_MIPS64)
1288 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1289 {
1290 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1291 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1292 }
1293 #endif
1294
1295 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1296 {
1297 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1298 }
1299
1300 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1301 {
1302 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1303 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1304 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1305 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1306 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1307 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1308 }
1309 }
1310
1311 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1312 {
1313 /* SmartMIPS not implemented */
1314 /* 1k pages not implemented */
1315 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1316 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1317 compute_hflags(env);
1318 restore_pamask(env);
1319 }
1320
1321 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1322 {
1323 if (env->insn_flags & ISA_MIPS32R6) {
1324 if (arg1 < env->tlb->nb_tlb) {
1325 env->CP0_Wired = arg1;
1326 }
1327 } else {
1328 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1329 }
1330 }
1331
1332 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1333 {
1334 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1335 }
1336
1337 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1338 {
1339 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1340 }
1341
1342 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1343 {
1344 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1345 }
1346
1347 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1348 {
1349 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1350 }
1351
1352 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1353 {
1354 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1355 }
1356
1357 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1358 {
1359 uint32_t mask = 0x0000000F;
1360
1361 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1362 (env->insn_flags & ISA_MIPS32R6)) {
1363 mask |= (1 << 4);
1364 }
1365 if (env->insn_flags & ISA_MIPS32R6) {
1366 mask |= (1 << 5);
1367 }
1368 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1369 mask |= (1 << 29);
1370
1371 if (arg1 & (1 << 29)) {
1372 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1373 } else {
1374 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1375 }
1376 }
1377
1378 env->CP0_HWREna = arg1 & mask;
1379 }
1380
1381 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1382 {
1383 qemu_mutex_lock_iothread();
1384 cpu_mips_store_count(env, arg1);
1385 qemu_mutex_unlock_iothread();
1386 }
1387
1388 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1389 {
1390 target_ulong old, val, mask;
1391 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1392 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1393 mask |= 1 << CP0EnHi_EHINV;
1394 }
1395
1396 /* 1k pages not implemented */
1397 #if defined(TARGET_MIPS64)
1398 if (env->insn_flags & ISA_MIPS32R6) {
1399 int entryhi_r = extract64(arg1, 62, 2);
1400 int config0_at = extract32(env->CP0_Config0, 13, 2);
1401 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1402 if ((entryhi_r == 2) ||
1403 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1404 /* skip EntryHi.R field if new value is reserved */
1405 mask &= ~(0x3ull << 62);
1406 }
1407 }
1408 mask &= env->SEGMask;
1409 #endif
1410 old = env->CP0_EntryHi;
1411 val = (arg1 & mask) | (old & ~mask);
1412 env->CP0_EntryHi = val;
1413 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1414 sync_c0_entryhi(env, env->current_tc);
1415 }
1416 /* If the ASID changes, flush qemu's TLB. */
1417 if ((old & env->CP0_EntryHi_ASID_mask) !=
1418 (val & env->CP0_EntryHi_ASID_mask)) {
1419 cpu_mips_tlb_flush(env);
1420 }
1421 }
1422
1423 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1424 {
1425 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1427
1428 other->CP0_EntryHi = arg1;
1429 sync_c0_entryhi(other, other_tc);
1430 }
1431
1432 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1433 {
1434 qemu_mutex_lock_iothread();
1435 cpu_mips_store_compare(env, arg1);
1436 qemu_mutex_unlock_iothread();
1437 }
1438
1439 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1440 {
1441 MIPSCPU *cpu = mips_env_get_cpu(env);
1442 uint32_t val, old;
1443
1444 old = env->CP0_Status;
1445 cpu_mips_store_status(env, arg1);
1446 val = env->CP0_Status;
1447
1448 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1449 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1450 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1451 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1452 env->CP0_Cause);
1453 switch (env->hflags & MIPS_HFLAG_KSU) {
1454 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1455 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1456 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1457 default:
1458 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1459 break;
1460 }
1461 }
1462 }
1463
1464 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1465 {
1466 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1467 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1468 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1469
1470 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1471 sync_c0_status(env, other, other_tc);
1472 }
1473
1474 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1475 {
1476 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1477 }
1478
1479 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1480 {
1481 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1482 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1483 }
1484
1485 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1486 {
1487 qemu_mutex_lock_iothread();
1488 cpu_mips_store_cause(env, arg1);
1489 qemu_mutex_unlock_iothread();
1490 }
1491
1492 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1493 {
1494 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1495 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1496
1497 cpu_mips_store_cause(other, arg1);
1498 }
1499
1500 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1501 {
1502 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1503 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1504
1505 return other->CP0_EPC;
1506 }
1507
1508 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1509 {
1510 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1511 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1512
1513 return other->CP0_EBase;
1514 }
1515
1516 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1517 {
1518 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1519 }
1520
1521 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1522 {
1523 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1524 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1525 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1526 }
1527
1528 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1529 {
1530 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1531 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1532
1533 switch (idx) {
1534 case 0: return other->CP0_Config0;
1535 case 1: return other->CP0_Config1;
1536 case 2: return other->CP0_Config2;
1537 case 3: return other->CP0_Config3;
1538 /* 4 and 5 are reserved. */
1539 case 6: return other->CP0_Config6;
1540 case 7: return other->CP0_Config7;
1541 default:
1542 break;
1543 }
1544 return 0;
1545 }
1546
1547 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1548 {
1549 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1550 }
1551
1552 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1553 {
1554 /* tertiary/secondary caches not implemented */
1555 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1556 }
1557
1558 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1559 {
1560 if (env->insn_flags & ASE_MICROMIPS) {
1561 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1562 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1563 }
1564 }
1565
1566 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1567 {
1568 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1569 (arg1 & env->CP0_Config4_rw_bitmask);
1570 }
1571
1572 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1573 {
1574 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1575 (arg1 & env->CP0_Config5_rw_bitmask);
1576 compute_hflags(env);
1577 }
1578
1579 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1580 {
1581 target_long mask = env->CP0_LLAddr_rw_bitmask;
1582 arg1 = arg1 << env->CP0_LLAddr_shift;
1583 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1584 }
1585
1586 #define MTC0_MAAR_MASK(env) \
1587 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1588
1589 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1590 {
1591 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1592 }
1593
1594 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1595 {
1596 env->CP0_MAAR[env->CP0_MAARI] =
1597 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1598 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1599 }
1600
1601 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1602 {
1603 int index = arg1 & 0x3f;
1604 if (index == 0x3f) {
1605 /* Software may write all ones to INDEX to determine the
1606 maximum value supported. */
1607 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1608 } else if (index < MIPS_MAAR_MAX) {
1609 env->CP0_MAARI = index;
1610 }
1611 /* Other than the all ones, if the
1612 value written is not supported, then INDEX is unchanged
1613 from its previous value. */
1614 }
1615
1616 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1617 {
1618 /* Watch exceptions for instructions, data loads, data stores
1619 not implemented. */
1620 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1621 }
1622
1623 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1624 {
1625 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1626 env->CP0_WatchHi[sel] = arg1 & mask;
1627 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1628 }
1629
1630 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1631 {
1632 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1633 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1634 }
1635
1636 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1637 {
1638 env->CP0_Framemask = arg1; /* XXX */
1639 }
1640
1641 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1642 {
1643 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1644 if (arg1 & (1 << CP0DB_DM))
1645 env->hflags |= MIPS_HFLAG_DM;
1646 else
1647 env->hflags &= ~MIPS_HFLAG_DM;
1648 }
1649
1650 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1651 {
1652 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1653 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1654 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1655
1656 /* XXX: Might be wrong, check with EJTAG spec. */
1657 if (other_tc == other->current_tc)
1658 other->active_tc.CP0_Debug_tcstatus = val;
1659 else
1660 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1661 other->CP0_Debug = (other->CP0_Debug &
1662 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1663 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1664 }
1665
1666 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1667 {
1668 env->CP0_Performance0 = arg1 & 0x000007ff;
1669 }
1670
1671 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1672 {
1673 int32_t wst = arg1 & (1 << CP0EC_WST);
1674 int32_t spr = arg1 & (1 << CP0EC_SPR);
1675 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1676
1677 env->CP0_ErrCtl = wst | spr | itc;
1678
1679 if (itc && !wst && !spr) {
1680 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1681 } else {
1682 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1683 }
1684 }
1685
1686 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1687 {
1688 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1689 /* If CACHE instruction is configured for ITC tags then make all
1690 CP0.TagLo bits writable. The actual write to ITC Configuration
1691 Tag will take care of the read-only bits. */
1692 env->CP0_TagLo = arg1;
1693 } else {
1694 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1695 }
1696 }
1697
1698 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1699 {
1700 env->CP0_DataLo = arg1; /* XXX */
1701 }
1702
1703 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1704 {
1705 env->CP0_TagHi = arg1; /* XXX */
1706 }
1707
1708 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1709 {
1710 env->CP0_DataHi = arg1; /* XXX */
1711 }
1712
1713 /* MIPS MT functions */
1714 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1715 {
1716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1717 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1718
1719 if (other_tc == other->current_tc)
1720 return other->active_tc.gpr[sel];
1721 else
1722 return other->tcs[other_tc].gpr[sel];
1723 }
1724
1725 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1726 {
1727 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1728 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1729
1730 if (other_tc == other->current_tc)
1731 return other->active_tc.LO[sel];
1732 else
1733 return other->tcs[other_tc].LO[sel];
1734 }
1735
1736 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1737 {
1738 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1739 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1740
1741 if (other_tc == other->current_tc)
1742 return other->active_tc.HI[sel];
1743 else
1744 return other->tcs[other_tc].HI[sel];
1745 }
1746
1747 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1748 {
1749 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1750 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1751
1752 if (other_tc == other->current_tc)
1753 return other->active_tc.ACX[sel];
1754 else
1755 return other->tcs[other_tc].ACX[sel];
1756 }
1757
1758 target_ulong helper_mftdsp(CPUMIPSState *env)
1759 {
1760 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1761 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1762
1763 if (other_tc == other->current_tc)
1764 return other->active_tc.DSPControl;
1765 else
1766 return other->tcs[other_tc].DSPControl;
1767 }
1768
1769 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1770 {
1771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1772 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1773
1774 if (other_tc == other->current_tc)
1775 other->active_tc.gpr[sel] = arg1;
1776 else
1777 other->tcs[other_tc].gpr[sel] = arg1;
1778 }
1779
1780 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1781 {
1782 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1783 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1784
1785 if (other_tc == other->current_tc)
1786 other->active_tc.LO[sel] = arg1;
1787 else
1788 other->tcs[other_tc].LO[sel] = arg1;
1789 }
1790
1791 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1792 {
1793 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1794 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1795
1796 if (other_tc == other->current_tc)
1797 other->active_tc.HI[sel] = arg1;
1798 else
1799 other->tcs[other_tc].HI[sel] = arg1;
1800 }
1801
1802 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1803 {
1804 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1805 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1806
1807 if (other_tc == other->current_tc)
1808 other->active_tc.ACX[sel] = arg1;
1809 else
1810 other->tcs[other_tc].ACX[sel] = arg1;
1811 }
1812
1813 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1814 {
1815 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1816 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1817
1818 if (other_tc == other->current_tc)
1819 other->active_tc.DSPControl = arg1;
1820 else
1821 other->tcs[other_tc].DSPControl = arg1;
1822 }
1823
1824 /* MIPS MT functions */
1825 target_ulong helper_dmt(void)
1826 {
1827 // TODO
1828 return 0;
1829 }
1830
1831 target_ulong helper_emt(void)
1832 {
1833 // TODO
1834 return 0;
1835 }
1836
1837 target_ulong helper_dvpe(CPUMIPSState *env)
1838 {
1839 CPUState *other_cs = first_cpu;
1840 target_ulong prev = env->mvp->CP0_MVPControl;
1841
1842 CPU_FOREACH(other_cs) {
1843 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1844 /* Turn off all VPEs except the one executing the dvpe. */
1845 if (&other_cpu->env != env) {
1846 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1847 mips_vpe_sleep(other_cpu);
1848 }
1849 }
1850 return prev;
1851 }
1852
1853 target_ulong helper_evpe(CPUMIPSState *env)
1854 {
1855 CPUState *other_cs = first_cpu;
1856 target_ulong prev = env->mvp->CP0_MVPControl;
1857
1858 CPU_FOREACH(other_cs) {
1859 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1860
1861 if (&other_cpu->env != env
1862 /* If the VPE is WFI, don't disturb its sleep. */
1863 && !mips_vpe_is_wfi(other_cpu)) {
1864 /* Enable the VPE. */
1865 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1866 mips_vpe_wake(other_cpu); /* And wake it up. */
1867 }
1868 }
1869 return prev;
1870 }
1871 #endif /* !CONFIG_USER_ONLY */
1872
1873 void helper_fork(target_ulong arg1, target_ulong arg2)
1874 {
1875 // arg1 = rt, arg2 = rs
1876 // TODO: store to TC register
1877 }
1878
1879 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1880 {
1881 target_long arg1 = arg;
1882
1883 if (arg1 < 0) {
1884 /* No scheduling policy implemented. */
1885 if (arg1 != -2) {
1886 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1887 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1888 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1889 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1890 do_raise_exception(env, EXCP_THREAD, GETPC());
1891 }
1892 }
1893 } else if (arg1 == 0) {
1894 if (0 /* TODO: TC underflow */) {
1895 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1896 do_raise_exception(env, EXCP_THREAD, GETPC());
1897 } else {
1898 // TODO: Deallocate TC
1899 }
1900 } else if (arg1 > 0) {
1901 /* Yield qualifier inputs not implemented. */
1902 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1903 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1904 do_raise_exception(env, EXCP_THREAD, GETPC());
1905 }
1906 return env->CP0_YQMask;
1907 }
1908
1909 /* R6 Multi-threading */
1910 #ifndef CONFIG_USER_ONLY
1911 target_ulong helper_dvp(CPUMIPSState *env)
1912 {
1913 CPUState *other_cs = first_cpu;
1914 target_ulong prev = env->CP0_VPControl;
1915
1916 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1917 CPU_FOREACH(other_cs) {
1918 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1919 /* Turn off all VPs except the one executing the dvp. */
1920 if (&other_cpu->env != env) {
1921 mips_vpe_sleep(other_cpu);
1922 }
1923 }
1924 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1925 }
1926 return prev;
1927 }
1928
1929 target_ulong helper_evp(CPUMIPSState *env)
1930 {
1931 CPUState *other_cs = first_cpu;
1932 target_ulong prev = env->CP0_VPControl;
1933
1934 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1935 CPU_FOREACH(other_cs) {
1936 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1937 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1938 /* If the VP is WFI, don't disturb its sleep.
1939 * Otherwise, wake it up. */
1940 mips_vpe_wake(other_cpu);
1941 }
1942 }
1943 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1944 }
1945 return prev;
1946 }
1947 #endif /* !CONFIG_USER_ONLY */
1948
1949 #ifndef CONFIG_USER_ONLY
1950 /* TLB management */
1951 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1952 {
1953 /* Discard entries from env->tlb[first] onwards. */
1954 while (env->tlb->tlb_in_use > first) {
1955 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1956 }
1957 }
1958
1959 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1960 {
1961 #if defined(TARGET_MIPS64)
1962 return extract64(entrylo, 6, 54);
1963 #else
1964 return extract64(entrylo, 6, 24) | /* PFN */
1965 (extract64(entrylo, 32, 32) << 24); /* PFNX */
1966 #endif
1967 }
1968
1969 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1970 {
1971 r4k_tlb_t *tlb;
1972
1973 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1974 tlb = &env->tlb->mmu.r4k.tlb[idx];
1975 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1976 tlb->EHINV = 1;
1977 return;
1978 }
1979 tlb->EHINV = 0;
1980 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1981 #if defined(TARGET_MIPS64)
1982 tlb->VPN &= env->SEGMask;
1983 #endif
1984 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1985 tlb->PageMask = env->CP0_PageMask;
1986 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1987 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1988 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1989 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1990 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1991 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1992 tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1993 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1994 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1995 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1996 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1997 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1998 tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1999 }
2000
2001 void r4k_helper_tlbinv(CPUMIPSState *env)
2002 {
2003 int idx;
2004 r4k_tlb_t *tlb;
2005 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2006
2007 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2008 tlb = &env->tlb->mmu.r4k.tlb[idx];
2009 if (!tlb->G && tlb->ASID == ASID) {
2010 tlb->EHINV = 1;
2011 }
2012 }
2013 cpu_mips_tlb_flush(env);
2014 }
2015
2016 void r4k_helper_tlbinvf(CPUMIPSState *env)
2017 {
2018 int idx;
2019
2020 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2021 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2022 }
2023 cpu_mips_tlb_flush(env);
2024 }
2025
2026 void r4k_helper_tlbwi(CPUMIPSState *env)
2027 {
2028 r4k_tlb_t *tlb;
2029 int idx;
2030 target_ulong VPN;
2031 uint16_t ASID;
2032 bool G, V0, D0, V1, D1;
2033
2034 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2035 tlb = &env->tlb->mmu.r4k.tlb[idx];
2036 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2037 #if defined(TARGET_MIPS64)
2038 VPN &= env->SEGMask;
2039 #endif
2040 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2041 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2042 V0 = (env->CP0_EntryLo0 & 2) != 0;
2043 D0 = (env->CP0_EntryLo0 & 4) != 0;
2044 V1 = (env->CP0_EntryLo1 & 2) != 0;
2045 D1 = (env->CP0_EntryLo1 & 4) != 0;
2046
2047 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2048 permissions on the current entry. */
2049 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2050 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2051 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
2052 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2053 }
2054
2055 r4k_invalidate_tlb(env, idx, 0);
2056 r4k_fill_tlb(env, idx);
2057 }
2058
2059 void r4k_helper_tlbwr(CPUMIPSState *env)
2060 {
2061 int r = cpu_mips_get_random(env);
2062
2063 r4k_invalidate_tlb(env, r, 1);
2064 r4k_fill_tlb(env, r);
2065 }
2066
2067 void r4k_helper_tlbp(CPUMIPSState *env)
2068 {
2069 r4k_tlb_t *tlb;
2070 target_ulong mask;
2071 target_ulong tag;
2072 target_ulong VPN;
2073 uint16_t ASID;
2074 int i;
2075
2076 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2077 for (i = 0; i < env->tlb->nb_tlb; i++) {
2078 tlb = &env->tlb->mmu.r4k.tlb[i];
2079 /* 1k pages are not supported. */
2080 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2081 tag = env->CP0_EntryHi & ~mask;
2082 VPN = tlb->VPN & ~mask;
2083 #if defined(TARGET_MIPS64)
2084 tag &= env->SEGMask;
2085 #endif
2086 /* Check ASID, virtual page number & size */
2087 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2088 /* TLB match */
2089 env->CP0_Index = i;
2090 break;
2091 }
2092 }
2093 if (i == env->tlb->nb_tlb) {
2094 /* No match. Discard any shadow entries, if any of them match. */
2095 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2096 tlb = &env->tlb->mmu.r4k.tlb[i];
2097 /* 1k pages are not supported. */
2098 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2099 tag = env->CP0_EntryHi & ~mask;
2100 VPN = tlb->VPN & ~mask;
2101 #if defined(TARGET_MIPS64)
2102 tag &= env->SEGMask;
2103 #endif
2104 /* Check ASID, virtual page number & size */
2105 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2106 r4k_mips_tlb_flush_extra (env, i);
2107 break;
2108 }
2109 }
2110
2111 env->CP0_Index |= 0x80000000;
2112 }
2113 }
2114
2115 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2116 {
2117 #if defined(TARGET_MIPS64)
2118 return tlb_pfn << 6;
2119 #else
2120 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2121 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2122 #endif
2123 }
2124
2125 void r4k_helper_tlbr(CPUMIPSState *env)
2126 {
2127 r4k_tlb_t *tlb;
2128 uint16_t ASID;
2129 int idx;
2130
2131 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2132 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2133 tlb = &env->tlb->mmu.r4k.tlb[idx];
2134
2135 /* If this will change the current ASID, flush qemu's TLB. */
2136 if (ASID != tlb->ASID)
2137 cpu_mips_tlb_flush(env);
2138
2139 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2140
2141 if (tlb->EHINV) {
2142 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2143 env->CP0_PageMask = 0;
2144 env->CP0_EntryLo0 = 0;
2145 env->CP0_EntryLo1 = 0;
2146 } else {
2147 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2148 env->CP0_PageMask = tlb->PageMask;
2149 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2150 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2151 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2152 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2153 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2154 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2155 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2156 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2157 }
2158 }
2159
2160 void helper_tlbwi(CPUMIPSState *env)
2161 {
2162 env->tlb->helper_tlbwi(env);
2163 }
2164
2165 void helper_tlbwr(CPUMIPSState *env)
2166 {
2167 env->tlb->helper_tlbwr(env);
2168 }
2169
2170 void helper_tlbp(CPUMIPSState *env)
2171 {
2172 env->tlb->helper_tlbp(env);
2173 }
2174
2175 void helper_tlbr(CPUMIPSState *env)
2176 {
2177 env->tlb->helper_tlbr(env);
2178 }
2179
2180 void helper_tlbinv(CPUMIPSState *env)
2181 {
2182 env->tlb->helper_tlbinv(env);
2183 }
2184
2185 void helper_tlbinvf(CPUMIPSState *env)
2186 {
2187 env->tlb->helper_tlbinvf(env);
2188 }
2189
2190 /* Specials */
2191 target_ulong helper_di(CPUMIPSState *env)
2192 {
2193 target_ulong t0 = env->CP0_Status;
2194
2195 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2196 return t0;
2197 }
2198
2199 target_ulong helper_ei(CPUMIPSState *env)
2200 {
2201 target_ulong t0 = env->CP0_Status;
2202
2203 env->CP0_Status = t0 | (1 << CP0St_IE);
2204 return t0;
2205 }
2206
2207 static void debug_pre_eret(CPUMIPSState *env)
2208 {
2209 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2210 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2211 env->active_tc.PC, env->CP0_EPC);
2212 if (env->CP0_Status & (1 << CP0St_ERL))
2213 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2214 if (env->hflags & MIPS_HFLAG_DM)
2215 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2216 qemu_log("\n");
2217 }
2218 }
2219
2220 static void debug_post_eret(CPUMIPSState *env)
2221 {
2222 MIPSCPU *cpu = mips_env_get_cpu(env);
2223
2224 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2225 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2226 env->active_tc.PC, env->CP0_EPC);
2227 if (env->CP0_Status & (1 << CP0St_ERL))
2228 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2229 if (env->hflags & MIPS_HFLAG_DM)
2230 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2231 switch (env->hflags & MIPS_HFLAG_KSU) {
2232 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2233 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2234 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2235 default:
2236 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2237 break;
2238 }
2239 }
2240 }
2241
2242 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2243 {
2244 env->active_tc.PC = error_pc & ~(target_ulong)1;
2245 if (error_pc & 1) {
2246 env->hflags |= MIPS_HFLAG_M16;
2247 } else {
2248 env->hflags &= ~(MIPS_HFLAG_M16);
2249 }
2250 }
2251
2252 static inline void exception_return(CPUMIPSState *env)
2253 {
2254 debug_pre_eret(env);
2255 if (env->CP0_Status & (1 << CP0St_ERL)) {
2256 set_pc(env, env->CP0_ErrorEPC);
2257 env->CP0_Status &= ~(1 << CP0St_ERL);
2258 } else {
2259 set_pc(env, env->CP0_EPC);
2260 env->CP0_Status &= ~(1 << CP0St_EXL);
2261 }
2262 compute_hflags(env);
2263 debug_post_eret(env);
2264 }
2265
2266 void helper_eret(CPUMIPSState *env)
2267 {
2268 exception_return(env);
2269 env->lladdr = 1;
2270 }
2271
2272 void helper_eretnc(CPUMIPSState *env)
2273 {
2274 exception_return(env);
2275 }
2276
2277 void helper_deret(CPUMIPSState *env)
2278 {
2279 debug_pre_eret(env);
2280 set_pc(env, env->CP0_DEPC);
2281
2282 env->hflags &= ~MIPS_HFLAG_DM;
2283 compute_hflags(env);
2284 debug_post_eret(env);
2285 }
2286 #endif /* !CONFIG_USER_ONLY */
2287
2288 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2289 {
2290 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2291 return;
2292 }
2293 do_raise_exception(env, EXCP_RI, pc);
2294 }
2295
2296 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2297 {
2298 check_hwrena(env, 0, GETPC());
2299 return env->CP0_EBase & 0x3ff;
2300 }
2301
2302 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2303 {
2304 check_hwrena(env, 1, GETPC());
2305 return env->SYNCI_Step;
2306 }
2307
2308 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2309 {
2310 int32_t count;
2311 check_hwrena(env, 2, GETPC());
2312 #ifdef CONFIG_USER_ONLY
2313 count = env->CP0_Count;
2314 #else
2315 qemu_mutex_lock_iothread();
2316 count = (int32_t)cpu_mips_get_count(env);
2317 qemu_mutex_unlock_iothread();
2318 #endif
2319 return count;
2320 }
2321
2322 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2323 {
2324 check_hwrena(env, 3, GETPC());
2325 return env->CCRes;
2326 }
2327
2328 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2329 {
2330 check_hwrena(env, 4, GETPC());
2331 return env->CP0_Performance0;
2332 }
2333
2334 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2335 {
2336 check_hwrena(env, 5, GETPC());
2337 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2338 }
2339
2340 void helper_pmon(CPUMIPSState *env, int function)
2341 {
2342 function /= 2;
2343 switch (function) {
2344 case 2: /* TODO: char inbyte(int waitflag); */
2345 if (env->active_tc.gpr[4] == 0)
2346 env->active_tc.gpr[2] = -1;
2347 /* Fall through */
2348 case 11: /* TODO: char inbyte (void); */
2349 env->active_tc.gpr[2] = -1;
2350 break;
2351 case 3:
2352 case 12:
2353 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2354 break;
2355 case 17:
2356 break;
2357 case 158:
2358 {
2359 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2360 printf("%s", fmt);
2361 }
2362 break;
2363 }
2364 }
2365
2366 void helper_wait(CPUMIPSState *env)
2367 {
2368 CPUState *cs = CPU(mips_env_get_cpu(env));
2369
2370 cs->halted = 1;
2371 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2372 /* Last instruction in the block, PC was updated before
2373 - no need to recover PC and icount */
2374 raise_exception(env, EXCP_HLT);
2375 }
2376
2377 #if !defined(CONFIG_USER_ONLY)
2378
2379 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2380 MMUAccessType access_type,
2381 int mmu_idx, uintptr_t retaddr)
2382 {
2383 MIPSCPU *cpu = MIPS_CPU(cs);
2384 CPUMIPSState *env = &cpu->env;
2385 int error_code = 0;
2386 int excp;
2387
2388 env->CP0_BadVAddr = addr;
2389
2390 if (access_type == MMU_DATA_STORE) {
2391 excp = EXCP_AdES;
2392 } else {
2393 excp = EXCP_AdEL;
2394 if (access_type == MMU_INST_FETCH) {
2395 error_code |= EXCP_INST_NOTAVAIL;
2396 }
2397 }
2398
2399 do_raise_exception_err(env, excp, error_code, retaddr);
2400 }
2401
2402 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
2403 int mmu_idx, uintptr_t retaddr)
2404 {
2405 int ret;
2406
2407 ret = mips_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
2408 if (ret) {
2409 MIPSCPU *cpu = MIPS_CPU(cs);
2410 CPUMIPSState *env = &cpu->env;
2411
2412 do_raise_exception_err(env, cs->exception_index,
2413 env->error_code, retaddr);
2414 }
2415 }
2416
2417 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2418 bool is_write, bool is_exec, int unused,
2419 unsigned size)
2420 {
2421 MIPSCPU *cpu = MIPS_CPU(cs);
2422 CPUMIPSState *env = &cpu->env;
2423
2424 /*
2425 * Raising an exception with KVM enabled will crash because it won't be from
2426 * the main execution loop so the longjmp won't have a matching setjmp.
2427 * Until we can trigger a bus error exception through KVM lets just ignore
2428 * the access.
2429 */
2430 if (kvm_enabled()) {
2431 return;
2432 }
2433
2434 if (is_exec) {
2435 raise_exception(env, EXCP_IBE);
2436 } else {
2437 raise_exception(env, EXCP_DBE);
2438 }
2439 }
2440 #endif /* !CONFIG_USER_ONLY */
2441
2442 /* Complex FPU operations which may need stack space. */
2443
2444 #define FLOAT_TWO32 make_float32(1 << 30)
2445 #define FLOAT_TWO64 make_float64(1ULL << 62)
2446
2447 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2448 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2449
2450 /* convert MIPS rounding mode in FCR31 to IEEE library */
2451 unsigned int ieee_rm[] = {
2452 float_round_nearest_even,
2453 float_round_to_zero,
2454 float_round_up,
2455 float_round_down
2456 };
2457
2458 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2459 {
2460 target_ulong arg1 = 0;
2461
2462 switch (reg) {
2463 case 0:
2464 arg1 = (int32_t)env->active_fpu.fcr0;
2465 break;
2466 case 1:
2467 /* UFR Support - Read Status FR */
2468 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2469 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2470 arg1 = (int32_t)
2471 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2472 } else {
2473 do_raise_exception(env, EXCP_RI, GETPC());
2474 }
2475 }
2476 break;
2477 case 5:
2478 /* FRE Support - read Config5.FRE bit */
2479 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2480 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2481 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2482 } else {
2483 helper_raise_exception(env, EXCP_RI);
2484 }
2485 }
2486 break;
2487 case 25:
2488 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2489 break;
2490 case 26:
2491 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2492 break;
2493 case 28:
2494 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2495 break;
2496 default:
2497 arg1 = (int32_t)env->active_fpu.fcr31;
2498 break;
2499 }
2500
2501 return arg1;
2502 }
2503
2504 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2505 {
2506 switch (fs) {
2507 case 1:
2508 /* UFR Alias - Reset Status FR */
2509 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2510 return;
2511 }
2512 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2513 env->CP0_Status &= ~(1 << CP0St_FR);
2514 compute_hflags(env);
2515 } else {
2516 do_raise_exception(env, EXCP_RI, GETPC());
2517 }
2518 break;
2519 case 4:
2520 /* UNFR Alias - Set Status FR */
2521 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2522 return;
2523 }
2524 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2525 env->CP0_Status |= (1 << CP0St_FR);
2526 compute_hflags(env);
2527 } else {
2528 do_raise_exception(env, EXCP_RI, GETPC());
2529 }
2530 break;
2531 case 5:
2532 /* FRE Support - clear Config5.FRE bit */
2533 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2534 return;
2535 }
2536 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2537 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2538 compute_hflags(env);
2539 } else {
2540 helper_raise_exception(env, EXCP_RI);
2541 }
2542 break;
2543 case 6:
2544 /* FRE Support - set Config5.FRE bit */
2545 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2546 return;
2547 }
2548 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2549 env->CP0_Config5 |= (1 << CP0C5_FRE);
2550 compute_hflags(env);
2551 } else {
2552 helper_raise_exception(env, EXCP_RI);
2553 }
2554 break;
2555 case 25:
2556 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2557 return;
2558 }
2559 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2560 ((arg1 & 0x1) << 23);
2561 break;
2562 case 26:
2563 if (arg1 & 0x007c0000)
2564 return;
2565 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2566 break;
2567 case 28:
2568 if (arg1 & 0x007c0000)
2569 return;
2570 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2571 ((arg1 & 0x4) << 22);
2572 break;
2573 case 31:
2574 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2575 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2576 break;
2577 default:
2578 return;
2579 }
2580 restore_fp_status(env);
2581 set_float_exception_flags(0, &env->active_fpu.fp_status);
2582 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2583 do_raise_exception(env, EXCP_FPE, GETPC());
2584 }
2585
2586 int ieee_ex_to_mips(int xcpt)
2587 {
2588 int ret = 0;
2589 if (xcpt) {
2590 if (xcpt & float_flag_invalid) {
2591 ret |= FP_INVALID;
2592 }
2593 if (xcpt & float_flag_overflow) {
2594 ret |= FP_OVERFLOW;
2595 }
2596 if (xcpt & float_flag_underflow) {
2597 ret |= FP_UNDERFLOW;
2598 }
2599 if (xcpt & float_flag_divbyzero) {
2600 ret |= FP_DIV0;
2601 }
2602 if (xcpt & float_flag_inexact) {
2603 ret |= FP_INEXACT;
2604 }
2605 }
2606 return ret;
2607 }
2608
2609 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2610 {
2611 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2612
2613 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2614
2615 if (tmp) {
2616 set_float_exception_flags(0, &env->active_fpu.fp_status);
2617
2618 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2619 do_raise_exception(env, EXCP_FPE, pc);
2620 } else {
2621 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2622 }
2623 }
2624 }
2625
2626 /* Float support.
2627 Single precition routines have a "s" suffix, double precision a
2628 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2629 paired single lower "pl", paired single upper "pu". */
2630
2631 /* unary operations, modifying fp status */
2632 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2633 {
2634 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2635 update_fcr31(env, GETPC());
2636 return fdt0;
2637 }
2638
2639 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2640 {
2641 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2642 update_fcr31(env, GETPC());
2643 return fst0;
2644 }
2645
2646 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2647 {
2648 uint64_t fdt2;
2649
2650 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2651 fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status);
2652 update_fcr31(env, GETPC());
2653 return fdt2;
2654 }
2655
2656 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2657 {
2658 uint64_t fdt2;
2659
2660 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2661 update_fcr31(env, GETPC());
2662 return fdt2;
2663 }
2664
2665 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2666 {
2667 uint64_t fdt2;
2668
2669 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2670 update_fcr31(env, GETPC());
2671 return fdt2;
2672 }
2673
2674 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2675 {
2676 uint64_t dt2;
2677
2678 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2679 if (get_float_exception_flags(&env->active_fpu.fp_status)
2680 & (float_flag_invalid | float_flag_overflow)) {
2681 dt2 = FP_TO_INT64_OVERFLOW;
2682 }
2683 update_fcr31(env, GETPC());
2684 return dt2;
2685 }
2686
2687 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2688 {
2689 uint64_t dt2;
2690
2691 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2692 if (get_float_exception_flags(&env->active_fpu.fp_status)
2693 & (float_flag_invalid | float_flag_overflow)) {
2694 dt2 = FP_TO_INT64_OVERFLOW;
2695 }
2696 update_fcr31(env, GETPC());
2697 return dt2;
2698 }
2699
2700 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2701 {
2702 uint32_t fst2;
2703 uint32_t fsth2;
2704
2705 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2706 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2707 update_fcr31(env, GETPC());
2708 return ((uint64_t)fsth2 << 32) | fst2;
2709 }
2710
2711 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2712 {
2713 uint32_t wt2;
2714 uint32_t wth2;
2715 int excp, excph;
2716
2717 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2718 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2719 if (excp & (float_flag_overflow | float_flag_invalid)) {
2720 wt2 = FP_TO_INT32_OVERFLOW;
2721 }
2722
2723 set_float_exception_flags(0, &env->active_fpu.fp_status);
2724 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2725 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2726 if (excph & (float_flag_overflow | float_flag_invalid)) {
2727 wth2 = FP_TO_INT32_OVERFLOW;
2728 }
2729
2730 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2731 update_fcr31(env, GETPC());
2732
2733 return ((uint64_t)wth2 << 32) | wt2;
2734 }
2735
2736 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2737 {
2738 uint32_t fst2;
2739
2740 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2741 fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status);
2742 update_fcr31(env, GETPC());
2743 return fst2;
2744 }
2745
2746 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2747 {
2748 uint32_t fst2;
2749
2750 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2751 update_fcr31(env, GETPC());
2752 return fst2;
2753 }
2754
2755 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2756 {
2757 uint32_t fst2;
2758
2759 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2760 update_fcr31(env, GETPC());
2761 return fst2;
2762 }
2763
2764 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2765 {
2766 uint32_t wt2;
2767
2768 wt2 = wt0;
2769 update_fcr31(env, GETPC());
2770 return wt2;
2771 }
2772
2773 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2774 {
2775 uint32_t wt2;
2776
2777 wt2 = wth0;
2778 update_fcr31(env, GETPC());
2779 return wt2;
2780 }
2781
2782 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
2783 {
2784 uint32_t wt2;
2785
2786 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2787 if (get_float_exception_flags(&env->active_fpu.fp_status)
2788 & (float_flag_invalid | float_flag_overflow)) {
2789 wt2 = FP_TO_INT32_OVERFLOW;
2790 }
2791 update_fcr31(env, GETPC());
2792 return wt2;
2793 }
2794
2795 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
2796 {
2797 uint32_t wt2;
2798
2799 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2800 if (get_float_exception_flags(&env->active_fpu.fp_status)
2801 & (float_flag_invalid | float_flag_overflow)) {
2802 wt2 = FP_TO_INT32_OVERFLOW;
2803 }
2804 update_fcr31(env, GETPC());
2805 return wt2;
2806 }
2807
2808 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
2809 {
2810 uint64_t dt2;
2811
2812 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2813 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2814 restore_rounding_mode(env);
2815 if (get_float_exception_flags(&env->active_fpu.fp_status)
2816 & (float_flag_invalid | float_flag_overflow)) {
2817 dt2 = FP_TO_INT64_OVERFLOW;
2818 }
2819 update_fcr31(env, GETPC());
2820 return dt2;
2821 }
2822
2823 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
2824 {
2825 uint64_t dt2;
2826
2827 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2828 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2829 restore_rounding_mode(env);
2830 if (get_float_exception_flags(&env->active_fpu.fp_status)
2831 & (float_flag_invalid | float_flag_overflow)) {
2832 dt2 = FP_TO_INT64_OVERFLOW;
2833 }
2834 update_fcr31(env, GETPC());
2835 return dt2;
2836 }
2837
2838 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
2839 {
2840 uint32_t wt2;
2841
2842 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2843 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2844 restore_rounding_mode(env);
2845 if (get_float_exception_flags(&env->active_fpu.fp_status)
2846 & (float_flag_invalid | float_flag_overflow)) {
2847 wt2 = FP_TO_INT32_OVERFLOW;
2848 }
2849 update_fcr31(env, GETPC());
2850 return wt2;
2851 }
2852
2853 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
2854 {
2855 uint32_t wt2;
2856
2857 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2858 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2859 restore_rounding_mode(env);
2860 if (get_float_exception_flags(&env->active_fpu.fp_status)
2861 & (float_flag_invalid | float_flag_overflow)) {
2862 wt2 = FP_TO_INT32_OVERFLOW;
2863 }
2864 update_fcr31(env, GETPC());
2865 return wt2;
2866 }
2867
2868 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
2869 {
2870 uint64_t dt2;
2871
2872 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2873 if (get_float_exception_flags(&env->active_fpu.fp_status)
2874 & (float_flag_invalid | float_flag_overflow)) {
2875 dt2 = FP_TO_INT64_OVERFLOW;
2876 }
2877 update_fcr31(env, GETPC());
2878 return dt2;
2879 }
2880
2881 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
2882 {
2883 uint64_t dt2;
2884
2885 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2886 if (get_float_exception_flags(&env->active_fpu.fp_status)
2887 & (float_flag_invalid | float_flag_overflow)) {
2888 dt2 = FP_TO_INT64_OVERFLOW;
2889 }
2890 update_fcr31(env, GETPC());
2891 return dt2;
2892 }
2893
2894 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
2895 {
2896 uint32_t wt2;
2897
2898 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2899 if (get_float_exception_flags(&env->active_fpu.fp_status)
2900 & (float_flag_invalid | float_flag_overflow)) {
2901 wt2 = FP_TO_INT32_OVERFLOW;
2902 }
2903 update_fcr31(env, GETPC());
2904 return wt2;
2905 }
2906
2907 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
2908 {
2909 uint32_t wt2;
2910
2911 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2912 if (get_float_exception_flags(&env->active_fpu.fp_status)
2913 & (float_flag_invalid | float_flag_overflow)) {
2914 wt2 = FP_TO_INT32_OVERFLOW;
2915 }
2916 update_fcr31(env, GETPC());
2917 return wt2;
2918 }
2919
2920 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
2921 {
2922 uint64_t dt2;
2923
2924 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2925 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2926 restore_rounding_mode(env);
2927 if (get_float_exception_flags(&env->active_fpu.fp_status)
2928 & (float_flag_invalid | float_flag_overflow)) {
2929 dt2 = FP_TO_INT64_OVERFLOW;
2930 }
2931 update_fcr31(env, GETPC());
2932 return dt2;
2933 }
2934
2935 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
2936 {
2937 uint64_t dt2;
2938
2939 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2940 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2941 restore_rounding_mode(env);
2942 if (get_float_exception_flags(&env->active_fpu.fp_status)
2943 & (float_flag_invalid | float_flag_overflow)) {
2944 dt2 = FP_TO_INT64_OVERFLOW;
2945 }
2946 update_fcr31(env, GETPC());
2947 return dt2;
2948 }
2949
2950 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
2951 {
2952 uint32_t wt2;
2953
2954 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2955 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2956 restore_rounding_mode(env);
2957 if (get_float_exception_flags(&env->active_fpu.fp_status)
2958 & (float_flag_invalid | float_flag_overflow)) {
2959 wt2 = FP_TO_INT32_OVERFLOW;
2960 }
2961 update_fcr31(env, GETPC());
2962 return wt2;
2963 }
2964
2965 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
2966 {
2967 uint32_t wt2;
2968
2969 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2970 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2971 restore_rounding_mode(env);
2972 if (get_float_exception_flags(&env->active_fpu.fp_status)
2973 & (float_flag_invalid | float_flag_overflow)) {
2974 wt2 = FP_TO_INT32_OVERFLOW;
2975 }
2976 update_fcr31(env, GETPC());
2977 return wt2;
2978 }
2979
2980 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
2981 {
2982 uint64_t dt2;
2983
2984 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2985 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2986 restore_rounding_mode(env);
2987 if (get_float_exception_flags(&env->active_fpu.fp_status)
2988 & (float_flag_invalid | float_flag_overflow)) {
2989 dt2 = FP_TO_INT64_OVERFLOW;
2990 }
2991 update_fcr31(env, GETPC());
2992 return dt2;
2993 }
2994
2995 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
2996 {
2997 uint64_t dt2;
2998
2999 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3000 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3001 restore_rounding_mode(env);
3002 if (get_float_exception_flags(&env->active_fpu.fp_status)
3003 & (float_flag_invalid | float_flag_overflow)) {
3004 dt2 = FP_TO_INT64_OVERFLOW;
3005 }
3006 update_fcr31(env, GETPC());
3007 return dt2;
3008 }
3009
3010 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3011 {
3012 uint32_t wt2;
3013
3014 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3015 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3016 restore_rounding_mode(env);
3017 if (get_float_exception_flags(&env->active_fpu.fp_status)
3018 & (float_flag_invalid | float_flag_overflow)) {
3019 wt2 = FP_TO_INT32_OVERFLOW;
3020 }
3021 update_fcr31(env, GETPC());
3022 return wt2;
3023 }
3024
3025 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3026 {
3027 uint32_t wt2;
3028
3029 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3030 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3031 restore_rounding_mode(env);
3032 if (get_float_exception_flags(&env->active_fpu.fp_status)
3033 & (float_flag_invalid | float_flag_overflow)) {
3034 wt2 = FP_TO_INT32_OVERFLOW;
3035 }
3036 update_fcr31(env, GETPC());
3037 return wt2;
3038 }
3039
3040 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3041 {
3042 uint64_t dt2;
3043
3044 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3045 if (get_float_exception_flags(&env->active_fpu.fp_status)
3046 & float_flag_invalid) {
3047 if (float64_is_any_nan(fdt0)) {
3048 dt2 = 0;
3049 }
3050 }
3051 update_fcr31(env, GETPC());
3052 return dt2;
3053 }
3054
3055 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3056 {
3057 uint64_t dt2;
3058
3059 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3060 if (get_float_exception_flags(&env->active_fpu.fp_status)
3061 & float_flag_invalid) {
3062 if (float32_is_any_nan(fst0)) {
3063 dt2 = 0;
3064 }
3065 }
3066 update_fcr31(env, GETPC());
3067 return dt2;
3068 }
3069
3070 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3071 {
3072 uint32_t wt2;
3073
3074 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3075 if (get_float_exception_flags(&env->active_fpu.fp_status)
3076 & float_flag_invalid) {
3077 if (float64_is_any_nan(fdt0)) {
3078 wt2 = 0;
3079 }
3080 }
3081 update_fcr31(env, GETPC());
3082 return wt2;
3083 }
3084
3085 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3086 {
3087 uint32_t wt2;
3088
3089 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3090 if (get_float_exception_flags(&env->active_fpu.fp_status)
3091 & float_flag_invalid) {
3092 if (float32_is_any_nan(fst0)) {
3093 wt2 = 0;
3094 }
3095 }
3096 update_fcr31(env, GETPC());
3097 return wt2;
3098 }
3099
3100 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3101 {
3102 uint64_t dt2;
3103
3104 set_float_rounding_mode(float_round_nearest_even,
3105 &env->active_fpu.fp_status);
3106 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3107 restore_rounding_mode(env);
3108 if (get_float_exception_flags(&env->active_fpu.fp_status)
3109 & float_flag_invalid) {
3110 if (float64_is_any_nan(fdt0)) {
3111 dt2 = 0;
3112 }
3113 }
3114 update_fcr31(env, GETPC());
3115 return dt2;
3116 }
3117
3118 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3119 {
3120 uint64_t dt2;
3121
3122 set_float_rounding_mode(float_round_nearest_even,
3123 &env->active_fpu.fp_status);
3124 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3125 restore_rounding_mode(env);
3126 if (get_float_exception_flags(&env->active_fpu.fp_status)
3127 & float_flag_invalid) {
3128 if (float32_is_any_nan(fst0)) {
3129 dt2 = 0;
3130 }
3131 }
3132 update_fcr31(env, GETPC());
3133 return dt2;
3134 }
3135
3136 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3137 {
3138 uint32_t wt2;
3139
3140 set_float_rounding_mode(float_round_nearest_even,
3141 &env->active_fpu.fp_status);
3142 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3143 restore_rounding_mode(env);
3144 if (get_float_exception_flags(&env->active_fpu.fp_status)
3145 & float_flag_invalid) {
3146 if (float64_is_any_nan(fdt0)) {
3147 wt2 = 0;
3148 }
3149 }
3150 update_fcr31(env, GETPC());
3151 return wt2;
3152 }
3153
3154 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3155 {
3156 uint32_t wt2;
3157
3158 set_float_rounding_mode(float_round_nearest_even,
3159 &env->active_fpu.fp_status);
3160 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3161 restore_rounding_mode(env);
3162 if (get_float_exception_flags(&env->active_fpu.fp_status)
3163 & float_flag_invalid) {
3164 if (float32_is_any_nan(fst0)) {
3165 wt2 = 0;
3166 }
3167 }
3168 update_fcr31(env, GETPC());
3169 return wt2;
3170 }
3171
3172 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3173 {
3174 uint64_t dt2;
3175
3176 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3177 if (get_float_exception_flags(&env->active_fpu.fp_status)
3178 & float_flag_invalid) {
3179 if (float64_is_any_nan(fdt0)) {
3180 dt2 = 0;
3181 }
3182 }
3183 update_fcr31(env, GETPC());
3184 return dt2;
3185 }
3186
3187 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3188 {
3189 uint64_t dt2;
3190
3191 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3192 if (get_float_exception_flags(&env->active_fpu.fp_status)
3193 & float_flag_invalid) {
3194 if (float32_is_any_nan(fst0)) {
3195 dt2 = 0;
3196 }
3197 }
3198 update_fcr31(env, GETPC());
3199 return dt2;
3200 }
3201
3202 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3203 {
3204 uint32_t wt2;
3205
3206 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3207 if (get_float_exception_flags(&env->active_fpu.fp_status)
3208 & float_flag_invalid) {
3209 if (float64_is_any_nan(fdt0)) {
3210 wt2 = 0;
3211 }
3212 }
3213 update_fcr31(env, GETPC());
3214 return wt2;
3215 }
3216
3217 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3218 {
3219 uint32_t wt2;
3220
3221 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3222 if (get_float_exception_flags(&env->active_fpu.fp_status)
3223 & float_flag_invalid) {
3224 if (float32_is_any_nan(fst0)) {
3225 wt2 = 0;
3226 }
3227 }
3228 update_fcr31(env, GETPC());
3229 return wt2;
3230 }
3231
3232 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3233 {
3234 uint64_t dt2;
3235
3236 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3237 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3238 restore_rounding_mode(env);
3239 if (get_float_exception_flags(&env->active_fpu.fp_status)
3240 & float_flag_invalid) {
3241 if (float64_is_any_nan(fdt0)) {
3242 dt2 = 0;
3243 }
3244 }
3245 update_fcr31(env, GETPC());
3246 return dt2;
3247 }
3248
3249 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3250 {
3251 uint64_t dt2;
3252
3253 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3254 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3255 restore_rounding_mode(env);
3256 if (get_float_exception_flags(&env->active_fpu.fp_status)
3257 & float_flag_invalid) {
3258 if (float32_is_any_nan(fst0)) {
3259 dt2 = 0;
3260 }
3261 }
3262 update_fcr31(env, GETPC());
3263 return dt2;
3264 }
3265
3266 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3267 {
3268 uint32_t wt2;
3269
3270 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3271 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3272 restore_rounding_mode(env);
3273 if (get_float_exception_flags(&env->active_fpu.fp_status)
3274 & float_flag_invalid) {
3275 if (float64_is_any_nan(fdt0)) {
3276 wt2 = 0;
3277 }
3278 }
3279 update_fcr31(env, GETPC());
3280 return wt2;
3281 }
3282
3283 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3284 {
3285 uint32_t wt2;
3286
3287 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3288 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3289 restore_rounding_mode(env);
3290 if (get_float_exception_flags(&env->active_fpu.fp_status)
3291 & float_flag_invalid) {
3292 if (float32_is_any_nan(fst0)) {
3293 wt2 = 0;
3294 }
3295 }
3296 update_fcr31(env, GETPC());
3297 return wt2;
3298 }
3299
3300 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3301 {
3302 uint64_t dt2;
3303
3304 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3305 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3306 restore_rounding_mode(env);
3307 if (get_float_exception_flags(&env->active_fpu.fp_status)
3308 & float_flag_invalid) {
3309 if (float64_is_any_nan(fdt0)) {
3310 dt2 = 0;
3311 }
3312 }
3313 update_fcr31(env, GETPC());
3314 return dt2;
3315 }
3316
3317 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3318 {
3319 uint64_t dt2;
3320
3321 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3322 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3323 restore_rounding_mode(env);
3324 if (get_float_exception_flags(&env->active_fpu.fp_status)
3325 & float_flag_invalid) {
3326 if (float32_is_any_nan(fst0)) {
3327 dt2 = 0;
3328 }
3329 }
3330 update_fcr31(env, GETPC());
3331 return dt2;
3332 }
3333
3334 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3335 {
3336 uint32_t wt2;
3337
3338 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3339 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3340 restore_rounding_mode(env);
3341 if (get_float_exception_flags(&env->active_fpu.fp_status)
3342 & float_flag_invalid) {
3343 if (float64_is_any_nan(fdt0)) {
3344 wt2 = 0;
3345 }
3346 }
3347 update_fcr31(env, GETPC());
3348 return wt2;
3349 }
3350
3351 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3352 {
3353 uint32_t wt2;
3354
3355 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3356 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3357 restore_rounding_mode(env);
3358 if (get_float_exception_flags(&env->active_fpu.fp_status)
3359 & float_flag_invalid) {
3360 if (float32_is_any_nan(fst0)) {
3361 wt2 = 0;
3362 }
3363 }
3364 update_fcr31(env, GETPC());
3365 return wt2;
3366 }
3367
3368 /* unary operations, not modifying fp status */
3369 #define FLOAT_UNOP(name) \
3370 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3371 { \
3372 return float64_ ## name(fdt0); \
3373 } \
3374 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3375 { \
3376 return float32_ ## name(fst0); \
3377 } \
3378 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3379 { \
3380 uint32_t wt0; \
3381 uint32_t wth0; \
3382 \
3383 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3384 wth0 = float32_ ## name(fdt0 >> 32); \
3385 return ((uint64_t)wth0 << 32) | wt0; \
3386 }
3387 FLOAT_UNOP(abs)
3388 FLOAT_UNOP(chs)
3389 #undef FLOAT_UNOP
3390
3391 /* MIPS specific unary operations */
3392 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3393 {
3394 uint64_t fdt2;
3395
3396 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3397 update_fcr31(env, GETPC());
3398 return fdt2;
3399 }
3400
3401 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3402 {
3403 uint32_t fst2;
3404
3405 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3406 update_fcr31(env, GETPC());
3407 return fst2;
3408 }
3409
3410 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3411 {
3412 uint64_t fdt2;
3413
3414 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3415 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3416 update_fcr31(env, GETPC());
3417 return fdt2;
3418 }
3419
3420 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3421 {
3422 uint32_t fst2;
3423
3424 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3425 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3426 update_fcr31(env, GETPC());
3427 return fst2;
3428 }
3429
3430 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3431 {
3432 uint64_t fdt2;
3433
3434 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3435 update_fcr31(env, GETPC());
3436 return fdt2;
3437 }
3438
3439 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3440 {
3441 uint32_t fst2;
3442
3443 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3444 update_fcr31(env, GETPC());
3445 return fst2;
3446 }
3447
3448 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3449 {
3450 uint32_t fst2;
3451 uint32_t fsth2;
3452
3453 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3454 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3455 update_fcr31(env, GETPC());
3456 return ((uint64_t)fsth2 << 32) | fst2;
3457 }
3458
3459 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3460 {
3461 uint64_t fdt2;
3462
3463 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3464 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3465 update_fcr31(env, GETPC());
3466 return fdt2;
3467 }
3468
3469 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3470 {
3471 uint32_t fst2;
3472
3473 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3474 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3475 update_fcr31(env, GETPC());
3476 return fst2;
3477 }
3478
3479 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3480 {
3481 uint32_t fst2;
3482 uint32_t fsth2;
3483
3484 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3485 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3486 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3487 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3488 update_fcr31(env, GETPC());
3489 return ((uint64_t)fsth2 << 32) | fst2;
3490 }
3491
3492 #define FLOAT_RINT(name, bits) \
3493 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3494 uint ## bits ## _t fs) \
3495 { \
3496 uint ## bits ## _t fdret; \
3497 \
3498 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3499 update_fcr31(env, GETPC()); \
3500 return fdret; \
3501 }
3502
3503 FLOAT_RINT(rint_s, 32)
3504 FLOAT_RINT(rint_d, 64)
3505 #undef FLOAT_RINT
3506
3507 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3508 #define FLOAT_CLASS_QUIET_NAN 0x002
3509 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3510 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3511 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3512 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3513 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3514 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3515 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3516 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3517
3518 #define FLOAT_CLASS(name, bits) \
3519 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3520 float_status *status) \
3521 { \
3522 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3523 return FLOAT_CLASS_SIGNALING_NAN; \
3524 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3525 return FLOAT_CLASS_QUIET_NAN; \
3526 } else if (float ## bits ## _is_neg(arg)) { \
3527 if (float ## bits ## _is_infinity(arg)) { \
3528 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3529 } else if (float ## bits ## _is_zero(arg)) { \
3530 return FLOAT_CLASS_NEGATIVE_ZERO; \
3531 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3532 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3533 } else { \
3534 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3535 } \
3536 } else { \
3537 if (float ## bits ## _is_infinity(arg)) { \
3538 return FLOAT_CLASS_POSITIVE_INFINITY; \
3539 } else if (float ## bits ## _is_zero(arg)) { \
3540 return FLOAT_CLASS_POSITIVE_ZERO; \
3541 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3542 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3543 } else { \
3544 return FLOAT_CLASS_POSITIVE_NORMAL; \
3545 } \
3546 } \
3547 } \
3548 \
3549 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3550 uint ## bits ## _t arg) \
3551 { \
3552 return float_ ## name(arg, &env->active_fpu.fp_status); \
3553 }
3554
3555 FLOAT_CLASS(class_s, 32)
3556 FLOAT_CLASS(class_d, 64)
3557 #undef FLOAT_CLASS
3558
3559 /* binary operations */
3560 #define FLOAT_BINOP(name) \
3561 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3562 uint64_t fdt0, uint64_t fdt1) \
3563 { \
3564 uint64_t dt2; \
3565 \
3566 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3567 update_fcr31(env, GETPC()); \
3568 return dt2; \
3569 } \
3570 \
3571 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3572 uint32_t fst0, uint32_t fst1) \
3573 { \
3574 uint32_t wt2; \
3575 \
3576 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3577 update_fcr31(env, GETPC()); \
3578 return wt2; \
3579 } \
3580 \
3581 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3582 uint64_t fdt0, \
3583 uint64_t fdt1) \
3584 { \
3585 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3586 uint32_t fsth0 = fdt0 >> 32; \
3587 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3588 uint32_t fsth1 = fdt1 >> 32; \
3589 uint32_t wt2; \
3590 uint32_t wth2; \
3591 \
3592 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3593 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3594 update_fcr31(env, GETPC()); \
3595 return ((uint64_t)wth2 << 32) | wt2; \
3596 }
3597
3598 FLOAT_BINOP(add)
3599 FLOAT_BINOP(sub)
3600 FLOAT_BINOP(mul)
3601 FLOAT_BINOP(div)
3602 #undef FLOAT_BINOP
3603
3604 /* MIPS specific binary operations */
3605 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3606 {
3607 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3608 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3609 update_fcr31(env, GETPC());
3610 return fdt2;
3611 }
3612
3613 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3614 {
3615 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3616 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3617 update_fcr31(env, GETPC());
3618 return fst2;
3619 }
3620
3621 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3622 {
3623 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3624 uint32_t fsth0 = fdt0 >> 32;
3625 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3626 uint32_t fsth2 = fdt2 >> 32;
3627
3628 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3629 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3630 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3631 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3632 update_fcr31(env, GETPC());
3633 return ((uint64_t)fsth2 << 32) | fst2;
3634 }
3635
3636 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3637 {
3638 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3639 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3640 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3641 update_fcr31(env, GETPC());
3642 return fdt2;
3643 }
3644
3645 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3646 {
3647 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3648 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3649 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3650 update_fcr31(env, GETPC());
3651 return fst2;
3652 }
3653
3654 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3655 {
3656 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3657 uint32_t fsth0 = fdt0 >> 32;
3658 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3659 uint32_t fsth2 = fdt2 >> 32;
3660
3661 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3662 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3663 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3664 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3665 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3666 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3667 update_fcr31(env, GETPC());
3668 return ((uint64_t)fsth2 << 32) | fst2;
3669 }
3670
3671 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3672 {
3673 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3674 uint32_t fsth0 = fdt0 >> 32;
3675 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3676 uint32_t fsth1 = fdt1 >> 32;
3677 uint32_t fst2;
3678 uint32_t fsth2;
3679
3680 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3681 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3682 update_fcr31(env, GETPC());
3683 return ((uint64_t)fsth2 << 32) | fst2;
3684 }
3685
3686 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3687 {
3688 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3689 uint32_t fsth0 = fdt0 >> 32;
3690 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3691 uint32_t fsth1 = fdt1 >> 32;
3692 uint32_t fst2;
3693 uint32_t fsth2;
3694
3695 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3696 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3697 update_fcr31(env, GETPC());
3698 return ((uint64_t)fsth2 << 32) | fst2;
3699 }
3700
3701 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3702 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3703 uint ## bits ## _t fs, \
3704 uint ## bits ## _t ft) \
3705 { \
3706 uint ## bits ## _t fdret; \
3707 \
3708 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3709 &env->active_fpu.fp_status); \
3710 update_fcr31(env, GETPC()); \
3711 return fdret; \
3712 }
3713
3714 FLOAT_MINMAX(max_s, 32, maxnum)
3715 FLOAT_MINMAX(max_d, 64, maxnum)
3716 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3717 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3718
3719 FLOAT_MINMAX(min_s, 32, minnum)
3720 FLOAT_MINMAX(min_d, 64, minnum)
3721 FLOAT_MINMAX(mina_s, 32, minnummag)
3722 FLOAT_MINMAX(mina_d, 64, minnummag)
3723 #undef FLOAT_MINMAX
3724
3725 /* ternary operations */
3726 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3727 { \
3728 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3729 if ((flags) & float_muladd_negate_c) { \
3730 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3731 } else { \
3732 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3733 } \
3734 if ((flags) & float_muladd_negate_result) { \
3735 a = prefix##_chs(a); \
3736 } \
3737 }
3738
3739 /* FMA based operations */
3740 #define FLOAT_FMA(name, type) \
3741 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3742 uint64_t fdt0, uint64_t fdt1, \
3743 uint64_t fdt2) \
3744 { \
3745 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3746 update_fcr31(env, GETPC()); \
3747 return fdt0; \
3748 } \
3749 \
3750 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3751 uint32_t fst0, uint32_t fst1, \
3752 uint32_t fst2) \
3753 { \
3754 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3755 update_fcr31(env, GETPC()); \
3756 return fst0; \
3757 } \
3758 \
3759 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3760 uint64_t fdt0, uint64_t fdt1, \
3761 uint64_t fdt2) \
3762 { \
3763 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3764 uint32_t fsth0 = fdt0 >> 32; \
3765 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3766 uint32_t fsth1 = fdt1 >> 32; \
3767 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3768 uint32_t fsth2 = fdt2 >> 32; \
3769 \
3770 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3771 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3772 update_fcr31(env, GETPC()); \
3773 return ((uint64_t)fsth0 << 32) | fst0; \
3774 }
3775 FLOAT_FMA(madd, 0)
3776 FLOAT_FMA(msub, float_muladd_negate_c)
3777 FLOAT_FMA(nmadd, float_muladd_negate_result)
3778 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3779 #undef FLOAT_FMA
3780
3781 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3782 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3783 uint ## bits ## _t fs, \
3784 uint ## bits ## _t ft, \
3785 uint ## bits ## _t fd) \
3786 { \
3787 uint ## bits ## _t fdret; \
3788 \
3789 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3790 &env->active_fpu.fp_status); \
3791 update_fcr31(env, GETPC()); \
3792 return fdret; \
3793 }
3794
3795 FLOAT_FMADDSUB(maddf_s, 32, 0)
3796 FLOAT_FMADDSUB(maddf_d, 64, 0)
3797 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3798 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3799 #undef FLOAT_FMADDSUB
3800
3801 /* compare operations */
3802 #define FOP_COND_D(op, cond) \
3803 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3804 uint64_t fdt1, int cc) \
3805 { \
3806 int c; \
3807 c = cond; \
3808 update_fcr31(env, GETPC()); \
3809 if (c) \
3810 SET_FP_COND(cc, env->active_fpu); \
3811 else \
3812 CLEAR_FP_COND(cc, env->active_fpu); \
3813 } \
3814 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3815 uint64_t fdt1, int cc) \
3816 { \
3817 int c; \
3818 fdt0 = float64_abs(fdt0); \
3819 fdt1 = float64_abs(fdt1); \
3820 c = cond; \
3821 update_fcr31(env, GETPC()); \
3822 if (c) \
3823 SET_FP_COND(cc, env->active_fpu); \
3824 else \
3825 CLEAR_FP_COND(cc, env->active_fpu); \
3826 }
3827
3828 /* NOTE: the comma operator will make "cond" to eval to false,
3829 * but float64_unordered_quiet() is still called. */
3830 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3831 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3832 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3833 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3834 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3835 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3836 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3837 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3838 /* NOTE: the comma operator will make "cond" to eval to false,
3839 * but float64_unordered() is still called. */
3840 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3841 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3842 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3843 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3844 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3845 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3846 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3847 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3848
3849 #define FOP_COND_S(op, cond) \
3850 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3851 uint32_t fst1, int cc) \
3852 { \
3853 int c; \
3854 c = cond; \
3855 update_fcr31(env, GETPC()); \
3856 if (c) \
3857 SET_FP_COND(cc, env->active_fpu); \
3858 else \
3859 CLEAR_FP_COND(cc, env->active_fpu); \
3860 } \
3861 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3862 uint32_t fst1, int cc) \
3863 { \
3864 int c; \
3865 fst0 = float32_abs(fst0); \
3866 fst1 = float32_abs(fst1); \
3867 c = cond; \
3868 update_fcr31(env, GETPC()); \
3869 if (c) \
3870 SET_FP_COND(cc, env->active_fpu); \
3871 else \
3872 CLEAR_FP_COND(cc, env->active_fpu); \
3873 }
3874
3875 /* NOTE: the comma operator will make "cond" to eval to false,
3876 * but float32_unordered_quiet() is still called. */
3877 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3878 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3879 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3880 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3881 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3882 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3883 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3884 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3885 /* NOTE: the comma operator will make "cond" to eval to false,
3886 * but float32_unordered() is still called. */
3887 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3888 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3889 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3890 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3891 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3892 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3893 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3894 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3895
3896 #define FOP_COND_PS(op, condl, condh) \
3897 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3898 uint64_t fdt1, int cc) \
3899 { \
3900 uint32_t fst0, fsth0, fst1, fsth1; \
3901 int ch, cl; \
3902 fst0 = fdt0 & 0XFFFFFFFF; \
3903 fsth0 = fdt0 >> 32; \
3904 fst1 = fdt1 & 0XFFFFFFFF; \
3905 fsth1 = fdt1 >> 32; \
3906 cl = condl; \
3907 ch = condh; \
3908 update_fcr31(env, GETPC()); \
3909 if (cl) \
3910 SET_FP_COND(cc, env->active_fpu); \
3911 else \
3912 CLEAR_FP_COND(cc, env->active_fpu); \
3913 if (ch) \
3914 SET_FP_COND(cc + 1, env->active_fpu); \
3915 else \
3916 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3917 } \
3918 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3919 uint64_t fdt1, int cc) \
3920 { \
3921 uint32_t fst0, fsth0, fst1, fsth1; \
3922 int ch, cl; \
3923 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3924 fsth0 = float32_abs(fdt0 >> 32); \
3925 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3926 fsth1 = float32_abs(fdt1 >> 32); \
3927 cl = condl; \
3928 ch = condh; \
3929 update_fcr31(env, GETPC()); \
3930 if (cl) \
3931 SET_FP_COND(cc, env->active_fpu); \
3932 else \
3933 CLEAR_FP_COND(cc, env->active_fpu); \
3934 if (ch) \
3935 SET_FP_COND(cc + 1, env->active_fpu); \
3936 else \
3937 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3938 }
3939
3940 /* NOTE: the comma operator will make "cond" to eval to false,
3941 * but float32_unordered_quiet() is still called. */
3942 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3943 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3944 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3945 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3946 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3947 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3948 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3949 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3950 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3951 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3952 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3953 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3954 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3955 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3956 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3957 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3958 /* NOTE: the comma operator will make "cond" to eval to false,
3959 * but float32_unordered() is still called. */
3960 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3961 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3962 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3963 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3964 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3965 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3966 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3967 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3968 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3969 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3970 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3971 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3972 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3973 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3974 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3975 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3976
3977 /* R6 compare operations */
3978 #define FOP_CONDN_D(op, cond) \
3979 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3980 uint64_t fdt1) \
3981 { \
3982 uint64_t c; \
3983 c = cond; \
3984 update_fcr31(env, GETPC()); \
3985 if (c) { \
3986 return -1; \
3987 } else { \
3988 return 0; \
3989 } \
3990 }
3991
3992 /* NOTE: the comma operator will make "cond" to eval to false,
3993 * but float64_unordered_quiet() is still called. */
3994 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3995 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3996 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3997 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3998 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3999 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4000 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4001 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4002 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4003 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4004 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4005 /* NOTE: the comma operator will make "cond" to eval to false,
4006 * but float64_unordered() is still called. */
4007 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4008 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4009 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4010 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4011 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4012 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4013 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4014 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4015 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4016 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4017 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4018 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4019 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4020 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4021 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4022 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4023 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4024 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4025 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4026 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4027 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4028 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4029 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4030 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4031 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4032
4033 #define FOP_CONDN_S(op, cond) \
4034 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4035 uint32_t fst1) \
4036 { \
4037 uint64_t c; \
4038 c = cond; \
4039 update_fcr31(env, GETPC()); \
4040 if (c) { \
4041 return -1; \
4042 } else { \
4043 return 0; \
4044 } \
4045 }
4046
4047 /* NOTE: the comma operator will make "cond" to eval to false,
4048 * but float32_unordered_quiet() is still called. */
4049 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4050 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4051 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4052 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4053 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4054 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4055 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4056 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4057 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4058 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4059 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4060 /* NOTE: the comma operator will make "cond" to eval to false,
4061 * but float32_unordered() is still called. */
4062 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4063 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4064 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4065 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4066 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4067 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4068 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4069 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4070 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4071 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4072 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4073 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4074 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4075 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4076 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4077 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4078 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4079 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4080 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4081 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4082 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4083 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4084 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4085 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4086 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4087
4088 /* MSA */
4089 /* Data format min and max values */
4090 #define DF_BITS(df) (1 << ((df) + 3))
4091
4092 /* Element-by-element access macros */
4093 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4094
4095 #if !defined(CONFIG_USER_ONLY)
4096 #define MEMOP_IDX(DF) \
4097 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4098 cpu_mmu_index(env, false));
4099 #else
4100 #define MEMOP_IDX(DF)
4101 #endif
4102
4103 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4104 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4105 target_ulong addr) \
4106 { \
4107 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4108 wr_t wx; \
4109 int i; \
4110 MEMOP_IDX(DF) \
4111 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4112 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4113 } \
4114 memcpy(pwd, &wx, sizeof(wr_t)); \
4115 }
4116
4117 #if !defined(CONFIG_USER_ONLY)
4118 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
4119 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
4120 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
4121 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
4122 #else
4123 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
4124 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
4125 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
4126 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4127 #endif
4128
4129 #define MSA_PAGESPAN(x) \
4130 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4131
4132 static inline void ensure_writable_pages(CPUMIPSState *env,
4133 target_ulong addr,
4134 int mmu_idx,
4135 uintptr_t retaddr)
4136 {
4137 #if !defined(CONFIG_USER_ONLY)
4138 target_ulong page_addr;
4139 if (unlikely(MSA_PAGESPAN(addr))) {
4140 /* first page */
4141 probe_write(env, addr, mmu_idx, retaddr);
4142 /* second page */
4143 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4144 probe_write(env, page_addr, mmu_idx, retaddr);
4145 }
4146 #endif
4147 }
4148
4149 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4150 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4151 target_ulong addr) \
4152 { \
4153 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4154 int mmu_idx = cpu_mmu_index(env, false); \
4155 int i; \
4156 MEMOP_IDX(DF) \
4157 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4158 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4159 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4160 } \
4161 }
4162
4163 #if !defined(CONFIG_USER_ONLY)
4164 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
4165 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
4166 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
4167 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
4168 #else
4169 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
4170 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
4171 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
4172 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4173 #endif
4174
4175 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4176 {
4177 #ifndef CONFIG_USER_ONLY
4178 target_ulong index = addr & 0x1fffffff;
4179 if (op == 9) {
4180 /* Index Store Tag */
4181 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4182 8, MEMTXATTRS_UNSPECIFIED);
4183 } else if (op == 5) {
4184 /* Index Load Tag */
4185 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4186 8, MEMTXATTRS_UNSPECIFIED);
4187 }
4188 #endif
4189 }
AR7 emulation for QEMU