hw/ppc/pnv_core.c

   1 /*
   2  * QEMU PowerPC PowerNV CPU Core model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "sysemu/sysemu.h"
  21 #include "qapi/error.h"
  22 #include "qemu/log.h"
  23 #include "target/ppc/cpu.h"
  24 #include "hw/ppc/ppc.h"
  25 #include "hw/ppc/pnv.h"
  26 #include "hw/ppc/pnv_core.h"
  27 #include "hw/ppc/pnv_xscom.h"
  28 #include "hw/ppc/xics.h"
  29
  30 static void powernv_cpu_reset(void *opaque)
  31 {
  32     PowerPCCPU *cpu = opaque;
  33     CPUState *cs = CPU(cpu);
  34     CPUPPCState *env = &cpu->env;
  35
  36     cpu_reset(cs);
  37
  38     /*
  39      * the skiboot firmware elects a primary thread to initialize the
  40      * system and it can be any.
  41      */
  42     env->gpr[3] = PNV_FDT_ADDR;
  43     env->nip = 0x10;
  44     env->msr |= MSR_HVB; /* Hypervisor mode */
  45 }
  46
  47 static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
  48 {
  49     CPUPPCState *env = &cpu->env;
  50     int core_pir;
  51     int thread_index = 0; /* TODO: TCG supports only one thread */
  52     ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
  53
  54     core_pir = object_property_get_int(OBJECT(cpu), "core-pir", &error_abort);
  55
  56     /*
  57      * The PIR of a thread is the core PIR + the thread index. We will
  58      * need to find a way to get the thread index when TCG supports
  59      * more than 1. We could use the object name ?
  60      */
  61     pir->default_value = core_pir + thread_index;
  62
  63     /* Set time-base frequency to 512 MHz */
  64     cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
  65
  66     qemu_register_reset(powernv_cpu_reset, cpu);
  67 }
  68
  69 /*
  70  * These values are read by the PowerNV HW monitors under Linux
  71  */
  72 #define PNV_XSCOM_EX_DTS_RESULT0     0x50000
  73 #define PNV_XSCOM_EX_DTS_RESULT1     0x50001
  74
  75 static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
  76                                     unsigned int width)
  77 {
  78     uint32_t offset = addr >> 3;
  79     uint64_t val = 0;
  80
  81     /* The result should be 38 C */
  82     switch (offset) {
  83     case PNV_XSCOM_EX_DTS_RESULT0:
  84         val = 0x26f024f023f0000ull;
  85         break;
  86     case PNV_XSCOM_EX_DTS_RESULT1:
  87         val = 0x24f000000000000ull;
  88         break;
  89     default:
  90         qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
  91                   addr);
  92     }
  93
  94     return val;
  95 }
  96
  97 static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
  98                                  unsigned int width)
  99 {
 100     qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
 101                   addr);
 102 }
 103
 104 static const MemoryRegionOps pnv_core_xscom_ops = {
 105     .read = pnv_core_xscom_read,
 106     .write = pnv_core_xscom_write,
 107     .valid.min_access_size = 8,
 108     .valid.max_access_size = 8,
 109     .impl.min_access_size = 8,
 110     .impl.max_access_size = 8,
 111     .endianness = DEVICE_BIG_ENDIAN,
 112 };
 113
 114 static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
 115 {
 116     Error *local_err = NULL;
 117     CPUState *cs = CPU(child);
 118     PowerPCCPU *cpu = POWERPC_CPU(cs);
 119     Object *obj;
 120
 121     object_property_set_bool(child, true, "realized", &local_err);
 122     if (local_err) {
 123         error_propagate(errp, local_err);
 124         return;
 125     }
 126
 127     obj = object_new(TYPE_PNV_ICP);
 128     object_property_add_child(child, "icp", obj, NULL);
 129     object_unref(obj);
 130     object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
 131                                    &error_abort);
 132     object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort);
 133     object_property_set_bool(obj, true, "realized", &local_err);
 134     if (local_err) {
 135         error_propagate(errp, local_err);
 136         return;
 137     }
 138
 139     powernv_cpu_init(cpu, &local_err);
 140     if (local_err) {
 141         object_unparent(obj);
 142         error_propagate(errp, local_err);
 143         return;
 144     }
 145 }
 146
 147 static void pnv_core_realize(DeviceState *dev, Error **errp)
 148 {
 149     PnvCore *pc = PNV_CORE(OBJECT(dev));
 150     CPUCore *cc = CPU_CORE(OBJECT(dev));
 151     PnvCoreClass *pcc = PNV_CORE_GET_CLASS(OBJECT(dev));
 152     const char *typename = object_class_get_name(pcc->cpu_oc);
 153     size_t size = object_type_get_instance_size(typename);
 154     Error *local_err = NULL;
 155     void *obj;
 156     int i, j;
 157     char name[32];
 158     Object *xi;
 159
 160     xi = object_property_get_link(OBJECT(dev), "xics", &local_err);
 161     if (!xi) {
 162         error_setg(errp, "%s: required link 'xics' not found: %s",
 163                    __func__, error_get_pretty(local_err));
 164         return;
 165     }
 166
 167     pc->threads = g_malloc0(size * cc->nr_threads);
 168     for (i = 0; i < cc->nr_threads; i++) {
 169         obj = pc->threads + i * size;
 170
 171         object_initialize(obj, size, typename);
 172
 173         snprintf(name, sizeof(name), "thread[%d]", i);
 174         object_property_add_child(OBJECT(pc), name, obj, &local_err);
 175         object_property_add_alias(obj, "core-pir", OBJECT(pc),
 176                                   "pir", &local_err);
 177         if (local_err) {
 178             goto err;
 179         }
 180         object_unref(obj);
 181     }
 182
 183     for (j = 0; j < cc->nr_threads; j++) {
 184         obj = pc->threads + j * size;
 185
 186         pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
 187         if (local_err) {
 188             goto err;
 189         }
 190     }
 191
 192     snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
 193     pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
 194                           pc, name, PNV_XSCOM_EX_CORE_SIZE);
 195     return;
 196
 197 err:
 198     while (--i >= 0) {
 199         obj = pc->threads + i * size;
 200         object_unparent(obj);
 201     }
 202     g_free(pc->threads);
 203     error_propagate(errp, local_err);
 204 }
 205
 206 static Property pnv_core_properties[] = {
 207     DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
 208     DEFINE_PROP_END_OF_LIST(),
 209 };
 210
 211 static void pnv_core_class_init(ObjectClass *oc, void *data)
 212 {
 213     DeviceClass *dc = DEVICE_CLASS(oc);
 214     PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
 215
 216     dc->realize = pnv_core_realize;
 217     dc->props = pnv_core_properties;
 218     pcc->cpu_oc = cpu_class_by_name(TYPE_POWERPC_CPU, data);
 219 }
 220
 221 static const TypeInfo pnv_core_info = {
 222     .name           = TYPE_PNV_CORE,
 223     .parent         = TYPE_CPU_CORE,
 224     .instance_size  = sizeof(PnvCore),
 225     .class_size     = sizeof(PnvCoreClass),
 226     .abstract       = true,
 227 };
 228
 229 static const char *pnv_core_models[] = {
 230     "POWER8E", "POWER8", "POWER8NVL", "POWER9"
 231 };
 232
 233 static void pnv_core_register_types(void)
 234 {
 235     int i ;
 236
 237     type_register_static(&pnv_core_info);
 238     for (i = 0; i < ARRAY_SIZE(pnv_core_models); ++i) {
 239         TypeInfo ti = {
 240             .parent = TYPE_PNV_CORE,
 241             .instance_size = sizeof(PnvCore),
 242             .class_init = pnv_core_class_init,
 243             .class_data = (void *) pnv_core_models[i],
 244         };
 245         ti.name = pnv_core_typename(pnv_core_models[i]);
 246         type_register(&ti);
 247         g_free((void *)ti.name);
 248     }
 249 }
 250
 251 type_init(pnv_core_register_types)
 252
 253 char *pnv_core_typename(const char *model)
 254 {
 255     return g_strdup_printf(TYPE_PNV_CORE "-%s", model);
 256 }