2 * IMX25 Clock Control Module
4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
10 * To get the timer frequencies right, we need to emulate at least part of
14 #include "qemu/osdep.h"
15 #include "hw/misc/imx25_ccm.h"
18 #ifndef DEBUG_IMX25_CCM
19 #define DEBUG_IMX25_CCM 0
22 #define DPRINTF(fmt, args...) \
24 if (DEBUG_IMX25_CCM) { \
25 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX25_CCM, \
30 static const char *imx25_ccm_reg_name(uint32_t reg
)
32 static char unknown
[20];
35 case IMX25_CCM_MPCTL_REG
:
37 case IMX25_CCM_UPCTL_REG
:
39 case IMX25_CCM_CCTL_REG
:
41 case IMX25_CCM_CGCR0_REG
:
43 case IMX25_CCM_CGCR1_REG
:
45 case IMX25_CCM_CGCR2_REG
:
47 case IMX25_CCM_PCDR0_REG
:
49 case IMX25_CCM_PCDR1_REG
:
51 case IMX25_CCM_PCDR2_REG
:
53 case IMX25_CCM_PCDR3_REG
:
55 case IMX25_CCM_RCSR_REG
:
57 case IMX25_CCM_CRDR_REG
:
59 case IMX25_CCM_DCVR0_REG
:
61 case IMX25_CCM_DCVR1_REG
:
63 case IMX25_CCM_DCVR2_REG
:
65 case IMX25_CCM_DCVR3_REG
:
67 case IMX25_CCM_LTR0_REG
:
69 case IMX25_CCM_LTR1_REG
:
71 case IMX25_CCM_LTR2_REG
:
73 case IMX25_CCM_LTR3_REG
:
75 case IMX25_CCM_LTBR0_REG
:
77 case IMX25_CCM_LTBR1_REG
:
79 case IMX25_CCM_PMCR0_REG
:
81 case IMX25_CCM_PMCR1_REG
:
83 case IMX25_CCM_PMCR2_REG
:
85 case IMX25_CCM_MCR_REG
:
87 case IMX25_CCM_LPIMR0_REG
:
89 case IMX25_CCM_LPIMR1_REG
:
92 sprintf(unknown
, "[%d ?]", reg
);
96 #define CKIH_FREQ 24000000 /* 24MHz crystal input */
98 static const VMStateDescription vmstate_imx25_ccm
= {
99 .name
= TYPE_IMX25_CCM
,
101 .minimum_version_id
= 1,
102 .fields
= (VMStateField
[]) {
103 VMSTATE_UINT32_ARRAY(reg
, IMX25CCMState
, IMX25_CCM_MAX_REG
),
104 VMSTATE_END_OF_LIST()
108 static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState
*dev
)
111 IMX25CCMState
*s
= IMX25_CCM(dev
);
113 if (EXTRACT(s
->reg
[IMX25_CCM_CCTL_REG
], MPLL_BYPASS
)) {
116 freq
= imx_ccm_calc_pll(s
->reg
[IMX25_CCM_MPCTL_REG
], CKIH_FREQ
);
119 DPRINTF("freq = %d\n", freq
);
124 static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState
*dev
)
127 IMX25CCMState
*s
= IMX25_CCM(dev
);
129 freq
= imx25_ccm_get_mpll_clk(dev
);
131 if (EXTRACT(s
->reg
[IMX25_CCM_CCTL_REG
], ARM_SRC
)) {
132 freq
= (freq
* 3 / 4);
135 freq
= freq
/ (1 + EXTRACT(s
->reg
[IMX25_CCM_CCTL_REG
], ARM_CLK_DIV
));
137 DPRINTF("freq = %d\n", freq
);
142 static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState
*dev
)
145 IMX25CCMState
*s
= IMX25_CCM(dev
);
147 freq
= imx25_ccm_get_mcu_clk(dev
)
148 / (1 + EXTRACT(s
->reg
[IMX25_CCM_CCTL_REG
], AHB_CLK_DIV
));
150 DPRINTF("freq = %d\n", freq
);
155 static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState
*dev
)
159 freq
= imx25_ccm_get_ahb_clk(dev
) / 2;
161 DPRINTF("freq = %d\n", freq
);
166 static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState
*dev
, IMXClk clock
)
169 DPRINTF("Clock = %d)\n", clock
);
176 freq
= imx25_ccm_get_ipg_clk(dev
);
182 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: unsupported clock %d\n",
183 TYPE_IMX25_CCM
, __func__
, clock
);
187 DPRINTF("Clock = %d) = %d\n", clock
, freq
);
192 static void imx25_ccm_reset(DeviceState
*dev
)
194 IMX25CCMState
*s
= IMX25_CCM(dev
);
198 memset(s
->reg
, 0, IMX25_CCM_MAX_REG
* sizeof(uint32_t));
199 s
->reg
[IMX25_CCM_MPCTL_REG
] = 0x800b2c01;
200 s
->reg
[IMX25_CCM_UPCTL_REG
] = 0x84042800;
202 * The value below gives:
203 * CPU = 133 MHz, AHB = 66,5 MHz, IPG = 33 MHz.
205 s
->reg
[IMX25_CCM_CCTL_REG
] = 0xd0030000;
206 s
->reg
[IMX25_CCM_CGCR0_REG
] = 0x028A0100;
207 s
->reg
[IMX25_CCM_CGCR1_REG
] = 0x04008100;
208 s
->reg
[IMX25_CCM_CGCR2_REG
] = 0x00000438;
209 s
->reg
[IMX25_CCM_PCDR0_REG
] = 0x01010101;
210 s
->reg
[IMX25_CCM_PCDR1_REG
] = 0x01010101;
211 s
->reg
[IMX25_CCM_PCDR2_REG
] = 0x01010101;
212 s
->reg
[IMX25_CCM_PCDR3_REG
] = 0x01010101;
213 s
->reg
[IMX25_CCM_PMCR0_REG
] = 0x00A00000;
214 s
->reg
[IMX25_CCM_PMCR1_REG
] = 0x0000A030;
215 s
->reg
[IMX25_CCM_PMCR2_REG
] = 0x0000A030;
216 s
->reg
[IMX25_CCM_MCR_REG
] = 0x43000000;
219 * default boot will change the reset values to allow:
220 * CPU = 399 MHz, AHB = 133 MHz, IPG = 66,5 MHz.
221 * For some reason, this doesn't work. With the value below, linux
222 * detects a 88 MHz IPG CLK instead of 66,5 MHz.
223 s->reg[IMX25_CCM_CCTL_REG] = 0x20032000;
227 static uint64_t imx25_ccm_read(void *opaque
, hwaddr offset
, unsigned size
)
230 IMX25CCMState
*s
= (IMX25CCMState
*)opaque
;
233 value
= s
->reg
[offset
>> 2];
235 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
236 HWADDR_PRIx
"\n", TYPE_IMX25_CCM
, __func__
, offset
);
239 DPRINTF("reg[%s] => 0x%" PRIx32
"\n", imx25_ccm_reg_name(offset
>> 2),
245 static void imx25_ccm_write(void *opaque
, hwaddr offset
, uint64_t value
,
248 IMX25CCMState
*s
= (IMX25CCMState
*)opaque
;
250 DPRINTF("reg[%s] <= 0x%" PRIx32
"\n", imx25_ccm_reg_name(offset
>> 2),
255 * We will do a better implementation later. In particular some bits
256 * cannot be written to.
258 s
->reg
[offset
>> 2] = value
;
260 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
261 HWADDR_PRIx
"\n", TYPE_IMX25_CCM
, __func__
, offset
);
265 static const struct MemoryRegionOps imx25_ccm_ops
= {
266 .read
= imx25_ccm_read
,
267 .write
= imx25_ccm_write
,
268 .endianness
= DEVICE_NATIVE_ENDIAN
,
271 * Our device would not work correctly if the guest was doing
272 * unaligned access. This might not be a limitation on the real
273 * device but in practice there is no reason for a guest to access
274 * this device unaligned.
276 .min_access_size
= 4,
277 .max_access_size
= 4,
282 static void imx25_ccm_init(Object
*obj
)
284 DeviceState
*dev
= DEVICE(obj
);
285 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
286 IMX25CCMState
*s
= IMX25_CCM(obj
);
288 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &imx25_ccm_ops
, s
,
289 TYPE_IMX25_CCM
, 0x1000);
290 sysbus_init_mmio(sd
, &s
->iomem
);
293 static void imx25_ccm_class_init(ObjectClass
*klass
, void *data
)
295 DeviceClass
*dc
= DEVICE_CLASS(klass
);
296 IMXCCMClass
*ccm
= IMX_CCM_CLASS(klass
);
298 dc
->reset
= imx25_ccm_reset
;
299 dc
->vmsd
= &vmstate_imx25_ccm
;
300 dc
->desc
= "i.MX25 Clock Control Module";
302 ccm
->get_clock_frequency
= imx25_ccm_get_clock_frequency
;
305 static const TypeInfo imx25_ccm_info
= {
306 .name
= TYPE_IMX25_CCM
,
307 .parent
= TYPE_IMX_CCM
,
308 .instance_size
= sizeof(IMX25CCMState
),
309 .instance_init
= imx25_ccm_init
,
310 .class_init
= imx25_ccm_class_init
,
313 static void imx25_ccm_register_types(void)
315 type_register_static(&imx25_ccm_info
);
318 type_init(imx25_ccm_register_types
)