hw/sd/milkymist-memcard.c

   1 /*
   2  *  QEMU model of the Milkymist SD Card Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.milkymist.org/socdoc/memcard.pdf
  22  */
  23
  24 #include "hw/hw.h"
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "trace.h"
  28 #include "qemu/error-report.h"
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/blockdev.h"
  31 #include "hw/sd.h"
  32
  33 enum {
  34     ENABLE_CMD_TX   = (1<<0),
  35     ENABLE_CMD_RX   = (1<<1),
  36     ENABLE_DAT_TX   = (1<<2),
  37     ENABLE_DAT_RX   = (1<<3),
  38 };
  39
  40 enum {
  41     PENDING_CMD_TX   = (1<<0),
  42     PENDING_CMD_RX   = (1<<1),
  43     PENDING_DAT_TX   = (1<<2),
  44     PENDING_DAT_RX   = (1<<3),
  45 };
  46
  47 enum {
  48     START_CMD_TX    = (1<<0),
  49     START_DAT_RX    = (1<<1),
  50 };
  51
  52 enum {
  53     R_CLK2XDIV = 0,
  54     R_ENABLE,
  55     R_PENDING,
  56     R_START,
  57     R_CMD,
  58     R_DAT,
  59     R_MAX
  60 };
  61
  62 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
  63 #define MILKYMIST_MEMCARD(obj) \
  64     OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
  65
  66 struct MilkymistMemcardState {
  67     SysBusDevice parent_obj;
  68
  69     MemoryRegion regs_region;
  70     SDState *card;
  71
  72     int command_write_ptr;
  73     int response_read_ptr;
  74     int response_len;
  75     int ignore_next_cmd;
  76     int enabled;
  77     uint8_t command[6];
  78     uint8_t response[17];
  79     uint32_t regs[R_MAX];
  80 };
  81 typedef struct MilkymistMemcardState MilkymistMemcardState;
  82
  83 static void update_pending_bits(MilkymistMemcardState *s)
  84 {
  85     /* transmits are instantaneous, thus tx pending bits are never set */
  86     s->regs[R_PENDING] = 0;
  87     /* if rx is enabled the corresponding pending bits are always set */
  88     if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
  89         s->regs[R_PENDING] |= PENDING_CMD_RX;
  90     }
  91     if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
  92         s->regs[R_PENDING] |= PENDING_DAT_RX;
  93     }
  94 }
  95
  96 static void memcard_sd_command(MilkymistMemcardState *s)
  97 {
  98     SDRequest req;
  99
 100     req.cmd = s->command[0] & 0x3f;
 101     req.arg = (s->command[1] << 24) | (s->command[2] << 16)
 102               | (s->command[3] << 8) | s->command[4];
 103     req.crc = s->command[5];
 104
 105     s->response[0] = req.cmd;
 106     s->response_len = sd_do_command(s->card, &req, s->response+1);
 107     s->response_read_ptr = 0;
 108
 109     if (s->response_len == 16) {
 110         /* R2 response */
 111         s->response[0] = 0x3f;
 112         s->response_len += 1;
 113     } else if (s->response_len == 4) {
 114         /* no crc calculation, insert dummy byte */
 115         s->response[5] = 0;
 116         s->response_len += 2;
 117     }
 118
 119     if (req.cmd == 0) {
 120         /* next write is a dummy byte to clock the initialization of the sd
 121          * card */
 122         s->ignore_next_cmd = 1;
 123     }
 124 }
 125
 126 static uint64_t memcard_read(void *opaque, hwaddr addr,
 127                              unsigned size)
 128 {
 129     MilkymistMemcardState *s = opaque;
 130     uint32_t r = 0;
 131
 132     addr >>= 2;
 133     switch (addr) {
 134     case R_CMD:
 135         if (!s->enabled) {
 136             r = 0xff;
 137         } else {
 138             r = s->response[s->response_read_ptr++];
 139             if (s->response_read_ptr > s->response_len) {
 140                 error_report("milkymist_memcard: "
 141                         "read more cmd bytes than available. Clipping.");
 142                 s->response_read_ptr = 0;
 143             }
 144         }
 145         break;
 146     case R_DAT:
 147         if (!s->enabled) {
 148             r = 0xffffffff;
 149         } else {
 150             r = 0;
 151             r |= sd_read_data(s->card) << 24;
 152             r |= sd_read_data(s->card) << 16;
 153             r |= sd_read_data(s->card) << 8;
 154             r |= sd_read_data(s->card);
 155         }
 156         break;
 157     case R_CLK2XDIV:
 158     case R_ENABLE:
 159     case R_PENDING:
 160     case R_START:
 161         r = s->regs[addr];
 162         break;
 163
 164     default:
 165         error_report("milkymist_memcard: read access to unknown register 0x"
 166                 TARGET_FMT_plx, addr << 2);
 167         break;
 168     }
 169
 170     trace_milkymist_memcard_memory_read(addr << 2, r);
 171
 172     return r;
 173 }
 174
 175 static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
 176                           unsigned size)
 177 {
 178     MilkymistMemcardState *s = opaque;
 179
 180     trace_milkymist_memcard_memory_write(addr, value);
 181
 182     addr >>= 2;
 183     switch (addr) {
 184     case R_PENDING:
 185         /* clear rx pending bits */
 186         s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
 187         update_pending_bits(s);
 188         break;
 189     case R_CMD:
 190         if (!s->enabled) {
 191             break;
 192         }
 193         if (s->ignore_next_cmd) {
 194             s->ignore_next_cmd = 0;
 195             break;
 196         }
 197         s->command[s->command_write_ptr] = value & 0xff;
 198         s->command_write_ptr = (s->command_write_ptr + 1) % 6;
 199         if (s->command_write_ptr == 0) {
 200             memcard_sd_command(s);
 201         }
 202         break;
 203     case R_DAT:
 204         if (!s->enabled) {
 205             break;
 206         }
 207         sd_write_data(s->card, (value >> 24) & 0xff);
 208         sd_write_data(s->card, (value >> 16) & 0xff);
 209         sd_write_data(s->card, (value >> 8) & 0xff);
 210         sd_write_data(s->card, value & 0xff);
 211         break;
 212     case R_ENABLE:
 213         s->regs[addr] = value;
 214         update_pending_bits(s);
 215         break;
 216     case R_CLK2XDIV:
 217     case R_START:
 218         s->regs[addr] = value;
 219         break;
 220
 221     default:
 222         error_report("milkymist_memcard: write access to unknown register 0x"
 223                 TARGET_FMT_plx, addr << 2);
 224         break;
 225     }
 226 }
 227
 228 static const MemoryRegionOps memcard_mmio_ops = {
 229     .read = memcard_read,
 230     .write = memcard_write,
 231     .valid = {
 232         .min_access_size = 4,
 233         .max_access_size = 4,
 234     },
 235     .endianness = DEVICE_NATIVE_ENDIAN,
 236 };
 237
 238 static void milkymist_memcard_reset(DeviceState *d)
 239 {
 240     MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
 241     int i;
 242
 243     s->command_write_ptr = 0;
 244     s->response_read_ptr = 0;
 245     s->response_len = 0;
 246
 247     for (i = 0; i < R_MAX; i++) {
 248         s->regs[i] = 0;
 249     }
 250 }
 251
 252 static int milkymist_memcard_init(SysBusDevice *dev)
 253 {
 254     MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
 255     DriveInfo *dinfo;
 256     BlockBackend *blk;
 257
 258     dinfo = drive_get_next(IF_SD);
 259     blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
 260     s->card = sd_init(blk, false);
 261     if (s->card == NULL) {
 262         return -1;
 263     }
 264
 265     s->enabled = blk && blk_is_inserted(blk);
 266
 267     memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
 268             "milkymist-memcard", R_MAX * 4);
 269     sysbus_init_mmio(dev, &s->regs_region);
 270
 271     return 0;
 272 }
 273
 274 static const VMStateDescription vmstate_milkymist_memcard = {
 275     .name = "milkymist-memcard",
 276     .version_id = 1,
 277     .minimum_version_id = 1,
 278     .fields = (VMStateField[]) {
 279         VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
 280         VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
 281         VMSTATE_INT32(response_len, MilkymistMemcardState),
 282         VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
 283         VMSTATE_INT32(enabled, MilkymistMemcardState),
 284         VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
 285         VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
 286         VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
 287         VMSTATE_END_OF_LIST()
 288     }
 289 };
 290
 291 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
 292 {
 293     DeviceClass *dc = DEVICE_CLASS(klass);
 294     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 295
 296     k->init = milkymist_memcard_init;
 297     dc->reset = milkymist_memcard_reset;
 298     dc->vmsd = &vmstate_milkymist_memcard;
 299 }
 300
 301 static const TypeInfo milkymist_memcard_info = {
 302     .name          = TYPE_MILKYMIST_MEMCARD,
 303     .parent        = TYPE_SYS_BUS_DEVICE,
 304     .instance_size = sizeof(MilkymistMemcardState),
 305     .class_init    = milkymist_memcard_class_init,
 306 };
 307
 308 static void milkymist_memcard_register_types(void)
 309 {
 310     type_register_static(&milkymist_memcard_info);
 311 }
 312
 313 type_init(milkymist_memcard_register_types)