include/hw/riscv/numa.h

   1 /*
   2  * QEMU RISC-V NUMA Helper
   3  *
   4  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef RISCV_NUMA_H
  20 #define RISCV_NUMA_H
  21
  22 #include "hw/sysbus.h"
  23 #include "sysemu/numa.h"
  24
  25 /**
  26  * riscv_socket_count:
  27  * @ms: pointer to machine state
  28  *
  29  * Returns: number of sockets for a numa system and 1 for a non-numa system
  30  */
  31 int riscv_socket_count(const MachineState *ms);
  32
  33 /**
  34  * riscv_socket_first_hartid:
  35  * @ms: pointer to machine state
  36  * @socket_id: socket index
  37  *
  38  * Returns: first hartid for a valid socket and -1 for an invalid socket
  39  */
  40 int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
  41
  42 /**
  43  * riscv_socket_last_hartid:
  44  * @ms: pointer to machine state
  45  * @socket_id: socket index
  46  *
  47  * Returns: last hartid for a valid socket and -1 for an invalid socket
  48  */
  49 int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
  50
  51 /**
  52  * riscv_socket_hart_count:
  53  * @ms: pointer to machine state
  54  * @socket_id: socket index
  55  *
  56  * Returns: number of harts for a valid socket and -1 for an invalid socket
  57  */
  58 int riscv_socket_hart_count(const MachineState *ms, int socket_id);
  59
  60 /**
  61  * riscv_socket_mem_offset:
  62  * @ms: pointer to machine state
  63  * @socket_id: socket index
  64  *
  65  * Returns: offset of ram belonging to given socket
  66  */
  67 uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
  68
  69 /**
  70  * riscv_socket_mem_size:
  71  * @ms: pointer to machine state
  72  * @socket_id: socket index
  73  *
  74  * Returns: size of ram belonging to given socket
  75  */
  76 uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
  77
  78 /**
  79  * riscv_socket_check_hartids:
  80  * @ms: pointer to machine state
  81  * @socket_id: socket index
  82  *
  83  * Returns: true if hardids belonging to given socket are contiguous else false
  84  */
  85 bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
  86
  87 /**
  88  * riscv_socket_fdt_write_id:
  89  * @ms: pointer to machine state
  90  * @socket_id: socket index
  91  *
  92  * Write NUMA node-id FDT property for given FDT node
  93  */
  94 void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
  95                                const char *node_name, int socket_id);
  96
  97 /**
  98  * riscv_socket_fdt_write_distance_matrix:
  99  * @ms: pointer to machine state
 100  * @socket_id: socket index
 101  *
 102  * Write NUMA distance matrix in FDT for given machine
 103  */
 104 void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
 105
 106 CpuInstanceProperties
 107 riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
 108
 109 int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
 110
 111 const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
 112
 113 #endif /* RISCV_NUMA_H */