2 * ARM MPS2 AN505 FPGAIO emulation
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* This is a model of the "FPGA system control and I/O" block found
13 * in the AN505 FPGA image for the MPS2 devboard.
14 * It is documented in AN505:
15 * https://developer.arm.com/documentation/dai0505/latest/
18 #include "qemu/osdep.h"
20 #include "qemu/module.h"
21 #include "qapi/error.h"
23 #include "hw/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "hw/registerfields.h"
26 #include "hw/misc/mps2-fpgaio.h"
27 #include "hw/misc/led.h"
28 #include "hw/qdev-properties.h"
29 #include "qemu/timer.h"
41 static uint32_t counter_from_tickoff(int64_t now
, int64_t tick_offset
, int frq
)
43 return muldiv64(now
- tick_offset
, frq
, NANOSECONDS_PER_SECOND
);
46 static int64_t tickoff_from_counter(int64_t now
, uint32_t count
, int frq
)
48 return now
- muldiv64(count
, NANOSECONDS_PER_SECOND
, frq
);
51 static void resync_counter(MPS2FPGAIO
*s
)
54 * Update s->counter and s->pscntr to their true current values
55 * by calculating how many times PSCNTR has ticked since the
56 * last time we did a resync.
58 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
59 int64_t elapsed
= now
- s
->pscntr_sync_ticks
;
62 * Round elapsed down to a whole number of PSCNTR ticks, so we don't
63 * lose time if we do multiple resyncs in a single tick.
65 uint64_t ticks
= muldiv64(elapsed
, s
->prescale_clk
, NANOSECONDS_PER_SECOND
);
68 * Work out what PSCNTR and COUNTER have moved to. We assume that
69 * PSCNTR reloads from PRESCALE one tick-period after it hits zero,
70 * and that COUNTER increments at the same moment.
73 /* We haven't ticked since the last time we were asked */
75 } else if (ticks
< s
->pscntr
) {
76 /* We haven't yet reached zero, just reduce the PSCNTR */
79 if (s
->prescale
== 0) {
81 * If the reload value is zero then the PSCNTR will stick
82 * at zero once it reaches it, and so we will increment
83 * COUNTER every tick after that.
85 s
->counter
+= ticks
- s
->pscntr
;
89 * This is the complicated bit. This ASCII art diagram gives an
90 * example with PRESCALE==5 PSCNTR==7:
92 * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
93 * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5
95 * y 0 1 2 3 4 5 6 7 8 9 10 11 12
96 * x 0 1 2 3 4 5 0 1 2 3 4 5 0
98 * where x = y % (s->prescale + 1)
99 * and so PSCNTR = s->prescale - x
100 * and COUNTER is incremented by y / (s->prescale + 1)
102 * The case where PSCNTR < PRESCALE works out the same,
103 * though we must be careful to calculate y as 64-bit unsigned
104 * for all parts of the expression.
105 * y < 0 is not possible because that implies ticks < s->pscntr.
107 uint64_t y
= ticks
- s
->pscntr
+ s
->prescale
;
108 s
->pscntr
= s
->prescale
- (y
% (s
->prescale
+ 1));
109 s
->counter
+= y
/ (s
->prescale
+ 1);
114 * Only advance the sync time to the timestamp of the last PSCNTR tick,
115 * not all the way to 'now', so we don't lose time if we do multiple
116 * resyncs in a single tick.
118 s
->pscntr_sync_ticks
+= muldiv64(ticks
, NANOSECONDS_PER_SECOND
,
122 static uint64_t mps2_fpgaio_read(void *opaque
, hwaddr offset
, unsigned size
)
124 MPS2FPGAIO
*s
= MPS2_FPGAIO(opaque
);
133 /* User-pressable board buttons. We don't model that, so just return
145 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
146 r
= counter_from_tickoff(now
, s
->clk1hz_tick_offset
, 1);
149 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
150 r
= counter_from_tickoff(now
, s
->clk100hz_tick_offset
, 100);
161 if (!s
->has_switches
) {
164 /* User-togglable board switches. We don't model that, so report 0. */
169 qemu_log_mask(LOG_GUEST_ERROR
,
170 "MPS2 FPGAIO read: bad offset %x\n", (int) offset
);
175 trace_mps2_fpgaio_read(offset
, r
, size
);
179 static void mps2_fpgaio_write(void *opaque
, hwaddr offset
, uint64_t value
,
182 MPS2FPGAIO
*s
= MPS2_FPGAIO(opaque
);
185 trace_mps2_fpgaio_write(offset
, value
, size
);
189 if (s
->num_leds
!= 0) {
192 s
->led0
= value
& MAKE_64BIT_MASK(0, s
->num_leds
);
193 for (i
= 0; i
< s
->num_leds
; i
++) {
194 led_set_state(s
->led
[i
], value
& (1 << i
));
203 /* These are control bits for some of the other devices on the
204 * board (SPI, CLCD, etc). We don't implement that yet, so just
205 * make the bits read as written.
207 qemu_log_mask(LOG_UNIMP
,
208 "MPS2 FPGAIO: MISC control bits unimplemented\n");
212 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
213 s
->clk1hz_tick_offset
= tickoff_from_counter(now
, value
, 1);
216 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
217 s
->clk100hz_tick_offset
= tickoff_from_counter(now
, value
, 100);
228 qemu_log_mask(LOG_GUEST_ERROR
,
229 "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset
);
234 static const MemoryRegionOps mps2_fpgaio_ops
= {
235 .read
= mps2_fpgaio_read
,
236 .write
= mps2_fpgaio_write
,
237 .endianness
= DEVICE_LITTLE_ENDIAN
,
240 static void mps2_fpgaio_reset(DeviceState
*dev
)
242 MPS2FPGAIO
*s
= MPS2_FPGAIO(dev
);
243 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
245 trace_mps2_fpgaio_reset();
249 s
->clk1hz_tick_offset
= tickoff_from_counter(now
, 0, 1);
250 s
->clk100hz_tick_offset
= tickoff_from_counter(now
, 0, 100);
253 s
->pscntr_sync_ticks
= now
;
255 for (size_t i
= 0; i
< s
->num_leds
; i
++) {
256 device_cold_reset(DEVICE(s
->led
[i
]));
260 static void mps2_fpgaio_init(Object
*obj
)
262 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
263 MPS2FPGAIO
*s
= MPS2_FPGAIO(obj
);
265 memory_region_init_io(&s
->iomem
, obj
, &mps2_fpgaio_ops
, s
,
266 "mps2-fpgaio", 0x1000);
267 sysbus_init_mmio(sbd
, &s
->iomem
);
270 static void mps2_fpgaio_realize(DeviceState
*dev
, Error
**errp
)
272 MPS2FPGAIO
*s
= MPS2_FPGAIO(dev
);
275 if (s
->num_leds
> MPS2FPGAIO_MAX_LEDS
) {
276 error_setg(errp
, "num-leds cannot be greater than %d",
277 MPS2FPGAIO_MAX_LEDS
);
281 for (i
= 0; i
< s
->num_leds
; i
++) {
282 g_autofree
char *ledname
= g_strdup_printf("USERLED%d", i
);
283 s
->led
[i
] = led_create_simple(OBJECT(dev
), GPIO_POLARITY_ACTIVE_HIGH
,
284 LED_COLOR_GREEN
, ledname
);
288 static const VMStateDescription mps2_fpgaio_vmstate
= {
289 .name
= "mps2-fpgaio",
291 .minimum_version_id
= 2,
292 .fields
= (VMStateField
[]) {
293 VMSTATE_UINT32(led0
, MPS2FPGAIO
),
294 VMSTATE_UINT32(prescale
, MPS2FPGAIO
),
295 VMSTATE_UINT32(misc
, MPS2FPGAIO
),
296 VMSTATE_INT64(clk1hz_tick_offset
, MPS2FPGAIO
),
297 VMSTATE_INT64(clk100hz_tick_offset
, MPS2FPGAIO
),
298 VMSTATE_UINT32(counter
, MPS2FPGAIO
),
299 VMSTATE_UINT32(pscntr
, MPS2FPGAIO
),
300 VMSTATE_INT64(pscntr_sync_ticks
, MPS2FPGAIO
),
301 VMSTATE_END_OF_LIST()
305 static Property mps2_fpgaio_properties
[] = {
306 /* Frequency of the prescale counter */
307 DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO
, prescale_clk
, 20000000),
308 /* Number of LEDs controlled by LED0 register */
309 DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO
, num_leds
, 2),
310 DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO
, has_switches
, false),
311 DEFINE_PROP_END_OF_LIST(),
314 static void mps2_fpgaio_class_init(ObjectClass
*klass
, void *data
)
316 DeviceClass
*dc
= DEVICE_CLASS(klass
);
318 dc
->vmsd
= &mps2_fpgaio_vmstate
;
319 dc
->realize
= mps2_fpgaio_realize
;
320 dc
->reset
= mps2_fpgaio_reset
;
321 device_class_set_props(dc
, mps2_fpgaio_properties
);
324 static const TypeInfo mps2_fpgaio_info
= {
325 .name
= TYPE_MPS2_FPGAIO
,
326 .parent
= TYPE_SYS_BUS_DEVICE
,
327 .instance_size
= sizeof(MPS2FPGAIO
),
328 .instance_init
= mps2_fpgaio_init
,
329 .class_init
= mps2_fpgaio_class_init
,
332 static void mps2_fpgaio_register_types(void)
334 type_register_static(&mps2_fpgaio_info
);
337 type_init(mps2_fpgaio_register_types
);