tests/ahci-test.c

   1 /*
   2  * AHCI test cases
   3  *
   4  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28 #include <getopt.h>
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/libqos-pc.h"
  33 #include "libqos/ahci.h"
  34 #include "libqos/pci-pc.h"
  35 #include "libqos/malloc-pc.h"
  36
  37 #include "qemu-common.h"
  38 #include "qemu/host-utils.h"
  39
  40 #include "hw/pci/pci_ids.h"
  41 #include "hw/pci/pci_regs.h"
  42
  43 /* Test-specific defines. */
  44 #define TEST_IMAGE_SIZE    (64 * 1024 * 1024)
  45
  46 /*** Globals ***/
  47 static QGuestAllocator *guest_malloc;
  48 static char tmp_path[] = "/tmp/qtest.XXXXXX";
  49 static bool ahci_pedantic;
  50
  51 /*** IO macros for the AHCI memory registers. ***/
  52 #define AHCI_READ(OFST) qpci_io_readl(ahci->dev, ahci->hba_base + (OFST))
  53 #define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci->dev,                 \
  54                                              ahci->hba_base + (OFST), (VAL))
  55 #define AHCI_RREG(regno)      AHCI_READ(4 * (regno))
  56 #define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
  57 #define AHCI_SET(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) | (mask))
  58 #define AHCI_CLR(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) & ~(mask))
  59
  60 /*** IO macros for port-specific offsets inside of AHCI memory. ***/
  61 #define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
  62 #define PX_RREG(port, regno)      AHCI_RREG(PX_OFST((port), (regno)))
  63 #define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
  64 #define PX_SET(port, reg, mask)   PX_WREG((port), (reg),                \
  65                                           PX_RREG((port), (reg)) | (mask));
  66 #define PX_CLR(port, reg, mask)   PX_WREG((port), (reg),                \
  67                                           PX_RREG((port), (reg)) & ~(mask));
  68
  69 /*** Function Declarations ***/
  70 static QPCIDevice *get_ahci_device(uint32_t *fingerprint);
  71 static void start_ahci_device(AHCIQState *ahci);
  72 static void free_ahci_device(QPCIDevice *dev);
  73
  74 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
  75 static void ahci_test_pci_spec(AHCIQState *ahci);
  76 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
  77                                uint8_t offset);
  78 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
  79 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
  80 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
  81
  82 /*** Utilities ***/
  83
  84 static void string_bswap16(uint16_t *s, size_t bytes)
  85 {
  86     g_assert_cmphex((bytes & 1), ==, 0);
  87     bytes /= 2;
  88
  89     while (bytes--) {
  90         *s = bswap16(*s);
  91         s++;
  92     }
  93 }
  94
  95 /**
  96  * Locate, verify, and return a handle to the AHCI device.
  97  */
  98 static QPCIDevice *get_ahci_device(uint32_t *fingerprint)
  99 {
 100     QPCIDevice *ahci;
 101     uint32_t ahci_fingerprint;
 102     QPCIBus *pcibus;
 103
 104     pcibus = qpci_init_pc();
 105
 106     /* Find the AHCI PCI device and verify it's the right one. */
 107     ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
 108     g_assert(ahci != NULL);
 109
 110     ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
 111
 112     switch (ahci_fingerprint) {
 113     case AHCI_INTEL_ICH9:
 114         break;
 115     default:
 116         /* Unknown device. */
 117         g_assert_not_reached();
 118     }
 119
 120     if (fingerprint) {
 121         *fingerprint = ahci_fingerprint;
 122     }
 123     return ahci;
 124 }
 125
 126 static void free_ahci_device(QPCIDevice *dev)
 127 {
 128     QPCIBus *pcibus = dev ? dev->bus : NULL;
 129
 130     /* libqos doesn't have a function for this, so free it manually */
 131     g_free(dev);
 132     qpci_free_pc(pcibus);
 133 }
 134
 135 /*** Test Setup & Teardown ***/
 136
 137 /**
 138  * Start a Q35 machine and bookmark a handle to the AHCI device.
 139  */
 140 static AHCIQState *ahci_boot(void)
 141 {
 142     AHCIQState *s;
 143     const char *cli;
 144
 145     s = g_malloc0(sizeof(AHCIQState));
 146
 147     cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
 148         ",format=raw"
 149         " -M q35 "
 150         "-device ide-hd,drive=drive0 "
 151         "-global ide-hd.ver=%s";
 152     s->parent = qtest_pc_boot(cli, tmp_path, "testdisk", "version");
 153
 154     /* Verify that we have an AHCI device present. */
 155     s->dev = get_ahci_device(&s->fingerprint);
 156
 157     /* Stopgap: Copy the allocator reference */
 158     guest_malloc = s->parent->alloc;
 159
 160     return s;
 161 }
 162
 163 /**
 164  * Clean up the PCI device, then terminate the QEMU instance.
 165  */
 166 static void ahci_shutdown(AHCIQState *ahci)
 167 {
 168     QOSState *qs = ahci->parent;
 169     free_ahci_device(ahci->dev);
 170     g_free(ahci);
 171     qtest_shutdown(qs);
 172 }
 173
 174 /*** Logical Device Initialization ***/
 175
 176 /**
 177  * Start the PCI device and sanity-check default operation.
 178  */
 179 static void ahci_pci_enable(AHCIQState *ahci)
 180 {
 181     uint8_t reg;
 182
 183     start_ahci_device(ahci);
 184
 185     switch (ahci->fingerprint) {
 186     case AHCI_INTEL_ICH9:
 187         /* ICH9 has a register at PCI 0x92 that
 188          * acts as a master port enabler mask. */
 189         reg = qpci_config_readb(ahci->dev, 0x92);
 190         reg |= 0x3F;
 191         qpci_config_writeb(ahci->dev, 0x92, reg);
 192         /* 0...0111111b -- bit significant, ports 0-5 enabled. */
 193         ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
 194         break;
 195     }
 196
 197 }
 198
 199 /**
 200  * Map BAR5/ABAR, and engage the PCI device.
 201  */
 202 static void start_ahci_device(AHCIQState *ahci)
 203 {
 204     /* Map AHCI's ABAR (BAR5) */
 205     ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
 206
 207     /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
 208     qpci_device_enable(ahci->dev);
 209 }
 210
 211 /**
 212  * Test and initialize the AHCI's HBA memory areas.
 213  * Initialize and start any ports with devices attached.
 214  * Bring the HBA into the idle state.
 215  */
 216 static void ahci_hba_enable(AHCIQState *ahci)
 217 {
 218     /* Bits of interest in this section:
 219      * GHC.AE     Global Host Control / AHCI Enable
 220      * PxCMD.ST   Port Command: Start
 221      * PxCMD.SUD  "Spin Up Device"
 222      * PxCMD.POD  "Power On Device"
 223      * PxCMD.FRE  "FIS Receive Enable"
 224      * PxCMD.FR   "FIS Receive Running"
 225      * PxCMD.CR   "Command List Running"
 226      */
 227     uint32_t reg, ports_impl, clb, fb;
 228     uint16_t i;
 229     uint8_t num_cmd_slots;
 230
 231     g_assert(ahci != NULL);
 232
 233     /* Set GHC.AE to 1 */
 234     AHCI_SET(AHCI_GHC, AHCI_GHC_AE);
 235     reg = AHCI_RREG(AHCI_GHC);
 236     ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 237
 238     /* Cache CAP and CAP2. */
 239     ahci->cap = AHCI_RREG(AHCI_CAP);
 240     ahci->cap2 = AHCI_RREG(AHCI_CAP2);
 241
 242     /* Read CAP.NCS, how many command slots do we have? */
 243     num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
 244     g_test_message("Number of Command Slots: %u", num_cmd_slots);
 245
 246     /* Determine which ports are implemented. */
 247     ports_impl = AHCI_RREG(AHCI_PI);
 248
 249     for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
 250         if (!(ports_impl & 0x01)) {
 251             continue;
 252         }
 253
 254         g_test_message("Initializing port %u", i);
 255
 256         reg = PX_RREG(i, AHCI_PX_CMD);
 257         if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
 258                    AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
 259             g_test_message("port is idle");
 260         } else {
 261             g_test_message("port needs to be idled");
 262             PX_CLR(i, AHCI_PX_CMD, (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
 263             /* The port has 500ms to disengage. */
 264             usleep(500000);
 265             reg = PX_RREG(i, AHCI_PX_CMD);
 266             ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 267             ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 268             g_test_message("port is now idle");
 269             /* The spec does allow for possibly needing a PORT RESET
 270              * or HBA reset if we fail to idle the port. */
 271         }
 272
 273         /* Allocate Memory for the Command List Buffer & FIS Buffer */
 274         /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
 275         clb = guest_alloc(guest_malloc, num_cmd_slots * 0x20);
 276         g_test_message("CLB: 0x%08x", clb);
 277         PX_WREG(i, AHCI_PX_CLB, clb);
 278         g_assert_cmphex(clb, ==, PX_RREG(i, AHCI_PX_CLB));
 279
 280         /* PxFB space ... 0x100, as in 4.2.1 p 35 */
 281         fb = guest_alloc(guest_malloc, 0x100);
 282         g_test_message("FB: 0x%08x", fb);
 283         PX_WREG(i, AHCI_PX_FB, fb);
 284         g_assert_cmphex(fb, ==, PX_RREG(i, AHCI_PX_FB));
 285
 286         /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
 287         PX_WREG(i, AHCI_PX_SERR, 0xFFFFFFFF);
 288         PX_WREG(i, AHCI_PX_IS, 0xFFFFFFFF);
 289         AHCI_WREG(AHCI_IS, (1 << i));
 290
 291         /* Verify Interrupts Cleared */
 292         reg = PX_RREG(i, AHCI_PX_SERR);
 293         g_assert_cmphex(reg, ==, 0);
 294
 295         reg = PX_RREG(i, AHCI_PX_IS);
 296         g_assert_cmphex(reg, ==, 0);
 297
 298         reg = AHCI_RREG(AHCI_IS);
 299         ASSERT_BIT_CLEAR(reg, (1 << i));
 300
 301         /* Enable All Interrupts: */
 302         PX_WREG(i, AHCI_PX_IE, 0xFFFFFFFF);
 303         reg = PX_RREG(i, AHCI_PX_IE);
 304         g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
 305
 306         /* Enable the FIS Receive Engine. */
 307         PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
 308         reg = PX_RREG(i, AHCI_PX_CMD);
 309         ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
 310
 311         /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
 312          * physical presence, a device is present and may be started. However,
 313          * PxSERR.DIAG.X /may/ need to be cleared a priori. */
 314         reg = PX_RREG(i, AHCI_PX_SERR);
 315         if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
 316             PX_SET(i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
 317         }
 318
 319         reg = PX_RREG(i, AHCI_PX_TFD);
 320         if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
 321             reg = PX_RREG(i, AHCI_PX_SSTS);
 322             if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
 323                 /* Device Found: set PxCMD.ST := 1 */
 324                 PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
 325                 ASSERT_BIT_SET(PX_RREG(i, AHCI_PX_CMD), AHCI_PX_CMD_CR);
 326                 g_test_message("Started Device %u", i);
 327             } else if ((reg & AHCI_PX_SSTS_DET)) {
 328                 /* Device present, but in some unknown state. */
 329                 g_assert_not_reached();
 330             }
 331         }
 332     }
 333
 334     /* Enable GHC.IE */
 335     AHCI_SET(AHCI_GHC, AHCI_GHC_IE);
 336     reg = AHCI_RREG(AHCI_GHC);
 337     ASSERT_BIT_SET(reg, AHCI_GHC_IE);
 338
 339     /* TODO: The device should now be idling and waiting for commands.
 340      * In the future, a small test-case to inspect the Register D2H FIS
 341      * and clear the initial interrupts might be good. */
 342 }
 343
 344 /*** Specification Adherence Tests ***/
 345
 346 /**
 347  * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
 348  */
 349 static void ahci_test_pci_spec(AHCIQState *ahci)
 350 {
 351     uint8_t datab;
 352     uint16_t data;
 353     uint32_t datal;
 354
 355     /* Most of these bits should start cleared until we turn them on. */
 356     data = qpci_config_readw(ahci->dev, PCI_COMMAND);
 357     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
 358     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
 359     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);     /* Reserved */
 360     ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
 361     ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
 362     ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);        /* Reserved */
 363     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
 364     ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
 365     ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
 366     ASSERT_BIT_CLEAR(data, 0xF800);                  /* Reserved */
 367
 368     data = qpci_config_readw(ahci->dev, PCI_STATUS);
 369     ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);     /* Reserved */
 370     ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
 371     ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);      /* must be set */
 372     ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);         /* Reserved */
 373     ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
 374     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
 375     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
 376     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
 377     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
 378     ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
 379
 380     /* RID occupies the low byte, CCs occupy the high three. */
 381     datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
 382     if (ahci_pedantic) {
 383         /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
 384          * Though in practice this is likely seldom true. */
 385         ASSERT_BIT_CLEAR(datal, 0xFF);
 386     }
 387
 388     /* BCC *must* equal 0x01. */
 389     g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
 390     if (PCI_SCC(datal) == 0x01) {
 391         /* IDE */
 392         ASSERT_BIT_SET(0x80000000, datal);
 393         ASSERT_BIT_CLEAR(0x60000000, datal);
 394     } else if (PCI_SCC(datal) == 0x04) {
 395         /* RAID */
 396         g_assert_cmphex(PCI_PI(datal), ==, 0);
 397     } else if (PCI_SCC(datal) == 0x06) {
 398         /* AHCI */
 399         g_assert_cmphex(PCI_PI(datal), ==, 0x01);
 400     } else {
 401         g_assert_not_reached();
 402     }
 403
 404     datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
 405     g_assert_cmphex(datab, ==, 0);
 406
 407     datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
 408     g_assert_cmphex(datab, ==, 0);
 409
 410     /* Only the bottom 7 bits must be off. */
 411     datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
 412     ASSERT_BIT_CLEAR(datab, 0x7F);
 413
 414     /* BIST is optional, but the low 7 bits must always start off regardless. */
 415     datab = qpci_config_readb(ahci->dev, PCI_BIST);
 416     ASSERT_BIT_CLEAR(datab, 0x7F);
 417
 418     /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
 419     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 420     g_assert_cmphex(datal, ==, 0);
 421
 422     qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
 423     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 424     /* ABAR must be 32-bit, memory mapped, non-prefetchable and
 425      * must be >= 512 bytes. To that end, bits 0-8 must be off. */
 426     ASSERT_BIT_CLEAR(datal, 0xFF);
 427
 428     /* Capability list MUST be present, */
 429     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
 430     /* But these bits are reserved. */
 431     ASSERT_BIT_CLEAR(datal, ~0xFF);
 432     g_assert_cmphex(datal, !=, 0);
 433
 434     /* Check specification adherence for capability extenstions. */
 435     data = qpci_config_readw(ahci->dev, datal);
 436
 437     switch (ahci->fingerprint) {
 438     case AHCI_INTEL_ICH9:
 439         /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
 440         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
 441         break;
 442     default:
 443         /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
 444         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
 445     }
 446
 447     ahci_test_pci_caps(ahci, data, (uint8_t)datal);
 448
 449     /* Reserved. */
 450     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
 451     g_assert_cmphex(datal, ==, 0);
 452
 453     /* IPIN might vary, but ILINE must be off. */
 454     datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
 455     g_assert_cmphex(datab, ==, 0);
 456 }
 457
 458 /**
 459  * Test PCI capabilities for AHCI specification adherence.
 460  */
 461 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
 462                                uint8_t offset)
 463 {
 464     uint8_t cid = header & 0xFF;
 465     uint8_t next = header >> 8;
 466
 467     g_test_message("CID: %02x; next: %02x", cid, next);
 468
 469     switch (cid) {
 470     case PCI_CAP_ID_PM:
 471         ahci_test_pmcap(ahci, offset);
 472         break;
 473     case PCI_CAP_ID_MSI:
 474         ahci_test_msicap(ahci, offset);
 475         break;
 476     case PCI_CAP_ID_SATA:
 477         ahci_test_satacap(ahci, offset);
 478         break;
 479
 480     default:
 481         g_test_message("Unknown CAP 0x%02x", cid);
 482     }
 483
 484     if (next) {
 485         ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
 486     }
 487 }
 488
 489 /**
 490  * Test SATA PCI capabilitity for AHCI specification adherence.
 491  */
 492 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
 493 {
 494     uint16_t dataw;
 495     uint32_t datal;
 496
 497     g_test_message("Verifying SATACAP");
 498
 499     /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
 500     dataw = qpci_config_readw(ahci->dev, offset + 2);
 501     g_assert_cmphex(dataw, ==, 0x10);
 502
 503     /* Grab the SATACR1 register. */
 504     datal = qpci_config_readw(ahci->dev, offset + 4);
 505
 506     switch (datal & 0x0F) {
 507     case 0x04: /* BAR0 */
 508     case 0x05: /* BAR1 */
 509     case 0x06:
 510     case 0x07:
 511     case 0x08:
 512     case 0x09: /* BAR5 */
 513     case 0x0F: /* Immediately following SATACR1 in PCI config space. */
 514         break;
 515     default:
 516         /* Invalid BARLOC for the Index Data Pair. */
 517         g_assert_not_reached();
 518     }
 519
 520     /* Reserved. */
 521     g_assert_cmphex((datal >> 24), ==, 0x00);
 522 }
 523
 524 /**
 525  * Test MSI PCI capability for AHCI specification adherence.
 526  */
 527 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
 528 {
 529     uint16_t dataw;
 530     uint32_t datal;
 531
 532     g_test_message("Verifying MSICAP");
 533
 534     dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
 535     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
 536     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
 537     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
 538
 539     datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
 540     g_assert_cmphex(datal, ==, 0);
 541
 542     if (dataw & PCI_MSI_FLAGS_64BIT) {
 543         g_test_message("MSICAP is 64bit");
 544         datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
 545         g_assert_cmphex(datal, ==, 0);
 546         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
 547         g_assert_cmphex(dataw, ==, 0);
 548     } else {
 549         g_test_message("MSICAP is 32bit");
 550         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
 551         g_assert_cmphex(dataw, ==, 0);
 552     }
 553 }
 554
 555 /**
 556  * Test Power Management PCI capability for AHCI specification adherence.
 557  */
 558 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
 559 {
 560     uint16_t dataw;
 561
 562     g_test_message("Verifying PMCAP");
 563
 564     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
 565     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
 566     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
 567     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
 568     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
 569
 570     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
 571     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
 572     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
 573     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
 574     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
 575 }
 576
 577 static void ahci_test_hba_spec(AHCIQState *ahci)
 578 {
 579     unsigned i;
 580     uint32_t reg;
 581     uint32_t ports;
 582     uint8_t nports_impl;
 583     uint8_t maxports;
 584
 585     g_assert(ahci != NULL);
 586
 587     /*
 588      * Note that the AHCI spec does expect the BIOS to set up a few things:
 589      * CAP.SSS    - Support for staggered spin-up            (t/f)
 590      * CAP.SMPS   - Support for mechanical presence switches (t/f)
 591      * PI         - Ports Implemented                        (1-32)
 592      * PxCMD.HPCP - Hot Plug Capable Port
 593      * PxCMD.MPSP - Mechanical Presence Switch Present
 594      * PxCMD.CPD  - Cold Presence Detection support
 595      *
 596      * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
 597      * Foreach Port Implemented:
 598      * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
 599      * -PxCLB/U and PxFB/U are set to valid regions in memory
 600      * -PxSUD is set to 1.
 601      * -PxSSTS.DET is polled for presence; if detected, we continue:
 602      * -PxSERR is cleared with 1's.
 603      * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
 604      *  the device is ready.
 605      */
 606
 607     /* 1 CAP - Capabilities Register */
 608     ahci->cap = AHCI_RREG(AHCI_CAP);
 609     ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
 610
 611     /* 2 GHC - Global Host Control */
 612     reg = AHCI_RREG(AHCI_GHC);
 613     ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
 614     ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
 615     ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
 616     if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
 617         g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
 618         ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 619     } else {
 620         g_test_message("Supports AHCI/Legacy mix.");
 621         ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
 622     }
 623
 624     /* 3 IS - Interrupt Status */
 625     reg = AHCI_RREG(AHCI_IS);
 626     g_assert_cmphex(reg, ==, 0);
 627
 628     /* 4 PI - Ports Implemented */
 629     ports = AHCI_RREG(AHCI_PI);
 630     /* Ports Implemented must be non-zero. */
 631     g_assert_cmphex(ports, !=, 0);
 632     /* Ports Implemented must be <= Number of Ports. */
 633     nports_impl = ctpopl(ports);
 634     g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
 635
 636     /* Ports must be within the proper range. Given a mapping of SIZE,
 637      * 256 bytes are used for global HBA control, and the rest is used
 638      * for ports data, at 0x80 bytes each. */
 639     g_assert_cmphex(ahci->barsize, >, 0);
 640     maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
 641     /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
 642     g_assert_cmphex((reg >> maxports), ==, 0);
 643
 644     /* 5 AHCI Version */
 645     reg = AHCI_RREG(AHCI_VS);
 646     switch (reg) {
 647     case AHCI_VERSION_0_95:
 648     case AHCI_VERSION_1_0:
 649     case AHCI_VERSION_1_1:
 650     case AHCI_VERSION_1_2:
 651     case AHCI_VERSION_1_3:
 652         break;
 653     default:
 654         g_assert_not_reached();
 655     }
 656
 657     /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
 658     reg = AHCI_RREG(AHCI_CCCCTL);
 659     if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
 660         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
 661         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
 662         ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
 663         ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
 664     } else {
 665         g_assert_cmphex(reg, ==, 0);
 666     }
 667
 668     /* 7 CCC_PORTS */
 669     reg = AHCI_RREG(AHCI_CCCPORTS);
 670     /* Must be zeroes initially regardless of CAP.CCCS */
 671     g_assert_cmphex(reg, ==, 0);
 672
 673     /* 8 EM_LOC */
 674     reg = AHCI_RREG(AHCI_EMLOC);
 675     if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
 676         g_assert_cmphex(reg, ==, 0);
 677     }
 678
 679     /* 9 EM_CTL */
 680     reg = AHCI_RREG(AHCI_EMCTL);
 681     if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
 682         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
 683         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
 684         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
 685         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
 686     } else {
 687         g_assert_cmphex(reg, ==, 0);
 688     }
 689
 690     /* 10 CAP2 -- Capabilities Extended */
 691     ahci->cap2 = AHCI_RREG(AHCI_CAP2);
 692     ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
 693
 694     /* 11 BOHC -- Bios/OS Handoff Control */
 695     reg = AHCI_RREG(AHCI_BOHC);
 696     g_assert_cmphex(reg, ==, 0);
 697
 698     /* 12 -- 23: Reserved */
 699     g_test_message("Verifying HBA reserved area is empty.");
 700     for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
 701         reg = AHCI_RREG(i);
 702         g_assert_cmphex(reg, ==, 0);
 703     }
 704
 705     /* 24 -- 39: NVMHCI */
 706     if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
 707         g_test_message("Verifying HBA/NVMHCI area is empty.");
 708         for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
 709             reg = AHCI_RREG(i);
 710             g_assert_cmphex(reg, ==, 0);
 711         }
 712     }
 713
 714     /* 40 -- 63: Vendor */
 715     g_test_message("Verifying HBA/Vendor area is empty.");
 716     for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
 717         reg = AHCI_RREG(i);
 718         g_assert_cmphex(reg, ==, 0);
 719     }
 720
 721     /* 64 -- XX: Port Space */
 722     for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
 723         if (BITSET(ports, 0x1)) {
 724             g_test_message("Testing port %u for spec", i);
 725             ahci_test_port_spec(ahci, i);
 726         } else {
 727             uint16_t j;
 728             uint16_t low = AHCI_PORTS + (32 * i);
 729             uint16_t high = AHCI_PORTS + (32 * (i + 1));
 730             g_test_message("Asserting unimplemented port %u "
 731                            "(reg [%u-%u]) is empty.",
 732                            i, low, high - 1);
 733             for (j = low; j < high; ++j) {
 734                 reg = AHCI_RREG(j);
 735                 g_assert_cmphex(reg, ==, 0);
 736             }
 737         }
 738     }
 739 }
 740
 741 /**
 742  * Test the memory space for one port for specification adherence.
 743  */
 744 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
 745 {
 746     uint32_t reg;
 747     unsigned i;
 748
 749     /* (0) CLB */
 750     reg = PX_RREG(port, AHCI_PX_CLB);
 751     ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
 752
 753     /* (1) CLBU */
 754     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 755         reg = PX_RREG(port, AHCI_PX_CLBU);
 756         g_assert_cmphex(reg, ==, 0);
 757     }
 758
 759     /* (2) FB */
 760     reg = PX_RREG(port, AHCI_PX_FB);
 761     ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
 762
 763     /* (3) FBU */
 764     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 765         reg = PX_RREG(port, AHCI_PX_FBU);
 766         g_assert_cmphex(reg, ==, 0);
 767     }
 768
 769     /* (4) IS */
 770     reg = PX_RREG(port, AHCI_PX_IS);
 771     g_assert_cmphex(reg, ==, 0);
 772
 773     /* (5) IE */
 774     reg = PX_RREG(port, AHCI_PX_IE);
 775     g_assert_cmphex(reg, ==, 0);
 776
 777     /* (6) CMD */
 778     reg = PX_RREG(port, AHCI_PX_CMD);
 779     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
 780     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
 781     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
 782     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 783     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 784     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
 785     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
 786     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
 787     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
 788     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);  /* RW only if CAP.SALP */
 789     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);   /* RW only if CAP.SALP */
 790     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
 791     /* If CPDetect support does not exist, CPState must be off. */
 792     if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
 793         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
 794     }
 795     /* If MPSPresence is not set, MPSState must be off. */
 796     if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
 797         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 798     }
 799     /* If we do not support MPS, MPSS and MPSP must be off. */
 800     if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
 801         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 802         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
 803     }
 804     /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
 805     if (BITANY(reg, AHCI_PX_CMD_CPD || AHCI_PX_CMD_MPSP)) {
 806         ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
 807     }
 808     /* HPCP and ESP cannot both be active. */
 809     g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
 810     /* If CAP.FBSS is not set, FBSCP must not be set. */
 811     if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
 812         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
 813     }
 814
 815     /* (7) RESERVED */
 816     reg = PX_RREG(port, AHCI_PX_RES1);
 817     g_assert_cmphex(reg, ==, 0);
 818
 819     /* (8) TFD */
 820     reg = PX_RREG(port, AHCI_PX_TFD);
 821     /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
 822      * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
 823     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
 824     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
 825     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
 826     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
 827     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
 828     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 829     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
 830
 831     /* (9) SIG */
 832     /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
 833      * Even when GHC.ST is zero, the AHCI HBA may receive the initial
 834      * D2H register FIS and update the signature asynchronously,
 835      * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
 836
 837     /* (10) SSTS / SCR0: SStatus */
 838     reg = PX_RREG(port, AHCI_PX_SSTS);
 839     ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
 840     /* Even though the register should be 0 at boot, it is asynchronous and
 841      * prone to change, so we cannot test any well known value. */
 842
 843     /* (11) SCTL / SCR2: SControl */
 844     reg = PX_RREG(port, AHCI_PX_SCTL);
 845     g_assert_cmphex(reg, ==, 0);
 846
 847     /* (12) SERR / SCR1: SError */
 848     reg = PX_RREG(port, AHCI_PX_SERR);
 849     g_assert_cmphex(reg, ==, 0);
 850
 851     /* (13) SACT / SCR3: SActive */
 852     reg = PX_RREG(port, AHCI_PX_SACT);
 853     g_assert_cmphex(reg, ==, 0);
 854
 855     /* (14) CI */
 856     reg = PX_RREG(port, AHCI_PX_CI);
 857     g_assert_cmphex(reg, ==, 0);
 858
 859     /* (15) SNTF */
 860     reg = PX_RREG(port, AHCI_PX_SNTF);
 861     g_assert_cmphex(reg, ==, 0);
 862
 863     /* (16) FBS */
 864     reg = PX_RREG(port, AHCI_PX_FBS);
 865     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
 866     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
 867     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
 868     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
 869     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
 870     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
 871     if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
 872         /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
 873         g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
 874     }
 875
 876     /* [17 -- 27] RESERVED */
 877     for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
 878         reg = PX_RREG(port, i);
 879         g_assert_cmphex(reg, ==, 0);
 880     }
 881
 882     /* [28 -- 31] Vendor-Specific */
 883     for (i = AHCI_PX_VS; i < 32; ++i) {
 884         reg = PX_RREG(port, i);
 885         if (reg) {
 886             g_test_message("INFO: Vendor register %u non-empty", i);
 887         }
 888     }
 889 }
 890
 891 /**
 892  * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
 893  * device we see, then read and check the response.
 894  */
 895 static void ahci_test_identify(AHCIQState *ahci)
 896 {
 897     RegD2HFIS *d2h = g_malloc0(0x20);
 898     RegD2HFIS *pio = g_malloc0(0x20);
 899     RegH2DFIS fis;
 900     AHCICommand cmd;
 901     PRD prd;
 902     uint32_t ports, reg, clb, table, fb, data_ptr;
 903     uint16_t buff[256];
 904     unsigned i;
 905     int rc;
 906
 907     g_assert(ahci != NULL);
 908
 909     /* We need to:
 910      * (1) Create a Command Table Buffer and update the Command List Slot #0
 911      *     to point to this buffer.
 912      * (2) Construct an FIS host-to-device command structure, and write it to
 913      *     the top of the command table buffer.
 914      * (3) Create a data buffer for the IDENTIFY response to be sent to
 915      * (4) Create a Physical Region Descriptor that points to the data buffer,
 916      *     and write it to the bottom (offset 0x80) of the command table.
 917      * (5) Now, PxCLB points to the command list, command 0 points to
 918      *     our table, and our table contains an FIS instruction and a
 919      *     PRD that points to our rx buffer.
 920      * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
 921      */
 922
 923     /* Pick the first implemented and running port */
 924     ports = AHCI_RREG(AHCI_PI);
 925     for (i = 0; i < 32; ports >>= 1, ++i) {
 926         if (ports == 0) {
 927             i = 32;
 928         }
 929
 930         if (!(ports & 0x01)) {
 931             continue;
 932         }
 933
 934         reg = PX_RREG(i, AHCI_PX_CMD);
 935         if (BITSET(reg, AHCI_PX_CMD_ST)) {
 936             break;
 937         }
 938     }
 939     g_assert_cmphex(i, <, 32);
 940     g_test_message("Selected port %u for test", i);
 941
 942     /* Clear out this port's interrupts (ignore the init register d2h fis) */
 943     reg = PX_RREG(i, AHCI_PX_IS);
 944     PX_WREG(i, AHCI_PX_IS, reg);
 945     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
 946
 947     /* Wipe the FIS-Receive Buffer */
 948     fb = PX_RREG(i, AHCI_PX_FB);
 949     g_assert_cmphex(fb, !=, 0);
 950     qmemset(fb, 0x00, 0x100);
 951
 952     /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
 953     /* We need at least one PRD, so round up to the nearest 0x80 multiple.    */
 954     table = guest_alloc(guest_malloc, CMD_TBL_SIZ(1));
 955     g_assert(table);
 956     ASSERT_BIT_CLEAR(table, 0x7F);
 957
 958     /* Create a data buffer ... where we will dump the IDENTIFY data to. */
 959     data_ptr = guest_alloc(guest_malloc, 512);
 960     g_assert(data_ptr);
 961
 962     /* Grab the Command List Buffer pointer */
 963     clb = PX_RREG(i, AHCI_PX_CLB);
 964     g_assert(clb);
 965
 966     /* Copy the existing Command #0 structure from the CLB into local memory,
 967      * and build a new command #0. */
 968     memread(clb, &cmd, sizeof(cmd));
 969     cmd.b1 = 5;    /* reg_h2d_fis is 5 double-words long */
 970     cmd.b2 = 0x04; /* clear PxTFD.STS.BSY when done */
 971     cmd.prdtl = cpu_to_le16(1); /* One PRD table entry. */
 972     cmd.prdbc = 0;
 973     cmd.ctba = cpu_to_le32(table);
 974     cmd.ctbau = 0;
 975
 976     /* Construct our PRD, noting that DBC is 0-indexed. */
 977     prd.dba = cpu_to_le32(data_ptr);
 978     prd.dbau = 0;
 979     prd.res = 0;
 980     /* 511+1 bytes, request DPS interrupt */
 981     prd.dbc = cpu_to_le32(511 | 0x80000000);
 982
 983     /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
 984     memset(&fis, 0x00, sizeof(fis));
 985     fis.fis_type = 0x27; /* Register Host-to-Device FIS */
 986     fis.command = 0xEC;  /* IDENTIFY */
 987     fis.device = 0;
 988     fis.flags = 0x80;    /* Indicate this is a command FIS */
 989
 990     /* We've committed nothing yet, no interrupts should be posted yet. */
 991     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
 992
 993     /* Commit the Command FIS to the Command Table */
 994     memwrite(table, &fis, sizeof(fis));
 995
 996     /* Commit the PRD entry to the Command Table */
 997     memwrite(table + 0x80, &prd, sizeof(prd));
 998
 999     /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
1000     memwrite(clb, &cmd, sizeof(cmd));
1001
1002     /* Everything is in place, but we haven't given the go-ahead yet. */
1003     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1004
1005     /* Issue Command #0 via PxCI */
1006     PX_WREG(i, AHCI_PX_CI, (1 << 0));
1007     while (BITSET(PX_RREG(i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
1008         usleep(50);
1009     }
1010
1011     /* Check for expected interrupts */
1012     reg = PX_RREG(i, AHCI_PX_IS);
1013     ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS);
1014     ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS);
1015     /* BUG: we expect AHCI_PX_IS_DPS to be set. */
1016     ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS);
1017
1018     /* Clear expected interrupts and assert all interrupts now cleared. */
1019     PX_WREG(i, AHCI_PX_IS, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
1020     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1021
1022     /* Check for errors. */
1023     reg = PX_RREG(i, AHCI_PX_SERR);
1024     g_assert_cmphex(reg, ==, 0);
1025     reg = PX_RREG(i, AHCI_PX_TFD);
1026     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
1027     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
1028
1029     /* Investigate CMD #0, assert that we read 512 bytes */
1030     memread(clb, &cmd, sizeof(cmd));
1031     g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc));
1032
1033     /* Investigate FIS responses */
1034     memread(fb + 0x20, pio, 0x20);
1035     memread(fb + 0x40, d2h, 0x20);
1036     g_assert_cmphex(pio->fis_type, ==, 0x5f);
1037     g_assert_cmphex(d2h->fis_type, ==, 0x34);
1038     g_assert_cmphex(pio->flags, ==, d2h->flags);
1039     g_assert_cmphex(pio->status, ==, d2h->status);
1040     g_assert_cmphex(pio->error, ==, d2h->error);
1041
1042     reg = PX_RREG(i, AHCI_PX_TFD);
1043     g_assert_cmphex((reg & AHCI_PX_TFD_ERR), ==, pio->error);
1044     g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, pio->status);
1045     /* The PIO Setup FIS contains a "bytes read" field, which is a
1046      * 16-bit value. The Physical Region Descriptor Byte Count is
1047      * 32-bit, but for small transfers using one PRD, it should match. */
1048     g_assert_cmphex(le16_to_cpu(pio->res4), ==, le32_to_cpu(cmd.prdbc));
1049
1050     /* Last, but not least: Investigate the IDENTIFY response data. */
1051     memread(data_ptr, &buff, 512);
1052
1053     /* Check serial number/version in the buffer */
1054     /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
1055      * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
1056      * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
1057      * as a consequence, only needs to unchunk the data on LE machines. */
1058     string_bswap16(&buff[10], 20);
1059     rc = memcmp(&buff[10], "testdisk            ", 20);
1060     g_assert_cmphex(rc, ==, 0);
1061
1062     string_bswap16(&buff[23], 8);
1063     rc = memcmp(&buff[23], "version ", 8);
1064     g_assert_cmphex(rc, ==, 0);
1065
1066     g_free(d2h);
1067     g_free(pio);
1068 }
1069
1070 /******************************************************************************/
1071 /* Test Interfaces                                                            */
1072 /******************************************************************************/
1073
1074 /**
1075  * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1076  */
1077 static void test_sanity(void)
1078 {
1079     AHCIQState *ahci;
1080     ahci = ahci_boot();
1081     ahci_shutdown(ahci);
1082 }
1083
1084 /**
1085  * Ensure that the PCI configuration space for the AHCI device is in-line with
1086  * the AHCI 1.3 specification for initial values.
1087  */
1088 static void test_pci_spec(void)
1089 {
1090     AHCIQState *ahci;
1091     ahci = ahci_boot();
1092     ahci_test_pci_spec(ahci);
1093     ahci_shutdown(ahci);
1094 }
1095
1096 /**
1097  * Engage the PCI AHCI device and sanity check the response.
1098  * Perform additional PCI config space bringup for the HBA.
1099  */
1100 static void test_pci_enable(void)
1101 {
1102     AHCIQState *ahci;
1103
1104     ahci = ahci_boot();
1105     ahci_pci_enable(ahci);
1106     ahci_shutdown(ahci);
1107 }
1108
1109 /**
1110  * Investigate the memory mapped regions of the HBA,
1111  * and test them for AHCI specification adherence.
1112  */
1113 static void test_hba_spec(void)
1114 {
1115     AHCIQState *ahci;
1116
1117     ahci = ahci_boot();
1118     ahci_pci_enable(ahci);
1119     ahci_test_hba_spec(ahci);
1120     ahci_shutdown(ahci);
1121 }
1122
1123 /**
1124  * Engage the HBA functionality of the AHCI PCI device,
1125  * and bring it into a functional idle state.
1126  */
1127 static void test_hba_enable(void)
1128 {
1129     AHCIQState *ahci;
1130
1131     ahci = ahci_boot();
1132     ahci_pci_enable(ahci);
1133     ahci_hba_enable(ahci);
1134     ahci_shutdown(ahci);
1135 }
1136
1137 /**
1138  * Bring up the device and issue an IDENTIFY command.
1139  * Inspect the state of the HBA device and the data returned.
1140  */
1141 static void test_identify(void)
1142 {
1143     AHCIQState *ahci;
1144
1145     ahci = ahci_boot();
1146     ahci_pci_enable(ahci);
1147     ahci_hba_enable(ahci);
1148     ahci_test_identify(ahci);
1149     ahci_shutdown(ahci);
1150 }
1151
1152 /******************************************************************************/
1153
1154 int main(int argc, char **argv)
1155 {
1156     const char *arch;
1157     int fd;
1158     int ret;
1159     int c;
1160
1161     static struct option long_options[] = {
1162         {"pedantic", no_argument, 0, 'p' },
1163         {0, 0, 0, 0},
1164     };
1165
1166     /* Should be first to utilize g_test functionality, So we can see errors. */
1167     g_test_init(&argc, &argv, NULL);
1168
1169     while (1) {
1170         c = getopt_long(argc, argv, "", long_options, NULL);
1171         if (c == -1) {
1172             break;
1173         }
1174         switch (c) {
1175         case -1:
1176             break;
1177         case 'p':
1178             ahci_pedantic = 1;
1179             break;
1180         default:
1181             fprintf(stderr, "Unrecognized ahci_test option.\n");
1182             g_assert_not_reached();
1183         }
1184     }
1185
1186     /* Check architecture */
1187     arch = qtest_get_arch();
1188     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1189         g_test_message("Skipping test for non-x86");
1190         return 0;
1191     }
1192
1193     /* Create a temporary raw image */
1194     fd = mkstemp(tmp_path);
1195     g_assert(fd >= 0);
1196     ret = ftruncate(fd, TEST_IMAGE_SIZE);
1197     g_assert(ret == 0);
1198     close(fd);
1199
1200     /* Run the tests */
1201     qtest_add_func("/ahci/sanity",     test_sanity);
1202     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
1203     qtest_add_func("/ahci/pci_enable", test_pci_enable);
1204     qtest_add_func("/ahci/hba_spec",   test_hba_spec);
1205     qtest_add_func("/ahci/hba_enable", test_hba_enable);
1206     qtest_add_func("/ahci/identify",   test_identify);
1207
1208     ret = g_test_run();
1209
1210     /* Cleanup */
1211     unlink(tmp_path);
1212
1213     return ret;
1214 }