include/hw/arm/fsl-imx31.h

   1 /*
   2  * Freescale i.MX31 SoC emulation
   3  *
   4  * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16
  17 #ifndef FSL_IMX31_H
  18 #define FSL_IMX31_H
  19
  20 #include "hw/arm/arm.h"
  21 #include "hw/intc/imx_avic.h"
  22 #include "hw/misc/imx_ccm.h"
  23 #include "hw/char/imx_serial.h"
  24 #include "hw/timer/imx_gpt.h"
  25 #include "hw/timer/imx_epit.h"
  26 #include "hw/i2c/imx_i2c.h"
  27 #include "exec/memory.h"
  28
  29 #define TYPE_FSL_IMX31 "fsl,imx31"
  30 #define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
  31
  32 #define FSL_IMX31_NUM_UARTS 2
  33 #define FSL_IMX31_NUM_EPITS 2
  34
  35 typedef struct FslIMX31State {
  36     /*< private >*/
  37     DeviceState parent_obj;
  38
  39     /*< public >*/
  40     ARMCPU         cpu;
  41     IMXAVICState   avic;
  42     IMXCCMState    ccm;
  43     IMXSerialState uart[FSL_IMX31_NUM_UARTS];
  44     IMXGPTState    gpt;
  45     IMXEPITState   epit[FSL_IMX31_NUM_EPITS];
  46     MemoryRegion   secure_rom;
  47     MemoryRegion   rom;
  48     MemoryRegion   iram;
  49     MemoryRegion   iram_alias;
  50 } FslIMX31State;
  51
  52 #define FSL_IMX31_SECURE_ROM_ADDR       0x00000000
  53 #define FSL_IMX31_SECURE_ROM_SIZE       0x4000
  54 #define FSL_IMX31_ROM_ADDR              0x00404000
  55 #define FSL_IMX31_ROM_SIZE              0x4000
  56 #define FSL_IMX31_IRAM_ALIAS_ADDR       0x10000000
  57 #define FSL_IMX31_IRAM_ALIAS_SIZE       0xFFC0000
  58 #define FSL_IMX31_IRAM_ADDR             0x1FFFC000
  59 #define FSL_IMX31_IRAM_SIZE             0x4000
  60 #define FSL_IMX31_UART1_ADDR            0x43F90000
  61 #define FSL_IMX31_UART1_SIZE            0x4000
  62 #define FSL_IMX31_UART2_ADDR            0x43F94000
  63 #define FSL_IMX31_UART2_SIZE            0x4000
  64 #define FSL_IMX31_CCM_ADDR              0x53F80000
  65 #define FSL_IMX31_CCM_SIZE              0x4000
  66 #define FSL_IMX31_GPT_ADDR              0x53F90000
  67 #define FSL_IMX31_GPT_SIZE              0x4000
  68 #define FSL_IMX31_EPIT1_ADDR            0x53F94000
  69 #define FSL_IMX31_EPIT1_SIZE            0x4000
  70 #define FSL_IMX31_EPIT2_ADDR            0x53F98000
  71 #define FSL_IMX31_EPIT2_SIZE            0x4000
  72 #define FSL_IMX31_AVIC_ADDR             0x68000000
  73 #define FSL_IMX31_AVIC_SIZE             0x100
  74 #define FSL_IMX31_SDRAM0_ADDR           0x80000000
  75 #define FSL_IMX31_SDRAM0_SIZE           0x10000000
  76 #define FSL_IMX31_SDRAM1_ADDR           0x90000000
  77 #define FSL_IMX31_SDRAM1_SIZE           0x10000000
  78 #define FSL_IMX31_FLASH0_ADDR           0xA0000000
  79 #define FSL_IMX31_FLASH0_SIZE           0x8000000
  80 #define FSL_IMX31_FLASH1_ADDR           0xA8000000
  81 #define FSL_IMX31_FLASH1_SIZE           0x8000000
  82 #define FSL_IMX31_CS2_ADDR              0xB0000000
  83 #define FSL_IMX31_CS2_SIZE              0x2000000
  84 #define FSL_IMX31_CS3_ADDR              0xB2000000
  85 #define FSL_IMX31_CS3_SIZE              0x2000000
  86 #define FSL_IMX31_CS4_ADDR              0xB4000000
  87 #define FSL_IMX31_CS4_SIZE              0x2000000
  88 #define FSL_IMX31_CS5_ADDR              0xB6000000
  89 #define FSL_IMX31_CS5_SIZE              0x2000000
  90 #define FSL_IMX31_NAND_ADDR             0xB8000000
  91 #define FSL_IMX31_NAND_SIZE             0x1000
  92
  93 #define FSL_IMX31_EPIT2_IRQ             27
  94 #define FSL_IMX31_EPIT1_IRQ             28
  95 #define FSL_IMX31_GPT_IRQ               29
  96 #define FSL_IMX31_UART2_IRQ             32
  97 #define FSL_IMX31_UART1_IRQ             45
  98
  99 #endif /* FSL_IMX31_H */