hw/misc/milkymist-hpdmc.c

   1 /*
   2  *  QEMU model of the Milkymist High Performance Dynamic Memory Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/hpdmc.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "qemu/error-report.h"
  29
  30 enum {
  31     R_SYSTEM = 0,
  32     R_BYPASS,
  33     R_TIMING,
  34     R_IODELAY,
  35     R_MAX
  36 };
  37
  38 enum {
  39     IODELAY_DQSDELAY_RDY = (1<<5),
  40     IODELAY_PLL1_LOCKED  = (1<<6),
  41     IODELAY_PLL2_LOCKED  = (1<<7),
  42 };
  43
  44 #define TYPE_MILKYMIST_HPDMC "milkymist-hpdmc"
  45 #define MILKYMIST_HPDMC(obj) \
  46     OBJECT_CHECK(MilkymistHpdmcState, (obj), TYPE_MILKYMIST_HPDMC)
  47
  48 struct MilkymistHpdmcState {
  49     SysBusDevice parent_obj;
  50
  51     MemoryRegion regs_region;
  52
  53     uint32_t regs[R_MAX];
  54 };
  55 typedef struct MilkymistHpdmcState MilkymistHpdmcState;
  56
  57 static uint64_t hpdmc_read(void *opaque, hwaddr addr,
  58                            unsigned size)
  59 {
  60     MilkymistHpdmcState *s = opaque;
  61     uint32_t r = 0;
  62
  63     addr >>= 2;
  64     switch (addr) {
  65     case R_SYSTEM:
  66     case R_BYPASS:
  67     case R_TIMING:
  68     case R_IODELAY:
  69         r = s->regs[addr];
  70         break;
  71
  72     default:
  73         error_report("milkymist_hpdmc: read access to unknown register 0x"
  74                 TARGET_FMT_plx, addr << 2);
  75         break;
  76     }
  77
  78     trace_milkymist_hpdmc_memory_read(addr << 2, r);
  79
  80     return r;
  81 }
  82
  83 static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value,
  84                         unsigned size)
  85 {
  86     MilkymistHpdmcState *s = opaque;
  87
  88     trace_milkymist_hpdmc_memory_write(addr, value);
  89
  90     addr >>= 2;
  91     switch (addr) {
  92     case R_SYSTEM:
  93     case R_BYPASS:
  94     case R_TIMING:
  95         s->regs[addr] = value;
  96         break;
  97     case R_IODELAY:
  98         /* ignore writes */
  99         break;
 100
 101     default:
 102         error_report("milkymist_hpdmc: write access to unknown register 0x"
 103                 TARGET_FMT_plx, addr << 2);
 104         break;
 105     }
 106 }
 107
 108 static const MemoryRegionOps hpdmc_mmio_ops = {
 109     .read = hpdmc_read,
 110     .write = hpdmc_write,
 111     .valid = {
 112         .min_access_size = 4,
 113         .max_access_size = 4,
 114     },
 115     .endianness = DEVICE_NATIVE_ENDIAN,
 116 };
 117
 118 static void milkymist_hpdmc_reset(DeviceState *d)
 119 {
 120     MilkymistHpdmcState *s = MILKYMIST_HPDMC(d);
 121     int i;
 122
 123     for (i = 0; i < R_MAX; i++) {
 124         s->regs[i] = 0;
 125     }
 126
 127     /* defaults */
 128     s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED
 129                          | IODELAY_PLL2_LOCKED;
 130 }
 131
 132 static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp)
 133 {
 134     MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev);
 135
 136     memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s,
 137             "milkymist-hpdmc", R_MAX * 4);
 138     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region);
 139 }
 140
 141 static const VMStateDescription vmstate_milkymist_hpdmc = {
 142     .name = "milkymist-hpdmc",
 143     .version_id = 1,
 144     .minimum_version_id = 1,
 145     .fields = (VMStateField[]) {
 146         VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX),
 147         VMSTATE_END_OF_LIST()
 148     }
 149 };
 150
 151 static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data)
 152 {
 153     DeviceClass *dc = DEVICE_CLASS(klass);
 154
 155     dc->realize = milkymist_hpdmc_realize;
 156     dc->reset = milkymist_hpdmc_reset;
 157     dc->vmsd = &vmstate_milkymist_hpdmc;
 158 }
 159
 160 static const TypeInfo milkymist_hpdmc_info = {
 161     .name          = TYPE_MILKYMIST_HPDMC,
 162     .parent        = TYPE_SYS_BUS_DEVICE,
 163     .instance_size = sizeof(MilkymistHpdmcState),
 164     .class_init    = milkymist_hpdmc_class_init,
 165 };
 166
 167 static void milkymist_hpdmc_register_types(void)
 168 {
 169     type_register_static(&milkymist_hpdmc_info);
 170 }
 171
 172 type_init(milkymist_hpdmc_register_types)