include/hw/ppc/mac_dbdma.h

   1 /*
   2  * Copyright (c) 2009 Laurent Vivier
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22 #ifndef HW_MAC_DBDMA_H
  23 #define HW_MAC_DBDMA_H 1
  24
  25 #include "exec/memory.h"
  26
  27 typedef struct DBDMA_io DBDMA_io;
  28
  29 typedef void (*DBDMA_flush)(DBDMA_io *io);
  30 typedef void (*DBDMA_rw)(DBDMA_io *io);
  31 typedef void (*DBDMA_end)(DBDMA_io *io);
  32 struct DBDMA_io {
  33     void *opaque;
  34     void *channel;
  35     hwaddr addr;
  36     int len;
  37     int is_last;
  38     int is_dma_out;
  39     DBDMA_end dma_end;
  40     /* DMA is in progress, don't start another one */
  41     bool processing;
  42     /* unaligned last sector of a request */
  43     uint8_t head_remainder[0x200];
  44     uint8_t tail_remainder[0x200];
  45     QEMUIOVector iov;
  46 };
  47
  48 /*
  49  * DBDMA control/status registers.  All little-endian.
  50  */
  51
  52 #define DBDMA_CONTROL         0x00
  53 #define DBDMA_STATUS          0x01
  54 #define DBDMA_CMDPTR_HI       0x02
  55 #define DBDMA_CMDPTR_LO       0x03
  56 #define DBDMA_INTR_SEL        0x04
  57 #define DBDMA_BRANCH_SEL      0x05
  58 #define DBDMA_WAIT_SEL        0x06
  59 #define DBDMA_XFER_MODE       0x07
  60 #define DBDMA_DATA2PTR_HI     0x08
  61 #define DBDMA_DATA2PTR_LO     0x09
  62 #define DBDMA_RES1            0x0A
  63 #define DBDMA_ADDRESS_HI      0x0B
  64 #define DBDMA_BRANCH_ADDR_HI  0x0C
  65 #define DBDMA_RES2            0x0D
  66 #define DBDMA_RES3            0x0E
  67 #define DBDMA_RES4            0x0F
  68
  69 #define DBDMA_REGS            16
  70 #define DBDMA_SIZE            (DBDMA_REGS * sizeof(uint32_t))
  71
  72 #define DBDMA_CHANNEL_SHIFT   7
  73 #define DBDMA_CHANNEL_SIZE    (1 << DBDMA_CHANNEL_SHIFT)
  74
  75 #define DBDMA_CHANNELS        (0x1000 >> DBDMA_CHANNEL_SHIFT)
  76
  77 /* Bits in control and status registers */
  78
  79 #define RUN        0x8000
  80 #define PAUSE      0x4000
  81 #define FLUSH      0x2000
  82 #define WAKE       0x1000
  83 #define DEAD       0x0800
  84 #define ACTIVE     0x0400
  85 #define BT         0x0100
  86 #define DEVSTAT    0x00ff
  87
  88 /*
  89  * DBDMA command structure.  These fields are all little-endian!
  90  */
  91
  92 typedef struct dbdma_cmd {
  93     uint16_t req_count;          /* requested byte transfer count */
  94     uint16_t command;            /* command word (has bit-fields) */
  95     uint32_t phy_addr;           /* physical data address */
  96     uint32_t cmd_dep;            /* command-dependent field */
  97     uint16_t res_count;          /* residual count after completion */
  98     uint16_t xfer_status;        /* transfer status */
  99 } dbdma_cmd;
 100
 101 /* DBDMA command values in command field */
 102
 103 #define COMMAND_MASK    0xf000
 104 #define OUTPUT_MORE     0x0000        /* transfer memory data to stream */
 105 #define OUTPUT_LAST     0x1000        /* ditto followed by end marker */
 106 #define INPUT_MORE      0x2000        /* transfer stream data to memory */
 107 #define INPUT_LAST      0x3000        /* ditto, expect end marker */
 108 #define STORE_WORD      0x4000        /* write word (4 bytes) to device reg */
 109 #define LOAD_WORD       0x5000        /* read word (4 bytes) from device reg */
 110 #define DBDMA_NOP       0x6000        /* do nothing */
 111 #define DBDMA_STOP      0x7000        /* suspend processing */
 112
 113 /* Key values in command field */
 114
 115 #define KEY_MASK        0x0700
 116 #define KEY_STREAM0     0x0000        /* usual data stream */
 117 #define KEY_STREAM1     0x0100        /* control/status stream */
 118 #define KEY_STREAM2     0x0200        /* device-dependent stream */
 119 #define KEY_STREAM3     0x0300        /* device-dependent stream */
 120 #define KEY_STREAM4     0x0400        /* reserved */
 121 #define KEY_REGS        0x0500        /* device register space */
 122 #define KEY_SYSTEM      0x0600        /* system memory-mapped space */
 123 #define KEY_DEVICE      0x0700        /* device memory-mapped space */
 124
 125 /* Interrupt control values in command field */
 126
 127 #define INTR_MASK       0x0030
 128 #define INTR_NEVER      0x0000        /* don't interrupt */
 129 #define INTR_IFSET      0x0010        /* intr if condition bit is 1 */
 130 #define INTR_IFCLR      0x0020        /* intr if condition bit is 0 */
 131 #define INTR_ALWAYS     0x0030        /* always interrupt */
 132
 133 /* Branch control values in command field */
 134
 135 #define BR_MASK         0x000c
 136 #define BR_NEVER        0x0000        /* don't branch */
 137 #define BR_IFSET        0x0004        /* branch if condition bit is 1 */
 138 #define BR_IFCLR        0x0008        /* branch if condition bit is 0 */
 139 #define BR_ALWAYS       0x000c        /* always branch */
 140
 141 /* Wait control values in command field */
 142
 143 #define WAIT_MASK       0x0003
 144 #define WAIT_NEVER      0x0000        /* don't wait */
 145 #define WAIT_IFSET      0x0001        /* wait if condition bit is 1 */
 146 #define WAIT_IFCLR      0x0002        /* wait if condition bit is 0 */
 147 #define WAIT_ALWAYS     0x0003        /* always wait */
 148
 149 typedef struct DBDMA_channel {
 150     int channel;
 151     uint32_t regs[DBDMA_REGS];
 152     qemu_irq irq;
 153     DBDMA_io io;
 154     DBDMA_rw rw;
 155     DBDMA_flush flush;
 156     dbdma_cmd current;
 157 } DBDMA_channel;
 158
 159 typedef struct {
 160     MemoryRegion mem;
 161     DBDMA_channel channels[DBDMA_CHANNELS];
 162     QEMUBH *bh;
 163 } DBDMAState;
 164
 165 /* Externally callable functions */
 166
 167 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
 168                             DBDMA_rw rw, DBDMA_flush flush,
 169                             void *opaque);
 170 void DBDMA_kick(DBDMAState *dbdma);
 171 void* DBDMA_init (MemoryRegion **dbdma_mem);
 172
 173 #endif