hw/net/xilinx_ethlite.c

   1 /*
   2  * QEMU model of the Xilinx Ethernet Lite MAC.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/hw.h"
  28 #include "net/net.h"
  29
  30 #define D(x)
  31 #define R_TX_BUF0     0
  32 #define R_TX_LEN0     (0x07f4 / 4)
  33 #define R_TX_GIE0     (0x07f8 / 4)
  34 #define R_TX_CTRL0    (0x07fc / 4)
  35 #define R_TX_BUF1     (0x0800 / 4)
  36 #define R_TX_LEN1     (0x0ff4 / 4)
  37 #define R_TX_CTRL1    (0x0ffc / 4)
  38
  39 #define R_RX_BUF0     (0x1000 / 4)
  40 #define R_RX_CTRL0    (0x17fc / 4)
  41 #define R_RX_BUF1     (0x1800 / 4)
  42 #define R_RX_CTRL1    (0x1ffc / 4)
  43 #define R_MAX         (0x2000 / 4)
  44
  45 #define GIE_GIE    0x80000000
  46
  47 #define CTRL_I     0x8
  48 #define CTRL_P     0x2
  49 #define CTRL_S     0x1
  50
  51 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
  52 #define XILINX_ETHLITE(obj) \
  53     OBJECT_CHECK(struct xlx_ethlite, (obj), TYPE_XILINX_ETHLITE)
  54
  55 struct xlx_ethlite
  56 {
  57     SysBusDevice parent_obj;
  58
  59     MemoryRegion mmio;
  60     qemu_irq irq;
  61     NICState *nic;
  62     NICConf conf;
  63
  64     uint32_t c_tx_pingpong;
  65     uint32_t c_rx_pingpong;
  66     unsigned int txbuf;
  67     unsigned int rxbuf;
  68
  69     uint32_t regs[R_MAX];
  70 };
  71
  72 static inline void eth_pulse_irq(struct xlx_ethlite *s)
  73 {
  74     /* Only the first gie reg is active.  */
  75     if (s->regs[R_TX_GIE0] & GIE_GIE) {
  76         qemu_irq_pulse(s->irq);
  77     }
  78 }
  79
  80 static uint64_t
  81 eth_read(void *opaque, hwaddr addr, unsigned int size)
  82 {
  83     struct xlx_ethlite *s = opaque;
  84     uint32_t r = 0;
  85
  86     addr >>= 2;
  87
  88     switch (addr)
  89     {
  90         case R_TX_GIE0:
  91         case R_TX_LEN0:
  92         case R_TX_LEN1:
  93         case R_TX_CTRL1:
  94         case R_TX_CTRL0:
  95         case R_RX_CTRL1:
  96         case R_RX_CTRL0:
  97             r = s->regs[addr];
  98             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
  99             break;
 100
 101         default:
 102             r = tswap32(s->regs[addr]);
 103             break;
 104     }
 105     return r;
 106 }
 107
 108 static void
 109 eth_write(void *opaque, hwaddr addr,
 110           uint64_t val64, unsigned int size)
 111 {
 112     struct xlx_ethlite *s = opaque;
 113     unsigned int base = 0;
 114     uint32_t value = val64;
 115
 116     addr >>= 2;
 117     switch (addr)
 118     {
 119         case R_TX_CTRL0:
 120         case R_TX_CTRL1:
 121             if (addr == R_TX_CTRL1)
 122                 base = 0x800 / 4;
 123
 124             D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
 125                        __func__, addr * 4, value));
 126             if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
 127                 qemu_send_packet(qemu_get_queue(s->nic),
 128                                  (void *) &s->regs[base],
 129                                  s->regs[base + R_TX_LEN0]);
 130                 D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
 131                 if (s->regs[base + R_TX_CTRL0] & CTRL_I)
 132                     eth_pulse_irq(s);
 133             } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
 134                 memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
 135                 if (s->regs[base + R_TX_CTRL0] & CTRL_I)
 136                     eth_pulse_irq(s);
 137             }
 138
 139             /* We are fast and get ready pretty much immediately so
 140                we actually never flip the S nor P bits to one.  */
 141             s->regs[addr] = value & ~(CTRL_P | CTRL_S);
 142             break;
 143
 144         /* Keep these native.  */
 145         case R_RX_CTRL0:
 146         case R_RX_CTRL1:
 147             if (!(value & CTRL_S)) {
 148                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 149             }
 150             /* fall through */
 151         case R_TX_LEN0:
 152         case R_TX_LEN1:
 153         case R_TX_GIE0:
 154             D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
 155                        __func__, addr * 4, value));
 156             s->regs[addr] = value;
 157             break;
 158
 159         default:
 160             s->regs[addr] = tswap32(value);
 161             break;
 162     }
 163 }
 164
 165 static const MemoryRegionOps eth_ops = {
 166     .read = eth_read,
 167     .write = eth_write,
 168     .endianness = DEVICE_NATIVE_ENDIAN,
 169     .valid = {
 170         .min_access_size = 4,
 171         .max_access_size = 4
 172     }
 173 };
 174
 175 static int eth_can_rx(NetClientState *nc)
 176 {
 177     struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
 178     unsigned int rxbase = s->rxbuf * (0x800 / 4);
 179
 180     return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
 181 }
 182
 183 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 184 {
 185     struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
 186     unsigned int rxbase = s->rxbuf * (0x800 / 4);
 187
 188     /* DA filter.  */
 189     if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
 190         return size;
 191
 192     if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
 193         D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
 194         return -1;
 195     }
 196
 197     D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
 198     memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
 199
 200     s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
 201     if (s->regs[R_RX_CTRL0] & CTRL_I) {
 202         eth_pulse_irq(s);
 203     }
 204
 205     /* If c_rx_pingpong was set flip buffers.  */
 206     s->rxbuf ^= s->c_rx_pingpong;
 207     return size;
 208 }
 209
 210 static void xilinx_ethlite_reset(DeviceState *dev)
 211 {
 212     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
 213
 214     s->rxbuf = 0;
 215 }
 216
 217 static NetClientInfo net_xilinx_ethlite_info = {
 218     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 219     .size = sizeof(NICState),
 220     .can_receive = eth_can_rx,
 221     .receive = eth_rx,
 222 };
 223
 224 static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
 225 {
 226     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
 227
 228     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 229     s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
 230                           object_get_typename(OBJECT(dev)), dev->id, s);
 231     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 232 }
 233
 234 static void xilinx_ethlite_init(Object *obj)
 235 {
 236     struct xlx_ethlite *s = XILINX_ETHLITE(obj);
 237
 238     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 239
 240     memory_region_init_io(&s->mmio, obj, &eth_ops, s,
 241                           "xlnx.xps-ethernetlite", R_MAX * 4);
 242     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 243 }
 244
 245 static Property xilinx_ethlite_properties[] = {
 246     DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
 247     DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
 248     DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
 249     DEFINE_PROP_END_OF_LIST(),
 250 };
 251
 252 static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
 253 {
 254     DeviceClass *dc = DEVICE_CLASS(klass);
 255
 256     dc->realize = xilinx_ethlite_realize;
 257     dc->reset = xilinx_ethlite_reset;
 258     dc->props = xilinx_ethlite_properties;
 259 }
 260
 261 static const TypeInfo xilinx_ethlite_info = {
 262     .name          = TYPE_XILINX_ETHLITE,
 263     .parent        = TYPE_SYS_BUS_DEVICE,
 264     .instance_size = sizeof(struct xlx_ethlite),
 265     .instance_init = xilinx_ethlite_init,
 266     .class_init    = xilinx_ethlite_class_init,
 267 };
 268
 269 static void xilinx_ethlite_register_types(void)
 270 {
 271     type_register_static(&xilinx_ethlite_info);
 272 }
 273
 274 type_init(xilinx_ethlite_register_types)