hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "qemu/osdep.h"
  22 #include "hw/hw.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/isa/apm.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/acpi/acpi.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qemu/range.h"
  30 #include "exec/ioport.h"
  31 #include "hw/nvram/fw_cfg.h"
  32 #include "exec/address-spaces.h"
  33 #include "hw/acpi/piix4.h"
  34 #include "hw/acpi/pcihp.h"
  35 #include "hw/acpi/cpu_hotplug.h"
  36 #include "hw/hotplug.h"
  37 #include "hw/mem/pc-dimm.h"
  38 #include "hw/acpi/memory_hotplug.h"
  39 #include "hw/acpi/acpi_dev_interface.h"
  40 #include "hw/xen/xen.h"
  41
  42 //#define DEBUG
  43
  44 #ifdef DEBUG
  45 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  46 #else
  47 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  48 #endif
  49
  50 #define GPE_BASE 0xafe0
  51 #define GPE_LEN 4
  52
  53 struct pci_status {
  54     uint32_t up; /* deprecated, maintained for migration compatibility */
  55     uint32_t down;
  56 };
  57
  58 typedef struct PIIX4PMState {
  59     /*< private >*/
  60     PCIDevice parent_obj;
  61     /*< public >*/
  62
  63     MemoryRegion io;
  64     uint32_t io_base;
  65
  66     MemoryRegion io_gpe;
  67     ACPIREGS ar;
  68
  69     APMState apm;
  70
  71     PMSMBus smb;
  72     uint32_t smb_io_base;
  73
  74     qemu_irq irq;
  75     qemu_irq smi_irq;
  76     int smm_enabled;
  77     Notifier machine_ready;
  78     Notifier powerdown_notifier;
  79
  80     AcpiPciHpState acpi_pci_hotplug;
  81     bool use_acpi_pci_hotplug;
  82
  83     uint8_t disable_s3;
  84     uint8_t disable_s4;
  85     uint8_t s4_val;
  86
  87     AcpiCpuHotplug gpe_cpu;
  88
  89     MemHotplugState acpi_memory_hotplug;
  90 } PIIX4PMState;
  91
  92 #define TYPE_PIIX4_PM "PIIX4_PM"
  93
  94 #define PIIX4_PM(obj) \
  95     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  96
  97 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  98                                            PCIBus *bus, PIIX4PMState *s);
  99
 100 #define ACPI_ENABLE 0xf1
 101 #define ACPI_DISABLE 0xf0
 102
 103 static void pm_tmr_timer(ACPIREGS *ar)
 104 {
 105     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 106     acpi_update_sci(&s->ar, s->irq);
 107 }
 108
 109 static void apm_ctrl_changed(uint32_t val, void *arg)
 110 {
 111     PIIX4PMState *s = arg;
 112     PCIDevice *d = PCI_DEVICE(s);
 113
 114     /* ACPI specs 3.0, 4.7.2.5 */
 115     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 116     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 117         return;
 118     }
 119
 120     if (d->config[0x5b] & (1 << 1)) {
 121         if (s->smi_irq) {
 122             qemu_irq_raise(s->smi_irq);
 123         }
 124     }
 125 }
 126
 127 static void pm_io_space_update(PIIX4PMState *s)
 128 {
 129     PCIDevice *d = PCI_DEVICE(s);
 130
 131     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 132     s->io_base &= 0xffc0;
 133
 134     memory_region_transaction_begin();
 135     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 136     memory_region_set_address(&s->io, s->io_base);
 137     memory_region_transaction_commit();
 138 }
 139
 140 static void smbus_io_space_update(PIIX4PMState *s)
 141 {
 142     PCIDevice *d = PCI_DEVICE(s);
 143
 144     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 145     s->smb_io_base &= 0xffc0;
 146
 147     memory_region_transaction_begin();
 148     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 149     memory_region_set_address(&s->smb.io, s->smb_io_base);
 150     memory_region_transaction_commit();
 151 }
 152
 153 static void pm_write_config(PCIDevice *d,
 154                             uint32_t address, uint32_t val, int len)
 155 {
 156     pci_default_write_config(d, address, val, len);
 157     if (range_covers_byte(address, len, 0x80) ||
 158         ranges_overlap(address, len, 0x40, 4)) {
 159         pm_io_space_update((PIIX4PMState *)d);
 160     }
 161     if (range_covers_byte(address, len, 0xd2) ||
 162         ranges_overlap(address, len, 0x90, 4)) {
 163         smbus_io_space_update((PIIX4PMState *)d);
 164     }
 165 }
 166
 167 static int vmstate_acpi_post_load(void *opaque, int version_id)
 168 {
 169     PIIX4PMState *s = opaque;
 170
 171     pm_io_space_update(s);
 172     return 0;
 173 }
 174
 175 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 176  {                                                                   \
 177      .name       = (stringify(_field)),                              \
 178      .version_id = 0,                                                \
 179      .info       = &vmstate_info_uint16,                             \
 180      .size       = sizeof(uint16_t),                                 \
 181      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 182      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 183  }
 184
 185 static const VMStateDescription vmstate_gpe = {
 186     .name = "gpe",
 187     .version_id = 1,
 188     .minimum_version_id = 1,
 189     .fields = (VMStateField[]) {
 190         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 191         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 192         VMSTATE_END_OF_LIST()
 193     }
 194 };
 195
 196 static const VMStateDescription vmstate_pci_status = {
 197     .name = "pci_status",
 198     .version_id = 1,
 199     .minimum_version_id = 1,
 200     .fields = (VMStateField[]) {
 201         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 202         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 203         VMSTATE_END_OF_LIST()
 204     }
 205 };
 206
 207 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 208 {
 209     PIIX4PMState *s = opaque;
 210     int ret, i;
 211     uint16_t temp;
 212
 213     ret = pci_device_load(PCI_DEVICE(s), f);
 214     if (ret < 0) {
 215         return ret;
 216     }
 217     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 218     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 219     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 220
 221     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 222     if (ret) {
 223         return ret;
 224     }
 225
 226     timer_get(f, s->ar.tmr.timer);
 227     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 228
 229     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 230     for (i = 0; i < 3; i++) {
 231         qemu_get_be16s(f, &temp);
 232     }
 233
 234     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 235     for (i = 0; i < 3; i++) {
 236         qemu_get_be16s(f, &temp);
 237     }
 238
 239     ret = vmstate_load_state(f, &vmstate_pci_status,
 240         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 241     return ret;
 242 }
 243
 244 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 245 {
 246     PIIX4PMState *s = opaque;
 247     return s->use_acpi_pci_hotplug;
 248 }
 249
 250 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 251 {
 252     PIIX4PMState *s = opaque;
 253     return !s->use_acpi_pci_hotplug;
 254 }
 255
 256 static bool vmstate_test_use_memhp(void *opaque)
 257 {
 258     PIIX4PMState *s = opaque;
 259     return s->acpi_memory_hotplug.is_enabled;
 260 }
 261
 262 static const VMStateDescription vmstate_memhp_state = {
 263     .name = "piix4_pm/memhp",
 264     .version_id = 1,
 265     .minimum_version_id = 1,
 266     .minimum_version_id_old = 1,
 267     .needed = vmstate_test_use_memhp,
 268     .fields      = (VMStateField[]) {
 269         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 270         VMSTATE_END_OF_LIST()
 271     }
 272 };
 273
 274 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 275  * To support incoming qemu-kvm 1.2 migration, change version_id
 276  * and minimum_version_id to 2 below (which breaks migration from
 277  * qemu 1.2).
 278  *
 279  */
 280 static const VMStateDescription vmstate_acpi = {
 281     .name = "piix4_pm",
 282     .version_id = 3,
 283     .minimum_version_id = 3,
 284     .minimum_version_id_old = 1,
 285     .load_state_old = acpi_load_old,
 286     .post_load = vmstate_acpi_post_load,
 287     .fields = (VMStateField[]) {
 288         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 289         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 290         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 291         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 292         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 293         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 294         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 295         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 296         VMSTATE_STRUCT_TEST(
 297             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 298             PIIX4PMState,
 299             vmstate_test_no_use_acpi_pci_hotplug,
 300             2, vmstate_pci_status,
 301             struct AcpiPciHpPciStatus),
 302         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 303                             vmstate_test_use_acpi_pci_hotplug),
 304         VMSTATE_END_OF_LIST()
 305     },
 306     .subsections = (const VMStateDescription*[]) {
 307          &vmstate_memhp_state,
 308          NULL
 309     }
 310 };
 311
 312 static void piix4_reset(void *opaque)
 313 {
 314     PIIX4PMState *s = opaque;
 315     PCIDevice *d = PCI_DEVICE(s);
 316     uint8_t *pci_conf = d->config;
 317
 318     pci_conf[0x58] = 0;
 319     pci_conf[0x59] = 0;
 320     pci_conf[0x5a] = 0;
 321     pci_conf[0x5b] = 0;
 322
 323     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 324     pci_conf[0x80] = 0;
 325
 326     if (!s->smm_enabled) {
 327         /* Mark SMM as already inited (until KVM supports SMM). */
 328         pci_conf[0x5B] = 0x02;
 329     }
 330     pm_io_space_update(s);
 331     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 332 }
 333
 334 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 335 {
 336     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 337
 338     assert(s != NULL);
 339     acpi_pm1_evt_power_down(&s->ar);
 340 }
 341
 342 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 343                                  DeviceState *dev, Error **errp)
 344 {
 345     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 346
 347     if (s->acpi_memory_hotplug.is_enabled &&
 348         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 349         acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp);
 350     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 351         acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 352                                   errp);
 353     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 354         acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp);
 355     } else {
 356         error_setg(errp, "acpi: device plug request for not supported device"
 357                    " type: %s", object_get_typename(OBJECT(dev)));
 358     }
 359 }
 360
 361 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 362                                            DeviceState *dev, Error **errp)
 363 {
 364     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 365
 366     if (s->acpi_memory_hotplug.is_enabled &&
 367         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 368         acpi_memory_unplug_request_cb(&s->ar, s->irq, &s->acpi_memory_hotplug,
 369                                       dev, errp);
 370     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 371         acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 372                                     errp);
 373     } else {
 374         error_setg(errp, "acpi: device unplug request for not supported device"
 375                    " type: %s", object_get_typename(OBJECT(dev)));
 376     }
 377 }
 378
 379 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 380                                    DeviceState *dev, Error **errp)
 381 {
 382     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 383
 384     if (s->acpi_memory_hotplug.is_enabled &&
 385         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 386         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 387     } else {
 388         error_setg(errp, "acpi: device unplug for not supported device"
 389                    " type: %s", object_get_typename(OBJECT(dev)));
 390     }
 391 }
 392
 393 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 394 {
 395     PIIX4PMState *s = opaque;
 396
 397     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 398 }
 399
 400 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 401 {
 402     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 403     PCIDevice *d = PCI_DEVICE(s);
 404     MemoryRegion *io_as = pci_address_space_io(d);
 405     uint8_t *pci_conf;
 406
 407     pci_conf = d->config;
 408     pci_conf[0x5f] = 0x10 |
 409         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 410     pci_conf[0x63] = 0x60;
 411     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 412         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 413
 414     if (s->use_acpi_pci_hotplug) {
 415         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 416     } else {
 417         piix4_update_bus_hotplug(d->bus, s);
 418     }
 419 }
 420
 421 static void piix4_pm_add_propeties(PIIX4PMState *s)
 422 {
 423     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 424     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 425     static const uint32_t gpe0_blk = GPE_BASE;
 426     static const uint32_t gpe0_blk_len = GPE_LEN;
 427     static const uint16_t sci_int = 9;
 428
 429     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 430                                   &acpi_enable_cmd, NULL);
 431     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 432                                   &acpi_disable_cmd, NULL);
 433     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 434                                   &gpe0_blk, NULL);
 435     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 436                                   &gpe0_blk_len, NULL);
 437     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 438                                   &sci_int, NULL);
 439     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 440                                   &s->io_base, NULL);
 441 }
 442
 443 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 444 {
 445     PIIX4PMState *s = PIIX4_PM(dev);
 446     uint8_t *pci_conf;
 447
 448     pci_conf = dev->config;
 449     pci_conf[0x06] = 0x80;
 450     pci_conf[0x07] = 0x02;
 451     pci_conf[0x09] = 0x00;
 452     pci_conf[0x3d] = 0x01; // interrupt pin 1
 453
 454     /* APM */
 455     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 456
 457     if (!s->smm_enabled) {
 458         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 459          * support SMM mode. */
 460         pci_conf[0x5B] = 0x02;
 461     }
 462
 463     /* XXX: which specification is used ? The i82731AB has different
 464        mappings */
 465     pci_conf[0x90] = s->smb_io_base | 1;
 466     pci_conf[0x91] = s->smb_io_base >> 8;
 467     pci_conf[0xd2] = 0x09;
 468     pm_smbus_init(DEVICE(dev), &s->smb);
 469     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 470     memory_region_add_subregion(pci_address_space_io(dev),
 471                                 s->smb_io_base, &s->smb.io);
 472
 473     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 474     memory_region_set_enabled(&s->io, false);
 475     memory_region_add_subregion(pci_address_space_io(dev),
 476                                 0, &s->io);
 477
 478     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 479     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 480     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 481     acpi_gpe_init(&s->ar, GPE_LEN);
 482
 483     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 484     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 485
 486     s->machine_ready.notify = piix4_pm_machine_ready;
 487     qemu_add_machine_init_done_notifier(&s->machine_ready);
 488     qemu_register_reset(piix4_reset, s);
 489
 490     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 491
 492     piix4_pm_add_propeties(s);
 493 }
 494
 495 Object *piix4_pm_find(void)
 496 {
 497     bool ambig;
 498     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 499
 500     if (ambig || !o) {
 501         return NULL;
 502     }
 503     return o;
 504 }
 505
 506 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 507                       qemu_irq sci_irq, qemu_irq smi_irq,
 508                       int smm_enabled, DeviceState **piix4_pm)
 509 {
 510     DeviceState *dev;
 511     PIIX4PMState *s;
 512
 513     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 514     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 515     if (piix4_pm) {
 516         *piix4_pm = dev;
 517     }
 518
 519     s = PIIX4_PM(dev);
 520     s->irq = sci_irq;
 521     s->smi_irq = smi_irq;
 522     s->smm_enabled = smm_enabled;
 523     if (xen_enabled()) {
 524         s->use_acpi_pci_hotplug = false;
 525     }
 526
 527     qdev_init_nofail(dev);
 528
 529     return s->smb.smbus;
 530 }
 531
 532 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 533 {
 534     PIIX4PMState *s = opaque;
 535     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 536
 537     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 538     return val;
 539 }
 540
 541 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 542                        unsigned width)
 543 {
 544     PIIX4PMState *s = opaque;
 545
 546     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 547     acpi_update_sci(&s->ar, s->irq);
 548
 549     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 550 }
 551
 552 static const MemoryRegionOps piix4_gpe_ops = {
 553     .read = gpe_readb,
 554     .write = gpe_writeb,
 555     .valid.min_access_size = 1,
 556     .valid.max_access_size = 4,
 557     .impl.min_access_size = 1,
 558     .impl.max_access_size = 1,
 559     .endianness = DEVICE_LITTLE_ENDIAN,
 560 };
 561
 562 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 563                                            PCIBus *bus, PIIX4PMState *s)
 564 {
 565     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 566                           "acpi-gpe0", GPE_LEN);
 567     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 568
 569     acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 570                     s->use_acpi_pci_hotplug);
 571
 572     acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 573                           PIIX4_CPU_HOTPLUG_IO_BASE);
 574
 575     if (s->acpi_memory_hotplug.is_enabled) {
 576         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug);
 577     }
 578 }
 579
 580 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 581 {
 582     PIIX4PMState *s = PIIX4_PM(adev);
 583
 584     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 585 }
 586
 587 static Property piix4_pm_properties[] = {
 588     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 589     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 590     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 591     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 592     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 593                      use_acpi_pci_hotplug, true),
 594     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 595                      acpi_memory_hotplug.is_enabled, true),
 596     DEFINE_PROP_END_OF_LIST(),
 597 };
 598
 599 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 600 {
 601     DeviceClass *dc = DEVICE_CLASS(klass);
 602     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 603     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 604     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 605
 606     k->realize = piix4_pm_realize;
 607     k->config_write = pm_write_config;
 608     k->vendor_id = PCI_VENDOR_ID_INTEL;
 609     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 610     k->revision = 0x03;
 611     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 612     dc->desc = "PM";
 613     dc->vmsd = &vmstate_acpi;
 614     dc->props = piix4_pm_properties;
 615     /*
 616      * Reason: part of PIIX4 southbridge, needs to be wired up,
 617      * e.g. by mips_malta_init()
 618      */
 619     dc->cannot_instantiate_with_device_add_yet = true;
 620     dc->hotpluggable = false;
 621     hc->plug = piix4_device_plug_cb;
 622     hc->unplug_request = piix4_device_unplug_request_cb;
 623     hc->unplug = piix4_device_unplug_cb;
 624     adevc->ospm_status = piix4_ospm_status;
 625 }
 626
 627 static const TypeInfo piix4_pm_info = {
 628     .name          = TYPE_PIIX4_PM,
 629     .parent        = TYPE_PCI_DEVICE,
 630     .instance_size = sizeof(PIIX4PMState),
 631     .class_init    = piix4_pm_class_init,
 632     .interfaces = (InterfaceInfo[]) {
 633         { TYPE_HOTPLUG_HANDLER },
 634         { TYPE_ACPI_DEVICE_IF },
 635         { }
 636     }
 637 };
 638
 639 static void piix4_pm_register_types(void)
 640 {
 641     type_register_static(&piix4_pm_info);
 642 }
 643
 644 type_init(piix4_pm_register_types)