2 * Faraday FTGMAC100 Gigabit Ethernet
4 * Copyright (C) 2016-2017, IBM Corporation.
6 * Based on Coldfire Fast Ethernet Controller emulation.
8 * Copyright (c) 2007 CodeSourcery.
10 * This code is licensed under the GPL version 2 or later. See the
11 * COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
16 #include "hw/net/ftgmac100.h"
17 #include "sysemu/dma.h"
18 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "net/checksum.h"
23 #include "hw/net/mii.h"
24 #include "hw/qdev-properties.h"
25 #include "migration/vmstate.h"
33 #define FTGMAC100_ISR 0x00
34 #define FTGMAC100_IER 0x04
35 #define FTGMAC100_MAC_MADR 0x08
36 #define FTGMAC100_MAC_LADR 0x0c
37 #define FTGMAC100_MATH0 0x10
38 #define FTGMAC100_MATH1 0x14
39 #define FTGMAC100_NPTXPD 0x18
40 #define FTGMAC100_RXPD 0x1C
41 #define FTGMAC100_NPTXR_BADR 0x20
42 #define FTGMAC100_RXR_BADR 0x24
43 #define FTGMAC100_HPTXPD 0x28
44 #define FTGMAC100_HPTXR_BADR 0x2c
45 #define FTGMAC100_ITC 0x30
46 #define FTGMAC100_APTC 0x34
47 #define FTGMAC100_DBLAC 0x38
48 #define FTGMAC100_REVR 0x40
49 #define FTGMAC100_FEAR1 0x44
50 #define FTGMAC100_RBSR 0x4c
51 #define FTGMAC100_TPAFCR 0x48
53 #define FTGMAC100_MACCR 0x50
54 #define FTGMAC100_MACSR 0x54
55 #define FTGMAC100_PHYCR 0x60
56 #define FTGMAC100_PHYDATA 0x64
57 #define FTGMAC100_FCR 0x68
60 * Interrupt status register & interrupt enable register
62 #define FTGMAC100_INT_RPKT_BUF (1 << 0)
63 #define FTGMAC100_INT_RPKT_FIFO (1 << 1)
64 #define FTGMAC100_INT_NO_RXBUF (1 << 2)
65 #define FTGMAC100_INT_RPKT_LOST (1 << 3)
66 #define FTGMAC100_INT_XPKT_ETH (1 << 4)
67 #define FTGMAC100_INT_XPKT_FIFO (1 << 5)
68 #define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
69 #define FTGMAC100_INT_XPKT_LOST (1 << 7)
70 #define FTGMAC100_INT_AHB_ERR (1 << 8)
71 #define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
72 #define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
75 * Automatic polling timer control register
77 #define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf)
78 #define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
79 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf)
80 #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
83 * PHY control register
85 #define FTGMAC100_PHYCR_MIIRD (1 << 26)
86 #define FTGMAC100_PHYCR_MIIWR (1 << 27)
88 #define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f)
89 #define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f)
94 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
95 #define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff)
98 * PHY control register - New MDC/MDIO interface
100 #define FTGMAC100_PHYCR_NEW_DATA(x) (((x) >> 16) & 0xffff)
101 #define FTGMAC100_PHYCR_NEW_FIRE (1 << 15)
102 #define FTGMAC100_PHYCR_NEW_ST_22 (1 << 12)
103 #define FTGMAC100_PHYCR_NEW_OP(x) (((x) >> 10) & 3)
104 #define FTGMAC100_PHYCR_NEW_OP_WRITE 0x1
105 #define FTGMAC100_PHYCR_NEW_OP_READ 0x2
106 #define FTGMAC100_PHYCR_NEW_DEV(x) (((x) >> 5) & 0x1f)
107 #define FTGMAC100_PHYCR_NEW_REG(x) ((x) & 0x1f)
112 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31)
115 * MAC control register
117 #define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
118 #define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
119 #define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
120 #define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
121 #define FTGMAC100_MACCR_RM_VLAN (1 << 4)
122 #define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
123 #define FTGMAC100_MACCR_LOOP_EN (1 << 6)
124 #define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
125 #define FTGMAC100_MACCR_FULLDUP (1 << 8)
126 #define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
127 #define FTGMAC100_MACCR_CRC_APD (1 << 10) /* not needed */
128 #define FTGMAC100_MACCR_RX_RUNT (1 << 12)
129 #define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
130 #define FTGMAC100_MACCR_RX_ALL (1 << 14)
131 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
132 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
133 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
134 #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
135 #define FTGMAC100_MACCR_FAST_MODE (1 << 19)
136 #define FTGMAC100_MACCR_SW_RST (1 << 31)
139 * Transmit descriptor
141 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
142 #define FTGMAC100_TXDES0_EDOTR (1 << 15)
143 #define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
144 #define FTGMAC100_TXDES0_LTS (1 << 28)
145 #define FTGMAC100_TXDES0_FTS (1 << 29)
146 #define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30)
147 #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
149 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
150 #define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
151 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
152 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
153 #define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
154 #define FTGMAC100_TXDES1_LLC (1 << 22)
155 #define FTGMAC100_TXDES1_TX2FIC (1 << 30)
156 #define FTGMAC100_TXDES1_TXIC (1 << 31)
161 #define FTGMAC100_RXDES0_VDBC 0x3fff
162 #define FTGMAC100_RXDES0_EDORR (1 << 15)
163 #define FTGMAC100_RXDES0_MULTICAST (1 << 16)
164 #define FTGMAC100_RXDES0_BROADCAST (1 << 17)
165 #define FTGMAC100_RXDES0_RX_ERR (1 << 18)
166 #define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
167 #define FTGMAC100_RXDES0_FTL (1 << 20)
168 #define FTGMAC100_RXDES0_RUNT (1 << 21)
169 #define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
170 #define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
171 #define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
172 #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
173 #define FTGMAC100_RXDES0_LRS (1 << 28)
174 #define FTGMAC100_RXDES0_FRS (1 << 29)
175 #define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30)
176 #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
178 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
179 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
180 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
181 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
182 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
183 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
184 #define FTGMAC100_RXDES1_LLC (1 << 22)
185 #define FTGMAC100_RXDES1_DF (1 << 23)
186 #define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
187 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
188 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
189 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
192 * Receive and transmit Buffer Descriptor
197 uint32_t des2
; /* not used by HW */
201 #define FTGMAC100_DESC_ALIGNMENT 16
204 * Specific RTL8211E MII Registers
206 #define RTL8211E_MII_PHYCR 16 /* PHY Specific Control */
207 #define RTL8211E_MII_PHYSR 17 /* PHY Specific Status */
208 #define RTL8211E_MII_INER 18 /* Interrupt Enable */
209 #define RTL8211E_MII_INSR 19 /* Interrupt Status */
210 #define RTL8211E_MII_RXERC 24 /* Receive Error Counter */
211 #define RTL8211E_MII_LDPSR 27 /* Link Down Power Saving */
212 #define RTL8211E_MII_EPAGSR 30 /* Extension Page Select */
213 #define RTL8211E_MII_PAGSEL 31 /* Page Select */
216 * RTL8211E Interrupt Status
218 #define PHY_INT_AUTONEG_ERROR (1 << 15)
219 #define PHY_INT_PAGE_RECV (1 << 12)
220 #define PHY_INT_AUTONEG_COMPLETE (1 << 11)
221 #define PHY_INT_LINK_STATUS (1 << 10)
222 #define PHY_INT_ERROR (1 << 9)
223 #define PHY_INT_DOWN (1 << 8)
224 #define PHY_INT_JABBER (1 << 0)
227 * Max frame size for the receiving buffer
229 #define FTGMAC100_MAX_FRAME_SIZE 9220
231 /* Limits depending on the type of the frame
233 * 9216 for Jumbo frames (+ 4 for VLAN)
234 * 1518 for other frames (+ 4 for VLAN)
236 static int ftgmac100_max_frame_size(FTGMAC100State
*s
, uint16_t proto
)
238 int max
= (s
->maccr
& FTGMAC100_MACCR_JUMBO_LF
? 9216 : 1518);
240 return max
+ (proto
== ETH_P_VLAN
? 4 : 0);
243 static void ftgmac100_update_irq(FTGMAC100State
*s
)
245 qemu_set_irq(s
->irq
, s
->isr
& s
->ier
);
249 * The MII phy could raise a GPIO to the processor which in turn
250 * could be handled as an interrpt by the OS.
251 * For now we don't handle any GPIO/interrupt line, so the OS will
252 * have to poll for the PHY status.
254 static void phy_update_irq(FTGMAC100State
*s
)
256 ftgmac100_update_irq(s
);
259 static void phy_update_link(FTGMAC100State
*s
)
261 /* Autonegotiation status mirrors link status. */
262 if (qemu_get_queue(s
->nic
)->link_down
) {
263 s
->phy_status
&= ~(MII_BMSR_LINK_ST
| MII_BMSR_AN_COMP
);
264 s
->phy_int
|= PHY_INT_DOWN
;
266 s
->phy_status
|= (MII_BMSR_LINK_ST
| MII_BMSR_AN_COMP
);
267 s
->phy_int
|= PHY_INT_AUTONEG_COMPLETE
;
272 static void ftgmac100_set_link(NetClientState
*nc
)
274 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc
)));
277 static void phy_reset(FTGMAC100State
*s
)
279 s
->phy_status
= (MII_BMSR_100TX_FD
| MII_BMSR_100TX_HD
| MII_BMSR_10T_FD
|
280 MII_BMSR_10T_HD
| MII_BMSR_EXTSTAT
| MII_BMSR_MFPS
|
281 MII_BMSR_AN_COMP
| MII_BMSR_AUTONEG
| MII_BMSR_LINK_ST
|
283 s
->phy_control
= (MII_BMCR_AUTOEN
| MII_BMCR_FD
| MII_BMCR_SPEED1000
);
284 s
->phy_advertise
= (MII_ANAR_PAUSE_ASYM
| MII_ANAR_PAUSE
| MII_ANAR_TXFD
|
285 MII_ANAR_TX
| MII_ANAR_10FD
| MII_ANAR_10
|
291 static uint16_t do_phy_read(FTGMAC100State
*s
, uint8_t reg
)
296 case MII_BMCR
: /* Basic Control */
297 val
= s
->phy_control
;
299 case MII_BMSR
: /* Basic Status */
302 case MII_PHYID1
: /* ID1 */
303 val
= RTL8211E_PHYID1
;
305 case MII_PHYID2
: /* ID2 */
306 val
= RTL8211E_PHYID2
;
308 case MII_ANAR
: /* Auto-neg advertisement */
309 val
= s
->phy_advertise
;
311 case MII_ANLPAR
: /* Auto-neg Link Partner Ability */
312 val
= (MII_ANLPAR_ACK
| MII_ANLPAR_PAUSE
| MII_ANLPAR_TXFD
|
313 MII_ANLPAR_TX
| MII_ANLPAR_10FD
| MII_ANLPAR_10
|
316 case MII_ANER
: /* Auto-neg Expansion */
319 case MII_CTRL1000
: /* 1000BASE-T control */
320 val
= (MII_CTRL1000_HALF
| MII_CTRL1000_FULL
);
322 case MII_STAT1000
: /* 1000BASE-T status */
323 val
= MII_STAT1000_FULL
;
325 case RTL8211E_MII_INSR
: /* Interrupt status. */
330 case RTL8211E_MII_INER
: /* Interrupt enable */
331 val
= s
->phy_int_mask
;
333 case RTL8211E_MII_PHYCR
:
334 case RTL8211E_MII_PHYSR
:
335 case RTL8211E_MII_RXERC
:
336 case RTL8211E_MII_LDPSR
:
337 case RTL8211E_MII_EPAGSR
:
338 case RTL8211E_MII_PAGSEL
:
339 qemu_log_mask(LOG_UNIMP
, "%s: reg %d not implemented\n",
344 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset %d\n",
353 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \
354 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
355 MII_BMCR_FD | MII_BMCR_CTST)
356 #define MII_ANAR_MASK 0x2d7f
358 static void do_phy_write(FTGMAC100State
*s
, uint8_t reg
, uint16_t val
)
361 case MII_BMCR
: /* Basic Control */
362 if (val
& MII_BMCR_RESET
) {
365 s
->phy_control
= val
& MII_BMCR_MASK
;
366 /* Complete autonegotiation immediately. */
367 if (val
& MII_BMCR_AUTOEN
) {
368 s
->phy_status
|= MII_BMSR_AN_COMP
;
372 case MII_ANAR
: /* Auto-neg advertisement */
373 s
->phy_advertise
= (val
& MII_ANAR_MASK
) | MII_ANAR_TX
;
375 case RTL8211E_MII_INER
: /* Interrupt enable */
376 s
->phy_int_mask
= val
& 0xff;
379 case RTL8211E_MII_PHYCR
:
380 case RTL8211E_MII_PHYSR
:
381 case RTL8211E_MII_RXERC
:
382 case RTL8211E_MII_LDPSR
:
383 case RTL8211E_MII_EPAGSR
:
384 case RTL8211E_MII_PAGSEL
:
385 qemu_log_mask(LOG_UNIMP
, "%s: reg %d not implemented\n",
389 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset %d\n",
395 static void do_phy_new_ctl(FTGMAC100State
*s
)
400 if (!(s
->phycr
& FTGMAC100_PHYCR_NEW_ST_22
)) {
401 qemu_log_mask(LOG_UNIMP
, "%s: unsupported ST code\n", __func__
);
406 if (!(s
->phycr
& FTGMAC100_PHYCR_NEW_FIRE
)) {
410 reg
= FTGMAC100_PHYCR_NEW_REG(s
->phycr
);
411 data
= FTGMAC100_PHYCR_NEW_DATA(s
->phycr
);
413 switch (FTGMAC100_PHYCR_NEW_OP(s
->phycr
)) {
414 case FTGMAC100_PHYCR_NEW_OP_WRITE
:
415 do_phy_write(s
, reg
, data
);
417 case FTGMAC100_PHYCR_NEW_OP_READ
:
418 s
->phydata
= do_phy_read(s
, reg
) & 0xffff;
421 qemu_log_mask(LOG_GUEST_ERROR
, "%s: invalid OP code %08x\n",
425 s
->phycr
&= ~FTGMAC100_PHYCR_NEW_FIRE
;
428 static void do_phy_ctl(FTGMAC100State
*s
)
430 uint8_t reg
= FTGMAC100_PHYCR_REG(s
->phycr
);
432 if (s
->phycr
& FTGMAC100_PHYCR_MIIWR
) {
433 do_phy_write(s
, reg
, s
->phydata
& 0xffff);
434 s
->phycr
&= ~FTGMAC100_PHYCR_MIIWR
;
435 } else if (s
->phycr
& FTGMAC100_PHYCR_MIIRD
) {
436 s
->phydata
= do_phy_read(s
, reg
) << 16;
437 s
->phycr
&= ~FTGMAC100_PHYCR_MIIRD
;
439 qemu_log_mask(LOG_GUEST_ERROR
, "%s: no OP code %08x\n",
444 static int ftgmac100_read_bd(FTGMAC100Desc
*bd
, dma_addr_t addr
)
446 if (dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
))) {
447 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to read descriptor @ 0x%"
448 HWADDR_PRIx
"\n", __func__
, addr
);
451 bd
->des0
= le32_to_cpu(bd
->des0
);
452 bd
->des1
= le32_to_cpu(bd
->des1
);
453 bd
->des2
= le32_to_cpu(bd
->des2
);
454 bd
->des3
= le32_to_cpu(bd
->des3
);
458 static int ftgmac100_write_bd(FTGMAC100Desc
*bd
, dma_addr_t addr
)
462 lebd
.des0
= cpu_to_le32(bd
->des0
);
463 lebd
.des1
= cpu_to_le32(bd
->des1
);
464 lebd
.des2
= cpu_to_le32(bd
->des2
);
465 lebd
.des3
= cpu_to_le32(bd
->des3
);
466 if (dma_memory_write(&address_space_memory
, addr
, &lebd
, sizeof(lebd
))) {
467 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to write descriptor @ 0x%"
468 HWADDR_PRIx
"\n", __func__
, addr
);
474 static void ftgmac100_do_tx(FTGMAC100State
*s
, uint32_t tx_ring
,
475 uint32_t tx_descriptor
)
478 uint8_t *ptr
= s
->frame
;
479 uint32_t addr
= tx_descriptor
;
486 if (ftgmac100_read_bd(&bd
, addr
) ||
487 ((bd
.des0
& FTGMAC100_TXDES0_TXDMA_OWN
) == 0)) {
488 /* Run out of descriptors to transmit. */
489 s
->isr
|= FTGMAC100_INT_NO_NPTXBUF
;
493 /* record transmit flags as they are valid only on the first
495 if (bd
.des0
& FTGMAC100_TXDES0_FTS
) {
499 len
= FTGMAC100_TXDES0_TXBUF_SIZE(bd
.des0
);
500 if (frame_size
+ len
> sizeof(s
->frame
)) {
501 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %d bytes\n",
503 s
->isr
|= FTGMAC100_INT_XPKT_LOST
;
504 len
= sizeof(s
->frame
) - frame_size
;
507 if (dma_memory_read(&address_space_memory
, bd
.des3
, ptr
, len
)) {
508 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to read packet @ 0x%x\n",
510 s
->isr
|= FTGMAC100_INT_NO_NPTXBUF
;
515 if (bd
.des0
& FTGMAC100_TXDES0_FTS
&&
516 bd
.des1
& FTGMAC100_TXDES1_INS_VLANTAG
&&
517 be16_to_cpu(PKT_GET_ETH_HDR(ptr
)->h_proto
) != ETH_P_VLAN
) {
518 if (frame_size
+ len
+ 4 > sizeof(s
->frame
)) {
519 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %d bytes\n",
521 s
->isr
|= FTGMAC100_INT_XPKT_LOST
;
522 len
= sizeof(s
->frame
) - frame_size
- 4;
524 memmove(ptr
+ 16, ptr
+ 12, len
- 12);
525 stw_be_p(ptr
+ 12, ETH_P_VLAN
);
526 stw_be_p(ptr
+ 14, bd
.des1
);
532 if (bd
.des0
& FTGMAC100_TXDES0_LTS
) {
533 if (flags
& FTGMAC100_TXDES1_IP_CHKSUM
) {
534 net_checksum_calculate(s
->frame
, frame_size
);
536 /* Last buffer in frame. */
537 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
540 if (flags
& FTGMAC100_TXDES1_TXIC
) {
541 s
->isr
|= FTGMAC100_INT_XPKT_ETH
;
545 if (flags
& FTGMAC100_TXDES1_TX2FIC
) {
546 s
->isr
|= FTGMAC100_INT_XPKT_FIFO
;
548 bd
.des0
&= ~FTGMAC100_TXDES0_TXDMA_OWN
;
550 /* Write back the modified descriptor. */
551 ftgmac100_write_bd(&bd
, addr
);
552 /* Advance to the next descriptor. */
553 if (bd
.des0
& s
->txdes0_edotr
) {
556 addr
+= sizeof(FTGMAC100Desc
);
560 s
->tx_descriptor
= addr
;
562 ftgmac100_update_irq(s
);
565 static bool ftgmac100_can_receive(NetClientState
*nc
)
567 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
570 if ((s
->maccr
& (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
))
571 != (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
)) {
575 if (ftgmac100_read_bd(&bd
, s
->rx_descriptor
)) {
578 return !(bd
.des0
& FTGMAC100_RXDES0_RXPKT_RDY
);
582 * This is purely informative. The HW can poll the RW (and RX) ring
583 * buffers for available descriptors but we don't need to trigger a
584 * timer for that in qemu.
586 static uint32_t ftgmac100_rxpoll(FTGMAC100State
*s
)
590 * Speed TIME_SEL=0 TIME_SEL=1
592 * 10 51.2 ms 819.2 ms
593 * 100 5.12 ms 81.92 ms
594 * 1000 1.024 ms 16.384 ms
596 static const int div
[] = { 20, 200, 1000 };
598 uint32_t cnt
= 1024 * FTGMAC100_APTC_RXPOLL_CNT(s
->aptcr
);
599 uint32_t speed
= (s
->maccr
& FTGMAC100_MACCR_FAST_MODE
) ? 1 : 0;
601 if (s
->aptcr
& FTGMAC100_APTC_RXPOLL_TIME_SEL
) {
605 if (s
->maccr
& FTGMAC100_MACCR_GIGA_MODE
) {
609 return cnt
/ div
[speed
];
612 static void ftgmac100_reset(DeviceState
*d
)
614 FTGMAC100State
*s
= FTGMAC100(d
);
616 /* Reset the FTGMAC100 */
622 s
->rx_descriptor
= 0;
624 s
->tx_descriptor
= 0;
629 s
->dblac
= 0x00022f00;
643 static uint64_t ftgmac100_read(void *opaque
, hwaddr addr
, unsigned size
)
645 FTGMAC100State
*s
= FTGMAC100(opaque
);
647 switch (addr
& 0xff) {
652 case FTGMAC100_MAC_MADR
:
653 return (s
->conf
.macaddr
.a
[0] << 8) | s
->conf
.macaddr
.a
[1];
654 case FTGMAC100_MAC_LADR
:
655 return ((uint32_t) s
->conf
.macaddr
.a
[2] << 24) |
656 (s
->conf
.macaddr
.a
[3] << 16) | (s
->conf
.macaddr
.a
[4] << 8) |
657 s
->conf
.macaddr
.a
[5];
658 case FTGMAC100_MATH0
:
660 case FTGMAC100_MATH1
:
664 case FTGMAC100_DBLAC
:
668 case FTGMAC100_FEAR1
:
670 case FTGMAC100_TPAFCR
:
674 case FTGMAC100_MACCR
:
676 case FTGMAC100_PHYCR
:
678 case FTGMAC100_PHYDATA
:
681 /* We might want to support these one day */
682 case FTGMAC100_HPTXPD
: /* High Priority Transmit Poll Demand */
683 case FTGMAC100_HPTXR_BADR
: /* High Priority Transmit Ring Base Address */
684 case FTGMAC100_MACSR
: /* MAC Status Register (MACSR) */
685 qemu_log_mask(LOG_UNIMP
, "%s: read to unimplemented register 0x%"
686 HWADDR_PRIx
"\n", __func__
, addr
);
689 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset 0x%"
690 HWADDR_PRIx
"\n", __func__
, addr
);
695 static void ftgmac100_write(void *opaque
, hwaddr addr
,
696 uint64_t value
, unsigned size
)
698 FTGMAC100State
*s
= FTGMAC100(opaque
);
700 switch (addr
& 0xff) {
701 case FTGMAC100_ISR
: /* Interrupt status */
704 case FTGMAC100_IER
: /* Interrupt control */
707 case FTGMAC100_MAC_MADR
: /* MAC */
708 s
->conf
.macaddr
.a
[0] = value
>> 8;
709 s
->conf
.macaddr
.a
[1] = value
;
711 case FTGMAC100_MAC_LADR
:
712 s
->conf
.macaddr
.a
[2] = value
>> 24;
713 s
->conf
.macaddr
.a
[3] = value
>> 16;
714 s
->conf
.macaddr
.a
[4] = value
>> 8;
715 s
->conf
.macaddr
.a
[5] = value
;
717 case FTGMAC100_MATH0
: /* Multicast Address Hash Table 0 */
720 case FTGMAC100_MATH1
: /* Multicast Address Hash Table 1 */
723 case FTGMAC100_ITC
: /* TODO: Interrupt Timer Control */
726 case FTGMAC100_RXR_BADR
: /* Ring buffer address */
727 if (!QEMU_IS_ALIGNED(value
, FTGMAC100_DESC_ALIGNMENT
)) {
728 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad RX buffer alignment 0x%"
729 HWADDR_PRIx
"\n", __func__
, value
);
734 s
->rx_descriptor
= s
->rx_ring
;
737 case FTGMAC100_RBSR
: /* DMA buffer size */
741 case FTGMAC100_NPTXR_BADR
: /* Transmit buffer address */
742 if (!QEMU_IS_ALIGNED(value
, FTGMAC100_DESC_ALIGNMENT
)) {
743 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad TX buffer alignment 0x%"
744 HWADDR_PRIx
"\n", __func__
, value
);
748 s
->tx_descriptor
= s
->tx_ring
;
751 case FTGMAC100_NPTXPD
: /* Trigger transmit */
752 if ((s
->maccr
& (FTGMAC100_MACCR_TXDMA_EN
| FTGMAC100_MACCR_TXMAC_EN
))
753 == (FTGMAC100_MACCR_TXDMA_EN
| FTGMAC100_MACCR_TXMAC_EN
)) {
754 /* TODO: high priority tx ring */
755 ftgmac100_do_tx(s
, s
->tx_ring
, s
->tx_descriptor
);
757 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
758 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
762 case FTGMAC100_RXPD
: /* Receive Poll Demand Register */
763 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
764 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
768 case FTGMAC100_APTC
: /* Automatic polling */
771 if (FTGMAC100_APTC_RXPOLL_CNT(s
->aptcr
)) {
775 if (FTGMAC100_APTC_TXPOLL_CNT(s
->aptcr
)) {
776 qemu_log_mask(LOG_UNIMP
, "%s: no transmit polling\n", __func__
);
780 case FTGMAC100_MACCR
: /* MAC Device control */
782 if (value
& FTGMAC100_MACCR_SW_RST
) {
783 ftgmac100_reset(DEVICE(s
));
786 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
787 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
791 case FTGMAC100_PHYCR
: /* PHY Device control */
793 if (s
->revr
& FTGMAC100_REVR_NEW_MDIO_INTERFACE
) {
799 case FTGMAC100_PHYDATA
:
800 s
->phydata
= value
& 0xffff;
802 case FTGMAC100_DBLAC
: /* DMA Burst Length and Arbitration Control */
805 case FTGMAC100_REVR
: /* Feature Register */
808 case FTGMAC100_FEAR1
: /* Feature Register 1 */
811 case FTGMAC100_TPAFCR
: /* Transmit Priority Arbitration and FIFO Control */
814 case FTGMAC100_FCR
: /* Flow Control */
818 case FTGMAC100_HPTXPD
: /* High Priority Transmit Poll Demand */
819 case FTGMAC100_HPTXR_BADR
: /* High Priority Transmit Ring Base Address */
820 case FTGMAC100_MACSR
: /* MAC Status Register (MACSR) */
821 qemu_log_mask(LOG_UNIMP
, "%s: write to unimplemented register 0x%"
822 HWADDR_PRIx
"\n", __func__
, addr
);
825 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset 0x%"
826 HWADDR_PRIx
"\n", __func__
, addr
);
830 ftgmac100_update_irq(s
);
833 static int ftgmac100_filter(FTGMAC100State
*s
, const uint8_t *buf
, size_t len
)
837 if (s
->maccr
& FTGMAC100_MACCR_RX_ALL
) {
841 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf
))) {
843 if (!(s
->maccr
& FTGMAC100_MACCR_RX_BROADPKT
)) {
848 if (!(s
->maccr
& FTGMAC100_MACCR_RX_MULTIPKT
)) {
849 if (!(s
->maccr
& FTGMAC100_MACCR_HT_MULTI_EN
)) {
853 mcast_idx
= net_crc32_le(buf
, ETH_ALEN
);
854 mcast_idx
= (~(mcast_idx
>> 2)) & 0x3f;
855 if (!(s
->math
[mcast_idx
/ 32] & (1 << (mcast_idx
% 32)))) {
861 if (memcmp(s
->conf
.macaddr
.a
, buf
, 6)) {
870 static ssize_t
ftgmac100_receive(NetClientState
*nc
, const uint8_t *buf
,
873 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
882 uint32_t first
= FTGMAC100_RXDES0_FRS
;
883 uint16_t proto
= be16_to_cpu(PKT_GET_ETH_HDR(buf
)->h_proto
);
884 int max_frame_size
= ftgmac100_max_frame_size(s
, proto
);
886 if ((s
->maccr
& (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
))
887 != (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
)) {
891 /* TODO : Pad to minimum Ethernet frame length */
892 /* handle small packets. */
894 qemu_log_mask(LOG_GUEST_ERROR
, "%s: dropped frame of %zd bytes\n",
899 if (!ftgmac100_filter(s
, buf
, size
)) {
903 /* 4 bytes for the CRC. */
905 crc
= cpu_to_be32(crc32(~0, buf
, size
));
906 crc_ptr
= (uint8_t *) &crc
;
908 /* Huge frames are truncated. */
909 if (size
> max_frame_size
) {
910 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %zd bytes\n",
912 size
= max_frame_size
;
913 flags
|= FTGMAC100_RXDES0_FTL
;
916 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf
))) {
918 flags
|= FTGMAC100_RXDES0_BROADCAST
;
921 flags
|= FTGMAC100_RXDES0_MULTICAST
;
927 addr
= s
->rx_descriptor
;
929 if (!ftgmac100_can_receive(nc
)) {
930 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Unexpected packet\n", __func__
);
934 if (ftgmac100_read_bd(&bd
, addr
) ||
935 (bd
.des0
& FTGMAC100_RXDES0_RXPKT_RDY
)) {
936 /* No descriptors available. Bail out. */
937 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Lost end of frame\n",
939 s
->isr
|= FTGMAC100_INT_NO_RXBUF
;
942 buf_len
= (size
<= s
->rbsr
) ? size
: s
->rbsr
;
943 bd
.des0
|= buf_len
& 0x3fff;
946 /* The last 4 bytes are the CRC. */
951 if (first
&& proto
== ETH_P_VLAN
&& buf_len
>= 18) {
952 bd
.des1
= lduw_be_p(buf
+ 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL
;
954 if (s
->maccr
& FTGMAC100_MACCR_RM_VLAN
) {
955 dma_memory_write(&address_space_memory
, buf_addr
, buf
, 12);
956 dma_memory_write(&address_space_memory
, buf_addr
+ 12, buf
+ 16,
959 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
963 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
967 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
972 bd
.des0
|= first
| FTGMAC100_RXDES0_RXPKT_RDY
;
975 /* Last buffer in frame. */
976 bd
.des0
|= flags
| FTGMAC100_RXDES0_LRS
;
977 s
->isr
|= FTGMAC100_INT_RPKT_BUF
;
979 s
->isr
|= FTGMAC100_INT_RPKT_FIFO
;
981 ftgmac100_write_bd(&bd
, addr
);
982 if (bd
.des0
& s
->rxdes0_edorr
) {
985 addr
+= sizeof(FTGMAC100Desc
);
988 s
->rx_descriptor
= addr
;
990 ftgmac100_update_irq(s
);
994 static const MemoryRegionOps ftgmac100_ops
= {
995 .read
= ftgmac100_read
,
996 .write
= ftgmac100_write
,
997 .valid
.min_access_size
= 4,
998 .valid
.max_access_size
= 4,
999 .endianness
= DEVICE_LITTLE_ENDIAN
,
1002 static void ftgmac100_cleanup(NetClientState
*nc
)
1004 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
1009 static NetClientInfo net_ftgmac100_info
= {
1010 .type
= NET_CLIENT_DRIVER_NIC
,
1011 .size
= sizeof(NICState
),
1012 .can_receive
= ftgmac100_can_receive
,
1013 .receive
= ftgmac100_receive
,
1014 .cleanup
= ftgmac100_cleanup
,
1015 .link_status_changed
= ftgmac100_set_link
,
1018 static void ftgmac100_realize(DeviceState
*dev
, Error
**errp
)
1020 FTGMAC100State
*s
= FTGMAC100(dev
);
1021 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1024 s
->txdes0_edotr
= FTGMAC100_TXDES0_EDOTR_ASPEED
;
1025 s
->rxdes0_edorr
= FTGMAC100_RXDES0_EDORR_ASPEED
;
1027 s
->txdes0_edotr
= FTGMAC100_TXDES0_EDOTR
;
1028 s
->rxdes0_edorr
= FTGMAC100_RXDES0_EDORR
;
1031 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &ftgmac100_ops
, s
,
1032 TYPE_FTGMAC100
, 0x2000);
1033 sysbus_init_mmio(sbd
, &s
->iomem
);
1034 sysbus_init_irq(sbd
, &s
->irq
);
1035 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1037 s
->nic
= qemu_new_nic(&net_ftgmac100_info
, &s
->conf
,
1038 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
1039 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1042 static const VMStateDescription vmstate_ftgmac100
= {
1043 .name
= TYPE_FTGMAC100
,
1045 .minimum_version_id
= 1,
1046 .fields
= (VMStateField
[]) {
1047 VMSTATE_UINT32(irq_state
, FTGMAC100State
),
1048 VMSTATE_UINT32(isr
, FTGMAC100State
),
1049 VMSTATE_UINT32(ier
, FTGMAC100State
),
1050 VMSTATE_UINT32(rx_enabled
, FTGMAC100State
),
1051 VMSTATE_UINT32(rx_ring
, FTGMAC100State
),
1052 VMSTATE_UINT32(rbsr
, FTGMAC100State
),
1053 VMSTATE_UINT32(tx_ring
, FTGMAC100State
),
1054 VMSTATE_UINT32(rx_descriptor
, FTGMAC100State
),
1055 VMSTATE_UINT32(tx_descriptor
, FTGMAC100State
),
1056 VMSTATE_UINT32_ARRAY(math
, FTGMAC100State
, 2),
1057 VMSTATE_UINT32(itc
, FTGMAC100State
),
1058 VMSTATE_UINT32(aptcr
, FTGMAC100State
),
1059 VMSTATE_UINT32(dblac
, FTGMAC100State
),
1060 VMSTATE_UINT32(revr
, FTGMAC100State
),
1061 VMSTATE_UINT32(fear1
, FTGMAC100State
),
1062 VMSTATE_UINT32(tpafcr
, FTGMAC100State
),
1063 VMSTATE_UINT32(maccr
, FTGMAC100State
),
1064 VMSTATE_UINT32(phycr
, FTGMAC100State
),
1065 VMSTATE_UINT32(phydata
, FTGMAC100State
),
1066 VMSTATE_UINT32(fcr
, FTGMAC100State
),
1067 VMSTATE_UINT32(phy_status
, FTGMAC100State
),
1068 VMSTATE_UINT32(phy_control
, FTGMAC100State
),
1069 VMSTATE_UINT32(phy_advertise
, FTGMAC100State
),
1070 VMSTATE_UINT32(phy_int
, FTGMAC100State
),
1071 VMSTATE_UINT32(phy_int_mask
, FTGMAC100State
),
1072 VMSTATE_UINT32(txdes0_edotr
, FTGMAC100State
),
1073 VMSTATE_UINT32(rxdes0_edorr
, FTGMAC100State
),
1074 VMSTATE_END_OF_LIST()
1078 static Property ftgmac100_properties
[] = {
1079 DEFINE_PROP_BOOL("aspeed", FTGMAC100State
, aspeed
, false),
1080 DEFINE_NIC_PROPERTIES(FTGMAC100State
, conf
),
1081 DEFINE_PROP_END_OF_LIST(),
1084 static void ftgmac100_class_init(ObjectClass
*klass
, void *data
)
1086 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1088 dc
->vmsd
= &vmstate_ftgmac100
;
1089 dc
->reset
= ftgmac100_reset
;
1090 device_class_set_props(dc
, ftgmac100_properties
);
1091 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
1092 dc
->realize
= ftgmac100_realize
;
1093 dc
->desc
= "Faraday FTGMAC100 Gigabit Ethernet emulation";
1096 static const TypeInfo ftgmac100_info
= {
1097 .name
= TYPE_FTGMAC100
,
1098 .parent
= TYPE_SYS_BUS_DEVICE
,
1099 .instance_size
= sizeof(FTGMAC100State
),
1100 .class_init
= ftgmac100_class_init
,
1104 * AST2600 MII controller
1106 #define ASPEED_MII_PHYCR_FIRE BIT(31)
1107 #define ASPEED_MII_PHYCR_ST_22 BIT(28)
1108 #define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \
1109 ASPEED_MII_PHYCR_OP_READ))
1110 #define ASPEED_MII_PHYCR_OP_WRITE BIT(26)
1111 #define ASPEED_MII_PHYCR_OP_READ BIT(27)
1112 #define ASPEED_MII_PHYCR_DATA(x) (x & 0xffff)
1113 #define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f)
1114 #define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f)
1116 #define ASPEED_MII_PHYDATA_IDLE BIT(16)
1118 static void aspeed_mii_transition(AspeedMiiState
*s
, bool fire
)
1121 s
->phycr
|= ASPEED_MII_PHYCR_FIRE
;
1122 s
->phydata
&= ~ASPEED_MII_PHYDATA_IDLE
;
1124 s
->phycr
&= ~ASPEED_MII_PHYCR_FIRE
;
1125 s
->phydata
|= ASPEED_MII_PHYDATA_IDLE
;
1129 static void aspeed_mii_do_phy_ctl(AspeedMiiState
*s
)
1134 if (!(s
->phycr
& ASPEED_MII_PHYCR_ST_22
)) {
1135 aspeed_mii_transition(s
, !ASPEED_MII_PHYCR_FIRE
);
1136 qemu_log_mask(LOG_UNIMP
, "%s: unsupported ST code\n", __func__
);
1141 if (!(s
->phycr
& ASPEED_MII_PHYCR_FIRE
)) {
1145 reg
= ASPEED_MII_PHYCR_REG(s
->phycr
);
1146 data
= ASPEED_MII_PHYCR_DATA(s
->phycr
);
1148 switch (ASPEED_MII_PHYCR_OP(s
->phycr
)) {
1149 case ASPEED_MII_PHYCR_OP_WRITE
:
1150 do_phy_write(s
->nic
, reg
, data
);
1152 case ASPEED_MII_PHYCR_OP_READ
:
1153 s
->phydata
= (s
->phydata
& ~0xffff) | do_phy_read(s
->nic
, reg
);
1156 qemu_log_mask(LOG_GUEST_ERROR
, "%s: invalid OP code %08x\n",
1157 __func__
, s
->phycr
);
1160 aspeed_mii_transition(s
, !ASPEED_MII_PHYCR_FIRE
);
1163 static uint64_t aspeed_mii_read(void *opaque
, hwaddr addr
, unsigned size
)
1165 AspeedMiiState
*s
= ASPEED_MII(opaque
);
1173 g_assert_not_reached();
1177 static void aspeed_mii_write(void *opaque
, hwaddr addr
,
1178 uint64_t value
, unsigned size
)
1180 AspeedMiiState
*s
= ASPEED_MII(opaque
);
1184 s
->phycr
= value
& ~(s
->phycr
& ASPEED_MII_PHYCR_FIRE
);
1187 s
->phydata
= value
& ~(0xffff | ASPEED_MII_PHYDATA_IDLE
);
1190 g_assert_not_reached();
1193 aspeed_mii_transition(s
, !!(s
->phycr
& ASPEED_MII_PHYCR_FIRE
));
1194 aspeed_mii_do_phy_ctl(s
);
1197 static const MemoryRegionOps aspeed_mii_ops
= {
1198 .read
= aspeed_mii_read
,
1199 .write
= aspeed_mii_write
,
1200 .valid
.min_access_size
= 4,
1201 .valid
.max_access_size
= 4,
1202 .endianness
= DEVICE_LITTLE_ENDIAN
,
1205 static void aspeed_mii_reset(DeviceState
*dev
)
1207 AspeedMiiState
*s
= ASPEED_MII(dev
);
1212 aspeed_mii_transition(s
, !!(s
->phycr
& ASPEED_MII_PHYCR_FIRE
));
1215 static void aspeed_mii_realize(DeviceState
*dev
, Error
**errp
)
1217 AspeedMiiState
*s
= ASPEED_MII(dev
);
1218 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1222 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &aspeed_mii_ops
, s
,
1223 TYPE_ASPEED_MII
, 0x8);
1224 sysbus_init_mmio(sbd
, &s
->iomem
);
1227 static const VMStateDescription vmstate_aspeed_mii
= {
1228 .name
= TYPE_ASPEED_MII
,
1230 .minimum_version_id
= 1,
1231 .fields
= (VMStateField
[]) {
1232 VMSTATE_UINT32(phycr
, FTGMAC100State
),
1233 VMSTATE_UINT32(phydata
, FTGMAC100State
),
1234 VMSTATE_END_OF_LIST()
1238 static Property aspeed_mii_properties
[] = {
1239 DEFINE_PROP_LINK("nic", AspeedMiiState
, nic
, TYPE_FTGMAC100
,
1241 DEFINE_PROP_END_OF_LIST(),
1244 static void aspeed_mii_class_init(ObjectClass
*klass
, void *data
)
1246 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1248 dc
->vmsd
= &vmstate_aspeed_mii
;
1249 dc
->reset
= aspeed_mii_reset
;
1250 dc
->realize
= aspeed_mii_realize
;
1251 dc
->desc
= "Aspeed MII controller";
1252 device_class_set_props(dc
, aspeed_mii_properties
);
1255 static const TypeInfo aspeed_mii_info
= {
1256 .name
= TYPE_ASPEED_MII
,
1257 .parent
= TYPE_SYS_BUS_DEVICE
,
1258 .instance_size
= sizeof(AspeedMiiState
),
1259 .class_init
= aspeed_mii_class_init
,
1262 static void ftgmac100_register_types(void)
1264 type_register_static(&ftgmac100_info
);
1265 type_register_static(&aspeed_mii_info
);
1268 type_init(ftgmac100_register_types
)