| blob | 3d44b3947733649ae8cffa9e2a27e906ba2df907 |
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
21 #include "fpu_helper.h"
23 /* CPU / CPU family specific config register values. */
25 /* Have config1, uncached coherency */
26 #define MIPS_CONFIG0 \
27 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
29 /* Have config2, no coprocessor2 attached, no MDMX support attached,
30 no performance counters, watch registers present,
31 no code compression, EJTAG present, no FPU */
32 #define MIPS_CONFIG1 \
33 ((1U << CP0C1_M) | \
34 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
35 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
36 (0 << CP0C1_FP))
38 /* Have config3, no tertiary/secondary caches implemented */
39 #define MIPS_CONFIG2 \
40 ((1U << CP0C2_M))
42 /* No config4, no DSP ASE, no large physaddr (PABITS),
43 no external interrupt controller, no vectored interrupts,
44 no 1kb pages, no SmartMIPS ASE, no trace logic */
45 #define MIPS_CONFIG3 \
46 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
47 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
48 (0 << CP0C3_SM) | (0 << CP0C3_TL))
50 #define MIPS_CONFIG4 \
51 ((0 << CP0C4_M))
53 #define MIPS_CONFIG5 \
54 ((0 << CP0C5_M))
56 /*****************************************************************************/
57 /* MIPS CPU definitions */
58 const mips_def_t mips_defs[] =
59 {
60 {
61 .name = "4Kc",
62 .CP0_PRid = 0x00018000,
63 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
64 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
65 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
66 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
67 (0 << CP0C1_CA),
68 .CP0_Config2 = MIPS_CONFIG2,
69 .CP0_Config3 = MIPS_CONFIG3,
70 .CP0_LLAddr_rw_bitmask = 0,
71 .CP0_LLAddr_shift = 4,
72 .SYNCI_Step = 32,
73 .CCRes = 2,
74 .CP0_Status_rw_bitmask = 0x1278FF17,
75 .SEGBITS = 32,
76 .PABITS = 32,
77 .insn_flags = CPU_MIPS32R1,
78 .mmu_type = MMU_TYPE_R4000,
79 },
80 {
81 .name = "4Km",
82 .CP0_PRid = 0x00018300,
83 /* Config1 implemented, fixed mapping MMU,
84 no virtual icache, uncached coherency. */
85 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
86 .CP0_Config1 = MIPS_CONFIG1 |
87 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
88 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
89 (1 << CP0C1_CA),
90 .CP0_Config2 = MIPS_CONFIG2,
91 .CP0_Config3 = MIPS_CONFIG3,
92 .CP0_LLAddr_rw_bitmask = 0,
93 .CP0_LLAddr_shift = 4,
94 .SYNCI_Step = 32,
95 .CCRes = 2,
96 .CP0_Status_rw_bitmask = 0x1258FF17,
97 .SEGBITS = 32,
98 .PABITS = 32,
99 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
100 .mmu_type = MMU_TYPE_FMT,
101 },
102 {
103 .name = "4KEcR1",
104 .CP0_PRid = 0x00018400,
105 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
106 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
107 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
108 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
109 (0 << CP0C1_CA),
110 .CP0_Config2 = MIPS_CONFIG2,
111 .CP0_Config3 = MIPS_CONFIG3,
112 .CP0_LLAddr_rw_bitmask = 0,
113 .CP0_LLAddr_shift = 4,
114 .SYNCI_Step = 32,
115 .CCRes = 2,
116 .CP0_Status_rw_bitmask = 0x1278FF17,
117 .SEGBITS = 32,
118 .PABITS = 32,
119 .insn_flags = CPU_MIPS32R1,
120 .mmu_type = MMU_TYPE_R4000,
121 },
122 {
123 .name = "4KEmR1",
124 .CP0_PRid = 0x00018500,
125 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
126 .CP0_Config1 = MIPS_CONFIG1 |
127 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
128 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
129 (1 << CP0C1_CA),
130 .CP0_Config2 = MIPS_CONFIG2,
131 .CP0_Config3 = MIPS_CONFIG3,
132 .CP0_LLAddr_rw_bitmask = 0,
133 .CP0_LLAddr_shift = 4,
134 .SYNCI_Step = 32,
135 .CCRes = 2,
136 .CP0_Status_rw_bitmask = 0x1258FF17,
137 .SEGBITS = 32,
138 .PABITS = 32,
139 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
140 .mmu_type = MMU_TYPE_FMT,
141 },
142 {
143 .name = "4KEc",
144 .CP0_PRid = 0x00019000,
145 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
146 (MMU_TYPE_R4000 << CP0C0_MT),
147 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
148 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
149 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
150 (0 << CP0C1_CA),
151 .CP0_Config2 = MIPS_CONFIG2,
152 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
153 .CP0_LLAddr_rw_bitmask = 0,
154 .CP0_LLAddr_shift = 4,
155 .SYNCI_Step = 32,
156 .CCRes = 2,
157 .CP0_Status_rw_bitmask = 0x1278FF17,
158 .SEGBITS = 32,
159 .PABITS = 32,
160 .insn_flags = CPU_MIPS32R2,
161 .mmu_type = MMU_TYPE_R4000,
162 },
163 {
164 .name = "4KEm",
165 .CP0_PRid = 0x00019100,
166 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
167 (MMU_TYPE_FMT << CP0C0_MT),
168 .CP0_Config1 = MIPS_CONFIG1 |
169 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
170 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
171 (1 << CP0C1_CA),
172 .CP0_Config2 = MIPS_CONFIG2,
173 .CP0_Config3 = MIPS_CONFIG3,
174 .CP0_LLAddr_rw_bitmask = 0,
175 .CP0_LLAddr_shift = 4,
176 .SYNCI_Step = 32,
177 .CCRes = 2,
178 .CP0_Status_rw_bitmask = 0x1258FF17,
179 .SEGBITS = 32,
180 .PABITS = 32,
181 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
182 .mmu_type = MMU_TYPE_FMT,
183 },
184 {
185 .name = "24Kc",
186 .CP0_PRid = 0x00019300,
187 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
188 (MMU_TYPE_R4000 << CP0C0_MT),
189 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
190 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
191 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
192 (1 << CP0C1_CA),
193 .CP0_Config2 = MIPS_CONFIG2,
194 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
195 .CP0_LLAddr_rw_bitmask = 0,
196 .CP0_LLAddr_shift = 4,
197 .SYNCI_Step = 32,
198 .CCRes = 2,
199 /* No DSP implemented. */
200 .CP0_Status_rw_bitmask = 0x1278FF1F,
201 .SEGBITS = 32,
202 .PABITS = 32,
203 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
204 .mmu_type = MMU_TYPE_R4000,
205 },
206 {
207 .name = "24KEc",
208 .CP0_PRid = 0x00019600,
209 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
210 (MMU_TYPE_R4000 << CP0C0_MT),
211 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
212 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
213 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
214 (1 << CP0C1_CA),
215 .CP0_Config2 = MIPS_CONFIG2,
216 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
217 .CP0_LLAddr_rw_bitmask = 0,
218 .CP0_LLAddr_shift = 4,
219 .SYNCI_Step = 32,
220 .CCRes = 2,
221 /* we have a DSP, but no FPU */
222 .CP0_Status_rw_bitmask = 0x1378FF1F,
223 .SEGBITS = 32,
224 .PABITS = 32,
225 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
226 .mmu_type = MMU_TYPE_R4000,
227 },
228 {
229 .name = "24Kf",
230 .CP0_PRid = 0x00019300,
231 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
232 (MMU_TYPE_R4000 << CP0C0_MT),
233 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
234 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
235 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
236 (1 << CP0C1_CA),
237 .CP0_Config2 = MIPS_CONFIG2,
238 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
239 .CP0_LLAddr_rw_bitmask = 0,
240 .CP0_LLAddr_shift = 4,
241 .SYNCI_Step = 32,
242 .CCRes = 2,
243 /* No DSP implemented. */
244 .CP0_Status_rw_bitmask = 0x3678FF1F,
245 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
246 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
247 .CP1_fcr31 = 0,
248 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
249 .SEGBITS = 32,
250 .PABITS = 32,
251 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
252 .mmu_type = MMU_TYPE_R4000,
253 },
254 {
255 .name = "34Kf",
256 .CP0_PRid = 0x00019500,
257 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
258 (MMU_TYPE_R4000 << CP0C0_MT),
259 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
260 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
261 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
262 (1 << CP0C1_CA),
263 .CP0_Config2 = MIPS_CONFIG2,
264 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
265 (1 << CP0C3_DSPP),
266 .CP0_LLAddr_rw_bitmask = 0,
267 .CP0_LLAddr_shift = 0,
268 .SYNCI_Step = 32,
269 .CCRes = 2,
270 .CP0_Status_rw_bitmask = 0x3778FF1F,
271 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
272 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
273 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
274 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
275 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
276 (0xff << CP0TCSt_TASID),
277 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
278 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
279 .CP1_fcr31 = 0,
280 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
281 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
282 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
283 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
284 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
285 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
286 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
287 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
288 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
289 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
290 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
291 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
292 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
293 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
294 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
295 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
296 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
297 .SEGBITS = 32,
298 .PABITS = 32,
299 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
300 .mmu_type = MMU_TYPE_R4000,
301 },
302 {
303 .name = "74Kf",
304 .CP0_PRid = 0x00019700,
305 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
306 (MMU_TYPE_R4000 << CP0C0_MT),
307 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
308 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
309 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
310 (1 << CP0C1_CA),
311 .CP0_Config2 = MIPS_CONFIG2,
312 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
313 (1 << CP0C3_VInt),
314 .CP0_LLAddr_rw_bitmask = 0,
315 .CP0_LLAddr_shift = 4,
316 .SYNCI_Step = 32,
317 .CCRes = 2,
318 .CP0_Status_rw_bitmask = 0x3778FF1F,
319 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
320 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
321 .CP1_fcr31 = 0,
322 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
323 .SEGBITS = 32,
324 .PABITS = 32,
325 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
326 .mmu_type = MMU_TYPE_R4000,
327 },
328 {
329 .name = "M14K",
330 .CP0_PRid = 0x00019b00,
331 /* Config1 implemented, fixed mapping MMU,
332 no virtual icache, uncached coherency. */
333 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
334 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
335 .CP0_Config1 = MIPS_CONFIG1,
336 .CP0_Config2 = MIPS_CONFIG2,
337 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
338 .CP0_LLAddr_rw_bitmask = 0,
339 .CP0_LLAddr_shift = 4,
340 .SYNCI_Step = 32,
341 .CCRes = 2,
342 .CP0_Status_rw_bitmask = 0x1258FF17,
343 .SEGBITS = 32,
344 .PABITS = 32,
345 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
346 .mmu_type = MMU_TYPE_FMT,
347 },
348 {
349 .name = "M14Kc",
350 /* This is the TLB-based MMU core. */
351 .CP0_PRid = 0x00019c00,
352 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
353 (MMU_TYPE_R4000 << CP0C0_MT),
354 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
355 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
356 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
357 .CP0_Config2 = MIPS_CONFIG2,
358 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
359 .CP0_LLAddr_rw_bitmask = 0,
360 .CP0_LLAddr_shift = 4,
361 .SYNCI_Step = 32,
362 .CCRes = 2,
363 .CP0_Status_rw_bitmask = 0x1278FF17,
364 .SEGBITS = 32,
365 .PABITS = 32,
366 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
367 .mmu_type = MMU_TYPE_R4000,
368 },
369 {
370 /* FIXME:
371 * Config3: VZ, CTXTC, CDMM, TL
372 * Config4: MMUExtDef
373 * Config5: MRP
374 * FIR(FCR0): Has2008
375 * */
376 .name = "P5600",
377 .CP0_PRid = 0x0001A800,
378 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
379 (MMU_TYPE_R4000 << CP0C0_MT),
380 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
381 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
382 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
383 (1 << CP0C1_PC) | (1 << CP0C1_FP),
384 .CP0_Config2 = MIPS_CONFIG2,
385 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
386 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
387 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
388 (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
389 (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
390 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
391 (0x1c << CP0C4_KScrExist),
392 .CP0_Config4_rw_bitmask = 0,
393 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
394 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
395 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
396 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
397 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
398 .CP0_LLAddr_rw_bitmask = 0,
399 .CP0_LLAddr_shift = 0,
400 .SYNCI_Step = 32,
401 .CCRes = 2,
402 .CP0_Status_rw_bitmask = 0x3C68FF1F,
403 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
404 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
405 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
406 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
407 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
408 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
409 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
410 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
411 .SEGBITS = 32,
412 .PABITS = 40,
413 .insn_flags = CPU_MIPS32R5,
414 .mmu_type = MMU_TYPE_R4000,
415 },
416 {
417 /* A generic CPU supporting MIPS32 Release 6 ISA.
418 FIXME: Support IEEE 754-2008 FP.
419 Eventually this should be replaced by a real CPU model. */
420 .name = "mips32r6-generic",
421 .CP0_PRid = 0x00010000,
422 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
423 (MMU_TYPE_R4000 << CP0C0_MT),
424 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
425 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
426 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
427 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
428 .CP0_Config2 = MIPS_CONFIG2,
429 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
430 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
431 (1 << CP0C3_RXI) | (1U << CP0C3_M),
432 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
433 (3 << CP0C4_IE) | (1U << CP0C4_M),
434 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
435 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
436 (1 << CP0C5_UFE),
437 .CP0_LLAddr_rw_bitmask = 0,
438 .CP0_LLAddr_shift = 0,
439 .SYNCI_Step = 32,
440 .CCRes = 2,
441 .CP0_Status_rw_bitmask = 0x3058FF1F,
442 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
443 (1U << CP0PG_RIE),
444 .CP0_PageGrain_rw_bitmask = 0,
445 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
446 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
447 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
448 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
449 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
450 .SEGBITS = 32,
451 .PABITS = 32,
452 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
453 .mmu_type = MMU_TYPE_R4000,
454 },
455 {
456 .name = "I7200",
457 .CP0_PRid = 0x00010000,
458 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
459 (MMU_TYPE_R4000 << CP0C0_MT),
460 .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
461 (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
462 (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
463 (1 << CP0C1_EP),
464 .CP0_Config2 = MIPS_CONFIG2,
465 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
466 (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
467 (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
468 (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
469 (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
470 (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
471 (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
472 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
473 (2 << CP0C4_IE) | (1U << CP0C4_M),
474 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
475 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
476 (1 << CP0C5_UFE),
477 .CP0_LLAddr_rw_bitmask = 0,
478 .CP0_LLAddr_shift = 0,
479 .SYNCI_Step = 32,
480 .CCRes = 2,
481 .CP0_Status_rw_bitmask = 0x3158FF1F,
482 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
483 (1U << CP0PG_RIE),
484 .CP0_PageGrain_rw_bitmask = 0,
485 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
486 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
487 (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
488 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
489 .SEGBITS = 32,
490 .PABITS = 32,
491 .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
492 ASE_MT,
493 .mmu_type = MMU_TYPE_R4000,
494 },
495 #if defined(TARGET_MIPS64)
496 {
497 .name = "R4000",
498 .CP0_PRid = 0x00000400,
499 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
500 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
501 (2 << CP0C0_K0),
502 /* Note: Config1 is only used internally, the R4000 has only Config0. */
503 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
504 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
505 .CP0_LLAddr_shift = 4,
506 .SYNCI_Step = 16,
507 .CCRes = 2,
508 .CP0_Status_rw_bitmask = 0x3678FFFF,
509 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
510 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
511 .CP1_fcr31 = 0,
512 .CP1_fcr31_rw_bitmask = 0x0183FFFF,
513 .SEGBITS = 40,
514 .PABITS = 36,
515 .insn_flags = CPU_MIPS3,
516 .mmu_type = MMU_TYPE_R4000,
517 },
518 {
519 .name = "VR5432",
520 .CP0_PRid = 0x00005400,
521 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
522 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
523 (2 << CP0C0_K0),
524 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
525 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
526 .CP0_LLAddr_shift = 4,
527 .SYNCI_Step = 16,
528 .CCRes = 2,
529 .CP0_Status_rw_bitmask = 0x3678FFFF,
530 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
531 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
532 .CP1_fcr31 = 0,
533 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
534 .SEGBITS = 40,
535 .PABITS = 32,
536 .insn_flags = CPU_VR54XX,
537 .mmu_type = MMU_TYPE_R4000,
538 },
539 {
540 .name = "5Kc",
541 .CP0_PRid = 0x00018100,
542 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
543 (MMU_TYPE_R4000 << CP0C0_MT),
544 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
545 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
546 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
547 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
548 .CP0_Config2 = MIPS_CONFIG2,
549 .CP0_Config3 = MIPS_CONFIG3,
550 .CP0_LLAddr_rw_bitmask = 0,
551 .CP0_LLAddr_shift = 4,
552 .SYNCI_Step = 32,
553 .CCRes = 2,
554 .CP0_Status_rw_bitmask = 0x12F8FFFF,
555 .SEGBITS = 42,
556 .PABITS = 36,
557 .insn_flags = CPU_MIPS64R1,
558 .mmu_type = MMU_TYPE_R4000,
559 },
560 {
561 .name = "5Kf",
562 .CP0_PRid = 0x00018100,
563 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
564 (MMU_TYPE_R4000 << CP0C0_MT),
565 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
566 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
567 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
568 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
569 .CP0_Config2 = MIPS_CONFIG2,
570 .CP0_Config3 = MIPS_CONFIG3,
571 .CP0_LLAddr_rw_bitmask = 0,
572 .CP0_LLAddr_shift = 4,
573 .SYNCI_Step = 32,
574 .CCRes = 2,
575 .CP0_Status_rw_bitmask = 0x36F8FFFF,
576 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
577 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
578 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
579 .CP1_fcr31 = 0,
580 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
581 .SEGBITS = 42,
582 .PABITS = 36,
583 .insn_flags = CPU_MIPS64R1,
584 .mmu_type = MMU_TYPE_R4000,
585 },
586 {
587 .name = "20Kc",
588 /* We emulate a later version of the 20Kc, earlier ones had a broken
589 WAIT instruction. */
590 .CP0_PRid = 0x000182a0,
591 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
592 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
593 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
594 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
595 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
596 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
597 .CP0_Config2 = MIPS_CONFIG2,
598 .CP0_Config3 = MIPS_CONFIG3,
599 .CP0_LLAddr_rw_bitmask = 0,
600 .CP0_LLAddr_shift = 0,
601 .SYNCI_Step = 32,
602 .CCRes = 1,
603 .CP0_Status_rw_bitmask = 0x36FBFFFF,
604 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
605 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
606 (1 << FCR0_D) | (1 << FCR0_S) |
607 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
608 .CP1_fcr31 = 0,
609 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
610 .SEGBITS = 40,
611 .PABITS = 36,
612 .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
613 .mmu_type = MMU_TYPE_R4000,
614 },
615 {
616 /* A generic CPU providing MIPS64 Release 2 features.
617 FIXME: Eventually this should be replaced by a real CPU model. */
618 .name = "MIPS64R2-generic",
619 .CP0_PRid = 0x00010000,
620 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
621 (MMU_TYPE_R4000 << CP0C0_MT),
622 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
623 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
624 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
625 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
626 .CP0_Config2 = MIPS_CONFIG2,
627 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
628 .CP0_LLAddr_rw_bitmask = 0,
629 .CP0_LLAddr_shift = 0,
630 .SYNCI_Step = 32,
631 .CCRes = 2,
632 .CP0_Status_rw_bitmask = 0x36FBFFFF,
633 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
634 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
635 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
636 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
637 .CP1_fcr31 = 0,
638 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
639 .SEGBITS = 42,
640 .PABITS = 36,
641 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
642 .mmu_type = MMU_TYPE_R4000,
643 },
644 {
645 .name = "5KEc",
646 .CP0_PRid = 0x00018900,
647 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
648 (MMU_TYPE_R4000 << CP0C0_MT),
649 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
650 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
651 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
652 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
653 .CP0_Config2 = MIPS_CONFIG2,
654 .CP0_Config3 = MIPS_CONFIG3,
655 .CP0_LLAddr_rw_bitmask = 0,
656 .CP0_LLAddr_shift = 4,
657 .SYNCI_Step = 32,
658 .CCRes = 2,
659 .CP0_Status_rw_bitmask = 0x12F8FFFF,
660 .SEGBITS = 42,
661 .PABITS = 36,
662 .insn_flags = CPU_MIPS64R2,
663 .mmu_type = MMU_TYPE_R4000,
664 },
665 {
666 .name = "5KEf",
667 .CP0_PRid = 0x00018900,
668 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
669 (MMU_TYPE_R4000 << CP0C0_MT),
670 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
671 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
672 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
673 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
674 .CP0_Config2 = MIPS_CONFIG2,
675 .CP0_Config3 = MIPS_CONFIG3,
676 .CP0_LLAddr_rw_bitmask = 0,
677 .CP0_LLAddr_shift = 4,
678 .SYNCI_Step = 32,
679 .CCRes = 2,
680 .CP0_Status_rw_bitmask = 0x36F8FFFF,
681 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
682 (1 << FCR0_D) | (1 << FCR0_S) |
683 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
684 .SEGBITS = 42,
685 .PABITS = 36,
686 .insn_flags = CPU_MIPS64R2,
687 .mmu_type = MMU_TYPE_R4000,
688 },
689 {
690 .name = "I6400",
691 .CP0_PRid = 0x1A900,
692 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
693 (MMU_TYPE_R4000 << CP0C0_MT),
694 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
695 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
696 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
697 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
698 .CP0_Config2 = MIPS_CONFIG2,
699 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
700 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
701 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
702 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
703 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
704 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
705 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
706 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
707 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
708 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
709 .CP0_LLAddr_rw_bitmask = 0,
710 .CP0_LLAddr_shift = 0,
711 .SYNCI_Step = 32,
712 .CCRes = 2,
713 .CP0_Status_rw_bitmask = 0x30D8FFFF,
714 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
715 (1U << CP0PG_RIE),
716 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
717 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
718 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
719 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
720 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
721 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
722 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
723 .MSAIR = 0x03 << MSAIR_ProcID,
724 .SEGBITS = 48,
725 .PABITS = 48,
726 .insn_flags = CPU_MIPS64R6,
727 .mmu_type = MMU_TYPE_R4000,
728 },
729 {
730 .name = "I6500",
731 .CP0_PRid = 0x1B000,
732 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
733 (MMU_TYPE_R4000 << CP0C0_MT),
734 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
735 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
736 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
737 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
738 .CP0_Config2 = MIPS_CONFIG2,
739 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
740 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
741 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
742 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
743 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
744 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
745 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
746 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
747 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
748 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
749 .CP0_LLAddr_rw_bitmask = 0,
750 .CP0_LLAddr_shift = 0,
751 .SYNCI_Step = 64,
752 .CCRes = 2,
753 .CP0_Status_rw_bitmask = 0x30D8FFFF,
754 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
755 (1U << CP0PG_RIE),
756 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
757 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
758 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
759 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
760 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
761 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
762 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
763 .MSAIR = 0x03 << MSAIR_ProcID,
764 .SEGBITS = 48,
765 .PABITS = 48,
766 .insn_flags = CPU_MIPS64R6,
767 .mmu_type = MMU_TYPE_R4000,
768 },
769 {
770 .name = "Loongson-2E",
771 .CP0_PRid = 0x6302,
772 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
773 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
774 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
775 /* Note: Config1 is only used internally,
776 Loongson-2E has only Config0. */
777 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
778 .SYNCI_Step = 16,
779 .CCRes = 2,
780 .CP0_Status_rw_bitmask = 0x35D0FFFF,
781 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
782 .CP1_fcr31 = 0,
783 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
784 .SEGBITS = 40,
785 .PABITS = 40,
786 .insn_flags = CPU_LOONGSON2E,
787 .mmu_type = MMU_TYPE_R4000,
788 },
789 {
790 .name = "Loongson-2F",
791 .CP0_PRid = 0x6303,
792 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
793 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
794 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
795 /* Note: Config1 is only used internally,
796 Loongson-2F has only Config0. */
797 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
798 .SYNCI_Step = 16,
799 .CCRes = 2,
800 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
801 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
802 .CP1_fcr31 = 0,
803 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
804 .SEGBITS = 40,
805 .PABITS = 40,
806 .insn_flags = CPU_LOONGSON2F,
807 .mmu_type = MMU_TYPE_R4000,
808 },
809 {
810 .name = "Loongson-3A1000",
811 .CP0_PRid = 0x6305,
812 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
813 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
814 (MMU_TYPE_R4000 << CP0C0_MT),
815 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
816 (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
817 (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
818 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
819 .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
820 (3 << CP0C2_SA),
821 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
822 .CP0_LLAddr_rw_bitmask = 0,
823 .SYNCI_Step = 32,
824 .CCRes = 2,
825 .CP0_Status_rw_bitmask = 0x74D8FFFF,
826 .CP0_PageGrain = (1 << CP0PG_ELPA),
827 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
828 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
829 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
830 (0x1 << FCR0_D) | (0x1 << FCR0_S),
831 .CP1_fcr31 = 0,
832 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
833 .SEGBITS = 42,
834 .PABITS = 48,
835 .insn_flags = CPU_LOONGSON3A,
836 .mmu_type = MMU_TYPE_R4000,
837 },
838 {
839 .name = "Loongson-3A4000", /* GS464V-based */
840 .CP0_PRid = 0x14C000,
841 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
842 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
843 (MMU_TYPE_R4000 << CP0C0_MT),
844 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
845 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
846 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
847 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
848 .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
849 (15 << CP0C2_SA),
850 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
851 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
852 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
853 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
854 (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
855 .CP0_Config4_rw_bitmask = 0,
856 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
857 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
858 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
859 (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
860 .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
861 (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
862 (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
863 .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
864 (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
865 (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
866 (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
867 (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
868 (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
869 (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
870 (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
871 (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
872 (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
873 (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
874 (1 << CP0C6_DATAPREF),
875 .CP0_Config7 = 0,
876 .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
877 (1 << CP0C7_VFPUCGEN),
878 .CP0_LLAddr_rw_bitmask = 1,
879 .SYNCI_Step = 16,
880 .CCRes = 2,
881 .CP0_Status_rw_bitmask = 0x7DDBFFFF,
882 .CP0_PageGrain = (1 << CP0PG_ELPA),
883 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
884 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
885 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
886 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
887 (0x1 << FCR0_D) | (0x1 << FCR0_S),
888 .CP1_fcr31 = 0,
889 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
890 .SEGBITS = 48,
891 .PABITS = 48,
892 .insn_flags = CPU_LOONGSON3A,
893 .mmu_type = MMU_TYPE_R4000,
894 },
895 {
896 /* A generic CPU providing MIPS64 DSP R2 ASE features.
897 FIXME: Eventually this should be replaced by a real CPU model. */
898 .name = "mips64dspr2",
899 .CP0_PRid = 0x00010000,
900 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
901 (MMU_TYPE_R4000 << CP0C0_MT),
902 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
903 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
904 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
905 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
906 .CP0_Config2 = MIPS_CONFIG2,
907 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
908 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
909 .CP0_LLAddr_rw_bitmask = 0,
910 .CP0_LLAddr_shift = 0,
911 .SYNCI_Step = 32,
912 .CCRes = 2,
913 .CP0_Status_rw_bitmask = 0x37FBFFFF,
914 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
915 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
916 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
917 .CP1_fcr31 = 0,
918 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
919 .SEGBITS = 42,
920 .PABITS = 36,
921 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
922 .mmu_type = MMU_TYPE_R4000,
923 },
925 #endif
926 };
927 const int mips_defs_number = ARRAY_SIZE(mips_defs);
929 void mips_cpu_list(void)
930 {
931 int i;
933 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
934 qemu_printf("MIPS '%s'\n", mips_defs[i].name);
935 }
936 }
938 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
939 {
940 int i;
942 for (i = 0; i < MIPS_FPU_MAX; i++)
943 env->fpus[i].fcr0 = def->CP1_fcr0;
945 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
946 }
948 static void mvp_init(CPUMIPSState *env)
949 {
950 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
952 if (!ase_mt_available(env)) {
953 return;
954 }
956 /* MVPConf1 implemented, TLB sharable, no gating storage support,
957 programmable cache partitioning implemented, number of allocatable
958 and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
959 implemented, 5 TCs implemented. */
960 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
961 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
962 // TODO: actually do 2 VPEs.
963 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
964 // (0x04 << CP0MVPC0_PTC);
965 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
966 (0x00 << CP0MVPC0_PTC);
967 #if !defined(CONFIG_USER_ONLY)
968 /* Usermode has no TLB support */
969 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
970 #endif
972 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
973 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
974 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
975 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
976 (0x1 << CP0MVPC1_PCP1);
977 }
979 static void msa_reset(CPUMIPSState *env)
980 {
981 if (!ase_msa_available(env)) {
982 return;
983 }
985 #ifdef CONFIG_USER_ONLY
986 /* MSA access enabled */
987 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
988 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
989 #endif
991 /* MSA CSR:
992 - non-signaling floating point exception mode off (NX bit is 0)
993 - Cause, Enables, and Flags are all 0
994 - round to nearest / ties to even (RM bits are 0) */
995 env->active_tc.msacsr = 0;
997 restore_msa_fp_status(env);
999 /* tininess detected after rounding.*/
1000 set_float_detect_tininess(float_tininess_after_rounding,
1001 &env->active_tc.msa_fp_status);
1003 /* clear float_status exception flags */
1004 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
1006 /* clear float_status nan mode */
1007 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
1009 /* set proper signanling bit meaning ("1" means "quiet") */
1010 set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
1011 }