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spapr: Refactor spapr_populate_memory() to allow memoryless nodes
[qemu/ar7.git] / hw / ppc / ppc405_uc.c
bloba73e918a1435eda9606fbcbc88443486397063e3
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/ppc/ppc.h"
26 #include "hw/boards.h"
27 #include "ppc405.h"
28 #include "hw/char/serial.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
31 #include "qemu/log.h"
32 #include "exec/address-spaces.h"
33
34 //#define DEBUG_OPBA
35 //#define DEBUG_SDRAM
36 //#define DEBUG_GPIO
37 //#define DEBUG_SERIAL
38 //#define DEBUG_OCM
39 //#define DEBUG_I2C
40 //#define DEBUG_GPT
41 //#define DEBUG_MAL
42 //#define DEBUG_CLOCKS
43 //#define DEBUG_CLOCKS_LL
44
45 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
46 uint32_t flags)
47 {
48 CPUState *cs = CPU(ppc_env_get_cpu(env));
49 ram_addr_t bdloc;
50 int i, n;
51
52 /* We put the bd structure at the top of memory */
53 if (bd->bi_memsize >= 0x01000000UL)
54 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
55 else
56 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
57 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
58 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
59 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
60 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
61 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
62 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
63 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
64 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
65 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
66 for (i = 0; i < 6; i++) {
67 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
68 }
69 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
70 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
71 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
72 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
73 for (i = 0; i < 4; i++) {
74 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
75 }
76 for (i = 0; i < 32; i++) {
77 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
78 }
79 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
80 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
81 for (i = 0; i < 6; i++) {
82 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
83 }
84 n = 0x6A;
85 if (flags & 0x00000001) {
86 for (i = 0; i < 6; i++)
87 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
88 }
89 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
90 n += 4;
91 for (i = 0; i < 2; i++) {
92 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
93 n += 4;
94 }
95
96 return bdloc;
97 }
98
99 /*****************************************************************************/
100 /* Shared peripherals */
101
102 /*****************************************************************************/
103 /* Peripheral local bus arbitrer */
104 enum {
105 PLB0_BESR = 0x084,
106 PLB0_BEAR = 0x086,
107 PLB0_ACR = 0x087,
108 };
109
110 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
111 struct ppc4xx_plb_t {
112 uint32_t acr;
113 uint32_t bear;
114 uint32_t besr;
115 };
116
117 static uint32_t dcr_read_plb (void *opaque, int dcrn)
118 {
119 ppc4xx_plb_t *plb;
120 uint32_t ret;
121
122 plb = opaque;
123 switch (dcrn) {
124 case PLB0_ACR:
125 ret = plb->acr;
126 break;
127 case PLB0_BEAR:
128 ret = plb->bear;
129 break;
130 case PLB0_BESR:
131 ret = plb->besr;
132 break;
133 default:
134 /* Avoid gcc warning */
135 ret = 0;
136 break;
137 }
138
139 return ret;
140 }
141
142 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
143 {
144 ppc4xx_plb_t *plb;
145
146 plb = opaque;
147 switch (dcrn) {
148 case PLB0_ACR:
149 /* We don't care about the actual parameters written as
150 * we don't manage any priorities on the bus
151 */
152 plb->acr = val & 0xF8000000;
153 break;
154 case PLB0_BEAR:
155 /* Read only */
156 break;
157 case PLB0_BESR:
158 /* Write-clear */
159 plb->besr &= ~val;
160 break;
161 }
162 }
163
164 static void ppc4xx_plb_reset (void *opaque)
165 {
166 ppc4xx_plb_t *plb;
167
168 plb = opaque;
169 plb->acr = 0x00000000;
170 plb->bear = 0x00000000;
171 plb->besr = 0x00000000;
172 }
173
174 static void ppc4xx_plb_init(CPUPPCState *env)
175 {
176 ppc4xx_plb_t *plb;
177
178 plb = g_malloc0(sizeof(ppc4xx_plb_t));
179 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
180 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
181 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
182 qemu_register_reset(ppc4xx_plb_reset, plb);
183 }
184
185 /*****************************************************************************/
186 /* PLB to OPB bridge */
187 enum {
188 POB0_BESR0 = 0x0A0,
189 POB0_BESR1 = 0x0A2,
190 POB0_BEAR = 0x0A4,
191 };
192
193 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
194 struct ppc4xx_pob_t {
195 uint32_t bear;
196 uint32_t besr0;
197 uint32_t besr1;
198 };
199
200 static uint32_t dcr_read_pob (void *opaque, int dcrn)
201 {
202 ppc4xx_pob_t *pob;
203 uint32_t ret;
204
205 pob = opaque;
206 switch (dcrn) {
207 case POB0_BEAR:
208 ret = pob->bear;
209 break;
210 case POB0_BESR0:
211 ret = pob->besr0;
212 break;
213 case POB0_BESR1:
214 ret = pob->besr1;
215 break;
216 default:
217 /* Avoid gcc warning */
218 ret = 0;
219 break;
220 }
221
222 return ret;
223 }
224
225 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
226 {
227 ppc4xx_pob_t *pob;
228
229 pob = opaque;
230 switch (dcrn) {
231 case POB0_BEAR:
232 /* Read only */
233 break;
234 case POB0_BESR0:
235 /* Write-clear */
236 pob->besr0 &= ~val;
237 break;
238 case POB0_BESR1:
239 /* Write-clear */
240 pob->besr1 &= ~val;
241 break;
242 }
243 }
244
245 static void ppc4xx_pob_reset (void *opaque)
246 {
247 ppc4xx_pob_t *pob;
248
249 pob = opaque;
250 /* No error */
251 pob->bear = 0x00000000;
252 pob->besr0 = 0x0000000;
253 pob->besr1 = 0x0000000;
254 }
255
256 static void ppc4xx_pob_init(CPUPPCState *env)
257 {
258 ppc4xx_pob_t *pob;
259
260 pob = g_malloc0(sizeof(ppc4xx_pob_t));
261 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
262 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
263 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
264 qemu_register_reset(ppc4xx_pob_reset, pob);
265 }
266
267 /*****************************************************************************/
268 /* OPB arbitrer */
269 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
270 struct ppc4xx_opba_t {
271 MemoryRegion io;
272 uint8_t cr;
273 uint8_t pr;
274 };
275
276 static uint32_t opba_readb (void *opaque, hwaddr addr)
277 {
278 ppc4xx_opba_t *opba;
279 uint32_t ret;
280
281 #ifdef DEBUG_OPBA
282 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
283 #endif
284 opba = opaque;
285 switch (addr) {
286 case 0x00:
287 ret = opba->cr;
288 break;
289 case 0x01:
290 ret = opba->pr;
291 break;
292 default:
293 ret = 0x00;
294 break;
295 }
296
297 return ret;
298 }
299
300 static void opba_writeb (void *opaque,
301 hwaddr addr, uint32_t value)
302 {
303 ppc4xx_opba_t *opba;
304
305 #ifdef DEBUG_OPBA
306 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
307 value);
308 #endif
309 opba = opaque;
310 switch (addr) {
311 case 0x00:
312 opba->cr = value & 0xF8;
313 break;
314 case 0x01:
315 opba->pr = value & 0xFF;
316 break;
317 default:
318 break;
319 }
320 }
321
322 static uint32_t opba_readw (void *opaque, hwaddr addr)
323 {
324 uint32_t ret;
325
326 #ifdef DEBUG_OPBA
327 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
328 #endif
329 ret = opba_readb(opaque, addr) << 8;
330 ret |= opba_readb(opaque, addr + 1);
331
332 return ret;
333 }
334
335 static void opba_writew (void *opaque,
336 hwaddr addr, uint32_t value)
337 {
338 #ifdef DEBUG_OPBA
339 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
340 value);
341 #endif
342 opba_writeb(opaque, addr, value >> 8);
343 opba_writeb(opaque, addr + 1, value);
344 }
345
346 static uint32_t opba_readl (void *opaque, hwaddr addr)
347 {
348 uint32_t ret;
349
350 #ifdef DEBUG_OPBA
351 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
352 #endif
353 ret = opba_readb(opaque, addr) << 24;
354 ret |= opba_readb(opaque, addr + 1) << 16;
355
356 return ret;
357 }
358
359 static void opba_writel (void *opaque,
360 hwaddr addr, uint32_t value)
361 {
362 #ifdef DEBUG_OPBA
363 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
364 value);
365 #endif
366 opba_writeb(opaque, addr, value >> 24);
367 opba_writeb(opaque, addr + 1, value >> 16);
368 }
369
370 static const MemoryRegionOps opba_ops = {
371 .old_mmio = {
372 .read = { opba_readb, opba_readw, opba_readl, },
373 .write = { opba_writeb, opba_writew, opba_writel, },
374 },
375 .endianness = DEVICE_NATIVE_ENDIAN,
376 };
377
378 static void ppc4xx_opba_reset (void *opaque)
379 {
380 ppc4xx_opba_t *opba;
381
382 opba = opaque;
383 opba->cr = 0x00; /* No dynamic priorities - park disabled */
384 opba->pr = 0x11;
385 }
386
387 static void ppc4xx_opba_init(hwaddr base)
388 {
389 ppc4xx_opba_t *opba;
390
391 opba = g_malloc0(sizeof(ppc4xx_opba_t));
392 #ifdef DEBUG_OPBA
393 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
394 #endif
395 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
396 memory_region_add_subregion(get_system_memory(), base, &opba->io);
397 qemu_register_reset(ppc4xx_opba_reset, opba);
398 }
399
400 /*****************************************************************************/
401 /* Code decompression controller */
402 /* XXX: TODO */
403
404 /*****************************************************************************/
405 /* Peripheral controller */
406 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
407 struct ppc4xx_ebc_t {
408 uint32_t addr;
409 uint32_t bcr[8];
410 uint32_t bap[8];
411 uint32_t bear;
412 uint32_t besr0;
413 uint32_t besr1;
414 uint32_t cfg;
415 };
416
417 enum {
418 EBC0_CFGADDR = 0x012,
419 EBC0_CFGDATA = 0x013,
420 };
421
422 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
423 {
424 ppc4xx_ebc_t *ebc;
425 uint32_t ret;
426
427 ebc = opaque;
428 switch (dcrn) {
429 case EBC0_CFGADDR:
430 ret = ebc->addr;
431 break;
432 case EBC0_CFGDATA:
433 switch (ebc->addr) {
434 case 0x00: /* B0CR */
435 ret = ebc->bcr[0];
436 break;
437 case 0x01: /* B1CR */
438 ret = ebc->bcr[1];
439 break;
440 case 0x02: /* B2CR */
441 ret = ebc->bcr[2];
442 break;
443 case 0x03: /* B3CR */
444 ret = ebc->bcr[3];
445 break;
446 case 0x04: /* B4CR */
447 ret = ebc->bcr[4];
448 break;
449 case 0x05: /* B5CR */
450 ret = ebc->bcr[5];
451 break;
452 case 0x06: /* B6CR */
453 ret = ebc->bcr[6];
454 break;
455 case 0x07: /* B7CR */
456 ret = ebc->bcr[7];
457 break;
458 case 0x10: /* B0AP */
459 ret = ebc->bap[0];
460 break;
461 case 0x11: /* B1AP */
462 ret = ebc->bap[1];
463 break;
464 case 0x12: /* B2AP */
465 ret = ebc->bap[2];
466 break;
467 case 0x13: /* B3AP */
468 ret = ebc->bap[3];
469 break;
470 case 0x14: /* B4AP */
471 ret = ebc->bap[4];
472 break;
473 case 0x15: /* B5AP */
474 ret = ebc->bap[5];
475 break;
476 case 0x16: /* B6AP */
477 ret = ebc->bap[6];
478 break;
479 case 0x17: /* B7AP */
480 ret = ebc->bap[7];
481 break;
482 case 0x20: /* BEAR */
483 ret = ebc->bear;
484 break;
485 case 0x21: /* BESR0 */
486 ret = ebc->besr0;
487 break;
488 case 0x22: /* BESR1 */
489 ret = ebc->besr1;
490 break;
491 case 0x23: /* CFG */
492 ret = ebc->cfg;
493 break;
494 default:
495 ret = 0x00000000;
496 break;
497 }
498 break;
499 default:
500 ret = 0x00000000;
501 break;
502 }
503
504 return ret;
505 }
506
507 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
508 {
509 ppc4xx_ebc_t *ebc;
510
511 ebc = opaque;
512 switch (dcrn) {
513 case EBC0_CFGADDR:
514 ebc->addr = val;
515 break;
516 case EBC0_CFGDATA:
517 switch (ebc->addr) {
518 case 0x00: /* B0CR */
519 break;
520 case 0x01: /* B1CR */
521 break;
522 case 0x02: /* B2CR */
523 break;
524 case 0x03: /* B3CR */
525 break;
526 case 0x04: /* B4CR */
527 break;
528 case 0x05: /* B5CR */
529 break;
530 case 0x06: /* B6CR */
531 break;
532 case 0x07: /* B7CR */
533 break;
534 case 0x10: /* B0AP */
535 break;
536 case 0x11: /* B1AP */
537 break;
538 case 0x12: /* B2AP */
539 break;
540 case 0x13: /* B3AP */
541 break;
542 case 0x14: /* B4AP */
543 break;
544 case 0x15: /* B5AP */
545 break;
546 case 0x16: /* B6AP */
547 break;
548 case 0x17: /* B7AP */
549 break;
550 case 0x20: /* BEAR */
551 break;
552 case 0x21: /* BESR0 */
553 break;
554 case 0x22: /* BESR1 */
555 break;
556 case 0x23: /* CFG */
557 break;
558 default:
559 break;
560 }
561 break;
562 default:
563 break;
564 }
565 }
566
567 static void ebc_reset (void *opaque)
568 {
569 ppc4xx_ebc_t *ebc;
570 int i;
571
572 ebc = opaque;
573 ebc->addr = 0x00000000;
574 ebc->bap[0] = 0x7F8FFE80;
575 ebc->bcr[0] = 0xFFE28000;
576 for (i = 0; i < 8; i++) {
577 ebc->bap[i] = 0x00000000;
578 ebc->bcr[i] = 0x00000000;
579 }
580 ebc->besr0 = 0x00000000;
581 ebc->besr1 = 0x00000000;
582 ebc->cfg = 0x80400000;
583 }
584
585 static void ppc405_ebc_init(CPUPPCState *env)
586 {
587 ppc4xx_ebc_t *ebc;
588
589 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
590 qemu_register_reset(&ebc_reset, ebc);
591 ppc_dcr_register(env, EBC0_CFGADDR,
592 ebc, &dcr_read_ebc, &dcr_write_ebc);
593 ppc_dcr_register(env, EBC0_CFGDATA,
594 ebc, &dcr_read_ebc, &dcr_write_ebc);
595 }
596
597 /*****************************************************************************/
598 /* DMA controller */
599 enum {
600 DMA0_CR0 = 0x100,
601 DMA0_CT0 = 0x101,
602 DMA0_DA0 = 0x102,
603 DMA0_SA0 = 0x103,
604 DMA0_SG0 = 0x104,
605 DMA0_CR1 = 0x108,
606 DMA0_CT1 = 0x109,
607 DMA0_DA1 = 0x10A,
608 DMA0_SA1 = 0x10B,
609 DMA0_SG1 = 0x10C,
610 DMA0_CR2 = 0x110,
611 DMA0_CT2 = 0x111,
612 DMA0_DA2 = 0x112,
613 DMA0_SA2 = 0x113,
614 DMA0_SG2 = 0x114,
615 DMA0_CR3 = 0x118,
616 DMA0_CT3 = 0x119,
617 DMA0_DA3 = 0x11A,
618 DMA0_SA3 = 0x11B,
619 DMA0_SG3 = 0x11C,
620 DMA0_SR = 0x120,
621 DMA0_SGC = 0x123,
622 DMA0_SLP = 0x125,
623 DMA0_POL = 0x126,
624 };
625
626 typedef struct ppc405_dma_t ppc405_dma_t;
627 struct ppc405_dma_t {
628 qemu_irq irqs[4];
629 uint32_t cr[4];
630 uint32_t ct[4];
631 uint32_t da[4];
632 uint32_t sa[4];
633 uint32_t sg[4];
634 uint32_t sr;
635 uint32_t sgc;
636 uint32_t slp;
637 uint32_t pol;
638 };
639
640 static uint32_t dcr_read_dma (void *opaque, int dcrn)
641 {
642 return 0;
643 }
644
645 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
646 {
647 }
648
649 static void ppc405_dma_reset (void *opaque)
650 {
651 ppc405_dma_t *dma;
652 int i;
653
654 dma = opaque;
655 for (i = 0; i < 4; i++) {
656 dma->cr[i] = 0x00000000;
657 dma->ct[i] = 0x00000000;
658 dma->da[i] = 0x00000000;
659 dma->sa[i] = 0x00000000;
660 dma->sg[i] = 0x00000000;
661 }
662 dma->sr = 0x00000000;
663 dma->sgc = 0x00000000;
664 dma->slp = 0x7C000000;
665 dma->pol = 0x00000000;
666 }
667
668 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
669 {
670 ppc405_dma_t *dma;
671
672 dma = g_malloc0(sizeof(ppc405_dma_t));
673 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
674 qemu_register_reset(&ppc405_dma_reset, dma);
675 ppc_dcr_register(env, DMA0_CR0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_CT0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_DA0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_SA0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SG0,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_CR1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CT1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_DA1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_SA1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SG1,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_CR2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CT2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_DA2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_SA2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SG2,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_CR3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_CT3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_DA3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SA3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SG3,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SR,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SGC,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_SLP,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 ppc_dcr_register(env, DMA0_POL,
722 dma, &dcr_read_dma, &dcr_write_dma);
723 }
724
725 /*****************************************************************************/
726 /* GPIO */
727 typedef struct ppc405_gpio_t ppc405_gpio_t;
728 struct ppc405_gpio_t {
729 MemoryRegion io;
730 uint32_t or;
731 uint32_t tcr;
732 uint32_t osrh;
733 uint32_t osrl;
734 uint32_t tsrh;
735 uint32_t tsrl;
736 uint32_t odr;
737 uint32_t ir;
738 uint32_t rr1;
739 uint32_t isr1h;
740 uint32_t isr1l;
741 };
742
743 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
744 {
745 #ifdef DEBUG_GPIO
746 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
747 #endif
748
749 return 0;
750 }
751
752 static void ppc405_gpio_writeb (void *opaque,
753 hwaddr addr, uint32_t value)
754 {
755 #ifdef DEBUG_GPIO
756 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
757 value);
758 #endif
759 }
760
761 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
762 {
763 #ifdef DEBUG_GPIO
764 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
765 #endif
766
767 return 0;
768 }
769
770 static void ppc405_gpio_writew (void *opaque,
771 hwaddr addr, uint32_t value)
772 {
773 #ifdef DEBUG_GPIO
774 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
775 value);
776 #endif
777 }
778
779 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
780 {
781 #ifdef DEBUG_GPIO
782 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
783 #endif
784
785 return 0;
786 }
787
788 static void ppc405_gpio_writel (void *opaque,
789 hwaddr addr, uint32_t value)
790 {
791 #ifdef DEBUG_GPIO
792 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
793 value);
794 #endif
795 }
796
797 static const MemoryRegionOps ppc405_gpio_ops = {
798 .old_mmio = {
799 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
800 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
801 },
802 .endianness = DEVICE_NATIVE_ENDIAN,
803 };
804
805 static void ppc405_gpio_reset (void *opaque)
806 {
807 }
808
809 static void ppc405_gpio_init(hwaddr base)
810 {
811 ppc405_gpio_t *gpio;
812
813 gpio = g_malloc0(sizeof(ppc405_gpio_t));
814 #ifdef DEBUG_GPIO
815 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
816 #endif
817 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
818 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
819 qemu_register_reset(&ppc405_gpio_reset, gpio);
820 }
821
822 /*****************************************************************************/
823 /* On Chip Memory */
824 enum {
825 OCM0_ISARC = 0x018,
826 OCM0_ISACNTL = 0x019,
827 OCM0_DSARC = 0x01A,
828 OCM0_DSACNTL = 0x01B,
829 };
830
831 typedef struct ppc405_ocm_t ppc405_ocm_t;
832 struct ppc405_ocm_t {
833 MemoryRegion ram;
834 MemoryRegion isarc_ram;
835 MemoryRegion dsarc_ram;
836 uint32_t isarc;
837 uint32_t isacntl;
838 uint32_t dsarc;
839 uint32_t dsacntl;
840 };
841
842 static void ocm_update_mappings (ppc405_ocm_t *ocm,
843 uint32_t isarc, uint32_t isacntl,
844 uint32_t dsarc, uint32_t dsacntl)
845 {
846 #ifdef DEBUG_OCM
847 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
848 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
849 " (%08" PRIx32 " %08" PRIx32 ")\n",
850 isarc, isacntl, dsarc, dsacntl,
851 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
852 #endif
853 if (ocm->isarc != isarc ||
854 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
855 if (ocm->isacntl & 0x80000000) {
856 /* Unmap previously assigned memory region */
857 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
858 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
859 }
860 if (isacntl & 0x80000000) {
861 /* Map new instruction memory region */
862 #ifdef DEBUG_OCM
863 printf("OCM map ISA %08" PRIx32 "\n", isarc);
864 #endif
865 memory_region_add_subregion(get_system_memory(), isarc,
866 &ocm->isarc_ram);
867 }
868 }
869 if (ocm->dsarc != dsarc ||
870 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
871 if (ocm->dsacntl & 0x80000000) {
872 /* Beware not to unmap the region we just mapped */
873 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
874 /* Unmap previously assigned memory region */
875 #ifdef DEBUG_OCM
876 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
877 #endif
878 memory_region_del_subregion(get_system_memory(),
879 &ocm->dsarc_ram);
880 }
881 }
882 if (dsacntl & 0x80000000) {
883 /* Beware not to remap the region we just mapped */
884 if (!(isacntl & 0x80000000) || dsarc != isarc) {
885 /* Map new data memory region */
886 #ifdef DEBUG_OCM
887 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
888 #endif
889 memory_region_add_subregion(get_system_memory(), dsarc,
890 &ocm->dsarc_ram);
891 }
892 }
893 }
894 }
895
896 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
897 {
898 ppc405_ocm_t *ocm;
899 uint32_t ret;
900
901 ocm = opaque;
902 switch (dcrn) {
903 case OCM0_ISARC:
904 ret = ocm->isarc;
905 break;
906 case OCM0_ISACNTL:
907 ret = ocm->isacntl;
908 break;
909 case OCM0_DSARC:
910 ret = ocm->dsarc;
911 break;
912 case OCM0_DSACNTL:
913 ret = ocm->dsacntl;
914 break;
915 default:
916 ret = 0;
917 break;
918 }
919
920 return ret;
921 }
922
923 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
924 {
925 ppc405_ocm_t *ocm;
926 uint32_t isarc, dsarc, isacntl, dsacntl;
927
928 ocm = opaque;
929 isarc = ocm->isarc;
930 dsarc = ocm->dsarc;
931 isacntl = ocm->isacntl;
932 dsacntl = ocm->dsacntl;
933 switch (dcrn) {
934 case OCM0_ISARC:
935 isarc = val & 0xFC000000;
936 break;
937 case OCM0_ISACNTL:
938 isacntl = val & 0xC0000000;
939 break;
940 case OCM0_DSARC:
941 isarc = val & 0xFC000000;
942 break;
943 case OCM0_DSACNTL:
944 isacntl = val & 0xC0000000;
945 break;
946 }
947 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
948 ocm->isarc = isarc;
949 ocm->dsarc = dsarc;
950 ocm->isacntl = isacntl;
951 ocm->dsacntl = dsacntl;
952 }
953
954 static void ocm_reset (void *opaque)
955 {
956 ppc405_ocm_t *ocm;
957 uint32_t isarc, dsarc, isacntl, dsacntl;
958
959 ocm = opaque;
960 isarc = 0x00000000;
961 isacntl = 0x00000000;
962 dsarc = 0x00000000;
963 dsacntl = 0x00000000;
964 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
965 ocm->isarc = isarc;
966 ocm->dsarc = dsarc;
967 ocm->isacntl = isacntl;
968 ocm->dsacntl = dsacntl;
969 }
970
971 static void ppc405_ocm_init(CPUPPCState *env)
972 {
973 ppc405_ocm_t *ocm;
974
975 ocm = g_malloc0(sizeof(ppc405_ocm_t));
976 /* XXX: Size is 4096 or 0x04000000 */
977 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
978 vmstate_register_ram_global(&ocm->isarc_ram);
979 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
980 0, 4096);
981 qemu_register_reset(&ocm_reset, ocm);
982 ppc_dcr_register(env, OCM0_ISARC,
983 ocm, &dcr_read_ocm, &dcr_write_ocm);
984 ppc_dcr_register(env, OCM0_ISACNTL,
985 ocm, &dcr_read_ocm, &dcr_write_ocm);
986 ppc_dcr_register(env, OCM0_DSARC,
987 ocm, &dcr_read_ocm, &dcr_write_ocm);
988 ppc_dcr_register(env, OCM0_DSACNTL,
989 ocm, &dcr_read_ocm, &dcr_write_ocm);
990 }
991
992 /*****************************************************************************/
993 /* I2C controller */
994 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
995 struct ppc4xx_i2c_t {
996 qemu_irq irq;
997 MemoryRegion iomem;
998 uint8_t mdata;
999 uint8_t lmadr;
1000 uint8_t hmadr;
1001 uint8_t cntl;
1002 uint8_t mdcntl;
1003 uint8_t sts;
1004 uint8_t extsts;
1005 uint8_t sdata;
1006 uint8_t lsadr;
1007 uint8_t hsadr;
1008 uint8_t clkdiv;
1009 uint8_t intrmsk;
1010 uint8_t xfrcnt;
1011 uint8_t xtcntlss;
1012 uint8_t directcntl;
1013 };
1014
1015 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1016 {
1017 ppc4xx_i2c_t *i2c;
1018 uint32_t ret;
1019
1020 #ifdef DEBUG_I2C
1021 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1022 #endif
1023 i2c = opaque;
1024 switch (addr) {
1025 case 0x00:
1026 // i2c_readbyte(&i2c->mdata);
1027 ret = i2c->mdata;
1028 break;
1029 case 0x02:
1030 ret = i2c->sdata;
1031 break;
1032 case 0x04:
1033 ret = i2c->lmadr;
1034 break;
1035 case 0x05:
1036 ret = i2c->hmadr;
1037 break;
1038 case 0x06:
1039 ret = i2c->cntl;
1040 break;
1041 case 0x07:
1042 ret = i2c->mdcntl;
1043 break;
1044 case 0x08:
1045 ret = i2c->sts;
1046 break;
1047 case 0x09:
1048 ret = i2c->extsts;
1049 break;
1050 case 0x0A:
1051 ret = i2c->lsadr;
1052 break;
1053 case 0x0B:
1054 ret = i2c->hsadr;
1055 break;
1056 case 0x0C:
1057 ret = i2c->clkdiv;
1058 break;
1059 case 0x0D:
1060 ret = i2c->intrmsk;
1061 break;
1062 case 0x0E:
1063 ret = i2c->xfrcnt;
1064 break;
1065 case 0x0F:
1066 ret = i2c->xtcntlss;
1067 break;
1068 case 0x10:
1069 ret = i2c->directcntl;
1070 break;
1071 default:
1072 ret = 0x00;
1073 break;
1074 }
1075 #ifdef DEBUG_I2C
1076 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1077 #endif
1078
1079 return ret;
1080 }
1081
1082 static void ppc4xx_i2c_writeb (void *opaque,
1083 hwaddr addr, uint32_t value)
1084 {
1085 ppc4xx_i2c_t *i2c;
1086
1087 #ifdef DEBUG_I2C
1088 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1089 value);
1090 #endif
1091 i2c = opaque;
1092 switch (addr) {
1093 case 0x00:
1094 i2c->mdata = value;
1095 // i2c_sendbyte(&i2c->mdata);
1096 break;
1097 case 0x02:
1098 i2c->sdata = value;
1099 break;
1100 case 0x04:
1101 i2c->lmadr = value;
1102 break;
1103 case 0x05:
1104 i2c->hmadr = value;
1105 break;
1106 case 0x06:
1107 i2c->cntl = value;
1108 break;
1109 case 0x07:
1110 i2c->mdcntl = value & 0xDF;
1111 break;
1112 case 0x08:
1113 i2c->sts &= ~(value & 0x0A);
1114 break;
1115 case 0x09:
1116 i2c->extsts &= ~(value & 0x8F);
1117 break;
1118 case 0x0A:
1119 i2c->lsadr = value;
1120 break;
1121 case 0x0B:
1122 i2c->hsadr = value;
1123 break;
1124 case 0x0C:
1125 i2c->clkdiv = value;
1126 break;
1127 case 0x0D:
1128 i2c->intrmsk = value;
1129 break;
1130 case 0x0E:
1131 i2c->xfrcnt = value & 0x77;
1132 break;
1133 case 0x0F:
1134 i2c->xtcntlss = value;
1135 break;
1136 case 0x10:
1137 i2c->directcntl = value & 0x7;
1138 break;
1139 }
1140 }
1141
1142 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1143 {
1144 uint32_t ret;
1145
1146 #ifdef DEBUG_I2C
1147 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1148 #endif
1149 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1150 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1151
1152 return ret;
1153 }
1154
1155 static void ppc4xx_i2c_writew (void *opaque,
1156 hwaddr addr, uint32_t value)
1157 {
1158 #ifdef DEBUG_I2C
1159 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1160 value);
1161 #endif
1162 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1163 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1164 }
1165
1166 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1167 {
1168 uint32_t ret;
1169
1170 #ifdef DEBUG_I2C
1171 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1172 #endif
1173 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1174 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1175 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1176 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1177
1178 return ret;
1179 }
1180
1181 static void ppc4xx_i2c_writel (void *opaque,
1182 hwaddr addr, uint32_t value)
1183 {
1184 #ifdef DEBUG_I2C
1185 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1186 value);
1187 #endif
1188 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1189 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1190 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1191 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1192 }
1193
1194 static const MemoryRegionOps i2c_ops = {
1195 .old_mmio = {
1196 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1197 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1198 },
1199 .endianness = DEVICE_NATIVE_ENDIAN,
1200 };
1201
1202 static void ppc4xx_i2c_reset (void *opaque)
1203 {
1204 ppc4xx_i2c_t *i2c;
1205
1206 i2c = opaque;
1207 i2c->mdata = 0x00;
1208 i2c->sdata = 0x00;
1209 i2c->cntl = 0x00;
1210 i2c->mdcntl = 0x00;
1211 i2c->sts = 0x00;
1212 i2c->extsts = 0x00;
1213 i2c->clkdiv = 0x00;
1214 i2c->xfrcnt = 0x00;
1215 i2c->directcntl = 0x0F;
1216 }
1217
1218 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1219 {
1220 ppc4xx_i2c_t *i2c;
1221
1222 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1223 i2c->irq = irq;
1224 #ifdef DEBUG_I2C
1225 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1226 #endif
1227 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
1228 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1229 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1230 }
1231
1232 /*****************************************************************************/
1233 /* General purpose timers */
1234 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1235 struct ppc4xx_gpt_t {
1236 MemoryRegion iomem;
1237 int64_t tb_offset;
1238 uint32_t tb_freq;
1239 QEMUTimer *timer;
1240 qemu_irq irqs[5];
1241 uint32_t oe;
1242 uint32_t ol;
1243 uint32_t im;
1244 uint32_t is;
1245 uint32_t ie;
1246 uint32_t comp[5];
1247 uint32_t mask[5];
1248 };
1249
1250 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1251 {
1252 #ifdef DEBUG_GPT
1253 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1254 #endif
1255 /* XXX: generate a bus fault */
1256 return -1;
1257 }
1258
1259 static void ppc4xx_gpt_writeb (void *opaque,
1260 hwaddr addr, uint32_t value)
1261 {
1262 #ifdef DEBUG_I2C
1263 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1264 value);
1265 #endif
1266 /* XXX: generate a bus fault */
1267 }
1268
1269 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1270 {
1271 #ifdef DEBUG_GPT
1272 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1273 #endif
1274 /* XXX: generate a bus fault */
1275 return -1;
1276 }
1277
1278 static void ppc4xx_gpt_writew (void *opaque,
1279 hwaddr addr, uint32_t value)
1280 {
1281 #ifdef DEBUG_I2C
1282 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1283 value);
1284 #endif
1285 /* XXX: generate a bus fault */
1286 }
1287
1288 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1289 {
1290 /* XXX: TODO */
1291 return 0;
1292 }
1293
1294 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1295 {
1296 /* XXX: TODO */
1297 }
1298
1299 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1300 {
1301 uint32_t mask;
1302 int i;
1303
1304 mask = 0x80000000;
1305 for (i = 0; i < 5; i++) {
1306 if (gpt->oe & mask) {
1307 /* Output is enabled */
1308 if (ppc4xx_gpt_compare(gpt, i)) {
1309 /* Comparison is OK */
1310 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1311 } else {
1312 /* Comparison is KO */
1313 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1314 }
1315 }
1316 mask = mask >> 1;
1317 }
1318 }
1319
1320 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1321 {
1322 uint32_t mask;
1323 int i;
1324
1325 mask = 0x00008000;
1326 for (i = 0; i < 5; i++) {
1327 if (gpt->is & gpt->im & mask)
1328 qemu_irq_raise(gpt->irqs[i]);
1329 else
1330 qemu_irq_lower(gpt->irqs[i]);
1331 mask = mask >> 1;
1332 }
1333 }
1334
1335 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1336 {
1337 /* XXX: TODO */
1338 }
1339
1340 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1341 {
1342 ppc4xx_gpt_t *gpt;
1343 uint32_t ret;
1344 int idx;
1345
1346 #ifdef DEBUG_GPT
1347 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1348 #endif
1349 gpt = opaque;
1350 switch (addr) {
1351 case 0x00:
1352 /* Time base counter */
1353 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1354 gpt->tb_freq, get_ticks_per_sec());
1355 break;
1356 case 0x10:
1357 /* Output enable */
1358 ret = gpt->oe;
1359 break;
1360 case 0x14:
1361 /* Output level */
1362 ret = gpt->ol;
1363 break;
1364 case 0x18:
1365 /* Interrupt mask */
1366 ret = gpt->im;
1367 break;
1368 case 0x1C:
1369 case 0x20:
1370 /* Interrupt status */
1371 ret = gpt->is;
1372 break;
1373 case 0x24:
1374 /* Interrupt enable */
1375 ret = gpt->ie;
1376 break;
1377 case 0x80 ... 0x90:
1378 /* Compare timer */
1379 idx = (addr - 0x80) >> 2;
1380 ret = gpt->comp[idx];
1381 break;
1382 case 0xC0 ... 0xD0:
1383 /* Compare mask */
1384 idx = (addr - 0xC0) >> 2;
1385 ret = gpt->mask[idx];
1386 break;
1387 default:
1388 ret = -1;
1389 break;
1390 }
1391
1392 return ret;
1393 }
1394
1395 static void ppc4xx_gpt_writel (void *opaque,
1396 hwaddr addr, uint32_t value)
1397 {
1398 ppc4xx_gpt_t *gpt;
1399 int idx;
1400
1401 #ifdef DEBUG_I2C
1402 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1403 value);
1404 #endif
1405 gpt = opaque;
1406 switch (addr) {
1407 case 0x00:
1408 /* Time base counter */
1409 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1410 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1411 ppc4xx_gpt_compute_timer(gpt);
1412 break;
1413 case 0x10:
1414 /* Output enable */
1415 gpt->oe = value & 0xF8000000;
1416 ppc4xx_gpt_set_outputs(gpt);
1417 break;
1418 case 0x14:
1419 /* Output level */
1420 gpt->ol = value & 0xF8000000;
1421 ppc4xx_gpt_set_outputs(gpt);
1422 break;
1423 case 0x18:
1424 /* Interrupt mask */
1425 gpt->im = value & 0x0000F800;
1426 break;
1427 case 0x1C:
1428 /* Interrupt status set */
1429 gpt->is |= value & 0x0000F800;
1430 ppc4xx_gpt_set_irqs(gpt);
1431 break;
1432 case 0x20:
1433 /* Interrupt status clear */
1434 gpt->is &= ~(value & 0x0000F800);
1435 ppc4xx_gpt_set_irqs(gpt);
1436 break;
1437 case 0x24:
1438 /* Interrupt enable */
1439 gpt->ie = value & 0x0000F800;
1440 ppc4xx_gpt_set_irqs(gpt);
1441 break;
1442 case 0x80 ... 0x90:
1443 /* Compare timer */
1444 idx = (addr - 0x80) >> 2;
1445 gpt->comp[idx] = value & 0xF8000000;
1446 ppc4xx_gpt_compute_timer(gpt);
1447 break;
1448 case 0xC0 ... 0xD0:
1449 /* Compare mask */
1450 idx = (addr - 0xC0) >> 2;
1451 gpt->mask[idx] = value & 0xF8000000;
1452 ppc4xx_gpt_compute_timer(gpt);
1453 break;
1454 }
1455 }
1456
1457 static const MemoryRegionOps gpt_ops = {
1458 .old_mmio = {
1459 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1460 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1461 },
1462 .endianness = DEVICE_NATIVE_ENDIAN,
1463 };
1464
1465 static void ppc4xx_gpt_cb (void *opaque)
1466 {
1467 ppc4xx_gpt_t *gpt;
1468
1469 gpt = opaque;
1470 ppc4xx_gpt_set_irqs(gpt);
1471 ppc4xx_gpt_set_outputs(gpt);
1472 ppc4xx_gpt_compute_timer(gpt);
1473 }
1474
1475 static void ppc4xx_gpt_reset (void *opaque)
1476 {
1477 ppc4xx_gpt_t *gpt;
1478 int i;
1479
1480 gpt = opaque;
1481 timer_del(gpt->timer);
1482 gpt->oe = 0x00000000;
1483 gpt->ol = 0x00000000;
1484 gpt->im = 0x00000000;
1485 gpt->is = 0x00000000;
1486 gpt->ie = 0x00000000;
1487 for (i = 0; i < 5; i++) {
1488 gpt->comp[i] = 0x00000000;
1489 gpt->mask[i] = 0x00000000;
1490 }
1491 }
1492
1493 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1494 {
1495 ppc4xx_gpt_t *gpt;
1496 int i;
1497
1498 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1499 for (i = 0; i < 5; i++) {
1500 gpt->irqs[i] = irqs[i];
1501 }
1502 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1503 #ifdef DEBUG_GPT
1504 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1505 #endif
1506 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1507 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1508 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1509 }
1510
1511 /*****************************************************************************/
1512 /* MAL */
1513 enum {
1514 MAL0_CFG = 0x180,
1515 MAL0_ESR = 0x181,
1516 MAL0_IER = 0x182,
1517 MAL0_TXCASR = 0x184,
1518 MAL0_TXCARR = 0x185,
1519 MAL0_TXEOBISR = 0x186,
1520 MAL0_TXDEIR = 0x187,
1521 MAL0_RXCASR = 0x190,
1522 MAL0_RXCARR = 0x191,
1523 MAL0_RXEOBISR = 0x192,
1524 MAL0_RXDEIR = 0x193,
1525 MAL0_TXCTP0R = 0x1A0,
1526 MAL0_TXCTP1R = 0x1A1,
1527 MAL0_TXCTP2R = 0x1A2,
1528 MAL0_TXCTP3R = 0x1A3,
1529 MAL0_RXCTP0R = 0x1C0,
1530 MAL0_RXCTP1R = 0x1C1,
1531 MAL0_RCBS0 = 0x1E0,
1532 MAL0_RCBS1 = 0x1E1,
1533 };
1534
1535 typedef struct ppc40x_mal_t ppc40x_mal_t;
1536 struct ppc40x_mal_t {
1537 qemu_irq irqs[4];
1538 uint32_t cfg;
1539 uint32_t esr;
1540 uint32_t ier;
1541 uint32_t txcasr;
1542 uint32_t txcarr;
1543 uint32_t txeobisr;
1544 uint32_t txdeir;
1545 uint32_t rxcasr;
1546 uint32_t rxcarr;
1547 uint32_t rxeobisr;
1548 uint32_t rxdeir;
1549 uint32_t txctpr[4];
1550 uint32_t rxctpr[2];
1551 uint32_t rcbs[2];
1552 };
1553
1554 static void ppc40x_mal_reset (void *opaque);
1555
1556 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1557 {
1558 ppc40x_mal_t *mal;
1559 uint32_t ret;
1560
1561 mal = opaque;
1562 switch (dcrn) {
1563 case MAL0_CFG:
1564 ret = mal->cfg;
1565 break;
1566 case MAL0_ESR:
1567 ret = mal->esr;
1568 break;
1569 case MAL0_IER:
1570 ret = mal->ier;
1571 break;
1572 case MAL0_TXCASR:
1573 ret = mal->txcasr;
1574 break;
1575 case MAL0_TXCARR:
1576 ret = mal->txcarr;
1577 break;
1578 case MAL0_TXEOBISR:
1579 ret = mal->txeobisr;
1580 break;
1581 case MAL0_TXDEIR:
1582 ret = mal->txdeir;
1583 break;
1584 case MAL0_RXCASR:
1585 ret = mal->rxcasr;
1586 break;
1587 case MAL0_RXCARR:
1588 ret = mal->rxcarr;
1589 break;
1590 case MAL0_RXEOBISR:
1591 ret = mal->rxeobisr;
1592 break;
1593 case MAL0_RXDEIR:
1594 ret = mal->rxdeir;
1595 break;
1596 case MAL0_TXCTP0R:
1597 ret = mal->txctpr[0];
1598 break;
1599 case MAL0_TXCTP1R:
1600 ret = mal->txctpr[1];
1601 break;
1602 case MAL0_TXCTP2R:
1603 ret = mal->txctpr[2];
1604 break;
1605 case MAL0_TXCTP3R:
1606 ret = mal->txctpr[3];
1607 break;
1608 case MAL0_RXCTP0R:
1609 ret = mal->rxctpr[0];
1610 break;
1611 case MAL0_RXCTP1R:
1612 ret = mal->rxctpr[1];
1613 break;
1614 case MAL0_RCBS0:
1615 ret = mal->rcbs[0];
1616 break;
1617 case MAL0_RCBS1:
1618 ret = mal->rcbs[1];
1619 break;
1620 default:
1621 ret = 0;
1622 break;
1623 }
1624
1625 return ret;
1626 }
1627
1628 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1629 {
1630 ppc40x_mal_t *mal;
1631 int idx;
1632
1633 mal = opaque;
1634 switch (dcrn) {
1635 case MAL0_CFG:
1636 if (val & 0x80000000)
1637 ppc40x_mal_reset(mal);
1638 mal->cfg = val & 0x00FFC087;
1639 break;
1640 case MAL0_ESR:
1641 /* Read/clear */
1642 mal->esr &= ~val;
1643 break;
1644 case MAL0_IER:
1645 mal->ier = val & 0x0000001F;
1646 break;
1647 case MAL0_TXCASR:
1648 mal->txcasr = val & 0xF0000000;
1649 break;
1650 case MAL0_TXCARR:
1651 mal->txcarr = val & 0xF0000000;
1652 break;
1653 case MAL0_TXEOBISR:
1654 /* Read/clear */
1655 mal->txeobisr &= ~val;
1656 break;
1657 case MAL0_TXDEIR:
1658 /* Read/clear */
1659 mal->txdeir &= ~val;
1660 break;
1661 case MAL0_RXCASR:
1662 mal->rxcasr = val & 0xC0000000;
1663 break;
1664 case MAL0_RXCARR:
1665 mal->rxcarr = val & 0xC0000000;
1666 break;
1667 case MAL0_RXEOBISR:
1668 /* Read/clear */
1669 mal->rxeobisr &= ~val;
1670 break;
1671 case MAL0_RXDEIR:
1672 /* Read/clear */
1673 mal->rxdeir &= ~val;
1674 break;
1675 case MAL0_TXCTP0R:
1676 idx = 0;
1677 goto update_tx_ptr;
1678 case MAL0_TXCTP1R:
1679 idx = 1;
1680 goto update_tx_ptr;
1681 case MAL0_TXCTP2R:
1682 idx = 2;
1683 goto update_tx_ptr;
1684 case MAL0_TXCTP3R:
1685 idx = 3;
1686 update_tx_ptr:
1687 mal->txctpr[idx] = val;
1688 break;
1689 case MAL0_RXCTP0R:
1690 idx = 0;
1691 goto update_rx_ptr;
1692 case MAL0_RXCTP1R:
1693 idx = 1;
1694 update_rx_ptr:
1695 mal->rxctpr[idx] = val;
1696 break;
1697 case MAL0_RCBS0:
1698 idx = 0;
1699 goto update_rx_size;
1700 case MAL0_RCBS1:
1701 idx = 1;
1702 update_rx_size:
1703 mal->rcbs[idx] = val & 0x000000FF;
1704 break;
1705 }
1706 }
1707
1708 static void ppc40x_mal_reset (void *opaque)
1709 {
1710 ppc40x_mal_t *mal;
1711
1712 mal = opaque;
1713 mal->cfg = 0x0007C000;
1714 mal->esr = 0x00000000;
1715 mal->ier = 0x00000000;
1716 mal->rxcasr = 0x00000000;
1717 mal->rxdeir = 0x00000000;
1718 mal->rxeobisr = 0x00000000;
1719 mal->txcasr = 0x00000000;
1720 mal->txdeir = 0x00000000;
1721 mal->txeobisr = 0x00000000;
1722 }
1723
1724 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1725 {
1726 ppc40x_mal_t *mal;
1727 int i;
1728
1729 mal = g_malloc0(sizeof(ppc40x_mal_t));
1730 for (i = 0; i < 4; i++)
1731 mal->irqs[i] = irqs[i];
1732 qemu_register_reset(&ppc40x_mal_reset, mal);
1733 ppc_dcr_register(env, MAL0_CFG,
1734 mal, &dcr_read_mal, &dcr_write_mal);
1735 ppc_dcr_register(env, MAL0_ESR,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_IER,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_TXCASR,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_TXCARR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXEOBISR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_TXDEIR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_RXCASR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_RXCARR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXEOBISR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_RXDEIR,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_TXCTP0R,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_TXCTP1R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP2R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_TXCTP3R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_RXCTP0R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_RXCTP1R,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RCBS0,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 ppc_dcr_register(env, MAL0_RCBS1,
1770 mal, &dcr_read_mal, &dcr_write_mal);
1771 }
1772
1773 /*****************************************************************************/
1774 /* SPR */
1775 void ppc40x_core_reset(PowerPCCPU *cpu)
1776 {
1777 CPUPPCState *env = &cpu->env;
1778 target_ulong dbsr;
1779
1780 printf("Reset PowerPC core\n");
1781 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1782 dbsr = env->spr[SPR_40x_DBSR];
1783 dbsr &= ~0x00000300;
1784 dbsr |= 0x00000100;
1785 env->spr[SPR_40x_DBSR] = dbsr;
1786 }
1787
1788 void ppc40x_chip_reset(PowerPCCPU *cpu)
1789 {
1790 CPUPPCState *env = &cpu->env;
1791 target_ulong dbsr;
1792
1793 printf("Reset PowerPC chip\n");
1794 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1795 /* XXX: TODO reset all internal peripherals */
1796 dbsr = env->spr[SPR_40x_DBSR];
1797 dbsr &= ~0x00000300;
1798 dbsr |= 0x00000200;
1799 env->spr[SPR_40x_DBSR] = dbsr;
1800 }
1801
1802 void ppc40x_system_reset(PowerPCCPU *cpu)
1803 {
1804 printf("Reset PowerPC system\n");
1805 qemu_system_reset_request();
1806 }
1807
1808 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1809 {
1810 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1811
1812 switch ((val >> 28) & 0x3) {
1813 case 0x0:
1814 /* No action */
1815 break;
1816 case 0x1:
1817 /* Core reset */
1818 ppc40x_core_reset(cpu);
1819 break;
1820 case 0x2:
1821 /* Chip reset */
1822 ppc40x_chip_reset(cpu);
1823 break;
1824 case 0x3:
1825 /* System reset */
1826 ppc40x_system_reset(cpu);
1827 break;
1828 }
1829 }
1830
1831 /*****************************************************************************/
1832 /* PowerPC 405CR */
1833 enum {
1834 PPC405CR_CPC0_PLLMR = 0x0B0,
1835 PPC405CR_CPC0_CR0 = 0x0B1,
1836 PPC405CR_CPC0_CR1 = 0x0B2,
1837 PPC405CR_CPC0_PSR = 0x0B4,
1838 PPC405CR_CPC0_JTAGID = 0x0B5,
1839 PPC405CR_CPC0_ER = 0x0B9,
1840 PPC405CR_CPC0_FR = 0x0BA,
1841 PPC405CR_CPC0_SR = 0x0BB,
1842 };
1843
1844 enum {
1845 PPC405CR_CPU_CLK = 0,
1846 PPC405CR_TMR_CLK = 1,
1847 PPC405CR_PLB_CLK = 2,
1848 PPC405CR_SDRAM_CLK = 3,
1849 PPC405CR_OPB_CLK = 4,
1850 PPC405CR_EXT_CLK = 5,
1851 PPC405CR_UART_CLK = 6,
1852 PPC405CR_CLK_NB = 7,
1853 };
1854
1855 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1856 struct ppc405cr_cpc_t {
1857 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1858 uint32_t sysclk;
1859 uint32_t psr;
1860 uint32_t cr0;
1861 uint32_t cr1;
1862 uint32_t jtagid;
1863 uint32_t pllmr;
1864 uint32_t er;
1865 uint32_t fr;
1866 };
1867
1868 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1869 {
1870 uint64_t VCO_out, PLL_out;
1871 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1872 int M, D0, D1, D2;
1873
1874 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1875 if (cpc->pllmr & 0x80000000) {
1876 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1877 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1878 M = D0 * D1 * D2;
1879 VCO_out = cpc->sysclk * M;
1880 if (VCO_out < 400000000 || VCO_out > 800000000) {
1881 /* PLL cannot lock */
1882 cpc->pllmr &= ~0x80000000;
1883 goto bypass_pll;
1884 }
1885 PLL_out = VCO_out / D2;
1886 } else {
1887 /* Bypass PLL */
1888 bypass_pll:
1889 M = D0;
1890 PLL_out = cpc->sysclk * M;
1891 }
1892 CPU_clk = PLL_out;
1893 if (cpc->cr1 & 0x00800000)
1894 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1895 else
1896 TMR_clk = CPU_clk;
1897 PLB_clk = CPU_clk / D0;
1898 SDRAM_clk = PLB_clk;
1899 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1900 OPB_clk = PLB_clk / D0;
1901 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1902 EXT_clk = PLB_clk / D0;
1903 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1904 UART_clk = CPU_clk / D0;
1905 /* Setup CPU clocks */
1906 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1907 /* Setup time-base clock */
1908 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1909 /* Setup PLB clock */
1910 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1911 /* Setup SDRAM clock */
1912 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1913 /* Setup OPB clock */
1914 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1915 /* Setup external clock */
1916 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1917 /* Setup UART clock */
1918 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1919 }
1920
1921 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1922 {
1923 ppc405cr_cpc_t *cpc;
1924 uint32_t ret;
1925
1926 cpc = opaque;
1927 switch (dcrn) {
1928 case PPC405CR_CPC0_PLLMR:
1929 ret = cpc->pllmr;
1930 break;
1931 case PPC405CR_CPC0_CR0:
1932 ret = cpc->cr0;
1933 break;
1934 case PPC405CR_CPC0_CR1:
1935 ret = cpc->cr1;
1936 break;
1937 case PPC405CR_CPC0_PSR:
1938 ret = cpc->psr;
1939 break;
1940 case PPC405CR_CPC0_JTAGID:
1941 ret = cpc->jtagid;
1942 break;
1943 case PPC405CR_CPC0_ER:
1944 ret = cpc->er;
1945 break;
1946 case PPC405CR_CPC0_FR:
1947 ret = cpc->fr;
1948 break;
1949 case PPC405CR_CPC0_SR:
1950 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1951 break;
1952 default:
1953 /* Avoid gcc warning */
1954 ret = 0;
1955 break;
1956 }
1957
1958 return ret;
1959 }
1960
1961 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1962 {
1963 ppc405cr_cpc_t *cpc;
1964
1965 cpc = opaque;
1966 switch (dcrn) {
1967 case PPC405CR_CPC0_PLLMR:
1968 cpc->pllmr = val & 0xFFF77C3F;
1969 break;
1970 case PPC405CR_CPC0_CR0:
1971 cpc->cr0 = val & 0x0FFFFFFE;
1972 break;
1973 case PPC405CR_CPC0_CR1:
1974 cpc->cr1 = val & 0x00800000;
1975 break;
1976 case PPC405CR_CPC0_PSR:
1977 /* Read-only */
1978 break;
1979 case PPC405CR_CPC0_JTAGID:
1980 /* Read-only */
1981 break;
1982 case PPC405CR_CPC0_ER:
1983 cpc->er = val & 0xBFFC0000;
1984 break;
1985 case PPC405CR_CPC0_FR:
1986 cpc->fr = val & 0xBFFC0000;
1987 break;
1988 case PPC405CR_CPC0_SR:
1989 /* Read-only */
1990 break;
1991 }
1992 }
1993
1994 static void ppc405cr_cpc_reset (void *opaque)
1995 {
1996 ppc405cr_cpc_t *cpc;
1997 int D;
1998
1999 cpc = opaque;
2000 /* Compute PLLMR value from PSR settings */
2001 cpc->pllmr = 0x80000000;
2002 /* PFWD */
2003 switch ((cpc->psr >> 30) & 3) {
2004 case 0:
2005 /* Bypass */
2006 cpc->pllmr &= ~0x80000000;
2007 break;
2008 case 1:
2009 /* Divide by 3 */
2010 cpc->pllmr |= 5 << 16;
2011 break;
2012 case 2:
2013 /* Divide by 4 */
2014 cpc->pllmr |= 4 << 16;
2015 break;
2016 case 3:
2017 /* Divide by 6 */
2018 cpc->pllmr |= 2 << 16;
2019 break;
2020 }
2021 /* PFBD */
2022 D = (cpc->psr >> 28) & 3;
2023 cpc->pllmr |= (D + 1) << 20;
2024 /* PT */
2025 D = (cpc->psr >> 25) & 7;
2026 switch (D) {
2027 case 0x2:
2028 cpc->pllmr |= 0x13;
2029 break;
2030 case 0x4:
2031 cpc->pllmr |= 0x15;
2032 break;
2033 case 0x5:
2034 cpc->pllmr |= 0x16;
2035 break;
2036 default:
2037 break;
2038 }
2039 /* PDC */
2040 D = (cpc->psr >> 23) & 3;
2041 cpc->pllmr |= D << 26;
2042 /* ODP */
2043 D = (cpc->psr >> 21) & 3;
2044 cpc->pllmr |= D << 10;
2045 /* EBPD */
2046 D = (cpc->psr >> 17) & 3;
2047 cpc->pllmr |= D << 24;
2048 cpc->cr0 = 0x0000003C;
2049 cpc->cr1 = 0x2B0D8800;
2050 cpc->er = 0x00000000;
2051 cpc->fr = 0x00000000;
2052 ppc405cr_clk_setup(cpc);
2053 }
2054
2055 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2056 {
2057 int D;
2058
2059 /* XXX: this should be read from IO pins */
2060 cpc->psr = 0x00000000; /* 8 bits ROM */
2061 /* PFWD */
2062 D = 0x2; /* Divide by 4 */
2063 cpc->psr |= D << 30;
2064 /* PFBD */
2065 D = 0x1; /* Divide by 2 */
2066 cpc->psr |= D << 28;
2067 /* PDC */
2068 D = 0x1; /* Divide by 2 */
2069 cpc->psr |= D << 23;
2070 /* PT */
2071 D = 0x5; /* M = 16 */
2072 cpc->psr |= D << 25;
2073 /* ODP */
2074 D = 0x1; /* Divide by 2 */
2075 cpc->psr |= D << 21;
2076 /* EBDP */
2077 D = 0x2; /* Divide by 4 */
2078 cpc->psr |= D << 17;
2079 }
2080
2081 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2082 uint32_t sysclk)
2083 {
2084 ppc405cr_cpc_t *cpc;
2085
2086 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2087 memcpy(cpc->clk_setup, clk_setup,
2088 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2089 cpc->sysclk = sysclk;
2090 cpc->jtagid = 0x42051049;
2091 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2092 &dcr_read_crcpc, &dcr_write_crcpc);
2093 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2094 &dcr_read_crcpc, &dcr_write_crcpc);
2095 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2096 &dcr_read_crcpc, &dcr_write_crcpc);
2097 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2098 &dcr_read_crcpc, &dcr_write_crcpc);
2099 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2100 &dcr_read_crcpc, &dcr_write_crcpc);
2101 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2106 &dcr_read_crcpc, &dcr_write_crcpc);
2107 ppc405cr_clk_init(cpc);
2108 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2109 }
2110
2111 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2112 MemoryRegion ram_memories[4],
2113 hwaddr ram_bases[4],
2114 hwaddr ram_sizes[4],
2115 uint32_t sysclk, qemu_irq **picp,
2116 int do_init)
2117 {
2118 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2119 qemu_irq dma_irqs[4];
2120 PowerPCCPU *cpu;
2121 CPUPPCState *env;
2122 qemu_irq *pic, *irqs;
2123
2124 memset(clk_setup, 0, sizeof(clk_setup));
2125 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2126 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2127 env = &cpu->env;
2128 /* Memory mapped devices registers */
2129 /* PLB arbitrer */
2130 ppc4xx_plb_init(env);
2131 /* PLB to OPB bridge */
2132 ppc4xx_pob_init(env);
2133 /* OBP arbitrer */
2134 ppc4xx_opba_init(0xef600600);
2135 /* Universal interrupt controller */
2136 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2137 irqs[PPCUIC_OUTPUT_INT] =
2138 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2139 irqs[PPCUIC_OUTPUT_CINT] =
2140 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2141 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2142 *picp = pic;
2143 /* SDRAM controller */
2144 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2145 ram_bases, ram_sizes, do_init);
2146 /* External bus controller */
2147 ppc405_ebc_init(env);
2148 /* DMA controller */
2149 dma_irqs[0] = pic[26];
2150 dma_irqs[1] = pic[25];
2151 dma_irqs[2] = pic[24];
2152 dma_irqs[3] = pic[23];
2153 ppc405_dma_init(env, dma_irqs);
2154 /* Serial ports */
2155 if (serial_hds[0] != NULL) {
2156 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2157 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2158 DEVICE_BIG_ENDIAN);
2159 }
2160 if (serial_hds[1] != NULL) {
2161 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2162 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2163 DEVICE_BIG_ENDIAN);
2164 }
2165 /* IIC controller */
2166 ppc405_i2c_init(0xef600500, pic[2]);
2167 /* GPIO */
2168 ppc405_gpio_init(0xef600700);
2169 /* CPU control */
2170 ppc405cr_cpc_init(env, clk_setup, sysclk);
2171
2172 return env;
2173 }
2174
2175 /*****************************************************************************/
2176 /* PowerPC 405EP */
2177 /* CPU control */
2178 enum {
2179 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2180 PPC405EP_CPC0_BOOT = 0x0F1,
2181 PPC405EP_CPC0_EPCTL = 0x0F3,
2182 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2183 PPC405EP_CPC0_UCR = 0x0F5,
2184 PPC405EP_CPC0_SRR = 0x0F6,
2185 PPC405EP_CPC0_JTAGID = 0x0F7,
2186 PPC405EP_CPC0_PCI = 0x0F9,
2187 #if 0
2188 PPC405EP_CPC0_ER = xxx,
2189 PPC405EP_CPC0_FR = xxx,
2190 PPC405EP_CPC0_SR = xxx,
2191 #endif
2192 };
2193
2194 enum {
2195 PPC405EP_CPU_CLK = 0,
2196 PPC405EP_PLB_CLK = 1,
2197 PPC405EP_OPB_CLK = 2,
2198 PPC405EP_EBC_CLK = 3,
2199 PPC405EP_MAL_CLK = 4,
2200 PPC405EP_PCI_CLK = 5,
2201 PPC405EP_UART0_CLK = 6,
2202 PPC405EP_UART1_CLK = 7,
2203 PPC405EP_CLK_NB = 8,
2204 };
2205
2206 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2207 struct ppc405ep_cpc_t {
2208 uint32_t sysclk;
2209 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2210 uint32_t boot;
2211 uint32_t epctl;
2212 uint32_t pllmr[2];
2213 uint32_t ucr;
2214 uint32_t srr;
2215 uint32_t jtagid;
2216 uint32_t pci;
2217 /* Clock and power management */
2218 uint32_t er;
2219 uint32_t fr;
2220 uint32_t sr;
2221 };
2222
2223 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2224 {
2225 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2226 uint32_t UART0_clk, UART1_clk;
2227 uint64_t VCO_out, PLL_out;
2228 int M, D;
2229
2230 VCO_out = 0;
2231 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2232 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2233 #ifdef DEBUG_CLOCKS_LL
2234 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2235 #endif
2236 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2237 #ifdef DEBUG_CLOCKS_LL
2238 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2239 #endif
2240 VCO_out = cpc->sysclk * M * D;
2241 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2242 /* Error - unlock the PLL */
2243 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2244 #if 0
2245 cpc->pllmr[1] &= ~0x80000000;
2246 goto pll_bypass;
2247 #endif
2248 }
2249 PLL_out = VCO_out / D;
2250 /* Pretend the PLL is locked */
2251 cpc->boot |= 0x00000001;
2252 } else {
2253 #if 0
2254 pll_bypass:
2255 #endif
2256 PLL_out = cpc->sysclk;
2257 if (cpc->pllmr[1] & 0x40000000) {
2258 /* Pretend the PLL is not locked */
2259 cpc->boot &= ~0x00000001;
2260 }
2261 }
2262 /* Now, compute all other clocks */
2263 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2264 #ifdef DEBUG_CLOCKS_LL
2265 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2266 #endif
2267 CPU_clk = PLL_out / D;
2268 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2269 #ifdef DEBUG_CLOCKS_LL
2270 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2271 #endif
2272 PLB_clk = CPU_clk / D;
2273 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2274 #ifdef DEBUG_CLOCKS_LL
2275 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2276 #endif
2277 OPB_clk = PLB_clk / D;
2278 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2279 #ifdef DEBUG_CLOCKS_LL
2280 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2281 #endif
2282 EBC_clk = PLB_clk / D;
2283 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2284 #ifdef DEBUG_CLOCKS_LL
2285 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2286 #endif
2287 MAL_clk = PLB_clk / D;
2288 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2289 #ifdef DEBUG_CLOCKS_LL
2290 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2291 #endif
2292 PCI_clk = PLB_clk / D;
2293 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2294 #ifdef DEBUG_CLOCKS_LL
2295 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2296 #endif
2297 UART0_clk = PLL_out / D;
2298 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2299 #ifdef DEBUG_CLOCKS_LL
2300 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2301 #endif
2302 UART1_clk = PLL_out / D;
2303 #ifdef DEBUG_CLOCKS
2304 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2305 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2306 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2307 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2308 " UART1 %" PRIu32 "\n",
2309 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2310 UART0_clk, UART1_clk);
2311 #endif
2312 /* Setup CPU clocks */
2313 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2314 /* Setup PLB clock */
2315 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2316 /* Setup OPB clock */
2317 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2318 /* Setup external clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2320 /* Setup MAL clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2322 /* Setup PCI clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2324 /* Setup UART0 clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2326 /* Setup UART1 clock */
2327 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2328 }
2329
2330 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2331 {
2332 ppc405ep_cpc_t *cpc;
2333 uint32_t ret;
2334
2335 cpc = opaque;
2336 switch (dcrn) {
2337 case PPC405EP_CPC0_BOOT:
2338 ret = cpc->boot;
2339 break;
2340 case PPC405EP_CPC0_EPCTL:
2341 ret = cpc->epctl;
2342 break;
2343 case PPC405EP_CPC0_PLLMR0:
2344 ret = cpc->pllmr[0];
2345 break;
2346 case PPC405EP_CPC0_PLLMR1:
2347 ret = cpc->pllmr[1];
2348 break;
2349 case PPC405EP_CPC0_UCR:
2350 ret = cpc->ucr;
2351 break;
2352 case PPC405EP_CPC0_SRR:
2353 ret = cpc->srr;
2354 break;
2355 case PPC405EP_CPC0_JTAGID:
2356 ret = cpc->jtagid;
2357 break;
2358 case PPC405EP_CPC0_PCI:
2359 ret = cpc->pci;
2360 break;
2361 default:
2362 /* Avoid gcc warning */
2363 ret = 0;
2364 break;
2365 }
2366
2367 return ret;
2368 }
2369
2370 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2371 {
2372 ppc405ep_cpc_t *cpc;
2373
2374 cpc = opaque;
2375 switch (dcrn) {
2376 case PPC405EP_CPC0_BOOT:
2377 /* Read-only register */
2378 break;
2379 case PPC405EP_CPC0_EPCTL:
2380 /* Don't care for now */
2381 cpc->epctl = val & 0xC00000F3;
2382 break;
2383 case PPC405EP_CPC0_PLLMR0:
2384 cpc->pllmr[0] = val & 0x00633333;
2385 ppc405ep_compute_clocks(cpc);
2386 break;
2387 case PPC405EP_CPC0_PLLMR1:
2388 cpc->pllmr[1] = val & 0xC0F73FFF;
2389 ppc405ep_compute_clocks(cpc);
2390 break;
2391 case PPC405EP_CPC0_UCR:
2392 /* UART control - don't care for now */
2393 cpc->ucr = val & 0x003F7F7F;
2394 break;
2395 case PPC405EP_CPC0_SRR:
2396 cpc->srr = val;
2397 break;
2398 case PPC405EP_CPC0_JTAGID:
2399 /* Read-only */
2400 break;
2401 case PPC405EP_CPC0_PCI:
2402 cpc->pci = val;
2403 break;
2404 }
2405 }
2406
2407 static void ppc405ep_cpc_reset (void *opaque)
2408 {
2409 ppc405ep_cpc_t *cpc = opaque;
2410
2411 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2412 cpc->epctl = 0x00000000;
2413 cpc->pllmr[0] = 0x00011010;
2414 cpc->pllmr[1] = 0x40000000;
2415 cpc->ucr = 0x00000000;
2416 cpc->srr = 0x00040000;
2417 cpc->pci = 0x00000000;
2418 cpc->er = 0x00000000;
2419 cpc->fr = 0x00000000;
2420 cpc->sr = 0x00000000;
2421 ppc405ep_compute_clocks(cpc);
2422 }
2423
2424 /* XXX: sysclk should be between 25 and 100 MHz */
2425 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2426 uint32_t sysclk)
2427 {
2428 ppc405ep_cpc_t *cpc;
2429
2430 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2431 memcpy(cpc->clk_setup, clk_setup,
2432 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2433 cpc->jtagid = 0x20267049;
2434 cpc->sysclk = sysclk;
2435 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2436 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2437 &dcr_read_epcpc, &dcr_write_epcpc);
2438 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2439 &dcr_read_epcpc, &dcr_write_epcpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2450 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2451 &dcr_read_epcpc, &dcr_write_epcpc);
2452 #if 0
2453 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2454 &dcr_read_epcpc, &dcr_write_epcpc);
2455 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2456 &dcr_read_epcpc, &dcr_write_epcpc);
2457 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2458 &dcr_read_epcpc, &dcr_write_epcpc);
2459 #endif
2460 }
2461
2462 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2463 MemoryRegion ram_memories[2],
2464 hwaddr ram_bases[2],
2465 hwaddr ram_sizes[2],
2466 uint32_t sysclk, qemu_irq **picp,
2467 int do_init)
2468 {
2469 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2470 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2471 PowerPCCPU *cpu;
2472 CPUPPCState *env;
2473 qemu_irq *pic, *irqs;
2474
2475 memset(clk_setup, 0, sizeof(clk_setup));
2476 /* init CPUs */
2477 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2478 &tlb_clk_setup, sysclk);
2479 env = &cpu->env;
2480 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2481 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2482 /* Internal devices init */
2483 /* Memory mapped devices registers */
2484 /* PLB arbitrer */
2485 ppc4xx_plb_init(env);
2486 /* PLB to OPB bridge */
2487 ppc4xx_pob_init(env);
2488 /* OBP arbitrer */
2489 ppc4xx_opba_init(0xef600600);
2490 /* Initialize timers */
2491 ppc_booke_timers_init(cpu, sysclk, 0);
2492 /* Universal interrupt controller */
2493 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2494 irqs[PPCUIC_OUTPUT_INT] =
2495 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2496 irqs[PPCUIC_OUTPUT_CINT] =
2497 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2498 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2499 *picp = pic;
2500 /* SDRAM controller */
2501 /* XXX 405EP has no ECC interrupt */
2502 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2503 ram_bases, ram_sizes, do_init);
2504 /* External bus controller */
2505 ppc405_ebc_init(env);
2506 /* DMA controller */
2507 dma_irqs[0] = pic[5];
2508 dma_irqs[1] = pic[6];
2509 dma_irqs[2] = pic[7];
2510 dma_irqs[3] = pic[8];
2511 ppc405_dma_init(env, dma_irqs);
2512 /* IIC controller */
2513 ppc405_i2c_init(0xef600500, pic[2]);
2514 /* GPIO */
2515 ppc405_gpio_init(0xef600700);
2516 /* Serial ports */
2517 if (serial_hds[0] != NULL) {
2518 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2519 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2520 DEVICE_BIG_ENDIAN);
2521 }
2522 if (serial_hds[1] != NULL) {
2523 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2524 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2525 DEVICE_BIG_ENDIAN);
2526 }
2527 /* OCM */
2528 ppc405_ocm_init(env);
2529 /* GPT */
2530 gpt_irqs[0] = pic[19];
2531 gpt_irqs[1] = pic[20];
2532 gpt_irqs[2] = pic[21];
2533 gpt_irqs[3] = pic[22];
2534 gpt_irqs[4] = pic[23];
2535 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2536 /* PCI */
2537 /* Uses pic[3], pic[16], pic[18] */
2538 /* MAL */
2539 mal_irqs[0] = pic[11];
2540 mal_irqs[1] = pic[12];
2541 mal_irqs[2] = pic[13];
2542 mal_irqs[3] = pic[14];
2543 ppc405_mal_init(env, mal_irqs);
2544 /* Ethernet */
2545 /* Uses pic[9], pic[15], pic[17] */
2546 /* CPU control */
2547 ppc405ep_cpc_init(env, clk_setup, sysclk);
2548
2549 return env;
2550 }
AR7 emulation for QEMU