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target/arm: Check supported KVM features globally (not per vCPU)
[qemu/ar7.git] / hw / virtio / virtio-pci.c
blob7bc8c1c056e9acf6d2c27bc009ff527ce5d80fd5
1 /*
2 * Virtio PCI Bindings
3 *
4 * Copyright IBM, Corp. 2007
5 * Copyright (c) 2009 CodeSourcery
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 * Paul Brook <paul@codesourcery.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 *
14 * Contributions after 2012-01-13 are licensed under the terms of the
15 * GNU GPL, version 2 or (at your option) any later version.
16 */
17
18 #include "qemu/osdep.h"
19
20 #include "exec/memop.h"
21 #include "standard-headers/linux/virtio_pci.h"
22 #include "hw/virtio/virtio.h"
23 #include "migration/qemu-file-types.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/pci_bus.h"
26 #include "hw/qdev-properties.h"
27 #include "qapi/error.h"
28 #include "qemu/error-report.h"
29 #include "qemu/module.h"
30 #include "hw/pci/msi.h"
31 #include "hw/pci/msix.h"
32 #include "hw/loader.h"
33 #include "sysemu/kvm.h"
34 #include "virtio-pci.h"
35 #include "qemu/range.h"
36 #include "hw/virtio/virtio-bus.h"
37 #include "qapi/visitor.h"
38
39 #define VIRTIO_PCI_REGION_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_present(dev))
40
41 #undef VIRTIO_PCI_CONFIG
42
43 /* The remaining space is defined by each driver as the per-driver
44 * configuration space */
45 #define VIRTIO_PCI_CONFIG_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_enabled(dev))
46
47 static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
48 VirtIOPCIProxy *dev);
49 static void virtio_pci_reset(DeviceState *qdev);
50
51 /* virtio device */
52 /* DeviceState to VirtIOPCIProxy. For use off data-path. TODO: use QOM. */
53 static inline VirtIOPCIProxy *to_virtio_pci_proxy(DeviceState *d)
54 {
55 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
56 }
57
58 /* DeviceState to VirtIOPCIProxy. Note: used on datapath,
59 * be careful and test performance if you change this.
60 */
61 static inline VirtIOPCIProxy *to_virtio_pci_proxy_fast(DeviceState *d)
62 {
63 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
64 }
65
66 static void virtio_pci_notify(DeviceState *d, uint16_t vector)
67 {
68 VirtIOPCIProxy *proxy = to_virtio_pci_proxy_fast(d);
69
70 if (msix_enabled(&proxy->pci_dev))
71 msix_notify(&proxy->pci_dev, vector);
72 else {
73 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
74 pci_set_irq(&proxy->pci_dev, atomic_read(&vdev->isr) & 1);
75 }
76 }
77
78 static void virtio_pci_save_config(DeviceState *d, QEMUFile *f)
79 {
80 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
81 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
82
83 pci_device_save(&proxy->pci_dev, f);
84 msix_save(&proxy->pci_dev, f);
85 if (msix_present(&proxy->pci_dev))
86 qemu_put_be16(f, vdev->config_vector);
87 }
88
89 static const VMStateDescription vmstate_virtio_pci_modern_queue_state = {
90 .name = "virtio_pci/modern_queue_state",
91 .version_id = 1,
92 .minimum_version_id = 1,
93 .fields = (VMStateField[]) {
94 VMSTATE_UINT16(num, VirtIOPCIQueue),
95 VMSTATE_UNUSED(1), /* enabled was stored as be16 */
96 VMSTATE_BOOL(enabled, VirtIOPCIQueue),
97 VMSTATE_UINT32_ARRAY(desc, VirtIOPCIQueue, 2),
98 VMSTATE_UINT32_ARRAY(avail, VirtIOPCIQueue, 2),
99 VMSTATE_UINT32_ARRAY(used, VirtIOPCIQueue, 2),
100 VMSTATE_END_OF_LIST()
101 }
102 };
103
104 static bool virtio_pci_modern_state_needed(void *opaque)
105 {
106 VirtIOPCIProxy *proxy = opaque;
107
108 return virtio_pci_modern(proxy);
109 }
110
111 static const VMStateDescription vmstate_virtio_pci_modern_state_sub = {
112 .name = "virtio_pci/modern_state",
113 .version_id = 1,
114 .minimum_version_id = 1,
115 .needed = &virtio_pci_modern_state_needed,
116 .fields = (VMStateField[]) {
117 VMSTATE_UINT32(dfselect, VirtIOPCIProxy),
118 VMSTATE_UINT32(gfselect, VirtIOPCIProxy),
119 VMSTATE_UINT32_ARRAY(guest_features, VirtIOPCIProxy, 2),
120 VMSTATE_STRUCT_ARRAY(vqs, VirtIOPCIProxy, VIRTIO_QUEUE_MAX, 0,
121 vmstate_virtio_pci_modern_queue_state,
122 VirtIOPCIQueue),
123 VMSTATE_END_OF_LIST()
124 }
125 };
126
127 static const VMStateDescription vmstate_virtio_pci = {
128 .name = "virtio_pci",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .minimum_version_id_old = 1,
132 .fields = (VMStateField[]) {
133 VMSTATE_END_OF_LIST()
134 },
135 .subsections = (const VMStateDescription*[]) {
136 &vmstate_virtio_pci_modern_state_sub,
137 NULL
138 }
139 };
140
141 static bool virtio_pci_has_extra_state(DeviceState *d)
142 {
143 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
144
145 return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
146 }
147
148 static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
149 {
150 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
151
152 vmstate_save_state(f, &vmstate_virtio_pci, proxy, NULL);
153 }
154
155 static int virtio_pci_load_extra_state(DeviceState *d, QEMUFile *f)
156 {
157 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
158
159 return vmstate_load_state(f, &vmstate_virtio_pci, proxy, 1);
160 }
161
162 static void virtio_pci_save_queue(DeviceState *d, int n, QEMUFile *f)
163 {
164 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
165 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
166
167 if (msix_present(&proxy->pci_dev))
168 qemu_put_be16(f, virtio_queue_vector(vdev, n));
169 }
170
171 static int virtio_pci_load_config(DeviceState *d, QEMUFile *f)
172 {
173 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
174 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
175
176 int ret;
177 ret = pci_device_load(&proxy->pci_dev, f);
178 if (ret) {
179 return ret;
180 }
181 msix_unuse_all_vectors(&proxy->pci_dev);
182 msix_load(&proxy->pci_dev, f);
183 if (msix_present(&proxy->pci_dev)) {
184 qemu_get_be16s(f, &vdev->config_vector);
185 } else {
186 vdev->config_vector = VIRTIO_NO_VECTOR;
187 }
188 if (vdev->config_vector != VIRTIO_NO_VECTOR) {
189 return msix_vector_use(&proxy->pci_dev, vdev->config_vector);
190 }
191 return 0;
192 }
193
194 static int virtio_pci_load_queue(DeviceState *d, int n, QEMUFile *f)
195 {
196 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
197 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
198
199 uint16_t vector;
200 if (msix_present(&proxy->pci_dev)) {
201 qemu_get_be16s(f, &vector);
202 } else {
203 vector = VIRTIO_NO_VECTOR;
204 }
205 virtio_queue_set_vector(vdev, n, vector);
206 if (vector != VIRTIO_NO_VECTOR) {
207 return msix_vector_use(&proxy->pci_dev, vector);
208 }
209
210 return 0;
211 }
212
213 static bool virtio_pci_ioeventfd_enabled(DeviceState *d)
214 {
215 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
216
217 return (proxy->flags & VIRTIO_PCI_FLAG_USE_IOEVENTFD) != 0;
218 }
219
220 #define QEMU_VIRTIO_PCI_QUEUE_MEM_MULT 0x1000
221
222 static inline int virtio_pci_queue_mem_mult(struct VirtIOPCIProxy *proxy)
223 {
224 return (proxy->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ) ?
225 QEMU_VIRTIO_PCI_QUEUE_MEM_MULT : 4;
226 }
227
228 static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier,
229 int n, bool assign)
230 {
231 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
232 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
233 VirtQueue *vq = virtio_get_queue(vdev, n);
234 bool legacy = virtio_pci_legacy(proxy);
235 bool modern = virtio_pci_modern(proxy);
236 bool fast_mmio = kvm_ioeventfd_any_length_enabled();
237 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
238 MemoryRegion *modern_mr = &proxy->notify.mr;
239 MemoryRegion *modern_notify_mr = &proxy->notify_pio.mr;
240 MemoryRegion *legacy_mr = &proxy->bar;
241 hwaddr modern_addr = virtio_pci_queue_mem_mult(proxy) *
242 virtio_get_queue_index(vq);
243 hwaddr legacy_addr = VIRTIO_PCI_QUEUE_NOTIFY;
244
245 if (assign) {
246 if (modern) {
247 if (fast_mmio) {
248 memory_region_add_eventfd(modern_mr, modern_addr, 0,
249 false, n, notifier);
250 } else {
251 memory_region_add_eventfd(modern_mr, modern_addr, 2,
252 false, n, notifier);
253 }
254 if (modern_pio) {
255 memory_region_add_eventfd(modern_notify_mr, 0, 2,
256 true, n, notifier);
257 }
258 }
259 if (legacy) {
260 memory_region_add_eventfd(legacy_mr, legacy_addr, 2,
261 true, n, notifier);
262 }
263 } else {
264 if (modern) {
265 if (fast_mmio) {
266 memory_region_del_eventfd(modern_mr, modern_addr, 0,
267 false, n, notifier);
268 } else {
269 memory_region_del_eventfd(modern_mr, modern_addr, 2,
270 false, n, notifier);
271 }
272 if (modern_pio) {
273 memory_region_del_eventfd(modern_notify_mr, 0, 2,
274 true, n, notifier);
275 }
276 }
277 if (legacy) {
278 memory_region_del_eventfd(legacy_mr, legacy_addr, 2,
279 true, n, notifier);
280 }
281 }
282 return 0;
283 }
284
285 static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy)
286 {
287 virtio_bus_start_ioeventfd(&proxy->bus);
288 }
289
290 static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy)
291 {
292 virtio_bus_stop_ioeventfd(&proxy->bus);
293 }
294
295 static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
296 {
297 VirtIOPCIProxy *proxy = opaque;
298 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
299 hwaddr pa;
300
301 switch (addr) {
302 case VIRTIO_PCI_GUEST_FEATURES:
303 /* Guest does not negotiate properly? We have to assume nothing. */
304 if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
305 val = virtio_bus_get_vdev_bad_features(&proxy->bus);
306 }
307 virtio_set_features(vdev, val);
308 break;
309 case VIRTIO_PCI_QUEUE_PFN:
310 pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
311 if (pa == 0) {
312 virtio_pci_reset(DEVICE(proxy));
313 }
314 else
315 virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
316 break;
317 case VIRTIO_PCI_QUEUE_SEL:
318 if (val < VIRTIO_QUEUE_MAX)
319 vdev->queue_sel = val;
320 break;
321 case VIRTIO_PCI_QUEUE_NOTIFY:
322 if (val < VIRTIO_QUEUE_MAX) {
323 virtio_queue_notify(vdev, val);
324 }
325 break;
326 case VIRTIO_PCI_STATUS:
327 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
328 virtio_pci_stop_ioeventfd(proxy);
329 }
330
331 virtio_set_status(vdev, val & 0xFF);
332
333 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
334 virtio_pci_start_ioeventfd(proxy);
335 }
336
337 if (vdev->status == 0) {
338 virtio_pci_reset(DEVICE(proxy));
339 }
340
341 /* Linux before 2.6.34 drives the device without enabling
342 the PCI device bus master bit. Enable it automatically
343 for the guest. This is a PCI spec violation but so is
344 initiating DMA with bus master bit clear. */
345 if (val == (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER)) {
346 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
347 proxy->pci_dev.config[PCI_COMMAND] |
348 PCI_COMMAND_MASTER, 1);
349 }
350 break;
351 case VIRTIO_MSI_CONFIG_VECTOR:
352 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
353 /* Make it possible for guest to discover an error took place. */
354 if (msix_vector_use(&proxy->pci_dev, val) < 0)
355 val = VIRTIO_NO_VECTOR;
356 vdev->config_vector = val;
357 break;
358 case VIRTIO_MSI_QUEUE_VECTOR:
359 msix_vector_unuse(&proxy->pci_dev,
360 virtio_queue_vector(vdev, vdev->queue_sel));
361 /* Make it possible for guest to discover an error took place. */
362 if (msix_vector_use(&proxy->pci_dev, val) < 0)
363 val = VIRTIO_NO_VECTOR;
364 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
365 break;
366 default:
367 error_report("%s: unexpected address 0x%x value 0x%x",
368 __func__, addr, val);
369 break;
370 }
371 }
372
373 static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
374 {
375 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
376 uint32_t ret = 0xFFFFFFFF;
377
378 switch (addr) {
379 case VIRTIO_PCI_HOST_FEATURES:
380 ret = vdev->host_features;
381 break;
382 case VIRTIO_PCI_GUEST_FEATURES:
383 ret = vdev->guest_features;
384 break;
385 case VIRTIO_PCI_QUEUE_PFN:
386 ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
387 >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
388 break;
389 case VIRTIO_PCI_QUEUE_NUM:
390 ret = virtio_queue_get_num(vdev, vdev->queue_sel);
391 break;
392 case VIRTIO_PCI_QUEUE_SEL:
393 ret = vdev->queue_sel;
394 break;
395 case VIRTIO_PCI_STATUS:
396 ret = vdev->status;
397 break;
398 case VIRTIO_PCI_ISR:
399 /* reading from the ISR also clears it. */
400 ret = atomic_xchg(&vdev->isr, 0);
401 pci_irq_deassert(&proxy->pci_dev);
402 break;
403 case VIRTIO_MSI_CONFIG_VECTOR:
404 ret = vdev->config_vector;
405 break;
406 case VIRTIO_MSI_QUEUE_VECTOR:
407 ret = virtio_queue_vector(vdev, vdev->queue_sel);
408 break;
409 default:
410 break;
411 }
412
413 return ret;
414 }
415
416 static uint64_t virtio_pci_config_read(void *opaque, hwaddr addr,
417 unsigned size)
418 {
419 VirtIOPCIProxy *proxy = opaque;
420 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
421 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
422 uint64_t val = 0;
423 if (addr < config) {
424 return virtio_ioport_read(proxy, addr);
425 }
426 addr -= config;
427
428 switch (size) {
429 case 1:
430 val = virtio_config_readb(vdev, addr);
431 break;
432 case 2:
433 val = virtio_config_readw(vdev, addr);
434 if (virtio_is_big_endian(vdev)) {
435 val = bswap16(val);
436 }
437 break;
438 case 4:
439 val = virtio_config_readl(vdev, addr);
440 if (virtio_is_big_endian(vdev)) {
441 val = bswap32(val);
442 }
443 break;
444 }
445 return val;
446 }
447
448 static void virtio_pci_config_write(void *opaque, hwaddr addr,
449 uint64_t val, unsigned size)
450 {
451 VirtIOPCIProxy *proxy = opaque;
452 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
453 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
454 if (addr < config) {
455 virtio_ioport_write(proxy, addr, val);
456 return;
457 }
458 addr -= config;
459 /*
460 * Virtio-PCI is odd. Ioports are LE but config space is target native
461 * endian.
462 */
463 switch (size) {
464 case 1:
465 virtio_config_writeb(vdev, addr, val);
466 break;
467 case 2:
468 if (virtio_is_big_endian(vdev)) {
469 val = bswap16(val);
470 }
471 virtio_config_writew(vdev, addr, val);
472 break;
473 case 4:
474 if (virtio_is_big_endian(vdev)) {
475 val = bswap32(val);
476 }
477 virtio_config_writel(vdev, addr, val);
478 break;
479 }
480 }
481
482 static const MemoryRegionOps virtio_pci_config_ops = {
483 .read = virtio_pci_config_read,
484 .write = virtio_pci_config_write,
485 .impl = {
486 .min_access_size = 1,
487 .max_access_size = 4,
488 },
489 .endianness = DEVICE_LITTLE_ENDIAN,
490 };
491
492 static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy,
493 hwaddr *off, int len)
494 {
495 int i;
496 VirtIOPCIRegion *reg;
497
498 for (i = 0; i < ARRAY_SIZE(proxy->regs); ++i) {
499 reg = &proxy->regs[i];
500 if (*off >= reg->offset &&
501 *off + len <= reg->offset + reg->size) {
502 *off -= reg->offset;
503 return &reg->mr;
504 }
505 }
506
507 return NULL;
508 }
509
510 /* Below are generic functions to do memcpy from/to an address space,
511 * without byteswaps, with input validation.
512 *
513 * As regular address_space_* APIs all do some kind of byteswap at least for
514 * some host/target combinations, we are forced to explicitly convert to a
515 * known-endianness integer value.
516 * It doesn't really matter which endian format to go through, so the code
517 * below selects the endian that causes the least amount of work on the given
518 * host.
519 *
520 * Note: host pointer must be aligned.
521 */
522 static
523 void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
524 const uint8_t *buf, int len)
525 {
526 uint64_t val;
527 MemoryRegion *mr;
528
529 /* address_space_* APIs assume an aligned address.
530 * As address is under guest control, handle illegal values.
531 */
532 addr &= ~(len - 1);
533
534 mr = virtio_address_space_lookup(proxy, &addr, len);
535 if (!mr) {
536 return;
537 }
538
539 /* Make sure caller aligned buf properly */
540 assert(!(((uintptr_t)buf) & (len - 1)));
541
542 switch (len) {
543 case 1:
544 val = pci_get_byte(buf);
545 break;
546 case 2:
547 val = pci_get_word(buf);
548 break;
549 case 4:
550 val = pci_get_long(buf);
551 break;
552 default:
553 /* As length is under guest control, handle illegal values. */
554 return;
555 }
556 memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
557 MEMTXATTRS_UNSPECIFIED);
558 }
559
560 static void
561 virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
562 uint8_t *buf, int len)
563 {
564 uint64_t val;
565 MemoryRegion *mr;
566
567 /* address_space_* APIs assume an aligned address.
568 * As address is under guest control, handle illegal values.
569 */
570 addr &= ~(len - 1);
571
572 mr = virtio_address_space_lookup(proxy, &addr, len);
573 if (!mr) {
574 return;
575 }
576
577 /* Make sure caller aligned buf properly */
578 assert(!(((uintptr_t)buf) & (len - 1)));
579
580 memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
581 MEMTXATTRS_UNSPECIFIED);
582 switch (len) {
583 case 1:
584 pci_set_byte(buf, val);
585 break;
586 case 2:
587 pci_set_word(buf, val);
588 break;
589 case 4:
590 pci_set_long(buf, val);
591 break;
592 default:
593 /* As length is under guest control, handle illegal values. */
594 break;
595 }
596 }
597
598 static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
599 uint32_t val, int len)
600 {
601 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
602 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
603 struct virtio_pci_cfg_cap *cfg;
604
605 pci_default_write_config(pci_dev, address, val, len);
606
607 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
608 pcie_cap_flr_write_config(pci_dev, address, val, len);
609 }
610
611 if (range_covers_byte(address, len, PCI_COMMAND)) {
612 if (!(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
613 virtio_set_disabled(vdev, true);
614 virtio_pci_stop_ioeventfd(proxy);
615 virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK);
616 } else {
617 virtio_set_disabled(vdev, false);
618 }
619 }
620
621 if (proxy->config_cap &&
622 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
623 pci_cfg_data),
624 sizeof cfg->pci_cfg_data)) {
625 uint32_t off;
626 uint32_t len;
627
628 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
629 off = le32_to_cpu(cfg->cap.offset);
630 len = le32_to_cpu(cfg->cap.length);
631
632 if (len == 1 || len == 2 || len == 4) {
633 assert(len <= sizeof cfg->pci_cfg_data);
634 virtio_address_space_write(proxy, off, cfg->pci_cfg_data, len);
635 }
636 }
637 }
638
639 static uint32_t virtio_read_config(PCIDevice *pci_dev,
640 uint32_t address, int len)
641 {
642 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
643 struct virtio_pci_cfg_cap *cfg;
644
645 if (proxy->config_cap &&
646 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
647 pci_cfg_data),
648 sizeof cfg->pci_cfg_data)) {
649 uint32_t off;
650 uint32_t len;
651
652 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
653 off = le32_to_cpu(cfg->cap.offset);
654 len = le32_to_cpu(cfg->cap.length);
655
656 if (len == 1 || len == 2 || len == 4) {
657 assert(len <= sizeof cfg->pci_cfg_data);
658 virtio_address_space_read(proxy, off, cfg->pci_cfg_data, len);
659 }
660 }
661
662 return pci_default_read_config(pci_dev, address, len);
663 }
664
665 static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
666 unsigned int queue_no,
667 unsigned int vector)
668 {
669 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
670 int ret;
671
672 if (irqfd->users == 0) {
673 ret = kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_dev);
674 if (ret < 0) {
675 return ret;
676 }
677 irqfd->virq = ret;
678 }
679 irqfd->users++;
680 return 0;
681 }
682
683 static void kvm_virtio_pci_vq_vector_release(VirtIOPCIProxy *proxy,
684 unsigned int vector)
685 {
686 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
687 if (--irqfd->users == 0) {
688 kvm_irqchip_release_virq(kvm_state, irqfd->virq);
689 }
690 }
691
692 static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy,
693 unsigned int queue_no,
694 unsigned int vector)
695 {
696 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
697 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
698 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
699 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
700 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq);
701 }
702
703 static void kvm_virtio_pci_irqfd_release(VirtIOPCIProxy *proxy,
704 unsigned int queue_no,
705 unsigned int vector)
706 {
707 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
708 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
709 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
710 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
711 int ret;
712
713 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, irqfd->virq);
714 assert(ret == 0);
715 }
716
717 static int kvm_virtio_pci_vector_use(VirtIOPCIProxy *proxy, int nvqs)
718 {
719 PCIDevice *dev = &proxy->pci_dev;
720 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
721 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
722 unsigned int vector;
723 int ret, queue_no;
724
725 for (queue_no = 0; queue_no < nvqs; queue_no++) {
726 if (!virtio_queue_get_num(vdev, queue_no)) {
727 break;
728 }
729 vector = virtio_queue_vector(vdev, queue_no);
730 if (vector >= msix_nr_vectors_allocated(dev)) {
731 continue;
732 }
733 ret = kvm_virtio_pci_vq_vector_use(proxy, queue_no, vector);
734 if (ret < 0) {
735 goto undo;
736 }
737 /* If guest supports masking, set up irqfd now.
738 * Otherwise, delay until unmasked in the frontend.
739 */
740 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
741 ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
742 if (ret < 0) {
743 kvm_virtio_pci_vq_vector_release(proxy, vector);
744 goto undo;
745 }
746 }
747 }
748 return 0;
749
750 undo:
751 while (--queue_no >= 0) {
752 vector = virtio_queue_vector(vdev, queue_no);
753 if (vector >= msix_nr_vectors_allocated(dev)) {
754 continue;
755 }
756 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
757 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
758 }
759 kvm_virtio_pci_vq_vector_release(proxy, vector);
760 }
761 return ret;
762 }
763
764 static void kvm_virtio_pci_vector_release(VirtIOPCIProxy *proxy, int nvqs)
765 {
766 PCIDevice *dev = &proxy->pci_dev;
767 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
768 unsigned int vector;
769 int queue_no;
770 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
771
772 for (queue_no = 0; queue_no < nvqs; queue_no++) {
773 if (!virtio_queue_get_num(vdev, queue_no)) {
774 break;
775 }
776 vector = virtio_queue_vector(vdev, queue_no);
777 if (vector >= msix_nr_vectors_allocated(dev)) {
778 continue;
779 }
780 /* If guest supports masking, clean up irqfd now.
781 * Otherwise, it was cleaned when masked in the frontend.
782 */
783 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
784 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
785 }
786 kvm_virtio_pci_vq_vector_release(proxy, vector);
787 }
788 }
789
790 static int virtio_pci_vq_vector_unmask(VirtIOPCIProxy *proxy,
791 unsigned int queue_no,
792 unsigned int vector,
793 MSIMessage msg)
794 {
795 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
796 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
797 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
798 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
799 VirtIOIRQFD *irqfd;
800 int ret = 0;
801
802 if (proxy->vector_irqfd) {
803 irqfd = &proxy->vector_irqfd[vector];
804 if (irqfd->msg.data != msg.data || irqfd->msg.address != msg.address) {
805 ret = kvm_irqchip_update_msi_route(kvm_state, irqfd->virq, msg,
806 &proxy->pci_dev);
807 if (ret < 0) {
808 return ret;
809 }
810 kvm_irqchip_commit_routes(kvm_state);
811 }
812 }
813
814 /* If guest supports masking, irqfd is already setup, unmask it.
815 * Otherwise, set it up now.
816 */
817 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
818 k->guest_notifier_mask(vdev, queue_no, false);
819 /* Test after unmasking to avoid losing events. */
820 if (k->guest_notifier_pending &&
821 k->guest_notifier_pending(vdev, queue_no)) {
822 event_notifier_set(n);
823 }
824 } else {
825 ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
826 }
827 return ret;
828 }
829
830 static void virtio_pci_vq_vector_mask(VirtIOPCIProxy *proxy,
831 unsigned int queue_no,
832 unsigned int vector)
833 {
834 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
835 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
836
837 /* If guest supports masking, keep irqfd but mask it.
838 * Otherwise, clean it up now.
839 */
840 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
841 k->guest_notifier_mask(vdev, queue_no, true);
842 } else {
843 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
844 }
845 }
846
847 static int virtio_pci_vector_unmask(PCIDevice *dev, unsigned vector,
848 MSIMessage msg)
849 {
850 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
851 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
852 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
853 int ret, index, unmasked = 0;
854
855 while (vq) {
856 index = virtio_get_queue_index(vq);
857 if (!virtio_queue_get_num(vdev, index)) {
858 break;
859 }
860 if (index < proxy->nvqs_with_notifiers) {
861 ret = virtio_pci_vq_vector_unmask(proxy, index, vector, msg);
862 if (ret < 0) {
863 goto undo;
864 }
865 ++unmasked;
866 }
867 vq = virtio_vector_next_queue(vq);
868 }
869
870 return 0;
871
872 undo:
873 vq = virtio_vector_first_queue(vdev, vector);
874 while (vq && unmasked >= 0) {
875 index = virtio_get_queue_index(vq);
876 if (index < proxy->nvqs_with_notifiers) {
877 virtio_pci_vq_vector_mask(proxy, index, vector);
878 --unmasked;
879 }
880 vq = virtio_vector_next_queue(vq);
881 }
882 return ret;
883 }
884
885 static void virtio_pci_vector_mask(PCIDevice *dev, unsigned vector)
886 {
887 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
888 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
889 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
890 int index;
891
892 while (vq) {
893 index = virtio_get_queue_index(vq);
894 if (!virtio_queue_get_num(vdev, index)) {
895 break;
896 }
897 if (index < proxy->nvqs_with_notifiers) {
898 virtio_pci_vq_vector_mask(proxy, index, vector);
899 }
900 vq = virtio_vector_next_queue(vq);
901 }
902 }
903
904 static void virtio_pci_vector_poll(PCIDevice *dev,
905 unsigned int vector_start,
906 unsigned int vector_end)
907 {
908 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
909 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
910 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
911 int queue_no;
912 unsigned int vector;
913 EventNotifier *notifier;
914 VirtQueue *vq;
915
916 for (queue_no = 0; queue_no < proxy->nvqs_with_notifiers; queue_no++) {
917 if (!virtio_queue_get_num(vdev, queue_no)) {
918 break;
919 }
920 vector = virtio_queue_vector(vdev, queue_no);
921 if (vector < vector_start || vector >= vector_end ||
922 !msix_is_masked(dev, vector)) {
923 continue;
924 }
925 vq = virtio_get_queue(vdev, queue_no);
926 notifier = virtio_queue_get_guest_notifier(vq);
927 if (k->guest_notifier_pending) {
928 if (k->guest_notifier_pending(vdev, queue_no)) {
929 msix_set_pending(dev, vector);
930 }
931 } else if (event_notifier_test_and_clear(notifier)) {
932 msix_set_pending(dev, vector);
933 }
934 }
935 }
936
937 static int virtio_pci_set_guest_notifier(DeviceState *d, int n, bool assign,
938 bool with_irqfd)
939 {
940 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
941 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
942 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
943 VirtQueue *vq = virtio_get_queue(vdev, n);
944 EventNotifier *notifier = virtio_queue_get_guest_notifier(vq);
945
946 if (assign) {
947 int r = event_notifier_init(notifier, 0);
948 if (r < 0) {
949 return r;
950 }
951 virtio_queue_set_guest_notifier_fd_handler(vq, true, with_irqfd);
952 } else {
953 virtio_queue_set_guest_notifier_fd_handler(vq, false, with_irqfd);
954 event_notifier_cleanup(notifier);
955 }
956
957 if (!msix_enabled(&proxy->pci_dev) &&
958 vdev->use_guest_notifier_mask &&
959 vdc->guest_notifier_mask) {
960 vdc->guest_notifier_mask(vdev, n, !assign);
961 }
962
963 return 0;
964 }
965
966 static bool virtio_pci_query_guest_notifiers(DeviceState *d)
967 {
968 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
969 return msix_enabled(&proxy->pci_dev);
970 }
971
972 static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign)
973 {
974 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
975 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
976 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
977 int r, n;
978 bool with_irqfd = msix_enabled(&proxy->pci_dev) &&
979 kvm_msi_via_irqfd_enabled();
980
981 nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX);
982
983 /* When deassigning, pass a consistent nvqs value
984 * to avoid leaking notifiers.
985 */
986 assert(assign || nvqs == proxy->nvqs_with_notifiers);
987
988 proxy->nvqs_with_notifiers = nvqs;
989
990 /* Must unset vector notifier while guest notifier is still assigned */
991 if ((proxy->vector_irqfd || k->guest_notifier_mask) && !assign) {
992 msix_unset_vector_notifiers(&proxy->pci_dev);
993 if (proxy->vector_irqfd) {
994 kvm_virtio_pci_vector_release(proxy, nvqs);
995 g_free(proxy->vector_irqfd);
996 proxy->vector_irqfd = NULL;
997 }
998 }
999
1000 for (n = 0; n < nvqs; n++) {
1001 if (!virtio_queue_get_num(vdev, n)) {
1002 break;
1003 }
1004
1005 r = virtio_pci_set_guest_notifier(d, n, assign, with_irqfd);
1006 if (r < 0) {
1007 goto assign_error;
1008 }
1009 }
1010
1011 /* Must set vector notifier after guest notifier has been assigned */
1012 if ((with_irqfd || k->guest_notifier_mask) && assign) {
1013 if (with_irqfd) {
1014 proxy->vector_irqfd =
1015 g_malloc0(sizeof(*proxy->vector_irqfd) *
1016 msix_nr_vectors_allocated(&proxy->pci_dev));
1017 r = kvm_virtio_pci_vector_use(proxy, nvqs);
1018 if (r < 0) {
1019 goto assign_error;
1020 }
1021 }
1022 r = msix_set_vector_notifiers(&proxy->pci_dev,
1023 virtio_pci_vector_unmask,
1024 virtio_pci_vector_mask,
1025 virtio_pci_vector_poll);
1026 if (r < 0) {
1027 goto notifiers_error;
1028 }
1029 }
1030
1031 return 0;
1032
1033 notifiers_error:
1034 if (with_irqfd) {
1035 assert(assign);
1036 kvm_virtio_pci_vector_release(proxy, nvqs);
1037 }
1038
1039 assign_error:
1040 /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */
1041 assert(assign);
1042 while (--n >= 0) {
1043 virtio_pci_set_guest_notifier(d, n, !assign, with_irqfd);
1044 }
1045 return r;
1046 }
1047
1048 static int virtio_pci_set_host_notifier_mr(DeviceState *d, int n,
1049 MemoryRegion *mr, bool assign)
1050 {
1051 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
1052 int offset;
1053
1054 if (n >= VIRTIO_QUEUE_MAX || !virtio_pci_modern(proxy) ||
1055 virtio_pci_queue_mem_mult(proxy) != memory_region_size(mr)) {
1056 return -1;
1057 }
1058
1059 if (assign) {
1060 offset = virtio_pci_queue_mem_mult(proxy) * n;
1061 memory_region_add_subregion_overlap(&proxy->notify.mr, offset, mr, 1);
1062 } else {
1063 memory_region_del_subregion(&proxy->notify.mr, mr);
1064 }
1065
1066 return 0;
1067 }
1068
1069 static void virtio_pci_vmstate_change(DeviceState *d, bool running)
1070 {
1071 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
1072 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1073
1074 if (running) {
1075 /* Old QEMU versions did not set bus master enable on status write.
1076 * Detect DRIVER set and enable it.
1077 */
1078 if ((proxy->flags & VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION) &&
1079 (vdev->status & VIRTIO_CONFIG_S_DRIVER) &&
1080 !(proxy->pci_dev.config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
1081 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
1082 proxy->pci_dev.config[PCI_COMMAND] |
1083 PCI_COMMAND_MASTER, 1);
1084 }
1085 virtio_pci_start_ioeventfd(proxy);
1086 } else {
1087 virtio_pci_stop_ioeventfd(proxy);
1088 }
1089 }
1090
1091 /*
1092 * virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
1093 */
1094
1095 static int virtio_pci_query_nvectors(DeviceState *d)
1096 {
1097 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1098
1099 return proxy->nvectors;
1100 }
1101
1102 static AddressSpace *virtio_pci_get_dma_as(DeviceState *d)
1103 {
1104 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1105 PCIDevice *dev = &proxy->pci_dev;
1106
1107 return pci_get_address_space(dev);
1108 }
1109
1110 static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
1111 struct virtio_pci_cap *cap)
1112 {
1113 PCIDevice *dev = &proxy->pci_dev;
1114 int offset;
1115
1116 offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
1117 cap->cap_len, &error_abort);
1118
1119 assert(cap->cap_len >= sizeof *cap);
1120 memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
1121 cap->cap_len - PCI_CAP_FLAGS);
1122
1123 return offset;
1124 }
1125
1126 static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr,
1127 unsigned size)
1128 {
1129 VirtIOPCIProxy *proxy = opaque;
1130 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1131 uint32_t val = 0;
1132 int i;
1133
1134 switch (addr) {
1135 case VIRTIO_PCI_COMMON_DFSELECT:
1136 val = proxy->dfselect;
1137 break;
1138 case VIRTIO_PCI_COMMON_DF:
1139 if (proxy->dfselect <= 1) {
1140 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
1141
1142 val = (vdev->host_features & ~vdc->legacy_features) >>
1143 (32 * proxy->dfselect);
1144 }
1145 break;
1146 case VIRTIO_PCI_COMMON_GFSELECT:
1147 val = proxy->gfselect;
1148 break;
1149 case VIRTIO_PCI_COMMON_GF:
1150 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
1151 val = proxy->guest_features[proxy->gfselect];
1152 }
1153 break;
1154 case VIRTIO_PCI_COMMON_MSIX:
1155 val = vdev->config_vector;
1156 break;
1157 case VIRTIO_PCI_COMMON_NUMQ:
1158 for (i = 0; i < VIRTIO_QUEUE_MAX; ++i) {
1159 if (virtio_queue_get_num(vdev, i)) {
1160 val = i + 1;
1161 }
1162 }
1163 break;
1164 case VIRTIO_PCI_COMMON_STATUS:
1165 val = vdev->status;
1166 break;
1167 case VIRTIO_PCI_COMMON_CFGGENERATION:
1168 val = vdev->generation;
1169 break;
1170 case VIRTIO_PCI_COMMON_Q_SELECT:
1171 val = vdev->queue_sel;
1172 break;
1173 case VIRTIO_PCI_COMMON_Q_SIZE:
1174 val = virtio_queue_get_num(vdev, vdev->queue_sel);
1175 break;
1176 case VIRTIO_PCI_COMMON_Q_MSIX:
1177 val = virtio_queue_vector(vdev, vdev->queue_sel);
1178 break;
1179 case VIRTIO_PCI_COMMON_Q_ENABLE:
1180 val = proxy->vqs[vdev->queue_sel].enabled;
1181 break;
1182 case VIRTIO_PCI_COMMON_Q_NOFF:
1183 /* Simply map queues in order */
1184 val = vdev->queue_sel;
1185 break;
1186 case VIRTIO_PCI_COMMON_Q_DESCLO:
1187 val = proxy->vqs[vdev->queue_sel].desc[0];
1188 break;
1189 case VIRTIO_PCI_COMMON_Q_DESCHI:
1190 val = proxy->vqs[vdev->queue_sel].desc[1];
1191 break;
1192 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1193 val = proxy->vqs[vdev->queue_sel].avail[0];
1194 break;
1195 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1196 val = proxy->vqs[vdev->queue_sel].avail[1];
1197 break;
1198 case VIRTIO_PCI_COMMON_Q_USEDLO:
1199 val = proxy->vqs[vdev->queue_sel].used[0];
1200 break;
1201 case VIRTIO_PCI_COMMON_Q_USEDHI:
1202 val = proxy->vqs[vdev->queue_sel].used[1];
1203 break;
1204 default:
1205 val = 0;
1206 }
1207
1208 return val;
1209 }
1210
1211 static void virtio_pci_common_write(void *opaque, hwaddr addr,
1212 uint64_t val, unsigned size)
1213 {
1214 VirtIOPCIProxy *proxy = opaque;
1215 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1216
1217 switch (addr) {
1218 case VIRTIO_PCI_COMMON_DFSELECT:
1219 proxy->dfselect = val;
1220 break;
1221 case VIRTIO_PCI_COMMON_GFSELECT:
1222 proxy->gfselect = val;
1223 break;
1224 case VIRTIO_PCI_COMMON_GF:
1225 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
1226 proxy->guest_features[proxy->gfselect] = val;
1227 virtio_set_features(vdev,
1228 (((uint64_t)proxy->guest_features[1]) << 32) |
1229 proxy->guest_features[0]);
1230 }
1231 break;
1232 case VIRTIO_PCI_COMMON_MSIX:
1233 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
1234 /* Make it possible for guest to discover an error took place. */
1235 if (msix_vector_use(&proxy->pci_dev, val) < 0) {
1236 val = VIRTIO_NO_VECTOR;
1237 }
1238 vdev->config_vector = val;
1239 break;
1240 case VIRTIO_PCI_COMMON_STATUS:
1241 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
1242 virtio_pci_stop_ioeventfd(proxy);
1243 }
1244
1245 virtio_set_status(vdev, val & 0xFF);
1246
1247 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
1248 virtio_pci_start_ioeventfd(proxy);
1249 }
1250
1251 if (vdev->status == 0) {
1252 virtio_pci_reset(DEVICE(proxy));
1253 }
1254
1255 break;
1256 case VIRTIO_PCI_COMMON_Q_SELECT:
1257 if (val < VIRTIO_QUEUE_MAX) {
1258 vdev->queue_sel = val;
1259 }
1260 break;
1261 case VIRTIO_PCI_COMMON_Q_SIZE:
1262 proxy->vqs[vdev->queue_sel].num = val;
1263 virtio_queue_set_num(vdev, vdev->queue_sel,
1264 proxy->vqs[vdev->queue_sel].num);
1265 break;
1266 case VIRTIO_PCI_COMMON_Q_MSIX:
1267 msix_vector_unuse(&proxy->pci_dev,
1268 virtio_queue_vector(vdev, vdev->queue_sel));
1269 /* Make it possible for guest to discover an error took place. */
1270 if (msix_vector_use(&proxy->pci_dev, val) < 0) {
1271 val = VIRTIO_NO_VECTOR;
1272 }
1273 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
1274 break;
1275 case VIRTIO_PCI_COMMON_Q_ENABLE:
1276 if (val == 1) {
1277 virtio_queue_set_num(vdev, vdev->queue_sel,
1278 proxy->vqs[vdev->queue_sel].num);
1279 virtio_queue_set_rings(vdev, vdev->queue_sel,
1280 ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 |
1281 proxy->vqs[vdev->queue_sel].desc[0],
1282 ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 |
1283 proxy->vqs[vdev->queue_sel].avail[0],
1284 ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 |
1285 proxy->vqs[vdev->queue_sel].used[0]);
1286 proxy->vqs[vdev->queue_sel].enabled = 1;
1287 } else {
1288 virtio_error(vdev, "wrong value for queue_enable %"PRIx64, val);
1289 }
1290 break;
1291 case VIRTIO_PCI_COMMON_Q_DESCLO:
1292 proxy->vqs[vdev->queue_sel].desc[0] = val;
1293 break;
1294 case VIRTIO_PCI_COMMON_Q_DESCHI:
1295 proxy->vqs[vdev->queue_sel].desc[1] = val;
1296 break;
1297 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1298 proxy->vqs[vdev->queue_sel].avail[0] = val;
1299 break;
1300 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1301 proxy->vqs[vdev->queue_sel].avail[1] = val;
1302 break;
1303 case VIRTIO_PCI_COMMON_Q_USEDLO:
1304 proxy->vqs[vdev->queue_sel].used[0] = val;
1305 break;
1306 case VIRTIO_PCI_COMMON_Q_USEDHI:
1307 proxy->vqs[vdev->queue_sel].used[1] = val;
1308 break;
1309 default:
1310 break;
1311 }
1312 }
1313
1314
1315 static uint64_t virtio_pci_notify_read(void *opaque, hwaddr addr,
1316 unsigned size)
1317 {
1318 return 0;
1319 }
1320
1321 static void virtio_pci_notify_write(void *opaque, hwaddr addr,
1322 uint64_t val, unsigned size)
1323 {
1324 VirtIODevice *vdev = opaque;
1325 VirtIOPCIProxy *proxy = VIRTIO_PCI(DEVICE(vdev)->parent_bus->parent);
1326 unsigned queue = addr / virtio_pci_queue_mem_mult(proxy);
1327
1328 if (queue < VIRTIO_QUEUE_MAX) {
1329 virtio_queue_notify(vdev, queue);
1330 }
1331 }
1332
1333 static void virtio_pci_notify_write_pio(void *opaque, hwaddr addr,
1334 uint64_t val, unsigned size)
1335 {
1336 VirtIODevice *vdev = opaque;
1337 unsigned queue = val;
1338
1339 if (queue < VIRTIO_QUEUE_MAX) {
1340 virtio_queue_notify(vdev, queue);
1341 }
1342 }
1343
1344 static uint64_t virtio_pci_isr_read(void *opaque, hwaddr addr,
1345 unsigned size)
1346 {
1347 VirtIOPCIProxy *proxy = opaque;
1348 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1349 uint64_t val = atomic_xchg(&vdev->isr, 0);
1350 pci_irq_deassert(&proxy->pci_dev);
1351
1352 return val;
1353 }
1354
1355 static void virtio_pci_isr_write(void *opaque, hwaddr addr,
1356 uint64_t val, unsigned size)
1357 {
1358 }
1359
1360 static uint64_t virtio_pci_device_read(void *opaque, hwaddr addr,
1361 unsigned size)
1362 {
1363 VirtIODevice *vdev = opaque;
1364 uint64_t val = 0;
1365
1366 switch (size) {
1367 case 1:
1368 val = virtio_config_modern_readb(vdev, addr);
1369 break;
1370 case 2:
1371 val = virtio_config_modern_readw(vdev, addr);
1372 break;
1373 case 4:
1374 val = virtio_config_modern_readl(vdev, addr);
1375 break;
1376 }
1377 return val;
1378 }
1379
1380 static void virtio_pci_device_write(void *opaque, hwaddr addr,
1381 uint64_t val, unsigned size)
1382 {
1383 VirtIODevice *vdev = opaque;
1384 switch (size) {
1385 case 1:
1386 virtio_config_modern_writeb(vdev, addr, val);
1387 break;
1388 case 2:
1389 virtio_config_modern_writew(vdev, addr, val);
1390 break;
1391 case 4:
1392 virtio_config_modern_writel(vdev, addr, val);
1393 break;
1394 }
1395 }
1396
1397 static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy)
1398 {
1399 static const MemoryRegionOps common_ops = {
1400 .read = virtio_pci_common_read,
1401 .write = virtio_pci_common_write,
1402 .impl = {
1403 .min_access_size = 1,
1404 .max_access_size = 4,
1405 },
1406 .endianness = DEVICE_LITTLE_ENDIAN,
1407 };
1408 static const MemoryRegionOps isr_ops = {
1409 .read = virtio_pci_isr_read,
1410 .write = virtio_pci_isr_write,
1411 .impl = {
1412 .min_access_size = 1,
1413 .max_access_size = 4,
1414 },
1415 .endianness = DEVICE_LITTLE_ENDIAN,
1416 };
1417 static const MemoryRegionOps device_ops = {
1418 .read = virtio_pci_device_read,
1419 .write = virtio_pci_device_write,
1420 .impl = {
1421 .min_access_size = 1,
1422 .max_access_size = 4,
1423 },
1424 .endianness = DEVICE_LITTLE_ENDIAN,
1425 };
1426 static const MemoryRegionOps notify_ops = {
1427 .read = virtio_pci_notify_read,
1428 .write = virtio_pci_notify_write,
1429 .impl = {
1430 .min_access_size = 1,
1431 .max_access_size = 4,
1432 },
1433 .endianness = DEVICE_LITTLE_ENDIAN,
1434 };
1435 static const MemoryRegionOps notify_pio_ops = {
1436 .read = virtio_pci_notify_read,
1437 .write = virtio_pci_notify_write_pio,
1438 .impl = {
1439 .min_access_size = 1,
1440 .max_access_size = 4,
1441 },
1442 .endianness = DEVICE_LITTLE_ENDIAN,
1443 };
1444
1445
1446 memory_region_init_io(&proxy->common.mr, OBJECT(proxy),
1447 &common_ops,
1448 proxy,
1449 "virtio-pci-common",
1450 proxy->common.size);
1451
1452 memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),
1453 &isr_ops,
1454 proxy,
1455 "virtio-pci-isr",
1456 proxy->isr.size);
1457
1458 memory_region_init_io(&proxy->device.mr, OBJECT(proxy),
1459 &device_ops,
1460 virtio_bus_get_device(&proxy->bus),
1461 "virtio-pci-device",
1462 proxy->device.size);
1463
1464 memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),
1465 &notify_ops,
1466 virtio_bus_get_device(&proxy->bus),
1467 "virtio-pci-notify",
1468 proxy->notify.size);
1469
1470 memory_region_init_io(&proxy->notify_pio.mr, OBJECT(proxy),
1471 &notify_pio_ops,
1472 virtio_bus_get_device(&proxy->bus),
1473 "virtio-pci-notify-pio",
1474 proxy->notify_pio.size);
1475 }
1476
1477 static void virtio_pci_modern_region_map(VirtIOPCIProxy *proxy,
1478 VirtIOPCIRegion *region,
1479 struct virtio_pci_cap *cap,
1480 MemoryRegion *mr,
1481 uint8_t bar)
1482 {
1483 memory_region_add_subregion(mr, region->offset, &region->mr);
1484
1485 cap->cfg_type = region->type;
1486 cap->bar = bar;
1487 cap->offset = cpu_to_le32(region->offset);
1488 cap->length = cpu_to_le32(region->size);
1489 virtio_pci_add_mem_cap(proxy, cap);
1490
1491 }
1492
1493 static void virtio_pci_modern_mem_region_map(VirtIOPCIProxy *proxy,
1494 VirtIOPCIRegion *region,
1495 struct virtio_pci_cap *cap)
1496 {
1497 virtio_pci_modern_region_map(proxy, region, cap,
1498 &proxy->modern_bar, proxy->modern_mem_bar_idx);
1499 }
1500
1501 static void virtio_pci_modern_io_region_map(VirtIOPCIProxy *proxy,
1502 VirtIOPCIRegion *region,
1503 struct virtio_pci_cap *cap)
1504 {
1505 virtio_pci_modern_region_map(proxy, region, cap,
1506 &proxy->io_bar, proxy->modern_io_bar_idx);
1507 }
1508
1509 static void virtio_pci_modern_mem_region_unmap(VirtIOPCIProxy *proxy,
1510 VirtIOPCIRegion *region)
1511 {
1512 memory_region_del_subregion(&proxy->modern_bar,
1513 &region->mr);
1514 }
1515
1516 static void virtio_pci_modern_io_region_unmap(VirtIOPCIProxy *proxy,
1517 VirtIOPCIRegion *region)
1518 {
1519 memory_region_del_subregion(&proxy->io_bar,
1520 &region->mr);
1521 }
1522
1523 static void virtio_pci_pre_plugged(DeviceState *d, Error **errp)
1524 {
1525 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1526 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1527
1528 if (virtio_pci_modern(proxy)) {
1529 virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1);
1530 }
1531
1532 virtio_add_feature(&vdev->host_features, VIRTIO_F_BAD_FEATURE);
1533 }
1534
1535 /* This is called by virtio-bus just after the device is plugged. */
1536 static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
1537 {
1538 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1539 VirtioBusState *bus = &proxy->bus;
1540 bool legacy = virtio_pci_legacy(proxy);
1541 bool modern;
1542 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
1543 uint8_t *config;
1544 uint32_t size;
1545 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1546
1547 /*
1548 * Virtio capabilities present without
1549 * VIRTIO_F_VERSION_1 confuses guests
1550 */
1551 if (!proxy->ignore_backend_features &&
1552 !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) {
1553 virtio_pci_disable_modern(proxy);
1554
1555 if (!legacy) {
1556 error_setg(errp, "Device doesn't support modern mode, and legacy"
1557 " mode is disabled");
1558 error_append_hint(errp, "Set disable-legacy to off\n");
1559
1560 return;
1561 }
1562 }
1563
1564 modern = virtio_pci_modern(proxy);
1565
1566 config = proxy->pci_dev.config;
1567 if (proxy->class_code) {
1568 pci_config_set_class(config, proxy->class_code);
1569 }
1570
1571 if (legacy) {
1572 if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
1573 error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by"
1574 " neither legacy nor transitional device");
1575 return ;
1576 }
1577 /*
1578 * Legacy and transitional devices use specific subsystem IDs.
1579 * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID)
1580 * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default.
1581 */
1582 pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus));
1583 } else {
1584 /* pure virtio-1.0 */
1585 pci_set_word(config + PCI_VENDOR_ID,
1586 PCI_VENDOR_ID_REDHAT_QUMRANET);
1587 pci_set_word(config + PCI_DEVICE_ID,
1588 0x1040 + virtio_bus_get_vdev_id(bus));
1589 pci_config_set_revision(config, 1);
1590 }
1591 config[PCI_INTERRUPT_PIN] = 1;
1592
1593
1594 if (modern) {
1595 struct virtio_pci_cap cap = {
1596 .cap_len = sizeof cap,
1597 };
1598 struct virtio_pci_notify_cap notify = {
1599 .cap.cap_len = sizeof notify,
1600 .notify_off_multiplier =
1601 cpu_to_le32(virtio_pci_queue_mem_mult(proxy)),
1602 };
1603 struct virtio_pci_cfg_cap cfg = {
1604 .cap.cap_len = sizeof cfg,
1605 .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
1606 };
1607 struct virtio_pci_notify_cap notify_pio = {
1608 .cap.cap_len = sizeof notify,
1609 .notify_off_multiplier = cpu_to_le32(0x0),
1610 };
1611
1612 struct virtio_pci_cfg_cap *cfg_mask;
1613
1614 virtio_pci_modern_regions_init(proxy);
1615
1616 virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap);
1617 virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap);
1618 virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap);
1619 virtio_pci_modern_mem_region_map(proxy, &proxy->notify, &notify.cap);
1620
1621 if (modern_pio) {
1622 memory_region_init(&proxy->io_bar, OBJECT(proxy),
1623 "virtio-pci-io", 0x4);
1624
1625 pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx,
1626 PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar);
1627
1628 virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio,
1629 &notify_pio.cap);
1630 }
1631
1632 pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
1633 PCI_BASE_ADDRESS_SPACE_MEMORY |
1634 PCI_BASE_ADDRESS_MEM_PREFETCH |
1635 PCI_BASE_ADDRESS_MEM_TYPE_64,
1636 &proxy->modern_bar);
1637
1638 proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
1639 cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
1640 pci_set_byte(&cfg_mask->cap.bar, ~0x0);
1641 pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
1642 pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
1643 pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
1644 }
1645
1646 if (proxy->nvectors) {
1647 int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
1648 proxy->msix_bar_idx, NULL);
1649 if (err) {
1650 /* Notice when a system that supports MSIx can't initialize it */
1651 if (err != -ENOTSUP) {
1652 warn_report("unable to init msix vectors to %" PRIu32,
1653 proxy->nvectors);
1654 }
1655 proxy->nvectors = 0;
1656 }
1657 }
1658
1659 proxy->pci_dev.config_write = virtio_write_config;
1660 proxy->pci_dev.config_read = virtio_read_config;
1661
1662 if (legacy) {
1663 size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
1664 + virtio_bus_get_vdev_config_len(bus);
1665 size = pow2ceil(size);
1666
1667 memory_region_init_io(&proxy->bar, OBJECT(proxy),
1668 &virtio_pci_config_ops,
1669 proxy, "virtio-pci", size);
1670
1671 pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
1672 PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
1673 }
1674 }
1675
1676 static void virtio_pci_device_unplugged(DeviceState *d)
1677 {
1678 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1679 bool modern = virtio_pci_modern(proxy);
1680 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
1681
1682 virtio_pci_stop_ioeventfd(proxy);
1683
1684 if (modern) {
1685 virtio_pci_modern_mem_region_unmap(proxy, &proxy->common);
1686 virtio_pci_modern_mem_region_unmap(proxy, &proxy->isr);
1687 virtio_pci_modern_mem_region_unmap(proxy, &proxy->device);
1688 virtio_pci_modern_mem_region_unmap(proxy, &proxy->notify);
1689 if (modern_pio) {
1690 virtio_pci_modern_io_region_unmap(proxy, &proxy->notify_pio);
1691 }
1692 }
1693 }
1694
1695 static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
1696 {
1697 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
1698 VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev);
1699 bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
1700 !pci_bus_is_root(pci_get_bus(pci_dev));
1701
1702 if (kvm_enabled() && !kvm_has_many_ioeventfds()) {
1703 proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;
1704 }
1705
1706 /*
1707 * virtio pci bar layout used by default.
1708 * subclasses can re-arrange things if needed.
1709 *
1710 * region 0 -- virtio legacy io bar
1711 * region 1 -- msi-x bar
1712 * region 2 -- virtio modern io bar (off by default)
1713 * region 4+5 -- virtio modern memory (64bit) bar
1714 *
1715 */
1716 proxy->legacy_io_bar_idx = 0;
1717 proxy->msix_bar_idx = 1;
1718 proxy->modern_io_bar_idx = 2;
1719 proxy->modern_mem_bar_idx = 4;
1720
1721 proxy->common.offset = 0x0;
1722 proxy->common.size = 0x1000;
1723 proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;
1724
1725 proxy->isr.offset = 0x1000;
1726 proxy->isr.size = 0x1000;
1727 proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;
1728
1729 proxy->device.offset = 0x2000;
1730 proxy->device.size = 0x1000;
1731 proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;
1732
1733 proxy->notify.offset = 0x3000;
1734 proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;
1735 proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
1736
1737 proxy->notify_pio.offset = 0x0;
1738 proxy->notify_pio.size = 0x4;
1739 proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
1740
1741 /* subclasses can enforce modern, so do this unconditionally */
1742 memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",
1743 /* PCI BAR regions must be powers of 2 */
1744 pow2ceil(proxy->notify.offset + proxy->notify.size));
1745
1746 if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {
1747 proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
1748 }
1749
1750 if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {
1751 error_setg(errp, "device cannot work as neither modern nor legacy mode"
1752 " is enabled");
1753 error_append_hint(errp, "Set either disable-modern or disable-legacy"
1754 " to off\n");
1755 return;
1756 }
1757
1758 if (pcie_port && pci_is_express(pci_dev)) {
1759 int pos;
1760
1761 pos = pcie_endpoint_cap_init(pci_dev, 0);
1762 assert(pos > 0);
1763
1764 pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
1765 PCI_PM_SIZEOF, errp);
1766 if (pos < 0) {
1767 return;
1768 }
1769
1770 pci_dev->exp.pm_cap = pos;
1771
1772 /*
1773 * Indicates that this function complies with revision 1.2 of the
1774 * PCI Power Management Interface Specification.
1775 */
1776 pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
1777
1778 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
1779 /* Init error enabling flags */
1780 pcie_cap_deverr_init(pci_dev);
1781 }
1782
1783 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
1784 /* Init Link Control Register */
1785 pcie_cap_lnkctl_init(pci_dev);
1786 }
1787
1788 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
1789 /* Init Power Management Control Register */
1790 pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
1791 PCI_PM_CTRL_STATE_MASK);
1792 }
1793
1794 if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
1795 pcie_ats_init(pci_dev, 256);
1796 }
1797
1798 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
1799 /* Set Function Level Reset capability bit */
1800 pcie_cap_flr_init(pci_dev);
1801 }
1802 } else {
1803 /*
1804 * make future invocations of pci_is_express() return false
1805 * and pci_config_size() return PCI_CONFIG_SPACE_SIZE.
1806 */
1807 pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;
1808 }
1809
1810 virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
1811 if (k->realize) {
1812 k->realize(proxy, errp);
1813 }
1814 }
1815
1816 static void virtio_pci_exit(PCIDevice *pci_dev)
1817 {
1818 msix_uninit_exclusive_bar(pci_dev);
1819 }
1820
1821 static void virtio_pci_reset(DeviceState *qdev)
1822 {
1823 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
1824 VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
1825 PCIDevice *dev = PCI_DEVICE(qdev);
1826 int i;
1827
1828 virtio_pci_stop_ioeventfd(proxy);
1829 virtio_bus_reset(bus);
1830 msix_unuse_all_vectors(&proxy->pci_dev);
1831
1832 for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
1833 proxy->vqs[i].enabled = 0;
1834 proxy->vqs[i].num = 0;
1835 proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0;
1836 proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
1837 proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
1838 }
1839
1840 if (pci_is_express(dev)) {
1841 pcie_cap_deverr_reset(dev);
1842 pcie_cap_lnkctl_reset(dev);
1843
1844 pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
1845 }
1846 }
1847
1848 static Property virtio_pci_properties[] = {
1849 DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
1850 VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
1851 DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
1852 VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
1853 DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
1854 VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
1855 DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
1856 VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
1857 DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
1858 VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
1859 DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
1860 ignore_backend_features, false),
1861 DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
1862 VIRTIO_PCI_FLAG_ATS_BIT, false),
1863 DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
1864 VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
1865 DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
1866 VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
1867 DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
1868 VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
1869 DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
1870 VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
1871 DEFINE_PROP_END_OF_LIST(),
1872 };
1873
1874 static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
1875 {
1876 VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev);
1877 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
1878 PCIDevice *pci_dev = &proxy->pci_dev;
1879
1880 if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&
1881 virtio_pci_modern(proxy)) {
1882 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1883 }
1884
1885 vpciklass->parent_dc_realize(qdev, errp);
1886 }
1887
1888 static void virtio_pci_class_init(ObjectClass *klass, void *data)
1889 {
1890 DeviceClass *dc = DEVICE_CLASS(klass);
1891 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1892 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
1893
1894 device_class_set_props(dc, virtio_pci_properties);
1895 k->realize = virtio_pci_realize;
1896 k->exit = virtio_pci_exit;
1897 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1898 k->revision = VIRTIO_PCI_ABI_VERSION;
1899 k->class_id = PCI_CLASS_OTHERS;
1900 device_class_set_parent_realize(dc, virtio_pci_dc_realize,
1901 &vpciklass->parent_dc_realize);
1902 dc->reset = virtio_pci_reset;
1903 }
1904
1905 static const TypeInfo virtio_pci_info = {
1906 .name = TYPE_VIRTIO_PCI,
1907 .parent = TYPE_PCI_DEVICE,
1908 .instance_size = sizeof(VirtIOPCIProxy),
1909 .class_init = virtio_pci_class_init,
1910 .class_size = sizeof(VirtioPCIClass),
1911 .abstract = true,
1912 };
1913
1914 static Property virtio_pci_generic_properties[] = {
1915 DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy,
1916 ON_OFF_AUTO_AUTO),
1917 DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false),
1918 DEFINE_PROP_END_OF_LIST(),
1919 };
1920
1921 static void virtio_pci_base_class_init(ObjectClass *klass, void *data)
1922 {
1923 const VirtioPCIDeviceTypeInfo *t = data;
1924 if (t->class_init) {
1925 t->class_init(klass, NULL);
1926 }
1927 }
1928
1929 static void virtio_pci_generic_class_init(ObjectClass *klass, void *data)
1930 {
1931 DeviceClass *dc = DEVICE_CLASS(klass);
1932
1933 device_class_set_props(dc, virtio_pci_generic_properties);
1934 }
1935
1936 static void virtio_pci_transitional_instance_init(Object *obj)
1937 {
1938 VirtIOPCIProxy *proxy = VIRTIO_PCI(obj);
1939
1940 proxy->disable_legacy = ON_OFF_AUTO_OFF;
1941 proxy->disable_modern = false;
1942 }
1943
1944 static void virtio_pci_non_transitional_instance_init(Object *obj)
1945 {
1946 VirtIOPCIProxy *proxy = VIRTIO_PCI(obj);
1947
1948 proxy->disable_legacy = ON_OFF_AUTO_ON;
1949 proxy->disable_modern = false;
1950 }
1951
1952 void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t)
1953 {
1954 char *base_name = NULL;
1955 TypeInfo base_type_info = {
1956 .name = t->base_name,
1957 .parent = t->parent ? t->parent : TYPE_VIRTIO_PCI,
1958 .instance_size = t->instance_size,
1959 .instance_init = t->instance_init,
1960 .class_size = t->class_size,
1961 .abstract = true,
1962 .interfaces = t->interfaces,
1963 };
1964 TypeInfo generic_type_info = {
1965 .name = t->generic_name,
1966 .parent = base_type_info.name,
1967 .class_init = virtio_pci_generic_class_init,
1968 .interfaces = (InterfaceInfo[]) {
1969 { INTERFACE_PCIE_DEVICE },
1970 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1971 { }
1972 },
1973 };
1974
1975 if (!base_type_info.name) {
1976 /* No base type -> register a single generic device type */
1977 /* use intermediate %s-base-type to add generic device props */
1978 base_name = g_strdup_printf("%s-base-type", t->generic_name);
1979 base_type_info.name = base_name;
1980 base_type_info.class_init = virtio_pci_generic_class_init;
1981
1982 generic_type_info.parent = base_name;
1983 generic_type_info.class_init = virtio_pci_base_class_init;
1984 generic_type_info.class_data = (void *)t;
1985
1986 assert(!t->non_transitional_name);
1987 assert(!t->transitional_name);
1988 } else {
1989 base_type_info.class_init = virtio_pci_base_class_init;
1990 base_type_info.class_data = (void *)t;
1991 }
1992
1993 type_register(&base_type_info);
1994 if (generic_type_info.name) {
1995 type_register(&generic_type_info);
1996 }
1997
1998 if (t->non_transitional_name) {
1999 const TypeInfo non_transitional_type_info = {
2000 .name = t->non_transitional_name,
2001 .parent = base_type_info.name,
2002 .instance_init = virtio_pci_non_transitional_instance_init,
2003 .interfaces = (InterfaceInfo[]) {
2004 { INTERFACE_PCIE_DEVICE },
2005 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2006 { }
2007 },
2008 };
2009 type_register(&non_transitional_type_info);
2010 }
2011
2012 if (t->transitional_name) {
2013 const TypeInfo transitional_type_info = {
2014 .name = t->transitional_name,
2015 .parent = base_type_info.name,
2016 .instance_init = virtio_pci_transitional_instance_init,
2017 .interfaces = (InterfaceInfo[]) {
2018 /*
2019 * Transitional virtio devices work only as Conventional PCI
2020 * devices because they require PIO ports.
2021 */
2022 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2023 { }
2024 },
2025 };
2026 type_register(&transitional_type_info);
2027 }
2028 g_free(base_name);
2029 }
2030
2031 /* virtio-pci-bus */
2032
2033 static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
2034 VirtIOPCIProxy *dev)
2035 {
2036 DeviceState *qdev = DEVICE(dev);
2037 char virtio_bus_name[] = "virtio-bus";
2038
2039 qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
2040 virtio_bus_name);
2041 }
2042
2043 static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
2044 {
2045 BusClass *bus_class = BUS_CLASS(klass);
2046 VirtioBusClass *k = VIRTIO_BUS_CLASS(klass);
2047 bus_class->max_dev = 1;
2048 k->notify = virtio_pci_notify;
2049 k->save_config = virtio_pci_save_config;
2050 k->load_config = virtio_pci_load_config;
2051 k->save_queue = virtio_pci_save_queue;
2052 k->load_queue = virtio_pci_load_queue;
2053 k->save_extra_state = virtio_pci_save_extra_state;
2054 k->load_extra_state = virtio_pci_load_extra_state;
2055 k->has_extra_state = virtio_pci_has_extra_state;
2056 k->query_guest_notifiers = virtio_pci_query_guest_notifiers;
2057 k->set_guest_notifiers = virtio_pci_set_guest_notifiers;
2058 k->set_host_notifier_mr = virtio_pci_set_host_notifier_mr;
2059 k->vmstate_change = virtio_pci_vmstate_change;
2060 k->pre_plugged = virtio_pci_pre_plugged;
2061 k->device_plugged = virtio_pci_device_plugged;
2062 k->device_unplugged = virtio_pci_device_unplugged;
2063 k->query_nvectors = virtio_pci_query_nvectors;
2064 k->ioeventfd_enabled = virtio_pci_ioeventfd_enabled;
2065 k->ioeventfd_assign = virtio_pci_ioeventfd_assign;
2066 k->get_dma_as = virtio_pci_get_dma_as;
2067 }
2068
2069 static const TypeInfo virtio_pci_bus_info = {
2070 .name = TYPE_VIRTIO_PCI_BUS,
2071 .parent = TYPE_VIRTIO_BUS,
2072 .instance_size = sizeof(VirtioPCIBusState),
2073 .class_init = virtio_pci_bus_class_init,
2074 };
2075
2076 static void virtio_pci_register_types(void)
2077 {
2078 /* Base types: */
2079 type_register_static(&virtio_pci_bus_info);
2080 type_register_static(&virtio_pci_info);
2081 }
2082
2083 type_init(virtio_pci_register_types)
2084
AR7 emulation for QEMU