hw/char/ibex_uart.c

   1 /*
   2  * QEMU lowRISC Ibex UART device
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * For details check the documentation here:
   7  *    https://docs.opentitan.org/hw/ip/uart/doc/
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/char/ibex_uart.h"
  30 #include "hw/irq.h"
  31 #include "hw/qdev-properties.h"
  32 #include "migration/vmstate.h"
  33 #include "qemu/log.h"
  34 #include "qemu/module.h"
  35
  36 static void ibex_uart_update_irqs(IbexUartState *s)
  37 {
  38     if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK) {
  39         qemu_set_irq(s->tx_watermark, 1);
  40     } else {
  41         qemu_set_irq(s->tx_watermark, 0);
  42     }
  43
  44     if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK) {
  45         qemu_set_irq(s->rx_watermark, 1);
  46     } else {
  47         qemu_set_irq(s->rx_watermark, 0);
  48     }
  49
  50     if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) {
  51         qemu_set_irq(s->tx_empty, 1);
  52     } else {
  53         qemu_set_irq(s->tx_empty, 0);
  54     }
  55
  56     if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW) {
  57         qemu_set_irq(s->rx_overflow, 1);
  58     } else {
  59         qemu_set_irq(s->rx_overflow, 0);
  60     }
  61 }
  62
  63 static int ibex_uart_can_receive(void *opaque)
  64 {
  65     IbexUartState *s = opaque;
  66
  67     if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
  68         return 1;
  69     }
  70
  71     return 0;
  72 }
  73
  74 static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
  75 {
  76     IbexUartState *s = opaque;
  77     uint8_t rx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL)
  78                             >> FIFO_CTRL_RXILVL_SHIFT;
  79
  80     s->uart_rdata = *buf;
  81
  82     s->uart_status &= ~UART_STATUS_RXIDLE;
  83     s->uart_status &= ~UART_STATUS_RXEMPTY;
  84
  85     if (size > rx_fifo_level) {
  86         s->uart_intr_state |= INTR_STATE_RX_WATERMARK;
  87     }
  88
  89     ibex_uart_update_irqs(s);
  90 }
  91
  92 static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
  93                                void *opaque)
  94 {
  95     IbexUartState *s = opaque;
  96     uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
  97                             >> FIFO_CTRL_TXILVL_SHIFT;
  98     int ret;
  99
 100     /* instant drain the fifo when there's no back-end */
 101     if (!qemu_chr_fe_backend_connected(&s->chr)) {
 102         s->tx_level = 0;
 103         return FALSE;
 104     }
 105
 106     if (!s->tx_level) {
 107         s->uart_status &= ~UART_STATUS_TXFULL;
 108         s->uart_status |= UART_STATUS_TXEMPTY;
 109         s->uart_intr_state |= INTR_STATE_TX_EMPTY;
 110         s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
 111         ibex_uart_update_irqs(s);
 112         return FALSE;
 113     }
 114
 115     ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
 116
 117     if (ret >= 0) {
 118         s->tx_level -= ret;
 119         memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
 120     }
 121
 122     if (s->tx_level) {
 123         guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 124                                         ibex_uart_xmit, s);
 125         if (!r) {
 126             s->tx_level = 0;
 127             return FALSE;
 128         }
 129     }
 130
 131     /* Clear the TX Full bit */
 132     if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
 133         s->uart_status &= ~UART_STATUS_TXFULL;
 134     }
 135
 136     /* Disable the TX_WATERMARK IRQ */
 137     if (s->tx_level < tx_fifo_level) {
 138         s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
 139     }
 140
 141     /* Set TX empty */
 142     if (s->tx_level == 0) {
 143         s->uart_status |= UART_STATUS_TXEMPTY;
 144         s->uart_intr_state |= INTR_STATE_TX_EMPTY;
 145     }
 146
 147     ibex_uart_update_irqs(s);
 148     return FALSE;
 149 }
 150
 151 static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
 152                                int size)
 153 {
 154     uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 155     uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
 156                             >> FIFO_CTRL_TXILVL_SHIFT;
 157
 158     if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
 159         size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
 160         qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow");
 161     }
 162
 163     memcpy(s->tx_fifo + s->tx_level, buf, size);
 164     s->tx_level += size;
 165
 166     if (s->tx_level > 0) {
 167         s->uart_status &= ~UART_STATUS_TXEMPTY;
 168     }
 169
 170     if (s->tx_level >= tx_fifo_level) {
 171         s->uart_intr_state |= INTR_STATE_TX_WATERMARK;
 172         ibex_uart_update_irqs(s);
 173     }
 174
 175     if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
 176         s->uart_status |= UART_STATUS_TXFULL;
 177     }
 178
 179     timer_mod(s->fifo_trigger_handle, current_time +
 180               (s->char_tx_time * 4));
 181 }
 182
 183 static void ibex_uart_reset(DeviceState *dev)
 184 {
 185     IbexUartState *s = IBEX_UART(dev);
 186
 187     s->uart_intr_state = 0x00000000;
 188     s->uart_intr_state = 0x00000000;
 189     s->uart_intr_enable = 0x00000000;
 190     s->uart_ctrl = 0x00000000;
 191     s->uart_status = 0x0000003c;
 192     s->uart_rdata = 0x00000000;
 193     s->uart_fifo_ctrl = 0x00000000;
 194     s->uart_fifo_status = 0x00000000;
 195     s->uart_ovrd = 0x00000000;
 196     s->uart_val = 0x00000000;
 197     s->uart_timeout_ctrl = 0x00000000;
 198
 199     s->tx_level = 0;
 200
 201     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 202
 203     ibex_uart_update_irqs(s);
 204 }
 205
 206 static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 207                                        unsigned int size)
 208 {
 209     IbexUartState *s = opaque;
 210     uint64_t retvalue = 0;
 211
 212     switch (addr) {
 213     case IBEX_UART_INTR_STATE:
 214         retvalue = s->uart_intr_state;
 215         break;
 216     case IBEX_UART_INTR_ENABLE:
 217         retvalue = s->uart_intr_enable;
 218         break;
 219     case IBEX_UART_INTR_TEST:
 220         qemu_log_mask(LOG_GUEST_ERROR,
 221                       "%s: wdata is write only\n", __func__);
 222         break;
 223
 224     case IBEX_UART_CTRL:
 225         retvalue = s->uart_ctrl;
 226         break;
 227     case IBEX_UART_STATUS:
 228         retvalue = s->uart_status;
 229         break;
 230
 231     case IBEX_UART_RDATA:
 232         retvalue = s->uart_rdata;
 233         if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
 234             qemu_chr_fe_accept_input(&s->chr);
 235
 236             s->uart_status |= UART_STATUS_RXIDLE;
 237             s->uart_status |= UART_STATUS_RXEMPTY;
 238         }
 239         break;
 240     case IBEX_UART_WDATA:
 241         qemu_log_mask(LOG_GUEST_ERROR,
 242                       "%s: wdata is write only\n", __func__);
 243         break;
 244
 245     case IBEX_UART_FIFO_CTRL:
 246         retvalue = s->uart_fifo_ctrl;
 247         break;
 248     case IBEX_UART_FIFO_STATUS:
 249         retvalue = s->uart_fifo_status;
 250
 251         retvalue |= s->tx_level & 0x1F;
 252
 253         qemu_log_mask(LOG_UNIMP,
 254                       "%s: RX fifos are not supported\n", __func__);
 255         break;
 256
 257     case IBEX_UART_OVRD:
 258         retvalue = s->uart_ovrd;
 259         qemu_log_mask(LOG_UNIMP,
 260                       "%s: ovrd is not supported\n", __func__);
 261         break;
 262     case IBEX_UART_VAL:
 263         retvalue = s->uart_val;
 264         qemu_log_mask(LOG_UNIMP,
 265                       "%s: val is not supported\n", __func__);
 266         break;
 267     case IBEX_UART_TIMEOUT_CTRL:
 268         retvalue = s->uart_timeout_ctrl;
 269         qemu_log_mask(LOG_UNIMP,
 270                       "%s: timeout_ctrl is not supported\n", __func__);
 271         break;
 272     default:
 273         qemu_log_mask(LOG_GUEST_ERROR,
 274                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 275         return 0;
 276     }
 277
 278     return retvalue;
 279 }
 280
 281 static void ibex_uart_write(void *opaque, hwaddr addr,
 282                                   uint64_t val64, unsigned int size)
 283 {
 284     IbexUartState *s = opaque;
 285     uint32_t value = val64;
 286
 287     switch (addr) {
 288     case IBEX_UART_INTR_STATE:
 289         /* Write 1 clear */
 290         s->uart_intr_state &= ~value;
 291         ibex_uart_update_irqs(s);
 292         break;
 293     case IBEX_UART_INTR_ENABLE:
 294         s->uart_intr_enable = value;
 295         ibex_uart_update_irqs(s);
 296         break;
 297     case IBEX_UART_INTR_TEST:
 298         s->uart_intr_state |= value;
 299         ibex_uart_update_irqs(s);
 300         break;
 301
 302     case IBEX_UART_CTRL:
 303         s->uart_ctrl = value;
 304
 305         if (value & UART_CTRL_NF) {
 306             qemu_log_mask(LOG_UNIMP,
 307                           "%s: UART_CTRL_NF is not supported\n", __func__);
 308         }
 309         if (value & UART_CTRL_SLPBK) {
 310             qemu_log_mask(LOG_UNIMP,
 311                           "%s: UART_CTRL_SLPBK is not supported\n", __func__);
 312         }
 313         if (value & UART_CTRL_LLPBK) {
 314             qemu_log_mask(LOG_UNIMP,
 315                           "%s: UART_CTRL_LLPBK is not supported\n", __func__);
 316         }
 317         if (value & UART_CTRL_PARITY_EN) {
 318             qemu_log_mask(LOG_UNIMP,
 319                           "%s: UART_CTRL_PARITY_EN is not supported\n",
 320                           __func__);
 321         }
 322         if (value & UART_CTRL_PARITY_ODD) {
 323             qemu_log_mask(LOG_UNIMP,
 324                           "%s: UART_CTRL_PARITY_ODD is not supported\n",
 325                           __func__);
 326         }
 327         if (value & UART_CTRL_RXBLVL) {
 328             qemu_log_mask(LOG_UNIMP,
 329                           "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
 330         }
 331         if (value & UART_CTRL_NCO) {
 332             uint64_t baud = ((value & UART_CTRL_NCO) >> 16);
 333             baud *= 1000;
 334             baud /= 2 ^ 20;
 335
 336             s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
 337         }
 338         break;
 339     case IBEX_UART_STATUS:
 340         qemu_log_mask(LOG_GUEST_ERROR,
 341                       "%s: status is read only\n", __func__);
 342         break;
 343
 344     case IBEX_UART_RDATA:
 345         qemu_log_mask(LOG_GUEST_ERROR,
 346                       "%s: rdata is read only\n", __func__);
 347         break;
 348     case IBEX_UART_WDATA:
 349         uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 350         break;
 351
 352     case IBEX_UART_FIFO_CTRL:
 353         s->uart_fifo_ctrl = value;
 354
 355         if (value & FIFO_CTRL_RXRST) {
 356             qemu_log_mask(LOG_UNIMP,
 357                           "%s: RX fifos are not supported\n", __func__);
 358         }
 359         if (value & FIFO_CTRL_TXRST) {
 360             s->tx_level = 0;
 361         }
 362         break;
 363     case IBEX_UART_FIFO_STATUS:
 364         qemu_log_mask(LOG_GUEST_ERROR,
 365                       "%s: fifo_status is read only\n", __func__);
 366         break;
 367
 368     case IBEX_UART_OVRD:
 369         s->uart_ovrd = value;
 370         qemu_log_mask(LOG_UNIMP,
 371                       "%s: ovrd is not supported\n", __func__);
 372         break;
 373     case IBEX_UART_VAL:
 374         qemu_log_mask(LOG_GUEST_ERROR,
 375                       "%s: val is read only\n", __func__);
 376         break;
 377     case IBEX_UART_TIMEOUT_CTRL:
 378         s->uart_timeout_ctrl = value;
 379         qemu_log_mask(LOG_UNIMP,
 380                       "%s: timeout_ctrl is not supported\n", __func__);
 381         break;
 382     default:
 383         qemu_log_mask(LOG_GUEST_ERROR,
 384                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 385     }
 386 }
 387
 388 static void fifo_trigger_update(void *opaque)
 389 {
 390     IbexUartState *s = opaque;
 391
 392     if (s->uart_ctrl & UART_CTRL_TX_ENABLE) {
 393         ibex_uart_xmit(NULL, G_IO_OUT, s);
 394     }
 395 }
 396
 397 static const MemoryRegionOps ibex_uart_ops = {
 398     .read = ibex_uart_read,
 399     .write = ibex_uart_write,
 400     .endianness = DEVICE_NATIVE_ENDIAN,
 401     .impl.min_access_size = 4,
 402     .impl.max_access_size = 4,
 403 };
 404
 405 static int ibex_uart_post_load(void *opaque, int version_id)
 406 {
 407     IbexUartState *s = opaque;
 408
 409     ibex_uart_update_irqs(s);
 410     return 0;
 411 }
 412
 413 static const VMStateDescription vmstate_ibex_uart = {
 414     .name = TYPE_IBEX_UART,
 415     .version_id = 1,
 416     .minimum_version_id = 1,
 417     .post_load = ibex_uart_post_load,
 418     .fields = (VMStateField[]) {
 419         VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,
 420                             IBEX_UART_TX_FIFO_SIZE),
 421         VMSTATE_UINT32(tx_level, IbexUartState),
 422         VMSTATE_UINT64(char_tx_time, IbexUartState),
 423         VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState),
 424         VMSTATE_UINT32(uart_intr_state, IbexUartState),
 425         VMSTATE_UINT32(uart_intr_enable, IbexUartState),
 426         VMSTATE_UINT32(uart_ctrl, IbexUartState),
 427         VMSTATE_UINT32(uart_status, IbexUartState),
 428         VMSTATE_UINT32(uart_rdata, IbexUartState),
 429         VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState),
 430         VMSTATE_UINT32(uart_fifo_status, IbexUartState),
 431         VMSTATE_UINT32(uart_ovrd, IbexUartState),
 432         VMSTATE_UINT32(uart_val, IbexUartState),
 433         VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState),
 434         VMSTATE_END_OF_LIST()
 435     }
 436 };
 437
 438 static Property ibex_uart_properties[] = {
 439     DEFINE_PROP_CHR("chardev", IbexUartState, chr),
 440     DEFINE_PROP_END_OF_LIST(),
 441 };
 442
 443 static void ibex_uart_init(Object *obj)
 444 {
 445     IbexUartState *s = IBEX_UART(obj);
 446
 447     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
 448     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
 449     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
 450     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);
 451
 452     memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s,
 453                           TYPE_IBEX_UART, 0x400);
 454     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 455 }
 456
 457 static void ibex_uart_realize(DeviceState *dev, Error **errp)
 458 {
 459     IbexUartState *s = IBEX_UART(dev);
 460
 461     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 462                                           fifo_trigger_update, s);
 463
 464     qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive,
 465                              ibex_uart_receive, NULL, NULL,
 466                              s, NULL, true);
 467 }
 468
 469 static void ibex_uart_class_init(ObjectClass *klass, void *data)
 470 {
 471     DeviceClass *dc = DEVICE_CLASS(klass);
 472
 473     dc->reset = ibex_uart_reset;
 474     dc->realize = ibex_uart_realize;
 475     dc->vmsd = &vmstate_ibex_uart;
 476     device_class_set_props(dc, ibex_uart_properties);
 477 }
 478
 479 static const TypeInfo ibex_uart_info = {
 480     .name          = TYPE_IBEX_UART,
 481     .parent        = TYPE_SYS_BUS_DEVICE,
 482     .instance_size = sizeof(IbexUartState),
 483     .instance_init = ibex_uart_init,
 484     .class_init    = ibex_uart_class_init,
 485 };
 486
 487 static void ibex_uart_register_types(void)
 488 {
 489     type_register_static(&ibex_uart_info);
 490 }
 491
 492 type_init(ibex_uart_register_types)