2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX6UL SOC emulation.
6 * Based on hw/arm/fsl-imx7.c
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #include "hw/arm/fsl-imx6ul.h"
22 #include "hw/misc/unimp.h"
23 #include "hw/usb/imx-usb-phy.h"
24 #include "hw/boards.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
31 static void fsl_imx6ul_init(Object
*obj
)
33 FslIMX6ULState
*s
= FSL_IMX6UL(obj
);
37 object_initialize_child(obj
, "cpu0", &s
->cpu
,
38 ARM_CPU_TYPE_NAME("cortex-a7"));
43 object_initialize_child(obj
, "a7mpcore", &s
->a7mpcore
,
49 object_initialize_child(obj
, "ccm", &s
->ccm
, TYPE_IMX6UL_CCM
);
54 object_initialize_child(obj
, "src", &s
->src
, TYPE_IMX6_SRC
);
59 object_initialize_child(obj
, "gpcv2", &s
->gpcv2
, TYPE_IMX_GPCV2
);
64 object_initialize_child(obj
, "snvs", &s
->snvs
, TYPE_IMX7_SNVS
);
69 object_initialize_child(obj
, "gpr", &s
->gpr
, TYPE_IMX7_GPR
);
74 for (i
= 0; i
< FSL_IMX6UL_NUM_GPIOS
; i
++) {
75 snprintf(name
, NAME_SIZE
, "gpio%d", i
);
76 object_initialize_child(obj
, name
, &s
->gpio
[i
], TYPE_IMX_GPIO
);
82 for (i
= 0; i
< FSL_IMX6UL_NUM_GPTS
; i
++) {
83 snprintf(name
, NAME_SIZE
, "gpt%d", i
);
84 object_initialize_child(obj
, name
, &s
->gpt
[i
], TYPE_IMX7_GPT
);
90 for (i
= 0; i
< FSL_IMX6UL_NUM_EPITS
; i
++) {
91 snprintf(name
, NAME_SIZE
, "epit%d", i
+ 1);
92 object_initialize_child(obj
, name
, &s
->epit
[i
], TYPE_IMX_EPIT
);
98 for (i
= 0; i
< FSL_IMX6UL_NUM_ECSPIS
; i
++) {
99 snprintf(name
, NAME_SIZE
, "spi%d", i
+ 1);
100 object_initialize_child(obj
, name
, &s
->spi
[i
], TYPE_IMX_SPI
);
106 for (i
= 0; i
< FSL_IMX6UL_NUM_I2CS
; i
++) {
107 snprintf(name
, NAME_SIZE
, "i2c%d", i
+ 1);
108 object_initialize_child(obj
, name
, &s
->i2c
[i
], TYPE_IMX_I2C
);
114 for (i
= 0; i
< FSL_IMX6UL_NUM_UARTS
; i
++) {
115 snprintf(name
, NAME_SIZE
, "uart%d", i
);
116 object_initialize_child(obj
, name
, &s
->uart
[i
], TYPE_IMX_SERIAL
);
122 for (i
= 0; i
< FSL_IMX6UL_NUM_ETHS
; i
++) {
123 snprintf(name
, NAME_SIZE
, "eth%d", i
);
124 object_initialize_child(obj
, name
, &s
->eth
[i
], TYPE_IMX_ENET
);
128 for (i
= 0; i
< FSL_IMX6UL_NUM_USB_PHYS
; i
++) {
129 snprintf(name
, NAME_SIZE
, "usbphy%d", i
);
130 object_initialize_child(obj
, name
, &s
->usbphy
[i
], TYPE_IMX_USBPHY
);
132 for (i
= 0; i
< FSL_IMX6UL_NUM_USBS
; i
++) {
133 snprintf(name
, NAME_SIZE
, "usb%d", i
);
134 object_initialize_child(obj
, name
, &s
->usb
[i
], TYPE_CHIPIDEA
);
140 for (i
= 0; i
< FSL_IMX6UL_NUM_USDHCS
; i
++) {
141 snprintf(name
, NAME_SIZE
, "usdhc%d", i
);
142 object_initialize_child(obj
, name
, &s
->usdhc
[i
], TYPE_IMX_USDHC
);
148 for (i
= 0; i
< FSL_IMX6UL_NUM_WDTS
; i
++) {
149 snprintf(name
, NAME_SIZE
, "wdt%d", i
);
150 object_initialize_child(obj
, name
, &s
->wdt
[i
], TYPE_IMX2_WDT
);
154 static void fsl_imx6ul_realize(DeviceState
*dev
, Error
**errp
)
156 MachineState
*ms
= MACHINE(qdev_get_machine());
157 FslIMX6ULState
*s
= FSL_IMX6UL(dev
);
159 char name
[NAME_SIZE
];
163 if (ms
->smp
.cpus
> 1) {
164 error_setg(errp
, "%s: Only a single CPU is supported (%d requested)",
165 TYPE_FSL_IMX6UL
, ms
->smp
.cpus
);
169 object_property_set_int(OBJECT(&s
->cpu
), QEMU_PSCI_CONDUIT_SMC
,
170 "psci-conduit", &error_abort
);
171 qdev_realize(DEVICE(&s
->cpu
), NULL
, &error_abort
);
176 object_property_set_int(OBJECT(&s
->a7mpcore
), 1, "num-cpu", &error_abort
);
177 object_property_set_int(OBJECT(&s
->a7mpcore
),
178 FSL_IMX6UL_MAX_IRQ
+ GIC_INTERNAL
,
179 "num-irq", &error_abort
);
180 sysbus_realize(SYS_BUS_DEVICE(&s
->a7mpcore
), &error_abort
);
181 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->a7mpcore
), 0, FSL_IMX6UL_A7MPCORE_ADDR
);
183 sbd
= SYS_BUS_DEVICE(&s
->a7mpcore
);
186 sysbus_connect_irq(sbd
, 0, qdev_get_gpio_in(d
, ARM_CPU_IRQ
));
187 sysbus_connect_irq(sbd
, 1, qdev_get_gpio_in(d
, ARM_CPU_FIQ
));
188 sysbus_connect_irq(sbd
, 2, qdev_get_gpio_in(d
, ARM_CPU_VIRQ
));
189 sysbus_connect_irq(sbd
, 3, qdev_get_gpio_in(d
, ARM_CPU_VFIQ
));
194 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR
,
200 for (i
= 0; i
< FSL_IMX6UL_NUM_GPTS
; i
++) {
201 static const hwaddr FSL_IMX6UL_GPTn_ADDR
[FSL_IMX6UL_NUM_GPTS
] = {
202 FSL_IMX6UL_GPT1_ADDR
,
203 FSL_IMX6UL_GPT2_ADDR
,
206 static const int FSL_IMX6UL_GPTn_IRQ
[FSL_IMX6UL_NUM_GPTS
] = {
211 s
->gpt
[i
].ccm
= IMX_CCM(&s
->ccm
);
212 sysbus_realize(SYS_BUS_DEVICE(&s
->gpt
[i
]), &error_abort
);
214 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0,
215 FSL_IMX6UL_GPTn_ADDR
[i
]);
217 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0,
218 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
219 FSL_IMX6UL_GPTn_IRQ
[i
]));
225 for (i
= 0; i
< FSL_IMX6UL_NUM_EPITS
; i
++) {
226 static const hwaddr FSL_IMX6UL_EPITn_ADDR
[FSL_IMX6UL_NUM_EPITS
] = {
227 FSL_IMX6UL_EPIT1_ADDR
,
228 FSL_IMX6UL_EPIT2_ADDR
,
231 static const int FSL_IMX6UL_EPITn_IRQ
[FSL_IMX6UL_NUM_EPITS
] = {
232 FSL_IMX6UL_EPIT1_IRQ
,
233 FSL_IMX6UL_EPIT2_IRQ
,
236 s
->epit
[i
].ccm
= IMX_CCM(&s
->ccm
);
237 sysbus_realize(SYS_BUS_DEVICE(&s
->epit
[i
]), &error_abort
);
239 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
240 FSL_IMX6UL_EPITn_ADDR
[i
]);
242 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
243 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
244 FSL_IMX6UL_EPITn_IRQ
[i
]));
250 for (i
= 0; i
< FSL_IMX6UL_NUM_GPIOS
; i
++) {
251 static const hwaddr FSL_IMX6UL_GPIOn_ADDR
[FSL_IMX6UL_NUM_GPIOS
] = {
252 FSL_IMX6UL_GPIO1_ADDR
,
253 FSL_IMX6UL_GPIO2_ADDR
,
254 FSL_IMX6UL_GPIO3_ADDR
,
255 FSL_IMX6UL_GPIO4_ADDR
,
256 FSL_IMX6UL_GPIO5_ADDR
,
259 static const int FSL_IMX6UL_GPIOn_LOW_IRQ
[FSL_IMX6UL_NUM_GPIOS
] = {
260 FSL_IMX6UL_GPIO1_LOW_IRQ
,
261 FSL_IMX6UL_GPIO2_LOW_IRQ
,
262 FSL_IMX6UL_GPIO3_LOW_IRQ
,
263 FSL_IMX6UL_GPIO4_LOW_IRQ
,
264 FSL_IMX6UL_GPIO5_LOW_IRQ
,
267 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ
[FSL_IMX6UL_NUM_GPIOS
] = {
268 FSL_IMX6UL_GPIO1_HIGH_IRQ
,
269 FSL_IMX6UL_GPIO2_HIGH_IRQ
,
270 FSL_IMX6UL_GPIO3_HIGH_IRQ
,
271 FSL_IMX6UL_GPIO4_HIGH_IRQ
,
272 FSL_IMX6UL_GPIO5_HIGH_IRQ
,
275 sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
[i
]), &error_abort
);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
278 FSL_IMX6UL_GPIOn_ADDR
[i
]);
280 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
281 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
282 FSL_IMX6UL_GPIOn_LOW_IRQ
[i
]));
284 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 1,
285 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
286 FSL_IMX6UL_GPIOn_HIGH_IRQ
[i
]));
290 * IOMUXC and IOMUXC_GPR
292 for (i
= 0; i
< 1; i
++) {
293 static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR
[FSL_IMX6UL_NUM_IOMUXCS
] = {
294 FSL_IMX6UL_IOMUXC_ADDR
,
295 FSL_IMX6UL_IOMUXC_GPR_ADDR
,
298 snprintf(name
, NAME_SIZE
, "iomuxc%d", i
);
299 create_unimplemented_device(name
, FSL_IMX6UL_IOMUXCn_ADDR
[i
], 0x4000);
305 sysbus_realize(SYS_BUS_DEVICE(&s
->ccm
), &error_abort
);
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX6UL_CCM_ADDR
);
311 sysbus_realize(SYS_BUS_DEVICE(&s
->src
), &error_abort
);
312 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->src
), 0, FSL_IMX6UL_SRC_ADDR
);
317 sysbus_realize(SYS_BUS_DEVICE(&s
->gpcv2
), &error_abort
);
318 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpcv2
), 0, FSL_IMX6UL_GPC_ADDR
);
320 /* Initialize all ECSPI */
321 for (i
= 0; i
< FSL_IMX6UL_NUM_ECSPIS
; i
++) {
322 static const hwaddr FSL_IMX6UL_SPIn_ADDR
[FSL_IMX6UL_NUM_ECSPIS
] = {
323 FSL_IMX6UL_ECSPI1_ADDR
,
324 FSL_IMX6UL_ECSPI2_ADDR
,
325 FSL_IMX6UL_ECSPI3_ADDR
,
326 FSL_IMX6UL_ECSPI4_ADDR
,
329 static const int FSL_IMX6UL_SPIn_IRQ
[FSL_IMX6UL_NUM_ECSPIS
] = {
330 FSL_IMX6UL_ECSPI1_IRQ
,
331 FSL_IMX6UL_ECSPI2_IRQ
,
332 FSL_IMX6UL_ECSPI3_IRQ
,
333 FSL_IMX6UL_ECSPI4_IRQ
,
336 /* Initialize the SPI */
337 sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), &error_abort
);
339 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
340 FSL_IMX6UL_SPIn_ADDR
[i
]);
342 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
343 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
344 FSL_IMX6UL_SPIn_IRQ
[i
]));
350 for (i
= 0; i
< FSL_IMX6UL_NUM_I2CS
; i
++) {
351 static const hwaddr FSL_IMX6UL_I2Cn_ADDR
[FSL_IMX6UL_NUM_I2CS
] = {
352 FSL_IMX6UL_I2C1_ADDR
,
353 FSL_IMX6UL_I2C2_ADDR
,
354 FSL_IMX6UL_I2C3_ADDR
,
355 FSL_IMX6UL_I2C4_ADDR
,
358 static const int FSL_IMX6UL_I2Cn_IRQ
[FSL_IMX6UL_NUM_I2CS
] = {
365 sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
[i
]), &error_abort
);
366 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, FSL_IMX6UL_I2Cn_ADDR
[i
]);
368 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
369 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
370 FSL_IMX6UL_I2Cn_IRQ
[i
]));
376 for (i
= 0; i
< FSL_IMX6UL_NUM_UARTS
; i
++) {
377 static const hwaddr FSL_IMX6UL_UARTn_ADDR
[FSL_IMX6UL_NUM_UARTS
] = {
378 FSL_IMX6UL_UART1_ADDR
,
379 FSL_IMX6UL_UART2_ADDR
,
380 FSL_IMX6UL_UART3_ADDR
,
381 FSL_IMX6UL_UART4_ADDR
,
382 FSL_IMX6UL_UART5_ADDR
,
383 FSL_IMX6UL_UART6_ADDR
,
384 FSL_IMX6UL_UART7_ADDR
,
385 FSL_IMX6UL_UART8_ADDR
,
388 static const int FSL_IMX6UL_UARTn_IRQ
[FSL_IMX6UL_NUM_UARTS
] = {
389 FSL_IMX6UL_UART1_IRQ
,
390 FSL_IMX6UL_UART2_IRQ
,
391 FSL_IMX6UL_UART3_IRQ
,
392 FSL_IMX6UL_UART4_IRQ
,
393 FSL_IMX6UL_UART5_IRQ
,
394 FSL_IMX6UL_UART6_IRQ
,
395 FSL_IMX6UL_UART7_IRQ
,
396 FSL_IMX6UL_UART8_IRQ
,
399 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
401 sysbus_realize(SYS_BUS_DEVICE(&s
->uart
[i
]), &error_abort
);
403 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
404 FSL_IMX6UL_UARTn_ADDR
[i
]);
406 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
407 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
408 FSL_IMX6UL_UARTn_IRQ
[i
]));
414 for (i
= 0; i
< FSL_IMX6UL_NUM_ETHS
; i
++) {
415 static const hwaddr FSL_IMX6UL_ENETn_ADDR
[FSL_IMX6UL_NUM_ETHS
] = {
416 FSL_IMX6UL_ENET1_ADDR
,
417 FSL_IMX6UL_ENET2_ADDR
,
420 static const int FSL_IMX6UL_ENETn_IRQ
[FSL_IMX6UL_NUM_ETHS
] = {
421 FSL_IMX6UL_ENET1_IRQ
,
422 FSL_IMX6UL_ENET2_IRQ
,
425 static const int FSL_IMX6UL_ENETn_TIMER_IRQ
[FSL_IMX6UL_NUM_ETHS
] = {
426 FSL_IMX6UL_ENET1_TIMER_IRQ
,
427 FSL_IMX6UL_ENET2_TIMER_IRQ
,
430 object_property_set_uint(OBJECT(&s
->eth
[i
]),
431 FSL_IMX6UL_ETH_NUM_TX_RINGS
,
432 "tx-ring-num", &error_abort
);
433 qdev_set_nic_properties(DEVICE(&s
->eth
[i
]), &nd_table
[i
]);
434 sysbus_realize(SYS_BUS_DEVICE(&s
->eth
[i
]), &error_abort
);
436 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->eth
[i
]), 0,
437 FSL_IMX6UL_ENETn_ADDR
[i
]);
439 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 0,
440 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
441 FSL_IMX6UL_ENETn_IRQ
[i
]));
443 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 1,
444 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
445 FSL_IMX6UL_ENETn_TIMER_IRQ
[i
]));
449 for (i
= 0; i
< FSL_IMX6UL_NUM_USB_PHYS
; i
++) {
450 sysbus_realize(SYS_BUS_DEVICE(&s
->usbphy
[i
]), &error_abort
);
451 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usbphy
[i
]), 0,
452 FSL_IMX6UL_USBPHY1_ADDR
+ i
* 0x1000);
455 for (i
= 0; i
< FSL_IMX6UL_NUM_USBS
; i
++) {
456 static const int FSL_IMX6UL_USBn_IRQ
[] = {
460 sysbus_realize(SYS_BUS_DEVICE(&s
->usb
[i
]), &error_abort
);
461 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
462 FSL_IMX6UL_USBO2_USB_ADDR
+ i
* 0x200);
463 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
464 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
465 FSL_IMX6UL_USBn_IRQ
[i
]));
471 for (i
= 0; i
< FSL_IMX6UL_NUM_USDHCS
; i
++) {
472 static const hwaddr FSL_IMX6UL_USDHCn_ADDR
[FSL_IMX6UL_NUM_USDHCS
] = {
473 FSL_IMX6UL_USDHC1_ADDR
,
474 FSL_IMX6UL_USDHC2_ADDR
,
477 static const int FSL_IMX6UL_USDHCn_IRQ
[FSL_IMX6UL_NUM_USDHCS
] = {
478 FSL_IMX6UL_USDHC1_IRQ
,
479 FSL_IMX6UL_USDHC2_IRQ
,
482 object_property_set_uint(OBJECT(&s
->usdhc
[i
]), SDHCI_VENDOR_IMX
,
483 "vendor", &error_abort
);
484 sysbus_realize(SYS_BUS_DEVICE(&s
->usdhc
[i
]), &error_abort
);
486 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0,
487 FSL_IMX6UL_USDHCn_ADDR
[i
]);
489 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0,
490 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
491 FSL_IMX6UL_USDHCn_IRQ
[i
]));
497 sysbus_realize(SYS_BUS_DEVICE(&s
->snvs
), &error_abort
);
498 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->snvs
), 0, FSL_IMX6UL_SNVS_HP_ADDR
);
503 for (i
= 0; i
< FSL_IMX6UL_NUM_WDTS
; i
++) {
504 static const hwaddr FSL_IMX6UL_WDOGn_ADDR
[FSL_IMX6UL_NUM_WDTS
] = {
505 FSL_IMX6UL_WDOG1_ADDR
,
506 FSL_IMX6UL_WDOG2_ADDR
,
507 FSL_IMX6UL_WDOG3_ADDR
,
509 static const int FSL_IMX6UL_WDOGn_IRQ
[FSL_IMX6UL_NUM_WDTS
] = {
510 FSL_IMX6UL_WDOG1_IRQ
,
511 FSL_IMX6UL_WDOG2_IRQ
,
512 FSL_IMX6UL_WDOG3_IRQ
,
515 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "pretimeout-support",
517 sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), &error_abort
);
519 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
520 FSL_IMX6UL_WDOGn_ADDR
[i
]);
521 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
522 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
523 FSL_IMX6UL_WDOGn_IRQ
[i
]));
529 sysbus_realize(SYS_BUS_DEVICE(&s
->gpr
), &error_abort
);
530 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpr
), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR
);
535 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR
, 0x4000);
540 create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR
, 0x4000);
541 create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR
, 0x4000);
542 create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR
, 0x4000);
543 create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR
, 0x4000);
548 create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR
, 0x4000);
549 create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR
, 0x4000);
554 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR
,
555 FSL_IMX6UL_APBH_DMA_SIZE
);
560 for (i
= 0; i
< FSL_IMX6UL_NUM_ADCS
; i
++) {
561 static const hwaddr FSL_IMX6UL_ADCn_ADDR
[FSL_IMX6UL_NUM_ADCS
] = {
562 FSL_IMX6UL_ADC1_ADDR
,
563 FSL_IMX6UL_ADC2_ADDR
,
566 snprintf(name
, NAME_SIZE
, "adc%d", i
);
567 create_unimplemented_device(name
, FSL_IMX6UL_ADCn_ADDR
[i
], 0x4000);
573 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR
, 0x4000);
578 memory_region_init_rom(&s
->rom
, OBJECT(dev
), "imx6ul.rom",
579 FSL_IMX6UL_ROM_SIZE
, &error_abort
);
580 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR
,
586 memory_region_init_rom(&s
->caam
, OBJECT(dev
), "imx6ul.caam",
587 FSL_IMX6UL_CAAM_MEM_SIZE
, &error_abort
);
588 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR
,
594 memory_region_init_ram(&s
->ocram
, NULL
, "imx6ul.ocram",
595 FSL_IMX6UL_OCRAM_MEM_SIZE
,
597 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR
,
601 * internal OCRAM (128 KB) is aliased over 512 KB
603 memory_region_init_alias(&s
->ocram_alias
, OBJECT(dev
),
604 "imx6ul.ocram_alias", &s
->ocram
, 0,
605 FSL_IMX6UL_OCRAM_ALIAS_SIZE
);
606 memory_region_add_subregion(get_system_memory(),
607 FSL_IMX6UL_OCRAM_ALIAS_ADDR
, &s
->ocram_alias
);
610 static void fsl_imx6ul_class_init(ObjectClass
*oc
, void *data
)
612 DeviceClass
*dc
= DEVICE_CLASS(oc
);
614 dc
->realize
= fsl_imx6ul_realize
;
615 dc
->desc
= "i.MX6UL SOC";
616 /* Reason: Uses serial_hds and nd_table in realize() directly */
617 dc
->user_creatable
= false;
620 static const TypeInfo fsl_imx6ul_type_info
= {
621 .name
= TYPE_FSL_IMX6UL
,
622 .parent
= TYPE_DEVICE
,
623 .instance_size
= sizeof(FslIMX6ULState
),
624 .instance_init
= fsl_imx6ul_init
,
625 .class_init
= fsl_imx6ul_class_init
,
628 static void fsl_imx6ul_register_types(void)
630 type_register_static(&fsl_imx6ul_type_info
);
632 type_init(fsl_imx6ul_register_types
)