include/hw/arm/bcm2835_arm_control.h

   1 /*
   2  *  linux/arch/arm/mach-bcm2708/arm_control.h
   3  *
   4  *  Copyright (C) 2010 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #ifndef BCM2708_ARM_CONTROL_H_
  22 #define BCM2708_ARM_CONTROL_H_
  23
  24 /*
  25  * Definitions and addresses for the ARM CONTROL logic
  26  * This file is manually generated.
  27  */
  28
  29 #define ARM_BASE  0x7E00B000
  30
  31 /* Basic configuration */
  32 #define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
  33 #define ARM_C0_SIZ128M   0x00000000
  34 #define ARM_C0_SIZ256M   0x00000001
  35 #define ARM_C0_SIZ512M   0x00000002
  36 #define ARM_C0_SIZ1G     0x00000003
  37 #define ARM_C0_BRESP0    0x00000000
  38 #define ARM_C0_BRESP1    0x00000004
  39 #define ARM_C0_BRESP2    0x00000008
  40 #define ARM_C0_BOOTHI    0x00000010
  41 #define ARM_C0_UNUSED05  0x00000020 /* free */
  42 #define ARM_C0_FULLPERI  0x00000040
  43 #define ARM_C0_UNUSED78  0x00000180 /* free */
  44 #define ARM_C0_JTAGMASK  0x00000E00
  45 #define ARM_C0_JTAGOFF   0x00000000
  46 #define ARM_C0_JTAGBASH  0x00000800 /* Debug on GPIO off */
  47 #define ARM_C0_JTAGGPIO  0x00000C00 /* Debug on GPIO on */
  48 #define ARM_C0_APROTMSK  0x0000F000
  49 #define ARM_C0_DBG0SYNC  0x00010000 /* VPU0 halt sync */
  50 #define ARM_C0_DBG1SYNC  0x00020000 /* VPU1 halt sync */
  51 #define ARM_C0_SWDBGREQ  0x00040000 /* HW debug request */
  52 #define ARM_C0_PASSHALT  0x00080000 /* ARM halt passed to debugger */
  53 #define ARM_C0_PRIO_PER  0x00F00000 /* per priority mask */
  54 #define ARM_C0_PRIO_L2   0x0F000000
  55 #define ARM_C0_PRIO_UC   0xF0000000
  56
  57 #define ARM_C0_APROTPASS  0x0000A000 /* Translate 1:1 */
  58 #define ARM_C0_APROTUSER  0x00000000 /* Only user mode */
  59 #define ARM_C0_APROTSYST  0x0000F000 /* Only system mode */
  60
  61
  62 #define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
  63 #define ARM_C1_TIMER     0x00000001 /* re-route timer IRQ  to VC */
  64 #define ARM_C1_MAIL      0x00000002 /* re-route Mail IRQ   to VC */
  65 #define ARM_C1_BELL0     0x00000004 /* re-route Doorbell 0 to VC */
  66 #define ARM_C1_BELL1     0x00000008 /* re-route Doorbell 1 to VC */
  67 #define ARM_C1_PERSON    0x00000100 /* peripherals on */
  68 #define ARM_C1_REQSTOP   0x00000200 /* ASYNC bridge request stop */
  69
  70 #define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
  71 #define ARM_S_ACKSTOP    0x80000000 /* Bridge stopped */
  72 #define ARM_S_READPEND   0x000003FF /* pending reads counter */
  73 #define ARM_S_WRITPEND   0x000FFC00 /* pending writes counter */
  74
  75 #define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
  76 #define ARM_EH_PERIBURST  0x00000001 /* Burst write seen on peri bus */
  77 #define ARM_EH_ILLADDRS1  0x00000002 /* Address bits 25-27 error */
  78 #define ARM_EH_ILLADDRS2  0x00000004 /* Address bits 31-28 error */
  79 #define ARM_EH_VPU0HALT   0x00000008 /* VPU0 halted & in debug mode */
  80 #define ARM_EH_VPU1HALT   0x00000010 /* VPU1 halted & in debug mode */
  81 #define ARM_EH_ARMHALT    0x00000020 /* ARM in halted debug mode */
  82
  83 #define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
  84 #define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
  85 #define ARM_IDVAL        0x364D5241
  86
  87 /* Translation memory */
  88 #define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
  89 /* 32 locations: 0x100.. 0x17F */
  90 /* 32 spare means we CAN go to 64 pages.... */
  91
  92
  93 /* Interrupts */
  94 #define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        /* Top IRQ bits */
  95 #define ARM_I0_TIMER    0x00000001 /* timer IRQ */
  96 #define ARM_I0_MAIL     0x00000002 /* Mail IRQ */
  97 #define ARM_I0_BELL0    0x00000004 /* Doorbell 0 */
  98 #define ARM_I0_BELL1    0x00000008 /* Doorbell 1 */
  99 #define ARM_I0_BANK1    0x00000100 /* Bank1 IRQ */
 100 #define ARM_I0_BANK2    0x00000200 /* Bank2 IRQ */
 101
 102 #define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
 103 /* todo: all I1_interrupt sources */
 104 #define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
 105 /* todo: all I2_interrupt sources */
 106
 107 #define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
 108 #define ARM_IF_INDEX    0x0000007F     /* FIQ select */
 109 #define ARM_IF_ENABLE   0x00000080     /* FIQ enable */
 110 #define ARM_IF_VCMASK   0x0000003F     /* FIQ = (index from VC source) */
 111 #define ARM_IF_TIMER    0x00000040     /* FIQ = ARM timer */
 112 #define ARM_IF_MAIL     0x00000041     /* FIQ = ARM Mail */
 113 #define ARM_IF_BELL0    0x00000042     /* FIQ = ARM Doorbell 0 */
 114 #define ARM_IF_BELL1    0x00000043     /* FIQ = ARM Doorbell 1 */
 115 #define ARM_IF_VP0HALT  0x00000044     /* FIQ = VPU0 Halt seen */
 116 #define ARM_IF_VP1HALT  0x00000045     /* FIQ = VPU1 Halt seen */
 117 #define ARM_IF_ILLEGAL  0x00000046     /* FIQ = Illegal access seen */
 118
 119 #define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
 120 #define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
 121 #define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
 122 #define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
 123 #define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
 124 #define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
 125 #define ARM_IE_TIMER    0x00000001     /* Timer IRQ */
 126 #define ARM_IE_MAIL     0x00000002     /* Mail IRQ */
 127 #define ARM_IE_BELL0    0x00000004     /* Doorbell 0 */
 128 #define ARM_IE_BELL1    0x00000008     /* Doorbell 1 */
 129 #define ARM_IE_VP0HALT  0x00000010     /* VPU0 Halt */
 130 #define ARM_IE_VP1HALT  0x00000020     /* VPU1 Halt */
 131 #define ARM_IE_ILLEGAL  0x00000040     /* Illegal access seen */
 132
 133 /* Timer */
 134 /* For reg. fields see sp804 spec. */
 135 #define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
 136 #define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
 137 #define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
 138 #define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
 139 #define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
 140 #define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
 141 #define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
 142 #define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
 143 #define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
 144
 145 #define TIMER_CTRL_ONESHOT  (1 << 0)
 146 #define TIMER_CTRL_32BIT    (1 << 1)
 147 #define TIMER_CTRL_DIV1     (0 << 2)
 148 #define TIMER_CTRL_DIV16    (1 << 2)
 149 #define TIMER_CTRL_DIV256   (2 << 2)
 150 #define TIMER_CTRL_IE       (1 << 5)
 151 #define TIMER_CTRL_PERIODIC (1 << 6)
 152 #define TIMER_CTRL_ENABLE   (1 << 7)
 153 #define TIMER_CTRL_DBGHALT  (1 << 8)
 154 #define TIMER_CTRL_ENAFREE  (1 << 9)
 155 #define TIMER_CTRL_FREEDIV_SHIFT 16)
 156 #define TIMER_CTRL_FREEDIV_MASK  0xff
 157
 158 /* Semaphores, Doorbells, Mailboxes */
 159 #define ARM_SBM_OWN0  (ARM_BASE+0x800)
 160 #define ARM_SBM_OWN1  (ARM_BASE+0x900)
 161 #define ARM_SBM_OWN2  (ARM_BASE+0xA00)
 162 #define ARM_SBM_OWN3  (ARM_BASE+0xB00)
 163
 164 /* MAILBOXES
 165  * Register flags are common across all
 166  * owner registers. See end of this section
 167  *
 168  * Semaphores, Doorbells, Mailboxes Owner 0
 169  *
 170  */
 171
 172 #define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
 173 #define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
 174 #define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
 175 #define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
 176 #define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
 177 #define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
 178 #define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
 179 #define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
 180 #define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
 181 #define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
 182 #define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
 183 #define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
 184 #define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
 185 /* MAILBOX 0 access in Owner 0 area */
 186 /* Some addresses should ONLY be used by owner 0 */
 187 #define ARM_0_MAIL0_WRT \
 188         HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) */
 189 #define ARM_0_MAIL0_RD \
 190         HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locs) Normal read */
 191 #define ARM_0_MAIL0_POL \
 192         HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  /* none-pop read */
 193 #define ARM_0_MAIL0_SND \
 194         HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  /* Sender read (only LS 2 bits) */
 195 #define ARM_0_MAIL0_STA \
 196         HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  /* Status read */
 197 #define ARM_0_MAIL0_CNF \
 198         HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  /* Config read/write */
 199 /* MAILBOX 1 access in Owner 0 area */
 200 /* Owner 0 should only WRITE to this mailbox */
 201 #define ARM_0_MAIL1_WRT \
 202         HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   /* .. 0xAC (4 locations) */
 203 /*#define ARM_0_MAIL1_RD \
 204         HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
 205 /*#define ARM_0_MAIL1_POL \
 206         HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
 207 /*#define ARM_0_MAIL1_SND \
 208         HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
 209 #define ARM_0_MAIL1_STA \
 210         HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   /* Status read */
 211 /*#define ARM_0_MAIL1_CNF \
 212         HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
 213 /* General SEM, BELL, MAIL config/status */
 214 #define ARM_0_SEMCLRDBG \
 215         HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  /* semaphore clear/debug register */
 216 #define ARM_0_BELLCLRDBG \
 217         HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  /* Doorbells clear/debug register */
 218 #define ARM_0_ALL_IRQS \
 219         HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  /* ALL interrupts */
 220 #define ARM_0_MY_IRQS \
 221         HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  /* IRQS pending for owner 0 */
 222
 223 /* Semaphores, Doorbells, Mailboxes Owner 1 */
 224 #define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
 225 #define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
 226 #define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
 227 #define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
 228 #define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
 229 #define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
 230 #define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
 231 #define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
 232 #define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
 233 #define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
 234 #define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
 235 #define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
 236 #define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
 237 /* MAILBOX 0 access in Owner 0 area */
 238 /* Owner 1 should only WRITE to this mailbox */
 239 #define ARM_1_MAIL0_WRT \
 240         HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  /* .. 0x8C (4 locations) */
 241 /*#define ARM_1_MAIL0_RD \
 242         HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
 243 /*#define ARM_1_MAIL0_POL \
 244         HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
 245 /*#define ARM_1_MAIL0_SND \
 246         HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
 247 #define ARM_1_MAIL0_STA \
 248         HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  /* Status read */
 249 /*#define ARM_1_MAIL0_CNF \
 250         HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
 251 /* MAILBOX 1 access in Owner 0 area */
 252 #define ARM_1_MAIL1_WRT \
 253         HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) */
 254 #define ARM_1_MAIL1_RD \
 255         HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locs) Normal read */
 256 #define ARM_1_MAIL1_POL \
 257         HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  /* none-pop read */
 258 #define ARM_1_MAIL1_SND \
 259         HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  /* Sender read (only LS 2 bits) */
 260 #define ARM_1_MAIL1_STA \
 261         HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  /* Status read */
 262 #define ARM_1_MAIL1_CNF \
 263         HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
 264 /* General SEM, BELL, MAIL config/status */
 265 #define ARM_1_SEMCLRDBG \
 266         HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  /* semaphore clear/debug register */
 267 #define ARM_1_BELLCLRDBG \
 268         HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  /* Doorbells clear/debug register */
 269 #define ARM_1_MY_IRQS \
 270         HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  /* IRQS pending for owner 1 */
 271 #define ARM_1_ALL_IRQS \
 272         HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  /* ALL interrupts */
 273
 274 /* Semaphores, Doorbells, Mailboxes Owner 2 */
 275 #define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
 276 #define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
 277 #define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
 278 #define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
 279 #define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
 280 #define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
 281 #define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
 282 #define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
 283 #define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
 284 #define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
 285 #define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
 286 #define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
 287 #define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
 288 /* MAILBOX 0 access in Owner 2 area */
 289 /* Owner 2 should only WRITE to this mailbox */
 290 #define ARM_2_MAIL0_WRT \
 291         HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   /* .. 0x8C (4 locations) */
 292 /*#define ARM_2_MAIL0_RD \
 293         HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  */ /* DO NOT USE THIS !!!!! */
 294 /*#define ARM_2_MAIL0_POL \
 295         HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  */ /* DO NOT USE THIS !!!!! */
 296 /*#define ARM_2_MAIL0_SND \
 297         HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  */ /* DO NOT USE THIS !!!!! */
 298 #define ARM_2_MAIL0_STA \
 299         HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   /* Status read */
 300 /*#define ARM_2_MAIL0_CNF \
 301         HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  */ /* DO NOT USE THIS !!!!! */
 302 /* MAILBOX 1 access in Owner 2 area */
 303 /* Owner 2 should only WRITE to this mailbox */
 304 #define ARM_2_MAIL1_WRT \
 305         HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   /* .. 0xAC (4 locations) */
 306 /*#define ARM_2_MAIL1_RD \
 307         HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
 308 /*#define ARM_2_MAIL1_POL \
 309         HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
 310 /*#define ARM_2_MAIL1_SND \
 311         HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
 312 #define ARM_2_MAIL1_STA \
 313         HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   /* Status read */
 314 /*#define ARM_2_MAIL1_CNF \
 315         HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
 316 /* General SEM, BELL, MAIL config/status */
 317 #define ARM_2_SEMCLRDBG \
 318         HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  /* semaphore clear/debug register */
 319 #define ARM_2_BELLCLRDBG \
 320         HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  /* Doorbells clear/debug register */
 321 #define ARM_2_MY_IRQS \
 322         HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  /* IRQS pending for owner 2 */
 323 #define ARM_2_ALL_IRQS \
 324         HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  /* ALL interrupts */
 325
 326 /* Semaphores, Doorbells, Mailboxes Owner 3 */
 327 #define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
 328 #define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
 329 #define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
 330 #define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
 331 #define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
 332 #define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
 333 #define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
 334 #define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
 335 #define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
 336 #define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
 337 #define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
 338 #define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
 339 #define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
 340 /* MAILBOX 0 access in Owner 3 area */
 341 /* Owner 3 should only WRITE to this mailbox */
 342 #define ARM_3_MAIL0_WRT \
 343         HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   /* .. 0x8C (4 locations) */
 344 /*#define ARM_3_MAIL0_RD \
 345         HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  */ /* DO NOT USE THIS !!!!! */
 346 /*#define ARM_3_MAIL0_POL \
 347         HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  */ /* DO NOT USE THIS !!!!! */
 348 /*#define ARM_3_MAIL0_SND \
 349         HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  */ /* DO NOT USE THIS !!!!! */
 350 #define ARM_3_MAIL0_STA \
 351         HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    /* Status read */
 352 /*#define ARM_3_MAIL0_CNF \
 353         HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  */ /* DO NOT USE THIS !!!!! */
 354 /* MAILBOX 1 access in Owner 3 area */
 355 /* Owner 3 should only WRITE to this mailbox */
 356 #define ARM_3_MAIL1_WRT \
 357         HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   /* .. 0xAC (4 locations) */
 358 /*#define ARM_3_MAIL1_RD \
 359         HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
 360 /*#define ARM_3_MAIL1_POL \
 361         HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
 362 /*#define ARM_3_MAIL1_SND \
 363         HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
 364 #define ARM_3_MAIL1_STA \
 365         HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   /* Status read */
 366 /*#define ARM_3_MAIL1_CNF \
 367         HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
 368 /* General SEM, BELL, MAIL config/status */
 369 #define ARM_3_SEMCLRDBG \
 370         HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  /* semaphore clear/debug register */
 371 #define ARM_3_BELLCLRDBG \
 372         HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  /* Doorbells clear/debug register */
 373 #define ARM_3_MY_IRQS \
 374         HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  /* IRQS pending for owner 3 */
 375 #define ARM_3_ALL_IRQS \
 376         HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  /* ALL interrupts */
 377
 378 /*  Mailbox flags. Valid for all owners */
 379
 380 /* Mailbox status register (...0x98) */
 381 #define ARM_MS_FULL       0x80000000
 382 #define ARM_MS_EMPTY      0x40000000
 383 #define ARM_MS_LEVEL      0x400000FF /* Max. value depends on mailbox depth */
 384
 385 /* MAILBOX config/status register (...0x9C) */
 386 /* ANY write to this register clears the error bits! */
 387 #define ARM_MC_IHAVEDATAIRQEN    0x00000001 /* mbox irq enable:  has data */
 388 #define ARM_MC_IHAVESPACEIRQEN   0x00000002 /* mbox irq enable:  has space */
 389 #define ARM_MC_OPPISEMPTYIRQEN   0x00000004 /* mbox irq enable: Opp is empty */
 390 #define ARM_MC_MAIL_CLEAR        0x00000008 /* mbox clear write 1, then  0 */
 391 #define ARM_MC_IHAVEDATAIRQPEND  0x00000010 /* mbox irq pending:  has space */
 392 #define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mbox irq pending: Opp is empty */
 393 #define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mbox irq pending */
 394 /* Bit 7 is unused */
 395 #define ARM_MC_ERRNOOWN   0x00000100 /* error : none owner read from mailbox */
 396 #define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
 397 #define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
 398
 399 /* Semaphore clear/debug register (...0xE0) */
 400 #define ARM_SD_OWN0      0x00000003  /* Owner of sem 0 */
 401 #define ARM_SD_OWN1      0x0000000C  /* Owner of sem 1 */
 402 #define ARM_SD_OWN2      0x00000030  /* Owner of sem 2 */
 403 #define ARM_SD_OWN3      0x000000C0  /* Owner of sem 3 */
 404 #define ARM_SD_OWN4      0x00000300  /* Owner of sem 4 */
 405 #define ARM_SD_OWN5      0x00000C00  /* Owner of sem 5 */
 406 #define ARM_SD_OWN6      0x00003000  /* Owner of sem 6 */
 407 #define ARM_SD_OWN7      0x0000C000  /* Owner of sem 7 */
 408 #define ARM_SD_SEM0      0x00010000  /* Status of sem 0 */
 409 #define ARM_SD_SEM1      0x00020000  /* Status of sem 1 */
 410 #define ARM_SD_SEM2      0x00040000  /* Status of sem 2 */
 411 #define ARM_SD_SEM3      0x00080000  /* Status of sem 3 */
 412 #define ARM_SD_SEM4      0x00100000  /* Status of sem 4 */
 413 #define ARM_SD_SEM5      0x00200000  /* Status of sem 5 */
 414 #define ARM_SD_SEM6      0x00400000  /* Status of sem 6 */
 415 #define ARM_SD_SEM7      0x00800000  /* Status of sem 7 */
 416
 417 /* Doorbells clear/debug register (...0xE4) */
 418 #define ARM_BD_OWN0      0x00000003  /* Owner of doorbell 0 */
 419 #define ARM_BD_OWN1      0x0000000C  /* Owner of doorbell 1 */
 420 #define ARM_BD_OWN2      0x00000030  /* Owner of doorbell 2 */
 421 #define ARM_BD_OWN3      0x000000C0  /* Owner of doorbell 3 */
 422 #define ARM_BD_BELL0     0x00000100  /* Status of doorbell 0 */
 423 #define ARM_BD_BELL1     0x00000200  /* Status of doorbell 1 */
 424 #define ARM_BD_BELL2     0x00000400  /* Status of doorbell 2 */
 425 #define ARM_BD_BELL3     0x00000800  /* Status of doorbell 3 */
 426
 427 /* MY IRQS register (...0xF8) */
 428 #define ARM_MYIRQ_BELL   0x00000001  /* This owner has a doorbell IRQ */
 429 #define ARM_MYIRQ_MAIL   0x00000002  /* This owner has a mailbox  IRQ */
 430
 431 /* ALL IRQS register (...0xF8) */
 432 #define ARM_AIS_BELL0 0x00000001  /* Doorbell 0 IRQ pending */
 433 #define ARM_AIS_BELL1 0x00000002  /* Doorbell 1 IRQ pending */
 434 #define ARM_AIS_BELL2 0x00000004  /* Doorbell 2 IRQ pending */
 435 #define ARM_AIS_BELL3 0x00000008  /* Doorbell 3 IRQ pending */
 436 #define ARM_AIS0_HAVEDATA 0x00000010  /* MAIL 0 has data IRQ pending */
 437 #define ARM_AIS0_HAVESPAC 0x00000020  /* MAIL 0 has space IRQ pending */
 438 #define ARM_AIS0_OPPEMPTY 0x00000040  /* MAIL 0 opposite is empty IRQ */
 439 #define ARM_AIS1_HAVEDATA 0x00000080  /* MAIL 1 has data IRQ pending */
 440 #define ARM_AIS1_HAVESPAC 0x00000100  /* MAIL 1 has space IRQ pending */
 441 #define ARM_AIS1_OPPEMPTY 0x00000200  /* MAIL 1 opposite is empty IRQ */
 442 /* Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
 443 /* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
 444 /* */
 445 /* ARM JTAG BASH */
 446 /* */
 447 #define AJB_BASE 0x7e2000c0
 448
 449 #define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
 450 #define   AJB_BITS0    0x000000
 451 #define   AJB_BITS4    0x000004
 452 #define   AJB_BITS8    0x000008
 453 #define   AJB_BITS12   0x00000C
 454 #define   AJB_BITS16   0x000010
 455 #define   AJB_BITS20   0x000014
 456 #define   AJB_BITS24   0x000018
 457 #define   AJB_BITS28   0x00001C
 458 #define   AJB_BITS32   0x000020
 459 #define   AJB_BITS34   0x000022
 460 #define   AJB_OUT_MS   0x000040
 461 #define   AJB_OUT_LS   0x000000
 462 #define   AJB_INV_CLK  0x000080
 463 #define   AJB_D0_RISE  0x000100
 464 #define   AJB_D0_FALL  0x000000
 465 #define   AJB_D1_RISE  0x000200
 466 #define   AJB_D1_FALL  0x000000
 467 #define   AJB_IN_RISE  0x000400
 468 #define   AJB_IN_FALL  0x000000
 469 #define   AJB_ENABLE   0x000800
 470 #define   AJB_HOLD0    0x000000
 471 #define   AJB_HOLD1    0x001000
 472 #define   AJB_HOLD2    0x002000
 473 #define   AJB_HOLD3    0x003000
 474 #define   AJB_RESETN   0x004000
 475 #define   AJB_CLKSHFT  16
 476 #define   AJB_BUSY     0x80000000
 477 #define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
 478 #define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
 479 #define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
 480
 481 #endif