target/arm/translate-vfp.inc.c

   1 /*
   2  *  ARM translation: AArch32 VFP instructions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *  Copyright (c) 2005-2007 CodeSourcery
   6  *  Copyright (c) 2007 OpenedHand, Ltd.
   7  *  Copyright (c) 2019 Linaro, Ltd.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 /*
  24  * This file is intended to be included from translate.c; it uses
  25  * some macros and definitions provided by that file.
  26  * It might be possible to convert it to a standalone .c file eventually.
  27  */
  28
  29 /* Include the generated VFP decoder */
  30 #include "decode-vfp.inc.c"
  31 #include "decode-vfp-uncond.inc.c"
  32
  33 /*
  34  * The imm8 encodes the sign bit, enough bits to represent an exponent in
  35  * the range 01....1xx to 10....0xx, and the most significant 4 bits of
  36  * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
  37  */
  38 uint64_t vfp_expand_imm(int size, uint8_t imm8)
  39 {
  40     uint64_t imm;
  41
  42     switch (size) {
  43     case MO_64:
  44         imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
  45             (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
  46             extract32(imm8, 0, 6);
  47         imm <<= 48;
  48         break;
  49     case MO_32:
  50         imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
  51             (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
  52             (extract32(imm8, 0, 6) << 3);
  53         imm <<= 16;
  54         break;
  55     case MO_16:
  56         imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
  57             (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
  58             (extract32(imm8, 0, 6) << 6);
  59         break;
  60     default:
  61         g_assert_not_reached();
  62     }
  63     return imm;
  64 }
  65
  66 /*
  67  * Return the offset of a 16-bit half of the specified VFP single-precision
  68  * register. If top is true, returns the top 16 bits; otherwise the bottom
  69  * 16 bits.
  70  */
  71 static inline long vfp_f16_offset(unsigned reg, bool top)
  72 {
  73     long offs = vfp_reg_offset(false, reg);
  74 #ifdef HOST_WORDS_BIGENDIAN
  75     if (!top) {
  76         offs += 2;
  77     }
  78 #else
  79     if (top) {
  80         offs += 2;
  81     }
  82 #endif
  83     return offs;
  84 }
  85
  86 /*
  87  * Check that VFP access is enabled. If it is, do the necessary
  88  * M-profile lazy-FP handling and then return true.
  89  * If not, emit code to generate an appropriate exception and
  90  * return false.
  91  * The ignore_vfp_enabled argument specifies that we should ignore
  92  * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
  93  * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
  94  */
  95 static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
  96 {
  97     if (s->fp_excp_el) {
  98         if (arm_dc_feature(s, ARM_FEATURE_M)) {
  99             gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
 100                                s->fp_excp_el);
 101         } else {
 102             gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 103                                syn_fp_access_trap(1, 0xe, false),
 104                                s->fp_excp_el);
 105         }
 106         return false;
 107     }
 108
 109     if (!s->vfp_enabled && !ignore_vfp_enabled) {
 110         assert(!arm_dc_feature(s, ARM_FEATURE_M));
 111         unallocated_encoding(s);
 112         return false;
 113     }
 114
 115     if (arm_dc_feature(s, ARM_FEATURE_M)) {
 116         /* Handle M-profile lazy FP state mechanics */
 117
 118         /* Trigger lazy-state preservation if necessary */
 119         if (s->v7m_lspact) {
 120             /*
 121              * Lazy state saving affects external memory and also the NVIC,
 122              * so we must mark it as an IO operation for icount.
 123              */
 124             if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
 125                 gen_io_start();
 126             }
 127             gen_helper_v7m_preserve_fp_state(cpu_env);
 128             if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
 129                 gen_io_end();
 130             }
 131             /*
 132              * If the preserve_fp_state helper doesn't throw an exception
 133              * then it will clear LSPACT; we don't need to repeat this for
 134              * any further FP insns in this TB.
 135              */
 136             s->v7m_lspact = false;
 137         }
 138
 139         /* Update ownership of FP context: set FPCCR.S to match current state */
 140         if (s->v8m_fpccr_s_wrong) {
 141             TCGv_i32 tmp;
 142
 143             tmp = load_cpu_field(v7m.fpccr[M_REG_S]);
 144             if (s->v8m_secure) {
 145                 tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK);
 146             } else {
 147                 tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK);
 148             }
 149             store_cpu_field(tmp, v7m.fpccr[M_REG_S]);
 150             /* Don't need to do this for any further FP insns in this TB */
 151             s->v8m_fpccr_s_wrong = false;
 152         }
 153
 154         if (s->v7m_new_fp_ctxt_needed) {
 155             /*
 156              * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
 157              * and the FPSCR.
 158              */
 159             TCGv_i32 control, fpscr;
 160             uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
 161
 162             fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
 163             gen_helper_vfp_set_fpscr(cpu_env, fpscr);
 164             tcg_temp_free_i32(fpscr);
 165             /*
 166              * We don't need to arrange to end the TB, because the only
 167              * parts of FPSCR which we cache in the TB flags are the VECLEN
 168              * and VECSTRIDE, and those don't exist for M-profile.
 169              */
 170
 171             if (s->v8m_secure) {
 172                 bits |= R_V7M_CONTROL_SFPA_MASK;
 173             }
 174             control = load_cpu_field(v7m.control[M_REG_S]);
 175             tcg_gen_ori_i32(control, control, bits);
 176             store_cpu_field(control, v7m.control[M_REG_S]);
 177             /* Don't need to do this for any further FP insns in this TB */
 178             s->v7m_new_fp_ctxt_needed = false;
 179         }
 180     }
 181
 182     return true;
 183 }
 184
 185 /*
 186  * The most usual kind of VFP access check, for everything except
 187  * FMXR/FMRX to the always-available special registers.
 188  */
 189 static bool vfp_access_check(DisasContext *s)
 190 {
 191     return full_vfp_access_check(s, false);
 192 }
 193
 194 static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
 195 {
 196     uint32_t rd, rn, rm;
 197     bool dp = a->dp;
 198
 199     if (!dc_isar_feature(aa32_vsel, s)) {
 200         return false;
 201     }
 202
 203     /* UNDEF accesses to D16-D31 if they don't exist */
 204     if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
 205         ((a->vm | a->vn | a->vd) & 0x10)) {
 206         return false;
 207     }
 208
 209     if (dp && !dc_isar_feature(aa32_fpdp, s)) {
 210         return false;
 211     }
 212
 213     rd = a->vd;
 214     rn = a->vn;
 215     rm = a->vm;
 216
 217     if (!vfp_access_check(s)) {
 218         return true;
 219     }
 220
 221     if (dp) {
 222         TCGv_i64 frn, frm, dest;
 223         TCGv_i64 tmp, zero, zf, nf, vf;
 224
 225         zero = tcg_const_i64(0);
 226
 227         frn = tcg_temp_new_i64();
 228         frm = tcg_temp_new_i64();
 229         dest = tcg_temp_new_i64();
 230
 231         zf = tcg_temp_new_i64();
 232         nf = tcg_temp_new_i64();
 233         vf = tcg_temp_new_i64();
 234
 235         tcg_gen_extu_i32_i64(zf, cpu_ZF);
 236         tcg_gen_ext_i32_i64(nf, cpu_NF);
 237         tcg_gen_ext_i32_i64(vf, cpu_VF);
 238
 239         neon_load_reg64(frn, rn);
 240         neon_load_reg64(frm, rm);
 241         switch (a->cc) {
 242         case 0: /* eq: Z */
 243             tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
 244                                 frn, frm);
 245             break;
 246         case 1: /* vs: V */
 247             tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero,
 248                                 frn, frm);
 249             break;
 250         case 2: /* ge: N == V -> N ^ V == 0 */
 251             tmp = tcg_temp_new_i64();
 252             tcg_gen_xor_i64(tmp, vf, nf);
 253             tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
 254                                 frn, frm);
 255             tcg_temp_free_i64(tmp);
 256             break;
 257         case 3: /* gt: !Z && N == V */
 258             tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero,
 259                                 frn, frm);
 260             tmp = tcg_temp_new_i64();
 261             tcg_gen_xor_i64(tmp, vf, nf);
 262             tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
 263                                 dest, frm);
 264             tcg_temp_free_i64(tmp);
 265             break;
 266         }
 267         neon_store_reg64(dest, rd);
 268         tcg_temp_free_i64(frn);
 269         tcg_temp_free_i64(frm);
 270         tcg_temp_free_i64(dest);
 271
 272         tcg_temp_free_i64(zf);
 273         tcg_temp_free_i64(nf);
 274         tcg_temp_free_i64(vf);
 275
 276         tcg_temp_free_i64(zero);
 277     } else {
 278         TCGv_i32 frn, frm, dest;
 279         TCGv_i32 tmp, zero;
 280
 281         zero = tcg_const_i32(0);
 282
 283         frn = tcg_temp_new_i32();
 284         frm = tcg_temp_new_i32();
 285         dest = tcg_temp_new_i32();
 286         neon_load_reg32(frn, rn);
 287         neon_load_reg32(frm, rm);
 288         switch (a->cc) {
 289         case 0: /* eq: Z */
 290             tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
 291                                 frn, frm);
 292             break;
 293         case 1: /* vs: V */
 294             tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero,
 295                                 frn, frm);
 296             break;
 297         case 2: /* ge: N == V -> N ^ V == 0 */
 298             tmp = tcg_temp_new_i32();
 299             tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
 300             tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
 301                                 frn, frm);
 302             tcg_temp_free_i32(tmp);
 303             break;
 304         case 3: /* gt: !Z && N == V */
 305             tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero,
 306                                 frn, frm);
 307             tmp = tcg_temp_new_i32();
 308             tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
 309             tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
 310                                 dest, frm);
 311             tcg_temp_free_i32(tmp);
 312             break;
 313         }
 314         neon_store_reg32(dest, rd);
 315         tcg_temp_free_i32(frn);
 316         tcg_temp_free_i32(frm);
 317         tcg_temp_free_i32(dest);
 318
 319         tcg_temp_free_i32(zero);
 320     }
 321
 322     return true;
 323 }
 324
 325 static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
 326 {
 327     uint32_t rd, rn, rm;
 328     bool dp = a->dp;
 329     bool vmin = a->op;
 330     TCGv_ptr fpst;
 331
 332     if (!dc_isar_feature(aa32_vminmaxnm, s)) {
 333         return false;
 334     }
 335
 336     /* UNDEF accesses to D16-D31 if they don't exist */
 337     if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
 338         ((a->vm | a->vn | a->vd) & 0x10)) {
 339         return false;
 340     }
 341
 342     if (dp && !dc_isar_feature(aa32_fpdp, s)) {
 343         return false;
 344     }
 345
 346     rd = a->vd;
 347     rn = a->vn;
 348     rm = a->vm;
 349
 350     if (!vfp_access_check(s)) {
 351         return true;
 352     }
 353
 354     fpst = get_fpstatus_ptr(0);
 355
 356     if (dp) {
 357         TCGv_i64 frn, frm, dest;
 358
 359         frn = tcg_temp_new_i64();
 360         frm = tcg_temp_new_i64();
 361         dest = tcg_temp_new_i64();
 362
 363         neon_load_reg64(frn, rn);
 364         neon_load_reg64(frm, rm);
 365         if (vmin) {
 366             gen_helper_vfp_minnumd(dest, frn, frm, fpst);
 367         } else {
 368             gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
 369         }
 370         neon_store_reg64(dest, rd);
 371         tcg_temp_free_i64(frn);
 372         tcg_temp_free_i64(frm);
 373         tcg_temp_free_i64(dest);
 374     } else {
 375         TCGv_i32 frn, frm, dest;
 376
 377         frn = tcg_temp_new_i32();
 378         frm = tcg_temp_new_i32();
 379         dest = tcg_temp_new_i32();
 380
 381         neon_load_reg32(frn, rn);
 382         neon_load_reg32(frm, rm);
 383         if (vmin) {
 384             gen_helper_vfp_minnums(dest, frn, frm, fpst);
 385         } else {
 386             gen_helper_vfp_maxnums(dest, frn, frm, fpst);
 387         }
 388         neon_store_reg32(dest, rd);
 389         tcg_temp_free_i32(frn);
 390         tcg_temp_free_i32(frm);
 391         tcg_temp_free_i32(dest);
 392     }
 393
 394     tcg_temp_free_ptr(fpst);
 395     return true;
 396 }
 397
 398 /*
 399  * Table for converting the most common AArch32 encoding of
 400  * rounding mode to arm_fprounding order (which matches the
 401  * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
 402  */
 403 static const uint8_t fp_decode_rm[] = {
 404     FPROUNDING_TIEAWAY,
 405     FPROUNDING_TIEEVEN,
 406     FPROUNDING_POSINF,
 407     FPROUNDING_NEGINF,
 408 };
 409
 410 static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
 411 {
 412     uint32_t rd, rm;
 413     bool dp = a->dp;
 414     TCGv_ptr fpst;
 415     TCGv_i32 tcg_rmode;
 416     int rounding = fp_decode_rm[a->rm];
 417
 418     if (!dc_isar_feature(aa32_vrint, s)) {
 419         return false;
 420     }
 421
 422     /* UNDEF accesses to D16-D31 if they don't exist */
 423     if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
 424         ((a->vm | a->vd) & 0x10)) {
 425         return false;
 426     }
 427
 428     if (dp && !dc_isar_feature(aa32_fpdp, s)) {
 429         return false;
 430     }
 431
 432     rd = a->vd;
 433     rm = a->vm;
 434
 435     if (!vfp_access_check(s)) {
 436         return true;
 437     }
 438
 439     fpst = get_fpstatus_ptr(0);
 440
 441     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
 442     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 443
 444     if (dp) {
 445         TCGv_i64 tcg_op;
 446         TCGv_i64 tcg_res;
 447         tcg_op = tcg_temp_new_i64();
 448         tcg_res = tcg_temp_new_i64();
 449         neon_load_reg64(tcg_op, rm);
 450         gen_helper_rintd(tcg_res, tcg_op, fpst);
 451         neon_store_reg64(tcg_res, rd);
 452         tcg_temp_free_i64(tcg_op);
 453         tcg_temp_free_i64(tcg_res);
 454     } else {
 455         TCGv_i32 tcg_op;
 456         TCGv_i32 tcg_res;
 457         tcg_op = tcg_temp_new_i32();
 458         tcg_res = tcg_temp_new_i32();
 459         neon_load_reg32(tcg_op, rm);
 460         gen_helper_rints(tcg_res, tcg_op, fpst);
 461         neon_store_reg32(tcg_res, rd);
 462         tcg_temp_free_i32(tcg_op);
 463         tcg_temp_free_i32(tcg_res);
 464     }
 465
 466     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 467     tcg_temp_free_i32(tcg_rmode);
 468
 469     tcg_temp_free_ptr(fpst);
 470     return true;
 471 }
 472
 473 static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
 474 {
 475     uint32_t rd, rm;
 476     bool dp = a->dp;
 477     TCGv_ptr fpst;
 478     TCGv_i32 tcg_rmode, tcg_shift;
 479     int rounding = fp_decode_rm[a->rm];
 480     bool is_signed = a->op;
 481
 482     if (!dc_isar_feature(aa32_vcvt_dr, s)) {
 483         return false;
 484     }
 485
 486     /* UNDEF accesses to D16-D31 if they don't exist */
 487     if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
 488         return false;
 489     }
 490
 491     if (dp && !dc_isar_feature(aa32_fpdp, s)) {
 492         return false;
 493     }
 494
 495     rd = a->vd;
 496     rm = a->vm;
 497
 498     if (!vfp_access_check(s)) {
 499         return true;
 500     }
 501
 502     fpst = get_fpstatus_ptr(0);
 503
 504     tcg_shift = tcg_const_i32(0);
 505
 506     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
 507     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 508
 509     if (dp) {
 510         TCGv_i64 tcg_double, tcg_res;
 511         TCGv_i32 tcg_tmp;
 512         tcg_double = tcg_temp_new_i64();
 513         tcg_res = tcg_temp_new_i64();
 514         tcg_tmp = tcg_temp_new_i32();
 515         neon_load_reg64(tcg_double, rm);
 516         if (is_signed) {
 517             gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
 518         } else {
 519             gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
 520         }
 521         tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
 522         neon_store_reg32(tcg_tmp, rd);
 523         tcg_temp_free_i32(tcg_tmp);
 524         tcg_temp_free_i64(tcg_res);
 525         tcg_temp_free_i64(tcg_double);
 526     } else {
 527         TCGv_i32 tcg_single, tcg_res;
 528         tcg_single = tcg_temp_new_i32();
 529         tcg_res = tcg_temp_new_i32();
 530         neon_load_reg32(tcg_single, rm);
 531         if (is_signed) {
 532             gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
 533         } else {
 534             gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
 535         }
 536         neon_store_reg32(tcg_res, rd);
 537         tcg_temp_free_i32(tcg_res);
 538         tcg_temp_free_i32(tcg_single);
 539     }
 540
 541     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 542     tcg_temp_free_i32(tcg_rmode);
 543
 544     tcg_temp_free_i32(tcg_shift);
 545
 546     tcg_temp_free_ptr(fpst);
 547
 548     return true;
 549 }
 550
 551 static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
 552 {
 553     /* VMOV scalar to general purpose register */
 554     TCGv_i32 tmp;
 555     int pass;
 556     uint32_t offset;
 557
 558     /* UNDEF accesses to D16-D31 if they don't exist */
 559     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
 560         return false;
 561     }
 562
 563     offset = a->index << a->size;
 564     pass = extract32(offset, 2, 1);
 565     offset = extract32(offset, 0, 2) * 8;
 566
 567     if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
 568         return false;
 569     }
 570
 571     if (!vfp_access_check(s)) {
 572         return true;
 573     }
 574
 575     tmp = neon_load_reg(a->vn, pass);
 576     switch (a->size) {
 577     case 0:
 578         if (offset) {
 579             tcg_gen_shri_i32(tmp, tmp, offset);
 580         }
 581         if (a->u) {
 582             gen_uxtb(tmp);
 583         } else {
 584             gen_sxtb(tmp);
 585         }
 586         break;
 587     case 1:
 588         if (a->u) {
 589             if (offset) {
 590                 tcg_gen_shri_i32(tmp, tmp, 16);
 591             } else {
 592                 gen_uxth(tmp);
 593             }
 594         } else {
 595             if (offset) {
 596                 tcg_gen_sari_i32(tmp, tmp, 16);
 597             } else {
 598                 gen_sxth(tmp);
 599             }
 600         }
 601         break;
 602     case 2:
 603         break;
 604     }
 605     store_reg(s, a->rt, tmp);
 606
 607     return true;
 608 }
 609
 610 static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
 611 {
 612     /* VMOV general purpose register to scalar */
 613     TCGv_i32 tmp, tmp2;
 614     int pass;
 615     uint32_t offset;
 616
 617     /* UNDEF accesses to D16-D31 if they don't exist */
 618     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
 619         return false;
 620     }
 621
 622     offset = a->index << a->size;
 623     pass = extract32(offset, 2, 1);
 624     offset = extract32(offset, 0, 2) * 8;
 625
 626     if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
 627         return false;
 628     }
 629
 630     if (!vfp_access_check(s)) {
 631         return true;
 632     }
 633
 634     tmp = load_reg(s, a->rt);
 635     switch (a->size) {
 636     case 0:
 637         tmp2 = neon_load_reg(a->vn, pass);
 638         tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
 639         tcg_temp_free_i32(tmp2);
 640         break;
 641     case 1:
 642         tmp2 = neon_load_reg(a->vn, pass);
 643         tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
 644         tcg_temp_free_i32(tmp2);
 645         break;
 646     case 2:
 647         break;
 648     }
 649     neon_store_reg(a->vn, pass, tmp);
 650
 651     return true;
 652 }
 653
 654 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 655 {
 656     /* VDUP (general purpose register) */
 657     TCGv_i32 tmp;
 658     int size, vec_size;
 659
 660     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 661         return false;
 662     }
 663
 664     /* UNDEF accesses to D16-D31 if they don't exist */
 665     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
 666         return false;
 667     }
 668
 669     if (a->b && a->e) {
 670         return false;
 671     }
 672
 673     if (a->q && (a->vn & 1)) {
 674         return false;
 675     }
 676
 677     vec_size = a->q ? 16 : 8;
 678     if (a->b) {
 679         size = 0;
 680     } else if (a->e) {
 681         size = 1;
 682     } else {
 683         size = 2;
 684     }
 685
 686     if (!vfp_access_check(s)) {
 687         return true;
 688     }
 689
 690     tmp = load_reg(s, a->rt);
 691     tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
 692                          vec_size, vec_size, tmp);
 693     tcg_temp_free_i32(tmp);
 694
 695     return true;
 696 }
 697
 698 static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
 699 {
 700     TCGv_i32 tmp;
 701     bool ignore_vfp_enabled = false;
 702
 703     if (arm_dc_feature(s, ARM_FEATURE_M)) {
 704         /*
 705          * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
 706          * Accesses to R15 are UNPREDICTABLE; we choose to undef.
 707          * (FPSCR -> r15 is a special case which writes to the PSR flags.)
 708          */
 709         if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
 710             return false;
 711         }
 712     }
 713
 714     switch (a->reg) {
 715     case ARM_VFP_FPSID:
 716         /*
 717          * VFPv2 allows access to FPSID from userspace; VFPv3 restricts
 718          * all ID registers to privileged access only.
 719          */
 720         if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
 721             return false;
 722         }
 723         ignore_vfp_enabled = true;
 724         break;
 725     case ARM_VFP_MVFR0:
 726     case ARM_VFP_MVFR1:
 727         if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
 728             return false;
 729         }
 730         ignore_vfp_enabled = true;
 731         break;
 732     case ARM_VFP_MVFR2:
 733         if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
 734             return false;
 735         }
 736         ignore_vfp_enabled = true;
 737         break;
 738     case ARM_VFP_FPSCR:
 739         break;
 740     case ARM_VFP_FPEXC:
 741         if (IS_USER(s)) {
 742             return false;
 743         }
 744         ignore_vfp_enabled = true;
 745         break;
 746     case ARM_VFP_FPINST:
 747     case ARM_VFP_FPINST2:
 748         /* Not present in VFPv3 */
 749         if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
 750             return false;
 751         }
 752         break;
 753     default:
 754         return false;
 755     }
 756
 757     if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
 758         return true;
 759     }
 760
 761     if (a->l) {
 762         /* VMRS, move VFP special register to gp register */
 763         switch (a->reg) {
 764         case ARM_VFP_FPSID:
 765         case ARM_VFP_FPEXC:
 766         case ARM_VFP_FPINST:
 767         case ARM_VFP_FPINST2:
 768         case ARM_VFP_MVFR0:
 769         case ARM_VFP_MVFR1:
 770         case ARM_VFP_MVFR2:
 771             tmp = load_cpu_field(vfp.xregs[a->reg]);
 772             break;
 773         case ARM_VFP_FPSCR:
 774             if (a->rt == 15) {
 775                 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
 776                 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
 777             } else {
 778                 tmp = tcg_temp_new_i32();
 779                 gen_helper_vfp_get_fpscr(tmp, cpu_env);
 780             }
 781             break;
 782         default:
 783             g_assert_not_reached();
 784         }
 785
 786         if (a->rt == 15) {
 787             /* Set the 4 flag bits in the CPSR.  */
 788             gen_set_nzcv(tmp);
 789             tcg_temp_free_i32(tmp);
 790         } else {
 791             store_reg(s, a->rt, tmp);
 792         }
 793     } else {
 794         /* VMSR, move gp register to VFP special register */
 795         switch (a->reg) {
 796         case ARM_VFP_FPSID:
 797         case ARM_VFP_MVFR0:
 798         case ARM_VFP_MVFR1:
 799         case ARM_VFP_MVFR2:
 800             /* Writes are ignored.  */
 801             break;
 802         case ARM_VFP_FPSCR:
 803             tmp = load_reg(s, a->rt);
 804             gen_helper_vfp_set_fpscr(cpu_env, tmp);
 805             tcg_temp_free_i32(tmp);
 806             gen_lookup_tb(s);
 807             break;
 808         case ARM_VFP_FPEXC:
 809             /*
 810              * TODO: VFP subarchitecture support.
 811              * For now, keep the EN bit only
 812              */
 813             tmp = load_reg(s, a->rt);
 814             tcg_gen_andi_i32(tmp, tmp, 1 << 30);
 815             store_cpu_field(tmp, vfp.xregs[a->reg]);
 816             gen_lookup_tb(s);
 817             break;
 818         case ARM_VFP_FPINST:
 819         case ARM_VFP_FPINST2:
 820             tmp = load_reg(s, a->rt);
 821             store_cpu_field(tmp, vfp.xregs[a->reg]);
 822             break;
 823         default:
 824             g_assert_not_reached();
 825         }
 826     }
 827
 828     return true;
 829 }
 830
 831 static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
 832 {
 833     TCGv_i32 tmp;
 834
 835     if (!vfp_access_check(s)) {
 836         return true;
 837     }
 838
 839     if (a->l) {
 840         /* VFP to general purpose register */
 841         tmp = tcg_temp_new_i32();
 842         neon_load_reg32(tmp, a->vn);
 843         if (a->rt == 15) {
 844             /* Set the 4 flag bits in the CPSR.  */
 845             gen_set_nzcv(tmp);
 846             tcg_temp_free_i32(tmp);
 847         } else {
 848             store_reg(s, a->rt, tmp);
 849         }
 850     } else {
 851         /* general purpose register to VFP */
 852         tmp = load_reg(s, a->rt);
 853         neon_store_reg32(tmp, a->vn);
 854         tcg_temp_free_i32(tmp);
 855     }
 856
 857     return true;
 858 }
 859
 860 static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
 861 {
 862     TCGv_i32 tmp;
 863
 864     /*
 865      * VMOV between two general-purpose registers and two single precision
 866      * floating point registers
 867      */
 868     if (!vfp_access_check(s)) {
 869         return true;
 870     }
 871
 872     if (a->op) {
 873         /* fpreg to gpreg */
 874         tmp = tcg_temp_new_i32();
 875         neon_load_reg32(tmp, a->vm);
 876         store_reg(s, a->rt, tmp);
 877         tmp = tcg_temp_new_i32();
 878         neon_load_reg32(tmp, a->vm + 1);
 879         store_reg(s, a->rt2, tmp);
 880     } else {
 881         /* gpreg to fpreg */
 882         tmp = load_reg(s, a->rt);
 883         neon_store_reg32(tmp, a->vm);
 884         tcg_temp_free_i32(tmp);
 885         tmp = load_reg(s, a->rt2);
 886         neon_store_reg32(tmp, a->vm + 1);
 887         tcg_temp_free_i32(tmp);
 888     }
 889
 890     return true;
 891 }
 892
 893 static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
 894 {
 895     TCGv_i32 tmp;
 896
 897     /*
 898      * VMOV between two general-purpose registers and one double precision
 899      * floating point register
 900      */
 901
 902     /* UNDEF accesses to D16-D31 if they don't exist */
 903     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
 904         return false;
 905     }
 906
 907     if (!vfp_access_check(s)) {
 908         return true;
 909     }
 910
 911     if (a->op) {
 912         /* fpreg to gpreg */
 913         tmp = tcg_temp_new_i32();
 914         neon_load_reg32(tmp, a->vm * 2);
 915         store_reg(s, a->rt, tmp);
 916         tmp = tcg_temp_new_i32();
 917         neon_load_reg32(tmp, a->vm * 2 + 1);
 918         store_reg(s, a->rt2, tmp);
 919     } else {
 920         /* gpreg to fpreg */
 921         tmp = load_reg(s, a->rt);
 922         neon_store_reg32(tmp, a->vm * 2);
 923         tcg_temp_free_i32(tmp);
 924         tmp = load_reg(s, a->rt2);
 925         neon_store_reg32(tmp, a->vm * 2 + 1);
 926         tcg_temp_free_i32(tmp);
 927     }
 928
 929     return true;
 930 }
 931
 932 static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
 933 {
 934     uint32_t offset;
 935     TCGv_i32 addr, tmp;
 936
 937     if (!vfp_access_check(s)) {
 938         return true;
 939     }
 940
 941     offset = a->imm << 2;
 942     if (!a->u) {
 943         offset = -offset;
 944     }
 945
 946     /* For thumb, use of PC is UNPREDICTABLE.  */
 947     addr = add_reg_for_lit(s, a->rn, offset);
 948     tmp = tcg_temp_new_i32();
 949     if (a->l) {
 950         gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 951         neon_store_reg32(tmp, a->vd);
 952     } else {
 953         neon_load_reg32(tmp, a->vd);
 954         gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 955     }
 956     tcg_temp_free_i32(tmp);
 957     tcg_temp_free_i32(addr);
 958
 959     return true;
 960 }
 961
 962 static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
 963 {
 964     uint32_t offset;
 965     TCGv_i32 addr;
 966     TCGv_i64 tmp;
 967
 968     /* UNDEF accesses to D16-D31 if they don't exist */
 969     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
 970         return false;
 971     }
 972
 973     if (!vfp_access_check(s)) {
 974         return true;
 975     }
 976
 977     offset = a->imm << 2;
 978     if (!a->u) {
 979         offset = -offset;
 980     }
 981
 982     /* For thumb, use of PC is UNPREDICTABLE.  */
 983     addr = add_reg_for_lit(s, a->rn, offset);
 984     tmp = tcg_temp_new_i64();
 985     if (a->l) {
 986         gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
 987         neon_store_reg64(tmp, a->vd);
 988     } else {
 989         neon_load_reg64(tmp, a->vd);
 990         gen_aa32_st64(s, tmp, addr, get_mem_index(s));
 991     }
 992     tcg_temp_free_i64(tmp);
 993     tcg_temp_free_i32(addr);
 994
 995     return true;
 996 }
 997
 998 static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
 999 {
1000     uint32_t offset;
1001     TCGv_i32 addr, tmp;
1002     int i, n;
1003
1004     n = a->imm;
1005
1006     if (n == 0 || (a->vd + n) > 32) {
1007         /*
1008          * UNPREDICTABLE cases for bad immediates: we choose to
1009          * UNDEF to avoid generating huge numbers of TCG ops
1010          */
1011         return false;
1012     }
1013     if (a->rn == 15 && a->w) {
1014         /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
1015         return false;
1016     }
1017
1018     if (!vfp_access_check(s)) {
1019         return true;
1020     }
1021
1022     /* For thumb, use of PC is UNPREDICTABLE.  */
1023     addr = add_reg_for_lit(s, a->rn, 0);
1024     if (a->p) {
1025         /* pre-decrement */
1026         tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
1027     }
1028
1029     if (s->v8m_stackcheck && a->rn == 13 && a->w) {
1030         /*
1031          * Here 'addr' is the lowest address we will store to,
1032          * and is either the old SP (if post-increment) or
1033          * the new SP (if pre-decrement). For post-increment
1034          * where the old value is below the limit and the new
1035          * value is above, it is UNKNOWN whether the limit check
1036          * triggers; we choose to trigger.
1037          */
1038         gen_helper_v8m_stackcheck(cpu_env, addr);
1039     }
1040
1041     offset = 4;
1042     tmp = tcg_temp_new_i32();
1043     for (i = 0; i < n; i++) {
1044         if (a->l) {
1045             /* load */
1046             gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
1047             neon_store_reg32(tmp, a->vd + i);
1048         } else {
1049             /* store */
1050             neon_load_reg32(tmp, a->vd + i);
1051             gen_aa32_st32(s, tmp, addr, get_mem_index(s));
1052         }
1053         tcg_gen_addi_i32(addr, addr, offset);
1054     }
1055     tcg_temp_free_i32(tmp);
1056     if (a->w) {
1057         /* writeback */
1058         if (a->p) {
1059             offset = -offset * n;
1060             tcg_gen_addi_i32(addr, addr, offset);
1061         }
1062         store_reg(s, a->rn, addr);
1063     } else {
1064         tcg_temp_free_i32(addr);
1065     }
1066
1067     return true;
1068 }
1069
1070 static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
1071 {
1072     uint32_t offset;
1073     TCGv_i32 addr;
1074     TCGv_i64 tmp;
1075     int i, n;
1076
1077     n = a->imm >> 1;
1078
1079     if (n == 0 || (a->vd + n) > 32 || n > 16) {
1080         /*
1081          * UNPREDICTABLE cases for bad immediates: we choose to
1082          * UNDEF to avoid generating huge numbers of TCG ops
1083          */
1084         return false;
1085     }
1086     if (a->rn == 15 && a->w) {
1087         /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
1088         return false;
1089     }
1090
1091     /* UNDEF accesses to D16-D31 if they don't exist */
1092     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) {
1093         return false;
1094     }
1095
1096     if (!vfp_access_check(s)) {
1097         return true;
1098     }
1099
1100     /* For thumb, use of PC is UNPREDICTABLE.  */
1101     addr = add_reg_for_lit(s, a->rn, 0);
1102     if (a->p) {
1103         /* pre-decrement */
1104         tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
1105     }
1106
1107     if (s->v8m_stackcheck && a->rn == 13 && a->w) {
1108         /*
1109          * Here 'addr' is the lowest address we will store to,
1110          * and is either the old SP (if post-increment) or
1111          * the new SP (if pre-decrement). For post-increment
1112          * where the old value is below the limit and the new
1113          * value is above, it is UNKNOWN whether the limit check
1114          * triggers; we choose to trigger.
1115          */
1116         gen_helper_v8m_stackcheck(cpu_env, addr);
1117     }
1118
1119     offset = 8;
1120     tmp = tcg_temp_new_i64();
1121     for (i = 0; i < n; i++) {
1122         if (a->l) {
1123             /* load */
1124             gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
1125             neon_store_reg64(tmp, a->vd + i);
1126         } else {
1127             /* store */
1128             neon_load_reg64(tmp, a->vd + i);
1129             gen_aa32_st64(s, tmp, addr, get_mem_index(s));
1130         }
1131         tcg_gen_addi_i32(addr, addr, offset);
1132     }
1133     tcg_temp_free_i64(tmp);
1134     if (a->w) {
1135         /* writeback */
1136         if (a->p) {
1137             offset = -offset * n;
1138         } else if (a->imm & 1) {
1139             offset = 4;
1140         } else {
1141             offset = 0;
1142         }
1143
1144         if (offset != 0) {
1145             tcg_gen_addi_i32(addr, addr, offset);
1146         }
1147         store_reg(s, a->rn, addr);
1148     } else {
1149         tcg_temp_free_i32(addr);
1150     }
1151
1152     return true;
1153 }
1154
1155 /*
1156  * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
1157  * The callback should emit code to write a value to vd. If
1158  * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
1159  * will contain the old value of the relevant VFP register;
1160  * otherwise it must be written to only.
1161  */
1162 typedef void VFPGen3OpSPFn(TCGv_i32 vd,
1163                            TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst);
1164 typedef void VFPGen3OpDPFn(TCGv_i64 vd,
1165                            TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst);
1166
1167 /*
1168  * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
1169  * The callback should emit code to write a value to vd (which
1170  * should be written to only).
1171  */
1172 typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm);
1173 typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm);
1174
1175 /*
1176  * Return true if the specified S reg is in a scalar bank
1177  * (ie if it is s0..s7)
1178  */
1179 static inline bool vfp_sreg_is_scalar(int reg)
1180 {
1181     return (reg & 0x18) == 0;
1182 }
1183
1184 /*
1185  * Return true if the specified D reg is in a scalar bank
1186  * (ie if it is d0..d3 or d16..d19)
1187  */
1188 static inline bool vfp_dreg_is_scalar(int reg)
1189 {
1190     return (reg & 0xc) == 0;
1191 }
1192
1193 /*
1194  * Advance the S reg number forwards by delta within its bank
1195  * (ie increment the low 3 bits but leave the rest the same)
1196  */
1197 static inline int vfp_advance_sreg(int reg, int delta)
1198 {
1199     return ((reg + delta) & 0x7) | (reg & ~0x7);
1200 }
1201
1202 /*
1203  * Advance the D reg number forwards by delta within its bank
1204  * (ie increment the low 2 bits but leave the rest the same)
1205  */
1206 static inline int vfp_advance_dreg(int reg, int delta)
1207 {
1208     return ((reg + delta) & 0x3) | (reg & ~0x3);
1209 }
1210
1211 /*
1212  * Perform a 3-operand VFP data processing instruction. fn is the
1213  * callback to do the actual operation; this function deals with the
1214  * code to handle looping around for VFP vector processing.
1215  */
1216 static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
1217                           int vd, int vn, int vm, bool reads_vd)
1218 {
1219     uint32_t delta_m = 0;
1220     uint32_t delta_d = 0;
1221     int veclen = s->vec_len;
1222     TCGv_i32 f0, f1, fd;
1223     TCGv_ptr fpst;
1224
1225     if (!dc_isar_feature(aa32_fpshvec, s) &&
1226         (veclen != 0 || s->vec_stride != 0)) {
1227         return false;
1228     }
1229
1230     if (!vfp_access_check(s)) {
1231         return true;
1232     }
1233
1234     if (veclen > 0) {
1235         /* Figure out what type of vector operation this is.  */
1236         if (vfp_sreg_is_scalar(vd)) {
1237             /* scalar */
1238             veclen = 0;
1239         } else {
1240             delta_d = s->vec_stride + 1;
1241
1242             if (vfp_sreg_is_scalar(vm)) {
1243                 /* mixed scalar/vector */
1244                 delta_m = 0;
1245             } else {
1246                 /* vector */
1247                 delta_m = delta_d;
1248             }
1249         }
1250     }
1251
1252     f0 = tcg_temp_new_i32();
1253     f1 = tcg_temp_new_i32();
1254     fd = tcg_temp_new_i32();
1255     fpst = get_fpstatus_ptr(0);
1256
1257     neon_load_reg32(f0, vn);
1258     neon_load_reg32(f1, vm);
1259
1260     for (;;) {
1261         if (reads_vd) {
1262             neon_load_reg32(fd, vd);
1263         }
1264         fn(fd, f0, f1, fpst);
1265         neon_store_reg32(fd, vd);
1266
1267         if (veclen == 0) {
1268             break;
1269         }
1270
1271         /* Set up the operands for the next iteration */
1272         veclen--;
1273         vd = vfp_advance_sreg(vd, delta_d);
1274         vn = vfp_advance_sreg(vn, delta_d);
1275         neon_load_reg32(f0, vn);
1276         if (delta_m) {
1277             vm = vfp_advance_sreg(vm, delta_m);
1278             neon_load_reg32(f1, vm);
1279         }
1280     }
1281
1282     tcg_temp_free_i32(f0);
1283     tcg_temp_free_i32(f1);
1284     tcg_temp_free_i32(fd);
1285     tcg_temp_free_ptr(fpst);
1286
1287     return true;
1288 }
1289
1290 static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
1291                           int vd, int vn, int vm, bool reads_vd)
1292 {
1293     uint32_t delta_m = 0;
1294     uint32_t delta_d = 0;
1295     int veclen = s->vec_len;
1296     TCGv_i64 f0, f1, fd;
1297     TCGv_ptr fpst;
1298
1299     /* UNDEF accesses to D16-D31 if they don't exist */
1300     if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) {
1301         return false;
1302     }
1303
1304     if (!dc_isar_feature(aa32_fpdp, s)) {
1305         return false;
1306     }
1307
1308     if (!dc_isar_feature(aa32_fpshvec, s) &&
1309         (veclen != 0 || s->vec_stride != 0)) {
1310         return false;
1311     }
1312
1313     if (!vfp_access_check(s)) {
1314         return true;
1315     }
1316
1317     if (veclen > 0) {
1318         /* Figure out what type of vector operation this is.  */
1319         if (vfp_dreg_is_scalar(vd)) {
1320             /* scalar */
1321             veclen = 0;
1322         } else {
1323             delta_d = (s->vec_stride >> 1) + 1;
1324
1325             if (vfp_dreg_is_scalar(vm)) {
1326                 /* mixed scalar/vector */
1327                 delta_m = 0;
1328             } else {
1329                 /* vector */
1330                 delta_m = delta_d;
1331             }
1332         }
1333     }
1334
1335     f0 = tcg_temp_new_i64();
1336     f1 = tcg_temp_new_i64();
1337     fd = tcg_temp_new_i64();
1338     fpst = get_fpstatus_ptr(0);
1339
1340     neon_load_reg64(f0, vn);
1341     neon_load_reg64(f1, vm);
1342
1343     for (;;) {
1344         if (reads_vd) {
1345             neon_load_reg64(fd, vd);
1346         }
1347         fn(fd, f0, f1, fpst);
1348         neon_store_reg64(fd, vd);
1349
1350         if (veclen == 0) {
1351             break;
1352         }
1353         /* Set up the operands for the next iteration */
1354         veclen--;
1355         vd = vfp_advance_dreg(vd, delta_d);
1356         vn = vfp_advance_dreg(vn, delta_d);
1357         neon_load_reg64(f0, vn);
1358         if (delta_m) {
1359             vm = vfp_advance_dreg(vm, delta_m);
1360             neon_load_reg64(f1, vm);
1361         }
1362     }
1363
1364     tcg_temp_free_i64(f0);
1365     tcg_temp_free_i64(f1);
1366     tcg_temp_free_i64(fd);
1367     tcg_temp_free_ptr(fpst);
1368
1369     return true;
1370 }
1371
1372 static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
1373 {
1374     uint32_t delta_m = 0;
1375     uint32_t delta_d = 0;
1376     int veclen = s->vec_len;
1377     TCGv_i32 f0, fd;
1378
1379     if (!dc_isar_feature(aa32_fpshvec, s) &&
1380         (veclen != 0 || s->vec_stride != 0)) {
1381         return false;
1382     }
1383
1384     if (!vfp_access_check(s)) {
1385         return true;
1386     }
1387
1388     if (veclen > 0) {
1389         /* Figure out what type of vector operation this is.  */
1390         if (vfp_sreg_is_scalar(vd)) {
1391             /* scalar */
1392             veclen = 0;
1393         } else {
1394             delta_d = s->vec_stride + 1;
1395
1396             if (vfp_sreg_is_scalar(vm)) {
1397                 /* mixed scalar/vector */
1398                 delta_m = 0;
1399             } else {
1400                 /* vector */
1401                 delta_m = delta_d;
1402             }
1403         }
1404     }
1405
1406     f0 = tcg_temp_new_i32();
1407     fd = tcg_temp_new_i32();
1408
1409     neon_load_reg32(f0, vm);
1410
1411     for (;;) {
1412         fn(fd, f0);
1413         neon_store_reg32(fd, vd);
1414
1415         if (veclen == 0) {
1416             break;
1417         }
1418
1419         if (delta_m == 0) {
1420             /* single source one-many */
1421             while (veclen--) {
1422                 vd = vfp_advance_sreg(vd, delta_d);
1423                 neon_store_reg32(fd, vd);
1424             }
1425             break;
1426         }
1427
1428         /* Set up the operands for the next iteration */
1429         veclen--;
1430         vd = vfp_advance_sreg(vd, delta_d);
1431         vm = vfp_advance_sreg(vm, delta_m);
1432         neon_load_reg32(f0, vm);
1433     }
1434
1435     tcg_temp_free_i32(f0);
1436     tcg_temp_free_i32(fd);
1437
1438     return true;
1439 }
1440
1441 static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
1442 {
1443     uint32_t delta_m = 0;
1444     uint32_t delta_d = 0;
1445     int veclen = s->vec_len;
1446     TCGv_i64 f0, fd;
1447
1448     /* UNDEF accesses to D16-D31 if they don't exist */
1449     if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) {
1450         return false;
1451     }
1452
1453     if (!dc_isar_feature(aa32_fpdp, s)) {
1454         return false;
1455     }
1456
1457     if (!dc_isar_feature(aa32_fpshvec, s) &&
1458         (veclen != 0 || s->vec_stride != 0)) {
1459         return false;
1460     }
1461
1462     if (!vfp_access_check(s)) {
1463         return true;
1464     }
1465
1466     if (veclen > 0) {
1467         /* Figure out what type of vector operation this is.  */
1468         if (vfp_dreg_is_scalar(vd)) {
1469             /* scalar */
1470             veclen = 0;
1471         } else {
1472             delta_d = (s->vec_stride >> 1) + 1;
1473
1474             if (vfp_dreg_is_scalar(vm)) {
1475                 /* mixed scalar/vector */
1476                 delta_m = 0;
1477             } else {
1478                 /* vector */
1479                 delta_m = delta_d;
1480             }
1481         }
1482     }
1483
1484     f0 = tcg_temp_new_i64();
1485     fd = tcg_temp_new_i64();
1486
1487     neon_load_reg64(f0, vm);
1488
1489     for (;;) {
1490         fn(fd, f0);
1491         neon_store_reg64(fd, vd);
1492
1493         if (veclen == 0) {
1494             break;
1495         }
1496
1497         if (delta_m == 0) {
1498             /* single source one-many */
1499             while (veclen--) {
1500                 vd = vfp_advance_dreg(vd, delta_d);
1501                 neon_store_reg64(fd, vd);
1502             }
1503             break;
1504         }
1505
1506         /* Set up the operands for the next iteration */
1507         veclen--;
1508         vd = vfp_advance_dreg(vd, delta_d);
1509         vd = vfp_advance_dreg(vm, delta_m);
1510         neon_load_reg64(f0, vm);
1511     }
1512
1513     tcg_temp_free_i64(f0);
1514     tcg_temp_free_i64(fd);
1515
1516     return true;
1517 }
1518
1519 static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
1520 {
1521     /* Note that order of inputs to the add matters for NaNs */
1522     TCGv_i32 tmp = tcg_temp_new_i32();
1523
1524     gen_helper_vfp_muls(tmp, vn, vm, fpst);
1525     gen_helper_vfp_adds(vd, vd, tmp, fpst);
1526     tcg_temp_free_i32(tmp);
1527 }
1528
1529 static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a)
1530 {
1531     return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true);
1532 }
1533
1534 static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
1535 {
1536     /* Note that order of inputs to the add matters for NaNs */
1537     TCGv_i64 tmp = tcg_temp_new_i64();
1538
1539     gen_helper_vfp_muld(tmp, vn, vm, fpst);
1540     gen_helper_vfp_addd(vd, vd, tmp, fpst);
1541     tcg_temp_free_i64(tmp);
1542 }
1543
1544 static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a)
1545 {
1546     return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true);
1547 }
1548
1549 static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
1550 {
1551     /*
1552      * VMLS: vd = vd + -(vn * vm)
1553      * Note that order of inputs to the add matters for NaNs.
1554      */
1555     TCGv_i32 tmp = tcg_temp_new_i32();
1556
1557     gen_helper_vfp_muls(tmp, vn, vm, fpst);
1558     gen_helper_vfp_negs(tmp, tmp);
1559     gen_helper_vfp_adds(vd, vd, tmp, fpst);
1560     tcg_temp_free_i32(tmp);
1561 }
1562
1563 static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a)
1564 {
1565     return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true);
1566 }
1567
1568 static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
1569 {
1570     /*
1571      * VMLS: vd = vd + -(vn * vm)
1572      * Note that order of inputs to the add matters for NaNs.
1573      */
1574     TCGv_i64 tmp = tcg_temp_new_i64();
1575
1576     gen_helper_vfp_muld(tmp, vn, vm, fpst);
1577     gen_helper_vfp_negd(tmp, tmp);
1578     gen_helper_vfp_addd(vd, vd, tmp, fpst);
1579     tcg_temp_free_i64(tmp);
1580 }
1581
1582 static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a)
1583 {
1584     return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true);
1585 }
1586
1587 static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
1588 {
1589     /*
1590      * VNMLS: -fd + (fn * fm)
1591      * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1592      * plausible looking simplifications because this will give wrong results
1593      * for NaNs.
1594      */
1595     TCGv_i32 tmp = tcg_temp_new_i32();
1596
1597     gen_helper_vfp_muls(tmp, vn, vm, fpst);
1598     gen_helper_vfp_negs(vd, vd);
1599     gen_helper_vfp_adds(vd, vd, tmp, fpst);
1600     tcg_temp_free_i32(tmp);
1601 }
1602
1603 static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a)
1604 {
1605     return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true);
1606 }
1607
1608 static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
1609 {
1610     /*
1611      * VNMLS: -fd + (fn * fm)
1612      * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1613      * plausible looking simplifications because this will give wrong results
1614      * for NaNs.
1615      */
1616     TCGv_i64 tmp = tcg_temp_new_i64();
1617
1618     gen_helper_vfp_muld(tmp, vn, vm, fpst);
1619     gen_helper_vfp_negd(vd, vd);
1620     gen_helper_vfp_addd(vd, vd, tmp, fpst);
1621     tcg_temp_free_i64(tmp);
1622 }
1623
1624 static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a)
1625 {
1626     return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
1627 }
1628
1629 static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
1630 {
1631     /* VNMLA: -fd + -(fn * fm) */
1632     TCGv_i32 tmp = tcg_temp_new_i32();
1633
1634     gen_helper_vfp_muls(tmp, vn, vm, fpst);
1635     gen_helper_vfp_negs(tmp, tmp);
1636     gen_helper_vfp_negs(vd, vd);
1637     gen_helper_vfp_adds(vd, vd, tmp, fpst);
1638     tcg_temp_free_i32(tmp);
1639 }
1640
1641 static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a)
1642 {
1643     return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true);
1644 }
1645
1646 static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
1647 {
1648     /* VNMLA: -fd + (fn * fm) */
1649     TCGv_i64 tmp = tcg_temp_new_i64();
1650
1651     gen_helper_vfp_muld(tmp, vn, vm, fpst);
1652     gen_helper_vfp_negd(tmp, tmp);
1653     gen_helper_vfp_negd(vd, vd);
1654     gen_helper_vfp_addd(vd, vd, tmp, fpst);
1655     tcg_temp_free_i64(tmp);
1656 }
1657
1658 static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a)
1659 {
1660     return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
1661 }
1662
1663 static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a)
1664 {
1665     return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false);
1666 }
1667
1668 static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a)
1669 {
1670     return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false);
1671 }
1672
1673 static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
1674 {
1675     /* VNMUL: -(fn * fm) */
1676     gen_helper_vfp_muls(vd, vn, vm, fpst);
1677     gen_helper_vfp_negs(vd, vd);
1678 }
1679
1680 static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a)
1681 {
1682     return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false);
1683 }
1684
1685 static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
1686 {
1687     /* VNMUL: -(fn * fm) */
1688     gen_helper_vfp_muld(vd, vn, vm, fpst);
1689     gen_helper_vfp_negd(vd, vd);
1690 }
1691
1692 static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a)
1693 {
1694     return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false);
1695 }
1696
1697 static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a)
1698 {
1699     return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false);
1700 }
1701
1702 static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a)
1703 {
1704     return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false);
1705 }
1706
1707 static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a)
1708 {
1709     return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false);
1710 }
1711
1712 static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a)
1713 {
1714     return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false);
1715 }
1716
1717 static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a)
1718 {
1719     return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false);
1720 }
1721
1722 static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
1723 {
1724     return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
1725 }
1726
1727 static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
1728 {
1729     /*
1730      * VFNMA : fd = muladd(-fd,  fn, fm)
1731      * VFNMS : fd = muladd(-fd, -fn, fm)
1732      * VFMA  : fd = muladd( fd,  fn, fm)
1733      * VFMS  : fd = muladd( fd, -fn, fm)
1734      *
1735      * These are fused multiply-add, and must be done as one floating
1736      * point operation with no rounding between the multiplication and
1737      * addition steps.  NB that doing the negations here as separate
1738      * steps is correct : an input NaN should come out with its sign
1739      * bit flipped if it is a negated-input.
1740      */
1741     TCGv_ptr fpst;
1742     TCGv_i32 vn, vm, vd;
1743
1744     /*
1745      * Present in VFPv4 only.
1746      * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
1747      * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
1748      */
1749     if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
1750         (s->vec_len != 0 || s->vec_stride != 0)) {
1751         return false;
1752     }
1753
1754     if (!vfp_access_check(s)) {
1755         return true;
1756     }
1757
1758     vn = tcg_temp_new_i32();
1759     vm = tcg_temp_new_i32();
1760     vd = tcg_temp_new_i32();
1761
1762     neon_load_reg32(vn, a->vn);
1763     neon_load_reg32(vm, a->vm);
1764     if (a->o2) {
1765         /* VFNMS, VFMS */
1766         gen_helper_vfp_negs(vn, vn);
1767     }
1768     neon_load_reg32(vd, a->vd);
1769     if (a->o1 & 1) {
1770         /* VFNMA, VFNMS */
1771         gen_helper_vfp_negs(vd, vd);
1772     }
1773     fpst = get_fpstatus_ptr(0);
1774     gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
1775     neon_store_reg32(vd, a->vd);
1776
1777     tcg_temp_free_ptr(fpst);
1778     tcg_temp_free_i32(vn);
1779     tcg_temp_free_i32(vm);
1780     tcg_temp_free_i32(vd);
1781
1782     return true;
1783 }
1784
1785 static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
1786 {
1787     /*
1788      * VFNMA : fd = muladd(-fd,  fn, fm)
1789      * VFNMS : fd = muladd(-fd, -fn, fm)
1790      * VFMA  : fd = muladd( fd,  fn, fm)
1791      * VFMS  : fd = muladd( fd, -fn, fm)
1792      *
1793      * These are fused multiply-add, and must be done as one floating
1794      * point operation with no rounding between the multiplication and
1795      * addition steps.  NB that doing the negations here as separate
1796      * steps is correct : an input NaN should come out with its sign
1797      * bit flipped if it is a negated-input.
1798      */
1799     TCGv_ptr fpst;
1800     TCGv_i64 vn, vm, vd;
1801
1802     /*
1803      * Present in VFPv4 only.
1804      * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
1805      * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
1806      */
1807     if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
1808         (s->vec_len != 0 || s->vec_stride != 0)) {
1809         return false;
1810     }
1811
1812     /* UNDEF accesses to D16-D31 if they don't exist. */
1813     if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x10)) {
1814         return false;
1815     }
1816
1817     if (!dc_isar_feature(aa32_fpdp, s)) {
1818         return false;
1819     }
1820
1821     if (!vfp_access_check(s)) {
1822         return true;
1823     }
1824
1825     vn = tcg_temp_new_i64();
1826     vm = tcg_temp_new_i64();
1827     vd = tcg_temp_new_i64();
1828
1829     neon_load_reg64(vn, a->vn);
1830     neon_load_reg64(vm, a->vm);
1831     if (a->o2) {
1832         /* VFNMS, VFMS */
1833         gen_helper_vfp_negd(vn, vn);
1834     }
1835     neon_load_reg64(vd, a->vd);
1836     if (a->o1 & 1) {
1837         /* VFNMA, VFNMS */
1838         gen_helper_vfp_negd(vd, vd);
1839     }
1840     fpst = get_fpstatus_ptr(0);
1841     gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
1842     neon_store_reg64(vd, a->vd);
1843
1844     tcg_temp_free_ptr(fpst);
1845     tcg_temp_free_i64(vn);
1846     tcg_temp_free_i64(vm);
1847     tcg_temp_free_i64(vd);
1848
1849     return true;
1850 }
1851
1852 static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
1853 {
1854     uint32_t delta_d = 0;
1855     int veclen = s->vec_len;
1856     TCGv_i32 fd;
1857     uint32_t vd;
1858
1859     vd = a->vd;
1860
1861     if (!dc_isar_feature(aa32_fpshvec, s) &&
1862         (veclen != 0 || s->vec_stride != 0)) {
1863         return false;
1864     }
1865
1866     if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
1867         return false;
1868     }
1869
1870     if (!vfp_access_check(s)) {
1871         return true;
1872     }
1873
1874     if (veclen > 0) {
1875         /* Figure out what type of vector operation this is.  */
1876         if (vfp_sreg_is_scalar(vd)) {
1877             /* scalar */
1878             veclen = 0;
1879         } else {
1880             delta_d = s->vec_stride + 1;
1881         }
1882     }
1883
1884     fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
1885
1886     for (;;) {
1887         neon_store_reg32(fd, vd);
1888
1889         if (veclen == 0) {
1890             break;
1891         }
1892
1893         /* Set up the operands for the next iteration */
1894         veclen--;
1895         vd = vfp_advance_sreg(vd, delta_d);
1896     }
1897
1898     tcg_temp_free_i32(fd);
1899     return true;
1900 }
1901
1902 static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
1903 {
1904     uint32_t delta_d = 0;
1905     int veclen = s->vec_len;
1906     TCGv_i64 fd;
1907     uint32_t vd;
1908
1909     vd = a->vd;
1910
1911     /* UNDEF accesses to D16-D31 if they don't exist. */
1912     if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) {
1913         return false;
1914     }
1915
1916     if (!dc_isar_feature(aa32_fpdp, s)) {
1917         return false;
1918     }
1919
1920     if (!dc_isar_feature(aa32_fpshvec, s) &&
1921         (veclen != 0 || s->vec_stride != 0)) {
1922         return false;
1923     }
1924
1925     if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
1926         return false;
1927     }
1928
1929     if (!vfp_access_check(s)) {
1930         return true;
1931     }
1932
1933     if (veclen > 0) {
1934         /* Figure out what type of vector operation this is.  */
1935         if (vfp_dreg_is_scalar(vd)) {
1936             /* scalar */
1937             veclen = 0;
1938         } else {
1939             delta_d = (s->vec_stride >> 1) + 1;
1940         }
1941     }
1942
1943     fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
1944
1945     for (;;) {
1946         neon_store_reg64(fd, vd);
1947
1948         if (veclen == 0) {
1949             break;
1950         }
1951
1952         /* Set up the operands for the next iteration */
1953         veclen--;
1954         vd = vfp_advance_dreg(vd, delta_d);
1955     }
1956
1957     tcg_temp_free_i64(fd);
1958     return true;
1959 }
1960
1961 static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a)
1962 {
1963     return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm);
1964 }
1965
1966 static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a)
1967 {
1968     return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm);
1969 }
1970
1971 static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
1972 {
1973     return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
1974 }
1975
1976 static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a)
1977 {
1978     return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
1979 }
1980
1981 static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a)
1982 {
1983     return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm);
1984 }
1985
1986 static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
1987 {
1988     return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
1989 }
1990
1991 static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
1992 {
1993     gen_helper_vfp_sqrts(vd, vm, cpu_env);
1994 }
1995
1996 static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a)
1997 {
1998     return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm);
1999 }
2000
2001 static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
2002 {
2003     gen_helper_vfp_sqrtd(vd, vm, cpu_env);
2004 }
2005
2006 static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a)
2007 {
2008     return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm);
2009 }
2010
2011 static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
2012 {
2013     TCGv_i32 vd, vm;
2014
2015     /* Vm/M bits must be zero for the Z variant */
2016     if (a->z && a->vm != 0) {
2017         return false;
2018     }
2019
2020     if (!vfp_access_check(s)) {
2021         return true;
2022     }
2023
2024     vd = tcg_temp_new_i32();
2025     vm = tcg_temp_new_i32();
2026
2027     neon_load_reg32(vd, a->vd);
2028     if (a->z) {
2029         tcg_gen_movi_i32(vm, 0);
2030     } else {
2031         neon_load_reg32(vm, a->vm);
2032     }
2033
2034     if (a->e) {
2035         gen_helper_vfp_cmpes(vd, vm, cpu_env);
2036     } else {
2037         gen_helper_vfp_cmps(vd, vm, cpu_env);
2038     }
2039
2040     tcg_temp_free_i32(vd);
2041     tcg_temp_free_i32(vm);
2042
2043     return true;
2044 }
2045
2046 static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
2047 {
2048     TCGv_i64 vd, vm;
2049
2050     /* Vm/M bits must be zero for the Z variant */
2051     if (a->z && a->vm != 0) {
2052         return false;
2053     }
2054
2055     /* UNDEF accesses to D16-D31 if they don't exist. */
2056     if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
2057         return false;
2058     }
2059
2060     if (!dc_isar_feature(aa32_fpdp, s)) {
2061         return false;
2062     }
2063
2064     if (!vfp_access_check(s)) {
2065         return true;
2066     }
2067
2068     vd = tcg_temp_new_i64();
2069     vm = tcg_temp_new_i64();
2070
2071     neon_load_reg64(vd, a->vd);
2072     if (a->z) {
2073         tcg_gen_movi_i64(vm, 0);
2074     } else {
2075         neon_load_reg64(vm, a->vm);
2076     }
2077
2078     if (a->e) {
2079         gen_helper_vfp_cmped(vd, vm, cpu_env);
2080     } else {
2081         gen_helper_vfp_cmpd(vd, vm, cpu_env);
2082     }
2083
2084     tcg_temp_free_i64(vd);
2085     tcg_temp_free_i64(vm);
2086
2087     return true;
2088 }
2089
2090 static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
2091 {
2092     TCGv_ptr fpst;
2093     TCGv_i32 ahp_mode;
2094     TCGv_i32 tmp;
2095
2096     if (!dc_isar_feature(aa32_fp16_spconv, s)) {
2097         return false;
2098     }
2099
2100     if (!vfp_access_check(s)) {
2101         return true;
2102     }
2103
2104     fpst = get_fpstatus_ptr(false);
2105     ahp_mode = get_ahp_flag();
2106     tmp = tcg_temp_new_i32();
2107     /* The T bit tells us if we want the low or high 16 bits of Vm */
2108     tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
2109     gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
2110     neon_store_reg32(tmp, a->vd);
2111     tcg_temp_free_i32(ahp_mode);
2112     tcg_temp_free_ptr(fpst);
2113     tcg_temp_free_i32(tmp);
2114     return true;
2115 }
2116
2117 static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
2118 {
2119     TCGv_ptr fpst;
2120     TCGv_i32 ahp_mode;
2121     TCGv_i32 tmp;
2122     TCGv_i64 vd;
2123
2124     if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
2125         return false;
2126     }
2127
2128     /* UNDEF accesses to D16-D31 if they don't exist. */
2129     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd  & 0x10)) {
2130         return false;
2131     }
2132
2133     if (!dc_isar_feature(aa32_fpdp, s)) {
2134         return false;
2135     }
2136
2137     if (!vfp_access_check(s)) {
2138         return true;
2139     }
2140
2141     fpst = get_fpstatus_ptr(false);
2142     ahp_mode = get_ahp_flag();
2143     tmp = tcg_temp_new_i32();
2144     /* The T bit tells us if we want the low or high 16 bits of Vm */
2145     tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
2146     vd = tcg_temp_new_i64();
2147     gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
2148     neon_store_reg64(vd, a->vd);
2149     tcg_temp_free_i32(ahp_mode);
2150     tcg_temp_free_ptr(fpst);
2151     tcg_temp_free_i32(tmp);
2152     tcg_temp_free_i64(vd);
2153     return true;
2154 }
2155
2156 static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
2157 {
2158     TCGv_ptr fpst;
2159     TCGv_i32 ahp_mode;
2160     TCGv_i32 tmp;
2161
2162     if (!dc_isar_feature(aa32_fp16_spconv, s)) {
2163         return false;
2164     }
2165
2166     if (!vfp_access_check(s)) {
2167         return true;
2168     }
2169
2170     fpst = get_fpstatus_ptr(false);
2171     ahp_mode = get_ahp_flag();
2172     tmp = tcg_temp_new_i32();
2173
2174     neon_load_reg32(tmp, a->vm);
2175     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
2176     tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
2177     tcg_temp_free_i32(ahp_mode);
2178     tcg_temp_free_ptr(fpst);
2179     tcg_temp_free_i32(tmp);
2180     return true;
2181 }
2182
2183 static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
2184 {
2185     TCGv_ptr fpst;
2186     TCGv_i32 ahp_mode;
2187     TCGv_i32 tmp;
2188     TCGv_i64 vm;
2189
2190     if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
2191         return false;
2192     }
2193
2194     /* UNDEF accesses to D16-D31 if they don't exist. */
2195     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm  & 0x10)) {
2196         return false;
2197     }
2198
2199     if (!dc_isar_feature(aa32_fpdp, s)) {
2200         return false;
2201     }
2202
2203     if (!vfp_access_check(s)) {
2204         return true;
2205     }
2206
2207     fpst = get_fpstatus_ptr(false);
2208     ahp_mode = get_ahp_flag();
2209     tmp = tcg_temp_new_i32();
2210     vm = tcg_temp_new_i64();
2211
2212     neon_load_reg64(vm, a->vm);
2213     gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
2214     tcg_temp_free_i64(vm);
2215     tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
2216     tcg_temp_free_i32(ahp_mode);
2217     tcg_temp_free_ptr(fpst);
2218     tcg_temp_free_i32(tmp);
2219     return true;
2220 }
2221
2222 static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
2223 {
2224     TCGv_ptr fpst;
2225     TCGv_i32 tmp;
2226
2227     if (!dc_isar_feature(aa32_vrint, s)) {
2228         return false;
2229     }
2230
2231     if (!vfp_access_check(s)) {
2232         return true;
2233     }
2234
2235     tmp = tcg_temp_new_i32();
2236     neon_load_reg32(tmp, a->vm);
2237     fpst = get_fpstatus_ptr(false);
2238     gen_helper_rints(tmp, tmp, fpst);
2239     neon_store_reg32(tmp, a->vd);
2240     tcg_temp_free_ptr(fpst);
2241     tcg_temp_free_i32(tmp);
2242     return true;
2243 }
2244
2245 static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
2246 {
2247     TCGv_ptr fpst;
2248     TCGv_i64 tmp;
2249
2250     if (!dc_isar_feature(aa32_vrint, s)) {
2251         return false;
2252     }
2253
2254     /* UNDEF accesses to D16-D31 if they don't exist. */
2255     if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
2256         return false;
2257     }
2258
2259     if (!dc_isar_feature(aa32_fpdp, s)) {
2260         return false;
2261     }
2262
2263     if (!vfp_access_check(s)) {
2264         return true;
2265     }
2266
2267     tmp = tcg_temp_new_i64();
2268     neon_load_reg64(tmp, a->vm);
2269     fpst = get_fpstatus_ptr(false);
2270     gen_helper_rintd(tmp, tmp, fpst);
2271     neon_store_reg64(tmp, a->vd);
2272     tcg_temp_free_ptr(fpst);
2273     tcg_temp_free_i64(tmp);
2274     return true;
2275 }
2276
2277 static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
2278 {
2279     TCGv_ptr fpst;
2280     TCGv_i32 tmp;
2281     TCGv_i32 tcg_rmode;
2282
2283     if (!dc_isar_feature(aa32_vrint, s)) {
2284         return false;
2285     }
2286
2287     if (!vfp_access_check(s)) {
2288         return true;
2289     }
2290
2291     tmp = tcg_temp_new_i32();
2292     neon_load_reg32(tmp, a->vm);
2293     fpst = get_fpstatus_ptr(false);
2294     tcg_rmode = tcg_const_i32(float_round_to_zero);
2295     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
2296     gen_helper_rints(tmp, tmp, fpst);
2297     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
2298     neon_store_reg32(tmp, a->vd);
2299     tcg_temp_free_ptr(fpst);
2300     tcg_temp_free_i32(tcg_rmode);
2301     tcg_temp_free_i32(tmp);
2302     return true;
2303 }
2304
2305 static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
2306 {
2307     TCGv_ptr fpst;
2308     TCGv_i64 tmp;
2309     TCGv_i32 tcg_rmode;
2310
2311     if (!dc_isar_feature(aa32_vrint, s)) {
2312         return false;
2313     }
2314
2315     /* UNDEF accesses to D16-D31 if they don't exist. */
2316     if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
2317         return false;
2318     }
2319
2320     if (!dc_isar_feature(aa32_fpdp, s)) {
2321         return false;
2322     }
2323
2324     if (!vfp_access_check(s)) {
2325         return true;
2326     }
2327
2328     tmp = tcg_temp_new_i64();
2329     neon_load_reg64(tmp, a->vm);
2330     fpst = get_fpstatus_ptr(false);
2331     tcg_rmode = tcg_const_i32(float_round_to_zero);
2332     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
2333     gen_helper_rintd(tmp, tmp, fpst);
2334     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
2335     neon_store_reg64(tmp, a->vd);
2336     tcg_temp_free_ptr(fpst);
2337     tcg_temp_free_i64(tmp);
2338     tcg_temp_free_i32(tcg_rmode);
2339     return true;
2340 }
2341
2342 static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
2343 {
2344     TCGv_ptr fpst;
2345     TCGv_i32 tmp;
2346
2347     if (!dc_isar_feature(aa32_vrint, s)) {
2348         return false;
2349     }
2350
2351     if (!vfp_access_check(s)) {
2352         return true;
2353     }
2354
2355     tmp = tcg_temp_new_i32();
2356     neon_load_reg32(tmp, a->vm);
2357     fpst = get_fpstatus_ptr(false);
2358     gen_helper_rints_exact(tmp, tmp, fpst);
2359     neon_store_reg32(tmp, a->vd);
2360     tcg_temp_free_ptr(fpst);
2361     tcg_temp_free_i32(tmp);
2362     return true;
2363 }
2364
2365 static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
2366 {
2367     TCGv_ptr fpst;
2368     TCGv_i64 tmp;
2369
2370     if (!dc_isar_feature(aa32_vrint, s)) {
2371         return false;
2372     }
2373
2374     /* UNDEF accesses to D16-D31 if they don't exist. */
2375     if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
2376         return false;
2377     }
2378
2379     if (!dc_isar_feature(aa32_fpdp, s)) {
2380         return false;
2381     }
2382
2383     if (!vfp_access_check(s)) {
2384         return true;
2385     }
2386
2387     tmp = tcg_temp_new_i64();
2388     neon_load_reg64(tmp, a->vm);
2389     fpst = get_fpstatus_ptr(false);
2390     gen_helper_rintd_exact(tmp, tmp, fpst);
2391     neon_store_reg64(tmp, a->vd);
2392     tcg_temp_free_ptr(fpst);
2393     tcg_temp_free_i64(tmp);
2394     return true;
2395 }
2396
2397 static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
2398 {
2399     TCGv_i64 vd;
2400     TCGv_i32 vm;
2401
2402     /* UNDEF accesses to D16-D31 if they don't exist. */
2403     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
2404         return false;
2405     }
2406
2407     if (!dc_isar_feature(aa32_fpdp, s)) {
2408         return false;
2409     }
2410
2411     if (!vfp_access_check(s)) {
2412         return true;
2413     }
2414
2415     vm = tcg_temp_new_i32();
2416     vd = tcg_temp_new_i64();
2417     neon_load_reg32(vm, a->vm);
2418     gen_helper_vfp_fcvtds(vd, vm, cpu_env);
2419     neon_store_reg64(vd, a->vd);
2420     tcg_temp_free_i32(vm);
2421     tcg_temp_free_i64(vd);
2422     return true;
2423 }
2424
2425 static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
2426 {
2427     TCGv_i64 vm;
2428     TCGv_i32 vd;
2429
2430     /* UNDEF accesses to D16-D31 if they don't exist. */
2431     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
2432         return false;
2433     }
2434
2435     if (!dc_isar_feature(aa32_fpdp, s)) {
2436         return false;
2437     }
2438
2439     if (!vfp_access_check(s)) {
2440         return true;
2441     }
2442
2443     vd = tcg_temp_new_i32();
2444     vm = tcg_temp_new_i64();
2445     neon_load_reg64(vm, a->vm);
2446     gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
2447     neon_store_reg32(vd, a->vd);
2448     tcg_temp_free_i32(vd);
2449     tcg_temp_free_i64(vm);
2450     return true;
2451 }
2452
2453 static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
2454 {
2455     TCGv_i32 vm;
2456     TCGv_ptr fpst;
2457
2458     if (!vfp_access_check(s)) {
2459         return true;
2460     }
2461
2462     vm = tcg_temp_new_i32();
2463     neon_load_reg32(vm, a->vm);
2464     fpst = get_fpstatus_ptr(false);
2465     if (a->s) {
2466         /* i32 -> f32 */
2467         gen_helper_vfp_sitos(vm, vm, fpst);
2468     } else {
2469         /* u32 -> f32 */
2470         gen_helper_vfp_uitos(vm, vm, fpst);
2471     }
2472     neon_store_reg32(vm, a->vd);
2473     tcg_temp_free_i32(vm);
2474     tcg_temp_free_ptr(fpst);
2475     return true;
2476 }
2477
2478 static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
2479 {
2480     TCGv_i32 vm;
2481     TCGv_i64 vd;
2482     TCGv_ptr fpst;
2483
2484     /* UNDEF accesses to D16-D31 if they don't exist. */
2485     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
2486         return false;
2487     }
2488
2489     if (!dc_isar_feature(aa32_fpdp, s)) {
2490         return false;
2491     }
2492
2493     if (!vfp_access_check(s)) {
2494         return true;
2495     }
2496
2497     vm = tcg_temp_new_i32();
2498     vd = tcg_temp_new_i64();
2499     neon_load_reg32(vm, a->vm);
2500     fpst = get_fpstatus_ptr(false);
2501     if (a->s) {
2502         /* i32 -> f64 */
2503         gen_helper_vfp_sitod(vd, vm, fpst);
2504     } else {
2505         /* u32 -> f64 */
2506         gen_helper_vfp_uitod(vd, vm, fpst);
2507     }
2508     neon_store_reg64(vd, a->vd);
2509     tcg_temp_free_i32(vm);
2510     tcg_temp_free_i64(vd);
2511     tcg_temp_free_ptr(fpst);
2512     return true;
2513 }
2514
2515 static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
2516 {
2517     TCGv_i32 vd;
2518     TCGv_i64 vm;
2519
2520     if (!dc_isar_feature(aa32_jscvt, s)) {
2521         return false;
2522     }
2523
2524     /* UNDEF accesses to D16-D31 if they don't exist. */
2525     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
2526         return false;
2527     }
2528
2529     if (!dc_isar_feature(aa32_fpdp, s)) {
2530         return false;
2531     }
2532
2533     if (!vfp_access_check(s)) {
2534         return true;
2535     }
2536
2537     vm = tcg_temp_new_i64();
2538     vd = tcg_temp_new_i32();
2539     neon_load_reg64(vm, a->vm);
2540     gen_helper_vjcvt(vd, vm, cpu_env);
2541     neon_store_reg32(vd, a->vd);
2542     tcg_temp_free_i64(vm);
2543     tcg_temp_free_i32(vd);
2544     return true;
2545 }
2546
2547 static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
2548 {
2549     TCGv_i32 vd, shift;
2550     TCGv_ptr fpst;
2551     int frac_bits;
2552
2553     if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
2554         return false;
2555     }
2556
2557     if (!vfp_access_check(s)) {
2558         return true;
2559     }
2560
2561     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
2562
2563     vd = tcg_temp_new_i32();
2564     neon_load_reg32(vd, a->vd);
2565
2566     fpst = get_fpstatus_ptr(false);
2567     shift = tcg_const_i32(frac_bits);
2568
2569     /* Switch on op:U:sx bits */
2570     switch (a->opc) {
2571     case 0:
2572         gen_helper_vfp_shtos(vd, vd, shift, fpst);
2573         break;
2574     case 1:
2575         gen_helper_vfp_sltos(vd, vd, shift, fpst);
2576         break;
2577     case 2:
2578         gen_helper_vfp_uhtos(vd, vd, shift, fpst);
2579         break;
2580     case 3:
2581         gen_helper_vfp_ultos(vd, vd, shift, fpst);
2582         break;
2583     case 4:
2584         gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst);
2585         break;
2586     case 5:
2587         gen_helper_vfp_tosls_round_to_zero(vd, vd, shift, fpst);
2588         break;
2589     case 6:
2590         gen_helper_vfp_touhs_round_to_zero(vd, vd, shift, fpst);
2591         break;
2592     case 7:
2593         gen_helper_vfp_touls_round_to_zero(vd, vd, shift, fpst);
2594         break;
2595     default:
2596         g_assert_not_reached();
2597     }
2598
2599     neon_store_reg32(vd, a->vd);
2600     tcg_temp_free_i32(vd);
2601     tcg_temp_free_i32(shift);
2602     tcg_temp_free_ptr(fpst);
2603     return true;
2604 }
2605
2606 static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
2607 {
2608     TCGv_i64 vd;
2609     TCGv_i32 shift;
2610     TCGv_ptr fpst;
2611     int frac_bits;
2612
2613     if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
2614         return false;
2615     }
2616
2617     /* UNDEF accesses to D16-D31 if they don't exist. */
2618     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
2619         return false;
2620     }
2621
2622     if (!dc_isar_feature(aa32_fpdp, s)) {
2623         return false;
2624     }
2625
2626     if (!vfp_access_check(s)) {
2627         return true;
2628     }
2629
2630     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
2631
2632     vd = tcg_temp_new_i64();
2633     neon_load_reg64(vd, a->vd);
2634
2635     fpst = get_fpstatus_ptr(false);
2636     shift = tcg_const_i32(frac_bits);
2637
2638     /* Switch on op:U:sx bits */
2639     switch (a->opc) {
2640     case 0:
2641         gen_helper_vfp_shtod(vd, vd, shift, fpst);
2642         break;
2643     case 1:
2644         gen_helper_vfp_sltod(vd, vd, shift, fpst);
2645         break;
2646     case 2:
2647         gen_helper_vfp_uhtod(vd, vd, shift, fpst);
2648         break;
2649     case 3:
2650         gen_helper_vfp_ultod(vd, vd, shift, fpst);
2651         break;
2652     case 4:
2653         gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst);
2654         break;
2655     case 5:
2656         gen_helper_vfp_tosld_round_to_zero(vd, vd, shift, fpst);
2657         break;
2658     case 6:
2659         gen_helper_vfp_touhd_round_to_zero(vd, vd, shift, fpst);
2660         break;
2661     case 7:
2662         gen_helper_vfp_tould_round_to_zero(vd, vd, shift, fpst);
2663         break;
2664     default:
2665         g_assert_not_reached();
2666     }
2667
2668     neon_store_reg64(vd, a->vd);
2669     tcg_temp_free_i64(vd);
2670     tcg_temp_free_i32(shift);
2671     tcg_temp_free_ptr(fpst);
2672     return true;
2673 }
2674
2675 static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
2676 {
2677     TCGv_i32 vm;
2678     TCGv_ptr fpst;
2679
2680     if (!vfp_access_check(s)) {
2681         return true;
2682     }
2683
2684     fpst = get_fpstatus_ptr(false);
2685     vm = tcg_temp_new_i32();
2686     neon_load_reg32(vm, a->vm);
2687
2688     if (a->s) {
2689         if (a->rz) {
2690             gen_helper_vfp_tosizs(vm, vm, fpst);
2691         } else {
2692             gen_helper_vfp_tosis(vm, vm, fpst);
2693         }
2694     } else {
2695         if (a->rz) {
2696             gen_helper_vfp_touizs(vm, vm, fpst);
2697         } else {
2698             gen_helper_vfp_touis(vm, vm, fpst);
2699         }
2700     }
2701     neon_store_reg32(vm, a->vd);
2702     tcg_temp_free_i32(vm);
2703     tcg_temp_free_ptr(fpst);
2704     return true;
2705 }
2706
2707 static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
2708 {
2709     TCGv_i32 vd;
2710     TCGv_i64 vm;
2711     TCGv_ptr fpst;
2712
2713     /* UNDEF accesses to D16-D31 if they don't exist. */
2714     if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
2715         return false;
2716     }
2717
2718     if (!dc_isar_feature(aa32_fpdp, s)) {
2719         return false;
2720     }
2721
2722     if (!vfp_access_check(s)) {
2723         return true;
2724     }
2725
2726     fpst = get_fpstatus_ptr(false);
2727     vm = tcg_temp_new_i64();
2728     vd = tcg_temp_new_i32();
2729     neon_load_reg64(vm, a->vm);
2730
2731     if (a->s) {
2732         if (a->rz) {
2733             gen_helper_vfp_tosizd(vd, vm, fpst);
2734         } else {
2735             gen_helper_vfp_tosid(vd, vm, fpst);
2736         }
2737     } else {
2738         if (a->rz) {
2739             gen_helper_vfp_touizd(vd, vm, fpst);
2740         } else {
2741             gen_helper_vfp_touid(vd, vm, fpst);
2742         }
2743     }
2744     neon_store_reg32(vd, a->vd);
2745     tcg_temp_free_i32(vd);
2746     tcg_temp_free_i64(vm);
2747     tcg_temp_free_ptr(fpst);
2748     return true;
2749 }