4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/kvm.h"
28 #include "qemu/range.h"
29 #include "qapi/qapi-commands-machine-target.h"
30 #include "qapi/error.h"
31 #include "qemu/guest-random.h"
34 #include "exec/cpu_ldst.h"
37 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
39 #ifndef CONFIG_USER_ONLY
41 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
42 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
43 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
44 target_ulong
*page_size_ptr
,
45 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
48 static void switch_mode(CPUARMState
*env
, int mode
);
50 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
54 /* VFP data registers are always little-endian. */
55 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
57 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
60 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
61 /* Aliases for Q regs. */
64 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
66 stq_le_p(buf
+ 8, q
[1]);
70 switch (reg
- nregs
) {
71 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
72 case 1: stl_p(buf
, vfp_get_fpscr(env
)); return 4;
73 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
78 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
84 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
87 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
90 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
92 q
[1] = ldq_le_p(buf
+ 8);
96 switch (reg
- nregs
) {
97 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
98 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
99 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
104 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
108 /* 128 bit FP register */
110 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
112 stq_le_p(buf
+ 8, q
[1]);
117 stl_p(buf
, vfp_get_fpsr(env
));
121 stl_p(buf
, vfp_get_fpcr(env
));
128 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
132 /* 128 bit FP register */
134 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
135 q
[0] = ldq_le_p(buf
);
136 q
[1] = ldq_le_p(buf
+ 8);
141 vfp_set_fpsr(env
, ldl_p(buf
));
145 vfp_set_fpcr(env
, ldl_p(buf
));
152 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
154 assert(ri
->fieldoffset
);
155 if (cpreg_field_is_64bit(ri
)) {
156 return CPREG_FIELD64(env
, ri
);
158 return CPREG_FIELD32(env
, ri
);
162 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
165 assert(ri
->fieldoffset
);
166 if (cpreg_field_is_64bit(ri
)) {
167 CPREG_FIELD64(env
, ri
) = value
;
169 CPREG_FIELD32(env
, ri
) = value
;
173 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
175 return (char *)env
+ ri
->fieldoffset
;
178 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
180 /* Raw read of a coprocessor register (as needed for migration, etc). */
181 if (ri
->type
& ARM_CP_CONST
) {
182 return ri
->resetvalue
;
183 } else if (ri
->raw_readfn
) {
184 return ri
->raw_readfn(env
, ri
);
185 } else if (ri
->readfn
) {
186 return ri
->readfn(env
, ri
);
188 return raw_read(env
, ri
);
192 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
195 /* Raw write of a coprocessor register (as needed for migration, etc).
196 * Note that constant registers are treated as write-ignored; the
197 * caller should check for success by whether a readback gives the
200 if (ri
->type
& ARM_CP_CONST
) {
202 } else if (ri
->raw_writefn
) {
203 ri
->raw_writefn(env
, ri
, v
);
204 } else if (ri
->writefn
) {
205 ri
->writefn(env
, ri
, v
);
207 raw_write(env
, ri
, v
);
211 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
213 ARMCPU
*cpu
= env_archcpu(env
);
214 const ARMCPRegInfo
*ri
;
217 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
218 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
220 if (cpreg_field_is_64bit(ri
)) {
221 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
223 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
229 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
234 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
236 /* Return true if the regdef would cause an assertion if you called
237 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
238 * program bug for it not to have the NO_RAW flag).
239 * NB that returning false here doesn't necessarily mean that calling
240 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
241 * read/write access functions which are safe for raw use" from "has
242 * read/write access functions which have side effects but has forgotten
243 * to provide raw access functions".
244 * The tests here line up with the conditions in read/write_raw_cp_reg()
245 * and assertions in raw_read()/raw_write().
247 if ((ri
->type
& ARM_CP_CONST
) ||
249 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
255 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
257 /* Write the coprocessor state from cpu->env to the (index,value) list. */
261 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
262 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
263 const ARMCPRegInfo
*ri
;
266 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
271 if (ri
->type
& ARM_CP_NO_RAW
) {
275 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
278 * Only sync if the previous list->cpustate sync succeeded.
279 * Rather than tracking the success/failure state for every
280 * item in the list, we just recheck "does the raw write we must
281 * have made in write_list_to_cpustate() read back OK" here.
283 uint64_t oldval
= cpu
->cpreg_values
[i
];
285 if (oldval
== newval
) {
289 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
290 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
294 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
296 cpu
->cpreg_values
[i
] = newval
;
301 bool write_list_to_cpustate(ARMCPU
*cpu
)
306 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
307 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
308 uint64_t v
= cpu
->cpreg_values
[i
];
309 const ARMCPRegInfo
*ri
;
311 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
316 if (ri
->type
& ARM_CP_NO_RAW
) {
319 /* Write value and confirm it reads back as written
320 * (to catch read-only registers and partially read-only
321 * registers where the incoming migration value doesn't match)
323 write_raw_cp_reg(&cpu
->env
, ri
, v
);
324 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
331 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
333 ARMCPU
*cpu
= opaque
;
335 const ARMCPRegInfo
*ri
;
337 regidx
= *(uint32_t *)key
;
338 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
340 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
341 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
342 /* The value array need not be initialized at this point */
343 cpu
->cpreg_array_len
++;
347 static void count_cpreg(gpointer key
, gpointer opaque
)
349 ARMCPU
*cpu
= opaque
;
351 const ARMCPRegInfo
*ri
;
353 regidx
= *(uint32_t *)key
;
354 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
356 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
357 cpu
->cpreg_array_len
++;
361 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
363 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
364 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
375 void init_cpreg_list(ARMCPU
*cpu
)
377 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
378 * Note that we require cpreg_tuples[] to be sorted by key ID.
383 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
384 keys
= g_list_sort(keys
, cpreg_key_compare
);
386 cpu
->cpreg_array_len
= 0;
388 g_list_foreach(keys
, count_cpreg
, cpu
);
390 arraylen
= cpu
->cpreg_array_len
;
391 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
392 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
393 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
394 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
395 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
396 cpu
->cpreg_array_len
= 0;
398 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
400 assert(cpu
->cpreg_array_len
== arraylen
);
406 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
407 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
409 * access_el3_aa32ns: Used to check AArch32 register views.
410 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
412 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
413 const ARMCPRegInfo
*ri
,
416 bool secure
= arm_is_secure_below_el3(env
);
418 assert(!arm_el_is_aa64(env
, 3));
420 return CP_ACCESS_TRAP_UNCATEGORIZED
;
425 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
426 const ARMCPRegInfo
*ri
,
429 if (!arm_el_is_aa64(env
, 3)) {
430 return access_el3_aa32ns(env
, ri
, isread
);
435 /* Some secure-only AArch32 registers trap to EL3 if used from
436 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
437 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
438 * We assume that the .access field is set to PL1_RW.
440 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
441 const ARMCPRegInfo
*ri
,
444 if (arm_current_el(env
) == 3) {
447 if (arm_is_secure_below_el3(env
)) {
448 return CP_ACCESS_TRAP_EL3
;
450 /* This will be EL1 NS and EL2 NS, which just UNDEF */
451 return CP_ACCESS_TRAP_UNCATEGORIZED
;
454 /* Check for traps to "powerdown debug" registers, which are controlled
457 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 int el
= arm_current_el(env
);
461 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
462 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
463 (arm_hcr_el2_eff(env
) & HCR_TGE
);
465 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
466 return CP_ACCESS_TRAP_EL2
;
468 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
469 return CP_ACCESS_TRAP_EL3
;
474 /* Check for traps to "debug ROM" registers, which are controlled
475 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
477 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
480 int el
= arm_current_el(env
);
481 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
482 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
483 (arm_hcr_el2_eff(env
) & HCR_TGE
);
485 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
486 return CP_ACCESS_TRAP_EL2
;
488 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
489 return CP_ACCESS_TRAP_EL3
;
494 /* Check for traps to general debug registers, which are controlled
495 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
497 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
500 int el
= arm_current_el(env
);
501 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
502 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
503 (arm_hcr_el2_eff(env
) & HCR_TGE
);
505 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
506 return CP_ACCESS_TRAP_EL2
;
508 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
509 return CP_ACCESS_TRAP_EL3
;
514 /* Check for traps to performance monitor registers, which are controlled
515 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
517 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
520 int el
= arm_current_el(env
);
522 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
523 && !arm_is_secure_below_el3(env
)) {
524 return CP_ACCESS_TRAP_EL2
;
526 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
527 return CP_ACCESS_TRAP_EL3
;
532 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
534 ARMCPU
*cpu
= env_archcpu(env
);
536 raw_write(env
, ri
, value
);
537 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
540 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
542 ARMCPU
*cpu
= env_archcpu(env
);
544 if (raw_read(env
, ri
) != value
) {
545 /* Unlike real hardware the qemu TLB uses virtual addresses,
546 * not modified virtual addresses, so this causes a TLB flush.
549 raw_write(env
, ri
, value
);
553 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 ARMCPU
*cpu
= env_archcpu(env
);
558 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
559 && !extended_addresses_enabled(env
)) {
560 /* For VMSA (when not using the LPAE long descriptor page table
561 * format) this register includes the ASID, so do a TLB flush.
562 * For PMSA it is purely a process ID and no action is needed.
566 raw_write(env
, ri
, value
);
569 /* IS variants of TLB operations must affect all cores */
570 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
573 CPUState
*cs
= env_cpu(env
);
575 tlb_flush_all_cpus_synced(cs
);
578 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
581 CPUState
*cs
= env_cpu(env
);
583 tlb_flush_all_cpus_synced(cs
);
586 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
589 CPUState
*cs
= env_cpu(env
);
591 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
594 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= env_cpu(env
);
599 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
603 * Non-IS variants of TLB operations are upgraded to
604 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
605 * force broadcast of these operations.
607 static bool tlb_force_broadcast(CPUARMState
*env
)
609 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
610 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
613 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 /* Invalidate all (TLBIALL) */
617 ARMCPU
*cpu
= env_archcpu(env
);
619 if (tlb_force_broadcast(env
)) {
620 tlbiall_is_write(env
, NULL
, value
);
627 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
630 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
631 ARMCPU
*cpu
= env_archcpu(env
);
633 if (tlb_force_broadcast(env
)) {
634 tlbimva_is_write(env
, NULL
, value
);
638 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
641 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
644 /* Invalidate by ASID (TLBIASID) */
645 ARMCPU
*cpu
= env_archcpu(env
);
647 if (tlb_force_broadcast(env
)) {
648 tlbiasid_is_write(env
, NULL
, value
);
655 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
658 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
659 ARMCPU
*cpu
= env_archcpu(env
);
661 if (tlb_force_broadcast(env
)) {
662 tlbimvaa_is_write(env
, NULL
, value
);
666 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
669 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
672 CPUState
*cs
= env_cpu(env
);
674 tlb_flush_by_mmuidx(cs
,
675 ARMMMUIdxBit_S12NSE1
|
676 ARMMMUIdxBit_S12NSE0
|
680 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
683 CPUState
*cs
= env_cpu(env
);
685 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
686 ARMMMUIdxBit_S12NSE1
|
687 ARMMMUIdxBit_S12NSE0
|
691 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
694 /* Invalidate by IPA. This has to invalidate any structures that
695 * contain only stage 2 translation information, but does not need
696 * to apply to structures that contain combined stage 1 and stage 2
697 * translation information.
698 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
700 CPUState
*cs
= env_cpu(env
);
703 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
707 pageaddr
= sextract64(value
<< 12, 0, 40);
709 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
712 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
715 CPUState
*cs
= env_cpu(env
);
718 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
722 pageaddr
= sextract64(value
<< 12, 0, 40);
724 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
728 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
731 CPUState
*cs
= env_cpu(env
);
733 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
736 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
739 CPUState
*cs
= env_cpu(env
);
741 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
744 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
747 CPUState
*cs
= env_cpu(env
);
748 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
750 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
753 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
756 CPUState
*cs
= env_cpu(env
);
757 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
759 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
763 static const ARMCPRegInfo cp_reginfo
[] = {
764 /* Define the secure and non-secure FCSE identifier CP registers
765 * separately because there is no secure bank in V8 (no _EL3). This allows
766 * the secure register to be properly reset and migrated. There is also no
767 * v8 EL1 version of the register so the non-secure instance stands alone.
770 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
771 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
772 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
773 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
774 { .name
= "FCSEIDR_S",
775 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
776 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
777 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
778 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
779 /* Define the secure and non-secure context identifier CP registers
780 * separately because there is no secure bank in V8 (no _EL3). This allows
781 * the secure register to be properly reset and migrated. In the
782 * non-secure case, the 32-bit register will have reset and migration
783 * disabled during registration as it is handled by the 64-bit instance.
785 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
786 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
787 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
788 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
789 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
790 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
791 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
792 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
793 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
794 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
798 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
799 /* NB: Some of these registers exist in v8 but with more precise
800 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
802 /* MMU Domain access control / MPU write buffer control */
804 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
805 .access
= PL1_RW
, .resetvalue
= 0,
806 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
807 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
808 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
809 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
810 * For v6 and v5, these mappings are overly broad.
812 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
813 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
814 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
815 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
816 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
817 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
818 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
819 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
820 /* Cache maintenance ops; some of this space may be overridden later. */
821 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
822 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
823 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
827 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
828 /* Not all pre-v6 cores implemented this WFI, so this is slightly
831 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
832 .access
= PL1_W
, .type
= ARM_CP_WFI
},
836 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
837 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
838 * is UNPREDICTABLE; we choose to NOP as most implementations do).
840 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
841 .access
= PL1_W
, .type
= ARM_CP_WFI
},
842 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
843 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
844 * OMAPCP will override this space.
846 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
847 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
849 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
850 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
852 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
853 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
854 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
856 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
857 * implementing it as RAZ means the "debug architecture version" bits
858 * will read as a reserved value, which should cause Linux to not try
859 * to use the debug hardware.
861 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
862 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
863 /* MMU TLB control. Note that the wildcarding means we cover not just
864 * the unified TLB ops but also the dside/iside/inner-shareable variants.
866 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
867 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
868 .type
= ARM_CP_NO_RAW
},
869 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
870 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
871 .type
= ARM_CP_NO_RAW
},
872 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
873 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
874 .type
= ARM_CP_NO_RAW
},
875 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
876 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
877 .type
= ARM_CP_NO_RAW
},
878 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
879 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
880 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
881 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
885 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
890 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
891 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
892 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
893 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
894 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
896 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
897 /* VFP coprocessor: cp10 & cp11 [23:20] */
898 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
900 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
901 /* ASEDIS [31] bit is RAO/WI */
905 /* VFPv3 and upwards with NEON implement 32 double precision
906 * registers (D0-D31).
908 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
909 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
910 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
918 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
919 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
921 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
922 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
923 value
&= ~(0xf << 20);
924 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
927 env
->cp15
.cpacr_el1
= value
;
930 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
933 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
934 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
936 uint64_t value
= env
->cp15
.cpacr_el1
;
938 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
939 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
940 value
&= ~(0xf << 20);
946 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 /* Call cpacr_write() so that we reset with the correct RAO bits set
949 * for our CPU features.
951 cpacr_write(env
, ri
, 0);
954 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
957 if (arm_feature(env
, ARM_FEATURE_V8
)) {
958 /* Check if CPACR accesses are to be trapped to EL2 */
959 if (arm_current_el(env
) == 1 &&
960 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
961 return CP_ACCESS_TRAP_EL2
;
962 /* Check if CPACR accesses are to be trapped to EL3 */
963 } else if (arm_current_el(env
) < 3 &&
964 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
965 return CP_ACCESS_TRAP_EL3
;
972 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
975 /* Check if CPTR accesses are set to trap to EL3 */
976 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
977 return CP_ACCESS_TRAP_EL3
;
983 static const ARMCPRegInfo v6_cp_reginfo
[] = {
984 /* prefetch by MVA in v6, NOP in v7 */
985 { .name
= "MVA_prefetch",
986 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
987 .access
= PL1_W
, .type
= ARM_CP_NOP
},
988 /* We need to break the TB after ISB to execute self-modifying code
989 * correctly and also to take any pending interrupts immediately.
990 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
992 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
993 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
994 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
995 .access
= PL0_W
, .type
= ARM_CP_NOP
},
996 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
997 .access
= PL0_W
, .type
= ARM_CP_NOP
},
998 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1001 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1003 /* Watchpoint Fault Address Register : should actually only be present
1004 * for 1136, 1176, 11MPCore.
1006 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1007 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1008 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1009 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1010 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1011 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1015 /* Definitions for the PMU registers */
1016 #define PMCRN_MASK 0xf800
1017 #define PMCRN_SHIFT 11
1025 #define PMXEVTYPER_P 0x80000000
1026 #define PMXEVTYPER_U 0x40000000
1027 #define PMXEVTYPER_NSK 0x20000000
1028 #define PMXEVTYPER_NSU 0x10000000
1029 #define PMXEVTYPER_NSH 0x08000000
1030 #define PMXEVTYPER_M 0x04000000
1031 #define PMXEVTYPER_MT 0x02000000
1032 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1033 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1034 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1035 PMXEVTYPER_M | PMXEVTYPER_MT | \
1036 PMXEVTYPER_EVTCOUNT)
1038 #define PMCCFILTR 0xf8000000
1039 #define PMCCFILTR_M PMXEVTYPER_M
1040 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1042 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1044 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1047 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1048 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1050 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1053 typedef struct pm_event
{
1054 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1055 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1056 bool (*supported
)(CPUARMState
*);
1058 * Retrieve the current count of the underlying event. The programmed
1059 * counters hold a difference from the return value from this function
1061 uint64_t (*get_count
)(CPUARMState
*);
1063 * Return how many nanoseconds it will take (at a minimum) for count events
1064 * to occur. A negative value indicates the counter will never overflow, or
1065 * that the counter has otherwise arranged for the overflow bit to be set
1066 * and the PMU interrupt to be raised on overflow.
1068 int64_t (*ns_per_count
)(uint64_t);
1071 static bool event_always_supported(CPUARMState
*env
)
1076 static uint64_t swinc_get_count(CPUARMState
*env
)
1079 * SW_INCR events are written directly to the pmevcntr's by writes to
1080 * PMSWINC, so there is no underlying count maintained by the PMU itself
1085 static int64_t swinc_ns_per(uint64_t ignored
)
1091 * Return the underlying cycle count for the PMU cycle counters. If we're in
1092 * usermode, simply return 0.
1094 static uint64_t cycles_get_count(CPUARMState
*env
)
1096 #ifndef CONFIG_USER_ONLY
1097 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1098 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1100 return cpu_get_host_ticks();
1104 #ifndef CONFIG_USER_ONLY
1105 static int64_t cycles_ns_per(uint64_t cycles
)
1107 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1110 static bool instructions_supported(CPUARMState
*env
)
1112 return use_icount
== 1 /* Precise instruction counting */;
1115 static uint64_t instructions_get_count(CPUARMState
*env
)
1117 return (uint64_t)cpu_get_icount_raw();
1120 static int64_t instructions_ns_per(uint64_t icount
)
1122 return cpu_icount_to_ns((int64_t)icount
);
1126 static const pm_event pm_events
[] = {
1127 { .number
= 0x000, /* SW_INCR */
1128 .supported
= event_always_supported
,
1129 .get_count
= swinc_get_count
,
1130 .ns_per_count
= swinc_ns_per
,
1132 #ifndef CONFIG_USER_ONLY
1133 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1134 .supported
= instructions_supported
,
1135 .get_count
= instructions_get_count
,
1136 .ns_per_count
= instructions_ns_per
,
1138 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1139 .supported
= event_always_supported
,
1140 .get_count
= cycles_get_count
,
1141 .ns_per_count
= cycles_ns_per
,
1147 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1148 * events (i.e. the statistical profiling extension), this implementation
1149 * should first be updated to something sparse instead of the current
1150 * supported_event_map[] array.
1152 #define MAX_EVENT_ID 0x11
1153 #define UNSUPPORTED_EVENT UINT16_MAX
1154 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1157 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1158 * of ARM event numbers to indices in our pm_events array.
1160 * Note: Events in the 0x40XX range are not currently supported.
1162 void pmu_init(ARMCPU
*cpu
)
1167 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1170 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1171 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1176 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1177 const pm_event
*cnt
= &pm_events
[i
];
1178 assert(cnt
->number
<= MAX_EVENT_ID
);
1179 /* We do not currently support events in the 0x40xx range */
1180 assert(cnt
->number
<= 0x3f);
1182 if (cnt
->supported(&cpu
->env
)) {
1183 supported_event_map
[cnt
->number
] = i
;
1184 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1185 if (cnt
->number
& 0x20) {
1186 cpu
->pmceid1
|= event_mask
;
1188 cpu
->pmceid0
|= event_mask
;
1195 * Check at runtime whether a PMU event is supported for the current machine
1197 static bool event_supported(uint16_t number
)
1199 if (number
> MAX_EVENT_ID
) {
1202 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1205 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1208 /* Performance monitor registers user accessibility is controlled
1209 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1210 * trapping to EL2 or EL3 for other accesses.
1212 int el
= arm_current_el(env
);
1214 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1215 return CP_ACCESS_TRAP
;
1217 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1218 && !arm_is_secure_below_el3(env
)) {
1219 return CP_ACCESS_TRAP_EL2
;
1221 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1222 return CP_ACCESS_TRAP_EL3
;
1225 return CP_ACCESS_OK
;
1228 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1229 const ARMCPRegInfo
*ri
,
1232 /* ER: event counter read trap control */
1233 if (arm_feature(env
, ARM_FEATURE_V8
)
1234 && arm_current_el(env
) == 0
1235 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1237 return CP_ACCESS_OK
;
1240 return pmreg_access(env
, ri
, isread
);
1243 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1244 const ARMCPRegInfo
*ri
,
1247 /* SW: software increment write trap control */
1248 if (arm_feature(env
, ARM_FEATURE_V8
)
1249 && arm_current_el(env
) == 0
1250 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1252 return CP_ACCESS_OK
;
1255 return pmreg_access(env
, ri
, isread
);
1258 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1259 const ARMCPRegInfo
*ri
,
1262 /* ER: event counter read trap control */
1263 if (arm_feature(env
, ARM_FEATURE_V8
)
1264 && arm_current_el(env
) == 0
1265 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1266 return CP_ACCESS_OK
;
1269 return pmreg_access(env
, ri
, isread
);
1272 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1273 const ARMCPRegInfo
*ri
,
1276 /* CR: cycle counter read trap control */
1277 if (arm_feature(env
, ARM_FEATURE_V8
)
1278 && arm_current_el(env
) == 0
1279 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1281 return CP_ACCESS_OK
;
1284 return pmreg_access(env
, ri
, isread
);
1287 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1288 * the current EL, security state, and register configuration.
1290 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1293 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1294 bool enabled
, prohibited
, filtered
;
1295 bool secure
= arm_is_secure(env
);
1296 int el
= arm_current_el(env
);
1297 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1299 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1303 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1304 (counter
< hpmn
|| counter
== 31)) {
1305 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1307 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1309 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1312 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1313 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1318 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1319 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1322 if (prohibited
&& counter
== 31) {
1323 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1326 if (counter
== 31) {
1327 filter
= env
->cp15
.pmccfiltr_el0
;
1329 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1332 p
= filter
& PMXEVTYPER_P
;
1333 u
= filter
& PMXEVTYPER_U
;
1334 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1335 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1336 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1337 m
= arm_el_is_aa64(env
, 1) &&
1338 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1341 filtered
= secure
? u
: u
!= nsu
;
1342 } else if (el
== 1) {
1343 filtered
= secure
? p
: p
!= nsk
;
1344 } else if (el
== 2) {
1350 if (counter
!= 31) {
1352 * If not checking PMCCNTR, ensure the counter is setup to an event we
1355 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1356 if (!event_supported(event
)) {
1361 return enabled
&& !prohibited
&& !filtered
;
1364 static void pmu_update_irq(CPUARMState
*env
)
1366 ARMCPU
*cpu
= env_archcpu(env
);
1367 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1368 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1372 * Ensure c15_ccnt is the guest-visible count so that operations such as
1373 * enabling/disabling the counter or filtering, modifying the count itself,
1374 * etc. can be done logically. This is essentially a no-op if the counter is
1375 * not enabled at the time of the call.
1377 static void pmccntr_op_start(CPUARMState
*env
)
1379 uint64_t cycles
= cycles_get_count(env
);
1381 if (pmu_counter_enabled(env
, 31)) {
1382 uint64_t eff_cycles
= cycles
;
1383 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1384 /* Increment once every 64 processor clock cycles */
1388 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1390 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1391 1ull << 63 : 1ull << 31;
1392 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1393 env
->cp15
.c9_pmovsr
|= (1 << 31);
1394 pmu_update_irq(env
);
1397 env
->cp15
.c15_ccnt
= new_pmccntr
;
1399 env
->cp15
.c15_ccnt_delta
= cycles
;
1403 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1404 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1407 static void pmccntr_op_finish(CPUARMState
*env
)
1409 if (pmu_counter_enabled(env
, 31)) {
1410 #ifndef CONFIG_USER_ONLY
1411 /* Calculate when the counter will next overflow */
1412 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1413 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1414 remaining_cycles
= (uint32_t)remaining_cycles
;
1416 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1418 if (overflow_in
> 0) {
1419 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1421 ARMCPU
*cpu
= env_archcpu(env
);
1422 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1426 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1427 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1428 /* Increment once every 64 processor clock cycles */
1431 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1435 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1438 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1440 if (event_supported(event
)) {
1441 uint16_t event_idx
= supported_event_map
[event
];
1442 count
= pm_events
[event_idx
].get_count(env
);
1445 if (pmu_counter_enabled(env
, counter
)) {
1446 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1448 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1449 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1450 pmu_update_irq(env
);
1452 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1454 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1457 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1459 if (pmu_counter_enabled(env
, counter
)) {
1460 #ifndef CONFIG_USER_ONLY
1461 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1462 uint16_t event_idx
= supported_event_map
[event
];
1463 uint64_t delta
= UINT32_MAX
-
1464 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1465 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1467 if (overflow_in
> 0) {
1468 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1470 ARMCPU
*cpu
= env_archcpu(env
);
1471 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1475 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1476 env
->cp15
.c14_pmevcntr
[counter
];
1480 void pmu_op_start(CPUARMState
*env
)
1483 pmccntr_op_start(env
);
1484 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1485 pmevcntr_op_start(env
, i
);
1489 void pmu_op_finish(CPUARMState
*env
)
1492 pmccntr_op_finish(env
);
1493 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1494 pmevcntr_op_finish(env
, i
);
1498 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1500 pmu_op_start(&cpu
->env
);
1503 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1505 pmu_op_finish(&cpu
->env
);
1508 void arm_pmu_timer_cb(void *opaque
)
1510 ARMCPU
*cpu
= opaque
;
1513 * Update all the counter values based on the current underlying counts,
1514 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1515 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1516 * counter may expire.
1518 pmu_op_start(&cpu
->env
);
1519 pmu_op_finish(&cpu
->env
);
1522 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1527 if (value
& PMCRC
) {
1528 /* The counter has been reset */
1529 env
->cp15
.c15_ccnt
= 0;
1532 if (value
& PMCRP
) {
1534 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1535 env
->cp15
.c14_pmevcntr
[i
] = 0;
1539 /* only the DP, X, D and E bits are writable */
1540 env
->cp15
.c9_pmcr
&= ~0x39;
1541 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1546 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1550 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1551 /* Increment a counter's count iff: */
1552 if ((value
& (1 << i
)) && /* counter's bit is set */
1553 /* counter is enabled and not filtered */
1554 pmu_counter_enabled(env
, i
) &&
1555 /* counter is SW_INCR */
1556 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1557 pmevcntr_op_start(env
, i
);
1560 * Detect if this write causes an overflow since we can't predict
1561 * PMSWINC overflows like we can for other events
1563 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1565 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1566 env
->cp15
.c9_pmovsr
|= (1 << i
);
1567 pmu_update_irq(env
);
1570 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1572 pmevcntr_op_finish(env
, i
);
1577 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1580 pmccntr_op_start(env
);
1581 ret
= env
->cp15
.c15_ccnt
;
1582 pmccntr_op_finish(env
);
1586 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1589 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1590 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1591 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1594 env
->cp15
.c9_pmselr
= value
& 0x1f;
1597 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1600 pmccntr_op_start(env
);
1601 env
->cp15
.c15_ccnt
= value
;
1602 pmccntr_op_finish(env
);
1605 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1608 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1610 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1613 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1616 pmccntr_op_start(env
);
1617 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1618 pmccntr_op_finish(env
);
1621 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1624 pmccntr_op_start(env
);
1625 /* M is not accessible from AArch32 */
1626 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1627 (value
& PMCCFILTR
);
1628 pmccntr_op_finish(env
);
1631 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1633 /* M is not visible in AArch32 */
1634 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1637 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1640 value
&= pmu_counter_mask(env
);
1641 env
->cp15
.c9_pmcnten
|= value
;
1644 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1647 value
&= pmu_counter_mask(env
);
1648 env
->cp15
.c9_pmcnten
&= ~value
;
1651 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1654 value
&= pmu_counter_mask(env
);
1655 env
->cp15
.c9_pmovsr
&= ~value
;
1656 pmu_update_irq(env
);
1659 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1662 value
&= pmu_counter_mask(env
);
1663 env
->cp15
.c9_pmovsr
|= value
;
1664 pmu_update_irq(env
);
1667 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1668 uint64_t value
, const uint8_t counter
)
1670 if (counter
== 31) {
1671 pmccfiltr_write(env
, ri
, value
);
1672 } else if (counter
< pmu_num_counters(env
)) {
1673 pmevcntr_op_start(env
, counter
);
1676 * If this counter's event type is changing, store the current
1677 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1678 * pmevcntr_op_finish has the correct baseline when it converts back to
1681 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1682 PMXEVTYPER_EVTCOUNT
;
1683 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1684 if (old_event
!= new_event
) {
1686 if (event_supported(new_event
)) {
1687 uint16_t event_idx
= supported_event_map
[new_event
];
1688 count
= pm_events
[event_idx
].get_count(env
);
1690 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1693 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1694 pmevcntr_op_finish(env
, counter
);
1696 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1697 * PMSELR value is equal to or greater than the number of implemented
1698 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1702 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1703 const uint8_t counter
)
1705 if (counter
== 31) {
1706 return env
->cp15
.pmccfiltr_el0
;
1707 } else if (counter
< pmu_num_counters(env
)) {
1708 return env
->cp15
.c14_pmevtyper
[counter
];
1711 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1712 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1718 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1721 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1722 pmevtyper_write(env
, ri
, value
, counter
);
1725 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1729 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1732 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1733 * pmu_op_finish calls when loading saved state for a migration. Because
1734 * we're potentially updating the type of event here, the value written to
1735 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1736 * different counter type. Therefore, we need to set this value to the
1737 * current count for the counter type we're writing so that pmu_op_finish
1738 * has the correct count for its calculation.
1740 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1741 if (event_supported(event
)) {
1742 uint16_t event_idx
= supported_event_map
[event
];
1743 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1744 pm_events
[event_idx
].get_count(env
);
1748 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1750 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1751 return pmevtyper_read(env
, ri
, counter
);
1754 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1757 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1760 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1762 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1765 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1766 uint64_t value
, uint8_t counter
)
1768 if (counter
< pmu_num_counters(env
)) {
1769 pmevcntr_op_start(env
, counter
);
1770 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1771 pmevcntr_op_finish(env
, counter
);
1774 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1775 * are CONSTRAINED UNPREDICTABLE.
1779 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1782 if (counter
< pmu_num_counters(env
)) {
1784 pmevcntr_op_start(env
, counter
);
1785 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1786 pmevcntr_op_finish(env
, counter
);
1789 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1790 * are CONSTRAINED UNPREDICTABLE. */
1795 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1798 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1799 pmevcntr_write(env
, ri
, value
, counter
);
1802 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1804 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1805 return pmevcntr_read(env
, ri
, counter
);
1808 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1812 assert(counter
< pmu_num_counters(env
));
1813 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1814 pmevcntr_write(env
, ri
, value
, counter
);
1817 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1819 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1820 assert(counter
< pmu_num_counters(env
));
1821 return env
->cp15
.c14_pmevcntr
[counter
];
1824 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1827 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1830 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1832 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1835 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1838 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1839 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1841 env
->cp15
.c9_pmuserenr
= value
& 1;
1845 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1848 /* We have no event counters so only the C bit can be changed */
1849 value
&= pmu_counter_mask(env
);
1850 env
->cp15
.c9_pminten
|= value
;
1851 pmu_update_irq(env
);
1854 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1857 value
&= pmu_counter_mask(env
);
1858 env
->cp15
.c9_pminten
&= ~value
;
1859 pmu_update_irq(env
);
1862 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1865 /* Note that even though the AArch64 view of this register has bits
1866 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1867 * architectural requirements for bits which are RES0 only in some
1868 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1869 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1871 raw_write(env
, ri
, value
& ~0x1FULL
);
1874 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1876 /* Begin with base v8.0 state. */
1877 uint32_t valid_mask
= 0x3fff;
1878 ARMCPU
*cpu
= env_archcpu(env
);
1880 if (arm_el_is_aa64(env
, 3)) {
1881 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1882 valid_mask
&= ~SCR_NET
;
1884 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1887 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1888 valid_mask
&= ~SCR_HCE
;
1890 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1891 * supported if EL2 exists. The bit is UNK/SBZP when
1892 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1893 * when EL2 is unavailable.
1894 * On ARMv8, this bit is always available.
1896 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1897 !arm_feature(env
, ARM_FEATURE_V8
)) {
1898 valid_mask
&= ~SCR_SMD
;
1901 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1902 valid_mask
|= SCR_TLOR
;
1904 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1905 valid_mask
|= SCR_API
| SCR_APK
;
1908 /* Clear all-context RES0 bits. */
1909 value
&= valid_mask
;
1910 raw_write(env
, ri
, value
);
1913 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1915 ARMCPU
*cpu
= env_archcpu(env
);
1917 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1920 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1921 ri
->secure
& ARM_CP_SECSTATE_S
);
1923 return cpu
->ccsidr
[index
];
1926 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1929 raw_write(env
, ri
, value
& 0xf);
1932 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1934 CPUState
*cs
= env_cpu(env
);
1935 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
1937 bool allow_virt
= (arm_current_el(env
) == 1 &&
1938 (!arm_is_secure_below_el3(env
) ||
1939 (env
->cp15
.scr_el3
& SCR_EEL2
)));
1941 if (allow_virt
&& (hcr_el2
& HCR_IMO
)) {
1942 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1946 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1951 if (allow_virt
&& (hcr_el2
& HCR_FMO
)) {
1952 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1956 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1961 /* External aborts are not possible in QEMU so A bit is always clear */
1965 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1966 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1967 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1968 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1969 /* Performance monitors are implementation defined in v7,
1970 * but with an ARM recommended set of registers, which we
1973 * Performance registers fall into three categories:
1974 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1975 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1976 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1977 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1978 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1980 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1981 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1982 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1983 .writefn
= pmcntenset_write
,
1984 .accessfn
= pmreg_access
,
1985 .raw_writefn
= raw_write
},
1986 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1987 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1988 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1989 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1990 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1991 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1993 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1994 .accessfn
= pmreg_access
,
1995 .writefn
= pmcntenclr_write
,
1996 .type
= ARM_CP_ALIAS
},
1997 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1998 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1999 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2000 .type
= ARM_CP_ALIAS
,
2001 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2002 .writefn
= pmcntenclr_write
},
2003 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2004 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2005 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2006 .accessfn
= pmreg_access
,
2007 .writefn
= pmovsr_write
,
2008 .raw_writefn
= raw_write
},
2009 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2010 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2011 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2012 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2013 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2014 .writefn
= pmovsr_write
,
2015 .raw_writefn
= raw_write
},
2016 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2017 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2018 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2019 .writefn
= pmswinc_write
},
2020 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2021 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2022 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2023 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2024 .writefn
= pmswinc_write
},
2025 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2026 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2027 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2028 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2029 .raw_writefn
= raw_write
},
2030 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2031 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2032 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2033 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2034 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2035 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2036 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2037 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2038 .accessfn
= pmreg_access_ccntr
},
2039 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2040 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2041 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2043 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2044 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2045 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2046 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2047 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2048 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2049 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2051 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2052 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2053 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2054 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2056 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2058 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2059 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2060 .accessfn
= pmreg_access
,
2061 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2062 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2063 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2064 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2065 .accessfn
= pmreg_access
,
2066 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2067 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2068 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2069 .accessfn
= pmreg_access_xevcntr
,
2070 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2071 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2072 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2073 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2074 .accessfn
= pmreg_access_xevcntr
,
2075 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2076 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2077 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2078 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2080 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2081 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2082 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2083 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2086 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2087 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2088 .access
= PL1_RW
, .accessfn
= access_tpm
,
2089 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2090 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2092 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2093 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2095 .access
= PL1_RW
, .accessfn
= access_tpm
,
2097 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2098 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2099 .resetvalue
= 0x0 },
2100 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2101 .access
= PL1_RW
, .accessfn
= access_tpm
,
2102 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2104 .writefn
= pmintenclr_write
, },
2105 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2106 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2107 .access
= PL1_RW
, .accessfn
= access_tpm
,
2108 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2109 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2110 .writefn
= pmintenclr_write
},
2111 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2112 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2113 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2114 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2115 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2116 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
2117 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2118 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2119 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2120 * just RAZ for all cores:
2122 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2123 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2124 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2125 /* Auxiliary fault status registers: these also are IMPDEF, and we
2126 * choose to RAZ/WI for all cores.
2128 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2129 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2130 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2131 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2132 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2133 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2134 /* MAIR can just read-as-written because we don't implement caches
2135 * and so don't need to care about memory attributes.
2137 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2138 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2139 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2141 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2142 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2143 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2145 /* For non-long-descriptor page tables these are PRRR and NMRR;
2146 * regardless they still act as reads-as-written for QEMU.
2148 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2149 * allows them to assign the correct fieldoffset based on the endianness
2150 * handled in the field definitions.
2152 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2153 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
2154 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2155 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2156 .resetfn
= arm_cp_reset_ignore
},
2157 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2158 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
2159 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2160 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2161 .resetfn
= arm_cp_reset_ignore
},
2162 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2163 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2164 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2165 /* 32 bit ITLB invalidates */
2166 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2167 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2168 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2169 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2170 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2171 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2172 /* 32 bit DTLB invalidates */
2173 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2174 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2175 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2176 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2177 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2178 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2179 /* 32 bit TLB invalidates */
2180 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2181 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2182 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2183 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2184 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2185 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2186 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2187 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2191 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2192 /* 32 bit TLB invalidates, Inner Shareable */
2193 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2194 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
2195 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2196 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2197 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2198 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2199 .writefn
= tlbiasid_is_write
},
2200 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2201 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2202 .writefn
= tlbimvaa_is_write
},
2206 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2207 /* PMOVSSET is not implemented in v7 before v7ve */
2208 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2209 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2210 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2211 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2212 .writefn
= pmovsset_write
,
2213 .raw_writefn
= raw_write
},
2214 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2215 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2216 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2217 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2218 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2219 .writefn
= pmovsset_write
,
2220 .raw_writefn
= raw_write
},
2224 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2231 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2234 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2235 return CP_ACCESS_TRAP
;
2237 return CP_ACCESS_OK
;
2240 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2241 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2242 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2244 .writefn
= teecr_write
},
2245 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2246 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2247 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2251 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2252 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2253 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2255 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2256 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2258 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2259 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2260 .resetfn
= arm_cp_reset_ignore
},
2261 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2262 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2263 .access
= PL0_R
|PL1_W
,
2264 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2266 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2267 .access
= PL0_R
|PL1_W
,
2268 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2269 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2270 .resetfn
= arm_cp_reset_ignore
},
2271 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2272 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2274 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2275 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2277 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2278 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2283 #ifndef CONFIG_USER_ONLY
2285 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2288 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2289 * Writable only at the highest implemented exception level.
2291 int el
= arm_current_el(env
);
2295 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
2296 return CP_ACCESS_TRAP
;
2300 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2301 arm_is_secure_below_el3(env
)) {
2302 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2303 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2311 if (!isread
&& el
< arm_highest_el(env
)) {
2312 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2315 return CP_ACCESS_OK
;
2318 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2321 unsigned int cur_el
= arm_current_el(env
);
2322 bool secure
= arm_is_secure(env
);
2324 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
2326 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2327 return CP_ACCESS_TRAP
;
2330 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2331 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2332 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
2333 return CP_ACCESS_TRAP_EL2
;
2335 return CP_ACCESS_OK
;
2338 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2341 unsigned int cur_el
= arm_current_el(env
);
2342 bool secure
= arm_is_secure(env
);
2344 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
2345 * EL0[PV]TEN is zero.
2348 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2349 return CP_ACCESS_TRAP
;
2352 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2353 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2354 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2355 return CP_ACCESS_TRAP_EL2
;
2357 return CP_ACCESS_OK
;
2360 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2361 const ARMCPRegInfo
*ri
,
2364 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2367 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2368 const ARMCPRegInfo
*ri
,
2371 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2374 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2377 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2380 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2383 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2386 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2387 const ARMCPRegInfo
*ri
,
2390 /* The AArch64 register view of the secure physical timer is
2391 * always accessible from EL3, and configurably accessible from
2394 switch (arm_current_el(env
)) {
2396 if (!arm_is_secure(env
)) {
2397 return CP_ACCESS_TRAP
;
2399 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2400 return CP_ACCESS_TRAP_EL3
;
2402 return CP_ACCESS_OK
;
2405 return CP_ACCESS_TRAP
;
2407 return CP_ACCESS_OK
;
2409 g_assert_not_reached();
2413 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2415 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
2418 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2420 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2423 /* Timer enabled: calculate and set current ISTATUS, irq, and
2424 * reset timer to when ISTATUS next has to change
2426 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2427 cpu
->env
.cp15
.cntvoff_el2
: 0;
2428 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2429 /* Note that this must be unsigned 64 bit arithmetic: */
2430 int istatus
= count
- offset
>= gt
->cval
;
2434 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2436 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2437 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2440 /* Next transition is when count rolls back over to zero */
2441 nexttick
= UINT64_MAX
;
2443 /* Next transition is when we hit cval */
2444 nexttick
= gt
->cval
+ offset
;
2446 /* Note that the desired next expiry time might be beyond the
2447 * signed-64-bit range of a QEMUTimer -- in this case we just
2448 * set the timer for as far in the future as possible. When the
2449 * timer expires we will reset the timer for any remaining period.
2451 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
2452 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
2454 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2455 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2457 /* Timer disabled: ISTATUS and timer output always clear */
2459 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2460 timer_del(cpu
->gt_timer
[timeridx
]);
2461 trace_arm_gt_recalc_disabled(timeridx
);
2465 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2468 ARMCPU
*cpu
= env_archcpu(env
);
2470 timer_del(cpu
->gt_timer
[timeridx
]);
2473 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2475 return gt_get_countervalue(env
);
2478 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2480 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
2483 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2487 trace_arm_gt_cval_write(timeridx
, value
);
2488 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2489 gt_recalc_timer(env_archcpu(env
), timeridx
);
2492 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2495 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2497 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2498 (gt_get_countervalue(env
) - offset
));
2501 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2505 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2507 trace_arm_gt_tval_write(timeridx
, value
);
2508 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2509 sextract64(value
, 0, 32);
2510 gt_recalc_timer(env_archcpu(env
), timeridx
);
2513 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2517 ARMCPU
*cpu
= env_archcpu(env
);
2518 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2520 trace_arm_gt_ctl_write(timeridx
, value
);
2521 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2522 if ((oldval
^ value
) & 1) {
2523 /* Enable toggled */
2524 gt_recalc_timer(cpu
, timeridx
);
2525 } else if ((oldval
^ value
) & 2) {
2526 /* IMASK toggled: don't need to recalculate,
2527 * just set the interrupt line based on ISTATUS
2529 int irqstate
= (oldval
& 4) && !(value
& 2);
2531 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2532 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2536 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2538 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2541 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2544 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2547 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2549 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2552 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2555 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2558 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2561 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2564 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2566 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2569 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2572 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2575 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2577 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2580 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2583 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2586 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2589 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2592 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2595 ARMCPU
*cpu
= env_archcpu(env
);
2597 trace_arm_gt_cntvoff_write(value
);
2598 raw_write(env
, ri
, value
);
2599 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2602 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2604 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2607 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2610 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2613 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2615 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2618 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2621 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2624 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2627 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2630 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2632 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2635 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2638 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2641 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2643 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2646 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2649 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2652 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2655 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2658 void arm_gt_ptimer_cb(void *opaque
)
2660 ARMCPU
*cpu
= opaque
;
2662 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2665 void arm_gt_vtimer_cb(void *opaque
)
2667 ARMCPU
*cpu
= opaque
;
2669 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2672 void arm_gt_htimer_cb(void *opaque
)
2674 ARMCPU
*cpu
= opaque
;
2676 gt_recalc_timer(cpu
, GTIMER_HYP
);
2679 void arm_gt_stimer_cb(void *opaque
)
2681 ARMCPU
*cpu
= opaque
;
2683 gt_recalc_timer(cpu
, GTIMER_SEC
);
2686 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2687 /* Note that CNTFRQ is purely reads-as-written for the benefit
2688 * of software; writing it doesn't actually change the timer frequency.
2689 * Our reset value matches the fixed frequency we implement the timer at.
2691 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2692 .type
= ARM_CP_ALIAS
,
2693 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2694 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2696 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2697 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2698 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2699 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2700 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
2702 /* overall control: mostly access permissions */
2703 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2704 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2706 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2709 /* per-timer control */
2710 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2711 .secure
= ARM_CP_SECSTATE_NS
,
2712 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2713 .accessfn
= gt_ptimer_access
,
2714 .fieldoffset
= offsetoflow32(CPUARMState
,
2715 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2716 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2718 { .name
= "CNTP_CTL_S",
2719 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2720 .secure
= ARM_CP_SECSTATE_S
,
2721 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2722 .accessfn
= gt_ptimer_access
,
2723 .fieldoffset
= offsetoflow32(CPUARMState
,
2724 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2725 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2727 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2728 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2729 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2730 .accessfn
= gt_ptimer_access
,
2731 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2733 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2735 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2736 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2737 .accessfn
= gt_vtimer_access
,
2738 .fieldoffset
= offsetoflow32(CPUARMState
,
2739 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2740 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2742 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2743 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2744 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2745 .accessfn
= gt_vtimer_access
,
2746 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2748 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2750 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2751 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2752 .secure
= ARM_CP_SECSTATE_NS
,
2753 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2754 .accessfn
= gt_ptimer_access
,
2755 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2757 { .name
= "CNTP_TVAL_S",
2758 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2759 .secure
= ARM_CP_SECSTATE_S
,
2760 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2761 .accessfn
= gt_ptimer_access
,
2762 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2764 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2765 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2766 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2767 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2768 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2770 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2771 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2772 .accessfn
= gt_vtimer_access
,
2773 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2775 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2776 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2777 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2778 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2779 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2781 /* The counter itself */
2782 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2783 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2784 .accessfn
= gt_pct_access
,
2785 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2787 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2788 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2789 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2790 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2792 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2793 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2794 .accessfn
= gt_vct_access
,
2795 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2797 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2798 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2799 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2800 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2802 /* Comparison value, indicating when the timer goes off */
2803 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2804 .secure
= ARM_CP_SECSTATE_NS
,
2806 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2807 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2808 .accessfn
= gt_ptimer_access
,
2809 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2811 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2812 .secure
= ARM_CP_SECSTATE_S
,
2814 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2815 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2816 .accessfn
= gt_ptimer_access
,
2817 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2819 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2820 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2823 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2824 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2825 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2827 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2829 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2830 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2831 .accessfn
= gt_vtimer_access
,
2832 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2834 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2835 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2838 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2839 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2840 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2842 /* Secure timer -- this is actually restricted to only EL3
2843 * and configurably Secure-EL1 via the accessfn.
2845 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2846 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2847 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2848 .accessfn
= gt_stimer_access
,
2849 .readfn
= gt_sec_tval_read
,
2850 .writefn
= gt_sec_tval_write
,
2851 .resetfn
= gt_sec_timer_reset
,
2853 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2854 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2855 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2856 .accessfn
= gt_stimer_access
,
2857 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2859 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2861 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2862 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2863 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2864 .accessfn
= gt_stimer_access
,
2865 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2866 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2873 /* In user-mode most of the generic timer registers are inaccessible
2874 * however modern kernels (4.12+) allow access to cntvct_el0
2877 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2879 /* Currently we have no support for QEMUTimer in linux-user so we
2880 * can't call gt_get_countervalue(env), instead we directly
2881 * call the lower level functions.
2883 return cpu_get_clock() / GTIMER_SCALE
;
2886 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2887 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2888 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2889 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
2890 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2891 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
2893 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2894 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2895 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2896 .readfn
= gt_virt_cnt_read
,
2903 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2905 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2906 raw_write(env
, ri
, value
);
2907 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2908 raw_write(env
, ri
, value
& 0xfffff6ff);
2910 raw_write(env
, ri
, value
& 0xfffff1ff);
2914 #ifndef CONFIG_USER_ONLY
2915 /* get_phys_addr() isn't present for user-mode-only targets */
2917 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2921 /* The ATS12NSO* operations must trap to EL3 if executed in
2922 * Secure EL1 (which can only happen if EL3 is AArch64).
2923 * They are simply UNDEF if executed from NS EL1.
2924 * They function normally from EL2 or EL3.
2926 if (arm_current_el(env
) == 1) {
2927 if (arm_is_secure_below_el3(env
)) {
2928 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2930 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2933 return CP_ACCESS_OK
;
2936 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2937 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2940 target_ulong page_size
;
2944 bool format64
= false;
2945 MemTxAttrs attrs
= {};
2946 ARMMMUFaultInfo fi
= {};
2947 ARMCacheAttrs cacheattrs
= {};
2949 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2950 &prot
, &page_size
, &fi
, &cacheattrs
);
2954 * Some kinds of translation fault must cause exceptions rather
2955 * than being reported in the PAR.
2957 int current_el
= arm_current_el(env
);
2959 uint32_t syn
, fsr
, fsc
;
2960 bool take_exc
= false;
2962 if (fi
.s1ptw
&& current_el
== 1 && !arm_is_secure(env
)
2963 && (mmu_idx
== ARMMMUIdx_S1NSE1
|| mmu_idx
== ARMMMUIdx_S1NSE0
)) {
2965 * Synchronous stage 2 fault on an access made as part of the
2966 * translation table walk for AT S1E0* or AT S1E1* insn
2967 * executed from NS EL1. If this is a synchronous external abort
2968 * and SCR_EL3.EA == 1, then we take a synchronous external abort
2969 * to EL3. Otherwise the fault is taken as an exception to EL2,
2970 * and HPFAR_EL2 holds the faulting IPA.
2972 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
2973 (env
->cp15
.scr_el3
& SCR_EA
)) {
2976 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
2980 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
2982 * Synchronous external aborts during a translation table walk
2983 * are taken as Data Abort exceptions.
2986 if (current_el
== 3) {
2992 target_el
= exception_target_el(env
);
2998 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
2999 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3000 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3001 fsr
= arm_fi_to_lfsc(&fi
);
3002 fsc
= extract32(fsr
, 0, 6);
3004 fsr
= arm_fi_to_sfsc(&fi
);
3008 * Report exception with ESR indicating a fault due to a
3009 * translation table walk for a cache maintenance instruction.
3011 syn
= syn_data_abort_no_iss(current_el
== target_el
,
3012 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3013 env
->exception
.vaddress
= value
;
3014 env
->exception
.fsr
= fsr
;
3015 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3021 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3024 * * TTBCR.EAE determines whether the result is returned using the
3025 * 32-bit or the 64-bit PAR format
3026 * * Instructions executed in Hyp mode always use the 64bit format
3028 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3029 * * The Non-secure TTBCR.EAE bit is set to 1
3030 * * The implementation includes EL2, and the value of HCR.VM is 1
3032 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3034 * ATS1Hx always uses the 64bit format.
3036 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3038 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3039 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
3040 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3042 format64
|= arm_current_el(env
) == 2;
3048 /* Create a 64-bit PAR */
3049 par64
= (1 << 11); /* LPAE bit always set */
3051 par64
|= phys_addr
& ~0xfffULL
;
3052 if (!attrs
.secure
) {
3053 par64
|= (1 << 9); /* NS */
3055 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3056 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3058 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3061 par64
|= (fsr
& 0x3f) << 1; /* FS */
3063 par64
|= (1 << 9); /* S */
3066 par64
|= (1 << 8); /* PTW */
3070 /* fsr is a DFSR/IFSR value for the short descriptor
3071 * translation table format (with WnR always clear).
3072 * Convert it to a 32-bit PAR.
3075 /* We do not set any attribute bits in the PAR */
3076 if (page_size
== (1 << 24)
3077 && arm_feature(env
, ARM_FEATURE_V7
)) {
3078 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3080 par64
= phys_addr
& 0xfffff000;
3082 if (!attrs
.secure
) {
3083 par64
|= (1 << 9); /* NS */
3086 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3088 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3089 ((fsr
& 0xf) << 1) | 1;
3095 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3097 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3100 int el
= arm_current_el(env
);
3101 bool secure
= arm_is_secure_below_el3(env
);
3103 switch (ri
->opc2
& 6) {
3105 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
3108 mmu_idx
= ARMMMUIdx_S1E3
;
3111 mmu_idx
= ARMMMUIdx_S1NSE1
;
3114 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3117 g_assert_not_reached();
3121 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3124 mmu_idx
= ARMMMUIdx_S1SE0
;
3127 mmu_idx
= ARMMMUIdx_S1NSE0
;
3130 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3133 g_assert_not_reached();
3137 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3138 mmu_idx
= ARMMMUIdx_S12NSE1
;
3141 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3142 mmu_idx
= ARMMMUIdx_S12NSE0
;
3145 g_assert_not_reached();
3148 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3150 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3153 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3156 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3159 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S1E2
);
3161 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3164 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3167 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3168 return CP_ACCESS_TRAP
;
3170 return CP_ACCESS_OK
;
3173 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3176 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3178 int secure
= arm_is_secure_below_el3(env
);
3180 switch (ri
->opc2
& 6) {
3183 case 0: /* AT S1E1R, AT S1E1W */
3184 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3186 case 4: /* AT S1E2R, AT S1E2W */
3187 mmu_idx
= ARMMMUIdx_S1E2
;
3189 case 6: /* AT S1E3R, AT S1E3W */
3190 mmu_idx
= ARMMMUIdx_S1E3
;
3193 g_assert_not_reached();
3196 case 2: /* AT S1E0R, AT S1E0W */
3197 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3199 case 4: /* AT S12E1R, AT S12E1W */
3200 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
3202 case 6: /* AT S12E0R, AT S12E0W */
3203 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
3206 g_assert_not_reached();
3209 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3213 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3214 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3215 .access
= PL1_RW
, .resetvalue
= 0,
3216 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3217 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3218 .writefn
= par_write
},
3219 #ifndef CONFIG_USER_ONLY
3220 /* This underdecoding is safe because the reginfo is NO_RAW. */
3221 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3222 .access
= PL1_W
, .accessfn
= ats_access
,
3223 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3228 /* Return basic MPU access permission bits. */
3229 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3236 for (i
= 0; i
< 16; i
+= 2) {
3237 ret
|= (val
>> i
) & mask
;
3243 /* Pad basic MPU access permission bits to extended format. */
3244 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3251 for (i
= 0; i
< 16; i
+= 2) {
3252 ret
|= (val
& mask
) << i
;
3258 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3261 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3264 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3266 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3269 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3272 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3275 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3277 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3280 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3282 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3288 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3292 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3295 ARMCPU
*cpu
= env_archcpu(env
);
3296 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3302 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3303 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3307 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3310 ARMCPU
*cpu
= env_archcpu(env
);
3311 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3313 if (value
>= nrgs
) {
3314 qemu_log_mask(LOG_GUEST_ERROR
,
3315 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3316 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3320 raw_write(env
, ri
, value
);
3323 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3324 /* Reset for all these registers is handled in arm_cpu_reset(),
3325 * because the PMSAv7 is also used by M-profile CPUs, which do
3326 * not register cpregs but still need the state to be reset.
3328 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3329 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3330 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3331 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3332 .resetfn
= arm_cp_reset_ignore
},
3333 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3334 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3335 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3336 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3337 .resetfn
= arm_cp_reset_ignore
},
3338 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3339 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3340 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3341 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3342 .resetfn
= arm_cp_reset_ignore
},
3343 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3345 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3346 .writefn
= pmsav7_rgnr_write
,
3347 .resetfn
= arm_cp_reset_ignore
},
3351 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3352 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3353 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3354 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3355 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3356 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3357 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3358 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3359 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3360 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3362 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3364 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3366 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3368 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3370 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3371 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3373 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3374 /* Protection region base and size registers */
3375 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3376 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3377 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3378 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3379 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3380 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3381 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3382 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3383 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3384 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3385 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3386 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3387 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3388 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3389 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3390 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3391 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3392 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3393 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3394 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3395 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3396 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3397 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3398 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3402 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3405 TCR
*tcr
= raw_ptr(env
, ri
);
3406 int maskshift
= extract32(value
, 0, 3);
3408 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3409 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3410 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3411 * using Long-desciptor translation table format */
3412 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3413 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3414 /* In an implementation that includes the Security Extensions
3415 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3416 * Short-descriptor translation table format.
3418 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3424 /* Update the masks corresponding to the TCR bank being written
3425 * Note that we always calculate mask and base_mask, but
3426 * they are only used for short-descriptor tables (ie if EAE is 0);
3427 * for long-descriptor tables the TCR fields are used differently
3428 * and the mask and base_mask values are meaningless.
3430 tcr
->raw_tcr
= value
;
3431 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3432 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3435 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3438 ARMCPU
*cpu
= env_archcpu(env
);
3439 TCR
*tcr
= raw_ptr(env
, ri
);
3441 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3442 /* With LPAE the TTBCR could result in a change of ASID
3443 * via the TTBCR.A1 bit, so do a TLB flush.
3445 tlb_flush(CPU(cpu
));
3447 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3448 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3449 vmsa_ttbcr_raw_write(env
, ri
, value
);
3452 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3454 TCR
*tcr
= raw_ptr(env
, ri
);
3456 /* Reset both the TCR as well as the masks corresponding to the bank of
3457 * the TCR being reset.
3461 tcr
->base_mask
= 0xffffc000u
;
3464 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3467 ARMCPU
*cpu
= env_archcpu(env
);
3468 TCR
*tcr
= raw_ptr(env
, ri
);
3470 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3471 tlb_flush(CPU(cpu
));
3472 tcr
->raw_tcr
= value
;
3475 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3478 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3479 if (cpreg_field_is_64bit(ri
) &&
3480 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3481 ARMCPU
*cpu
= env_archcpu(env
);
3482 tlb_flush(CPU(cpu
));
3484 raw_write(env
, ri
, value
);
3487 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3490 ARMCPU
*cpu
= env_archcpu(env
);
3491 CPUState
*cs
= CPU(cpu
);
3493 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
3494 if (raw_read(env
, ri
) != value
) {
3495 tlb_flush_by_mmuidx(cs
,
3496 ARMMMUIdxBit_S12NSE1
|
3497 ARMMMUIdxBit_S12NSE0
|
3499 raw_write(env
, ri
, value
);
3503 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3504 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3505 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3506 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3507 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3508 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3509 .access
= PL1_RW
, .resetvalue
= 0,
3510 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3511 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3512 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3513 .access
= PL1_RW
, .resetvalue
= 0,
3514 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3515 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3516 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3517 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3518 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3523 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3524 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3525 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3527 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3528 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3529 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3530 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3531 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3532 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3533 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3534 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3535 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3536 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3537 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3538 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3539 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3540 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
3541 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3542 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3543 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3544 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3545 .raw_writefn
= vmsa_ttbcr_raw_write
,
3546 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3547 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3551 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3552 * qemu tlbs nor adjusting cached masks.
3554 static const ARMCPRegInfo ttbcr2_reginfo
= {
3555 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3556 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3557 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3558 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
3561 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3564 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3565 /* The OS_TYPE bit in this register changes the reported CPUID! */
3566 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3567 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3570 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3573 env
->cp15
.c15_threadid
= value
& 0xffff;
3576 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3579 /* Wait-for-interrupt (deprecated) */
3580 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3583 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3586 /* On OMAP there are registers indicating the max/min index of dcache lines
3587 * containing a dirty line; cache flush operations have to reset these.
3589 env
->cp15
.c15_i_max
= 0x000;
3590 env
->cp15
.c15_i_min
= 0xff0;
3593 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3594 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3595 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3596 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3598 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3599 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3600 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3602 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3603 .writefn
= omap_ticonfig_write
},
3604 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3606 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3607 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3608 .access
= PL1_RW
, .resetvalue
= 0xff0,
3609 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3610 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3612 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3613 .writefn
= omap_threadid_write
},
3614 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3615 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3616 .type
= ARM_CP_NO_RAW
,
3617 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3618 /* TODO: Peripheral port remap register:
3619 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3620 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3623 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3624 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3625 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3626 .writefn
= omap_cachemaint_write
},
3627 { .name
= "C9", .cp
= 15, .crn
= 9,
3628 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3629 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3633 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3636 env
->cp15
.c15_cpar
= value
& 0x3fff;
3639 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3640 { .name
= "XSCALE_CPAR",
3641 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3642 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3643 .writefn
= xscale_cpar_write
, },
3644 { .name
= "XSCALE_AUXCR",
3645 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3646 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3648 /* XScale specific cache-lockdown: since we have no cache we NOP these
3649 * and hope the guest does not really rely on cache behaviour.
3651 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3652 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3653 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3654 { .name
= "XSCALE_UNLOCK_ICACHE",
3655 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3656 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3657 { .name
= "XSCALE_DCACHE_LOCK",
3658 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3659 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3660 { .name
= "XSCALE_UNLOCK_DCACHE",
3661 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3662 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3666 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3667 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3668 * implementation of this implementation-defined space.
3669 * Ideally this should eventually disappear in favour of actually
3670 * implementing the correct behaviour for all cores.
3672 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3673 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3675 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3680 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3681 /* Cache status: RAZ because we have no cache so it's always clean */
3682 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3683 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3688 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3689 /* We never have a a block transfer operation in progress */
3690 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3691 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3693 /* The cache ops themselves: these all NOP for QEMU */
3694 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3695 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3696 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3697 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3698 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
3699 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3700 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
3701 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3702 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
3703 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3704 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
3705 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3709 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
3710 /* The cache test-and-clean instructions always return (1 << 30)
3711 * to indicate that there are no dirty cache lines.
3713 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
3714 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3715 .resetvalue
= (1 << 30) },
3716 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
3717 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3718 .resetvalue
= (1 << 30) },
3722 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
3723 /* Ignore ReadBuffer accesses */
3724 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
3725 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3726 .access
= PL1_RW
, .resetvalue
= 0,
3727 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
3731 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3733 ARMCPU
*cpu
= env_archcpu(env
);
3734 unsigned int cur_el
= arm_current_el(env
);
3735 bool secure
= arm_is_secure(env
);
3737 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3738 return env
->cp15
.vpidr_el2
;
3740 return raw_read(env
, ri
);
3743 static uint64_t mpidr_read_val(CPUARMState
*env
)
3745 ARMCPU
*cpu
= env_archcpu(env
);
3746 uint64_t mpidr
= cpu
->mp_affinity
;
3748 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
3749 mpidr
|= (1U << 31);
3750 /* Cores which are uniprocessor (non-coherent)
3751 * but still implement the MP extensions set
3752 * bit 30. (For instance, Cortex-R5).
3754 if (cpu
->mp_is_up
) {
3755 mpidr
|= (1u << 30);
3761 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3763 unsigned int cur_el
= arm_current_el(env
);
3764 bool secure
= arm_is_secure(env
);
3766 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3767 return env
->cp15
.vmpidr_el2
;
3769 return mpidr_read_val(env
);
3772 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
3774 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
3775 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
3776 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3778 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3779 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
3780 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3782 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
3783 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
3784 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
3785 offsetof(CPUARMState
, cp15
.par_ns
)} },
3786 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
3787 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3788 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3789 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
3790 .writefn
= vmsa_ttbr_write
, },
3791 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
3792 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3793 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3794 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
3795 .writefn
= vmsa_ttbr_write
, },
3799 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3801 return vfp_get_fpcr(env
);
3804 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3807 vfp_set_fpcr(env
, value
);
3810 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3812 return vfp_get_fpsr(env
);
3815 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3818 vfp_set_fpsr(env
, value
);
3821 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3824 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
3825 return CP_ACCESS_TRAP
;
3827 return CP_ACCESS_OK
;
3830 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3833 env
->daif
= value
& PSTATE_DAIF
;
3836 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
3837 const ARMCPRegInfo
*ri
,
3840 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3841 * SCTLR_EL1.UCI is set.
3843 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
3844 return CP_ACCESS_TRAP
;
3846 return CP_ACCESS_OK
;
3849 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3850 * Page D4-1736 (DDI0487A.b)
3853 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3856 CPUState
*cs
= env_cpu(env
);
3857 bool sec
= arm_is_secure_below_el3(env
);
3860 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3861 ARMMMUIdxBit_S1SE1
|
3862 ARMMMUIdxBit_S1SE0
);
3864 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3865 ARMMMUIdxBit_S12NSE1
|
3866 ARMMMUIdxBit_S12NSE0
);
3870 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3873 CPUState
*cs
= env_cpu(env
);
3875 if (tlb_force_broadcast(env
)) {
3876 tlbi_aa64_vmalle1is_write(env
, NULL
, value
);
3880 if (arm_is_secure_below_el3(env
)) {
3881 tlb_flush_by_mmuidx(cs
,
3882 ARMMMUIdxBit_S1SE1
|
3883 ARMMMUIdxBit_S1SE0
);
3885 tlb_flush_by_mmuidx(cs
,
3886 ARMMMUIdxBit_S12NSE1
|
3887 ARMMMUIdxBit_S12NSE0
);
3891 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3894 /* Note that the 'ALL' scope must invalidate both stage 1 and
3895 * stage 2 translations, whereas most other scopes only invalidate
3896 * stage 1 translations.
3898 ARMCPU
*cpu
= env_archcpu(env
);
3899 CPUState
*cs
= CPU(cpu
);
3901 if (arm_is_secure_below_el3(env
)) {
3902 tlb_flush_by_mmuidx(cs
,
3903 ARMMMUIdxBit_S1SE1
|
3904 ARMMMUIdxBit_S1SE0
);
3906 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3907 tlb_flush_by_mmuidx(cs
,
3908 ARMMMUIdxBit_S12NSE1
|
3909 ARMMMUIdxBit_S12NSE0
|
3912 tlb_flush_by_mmuidx(cs
,
3913 ARMMMUIdxBit_S12NSE1
|
3914 ARMMMUIdxBit_S12NSE0
);
3919 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3922 ARMCPU
*cpu
= env_archcpu(env
);
3923 CPUState
*cs
= CPU(cpu
);
3925 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3928 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3931 ARMCPU
*cpu
= env_archcpu(env
);
3932 CPUState
*cs
= CPU(cpu
);
3934 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3937 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3940 /* Note that the 'ALL' scope must invalidate both stage 1 and
3941 * stage 2 translations, whereas most other scopes only invalidate
3942 * stage 1 translations.
3944 CPUState
*cs
= env_cpu(env
);
3945 bool sec
= arm_is_secure_below_el3(env
);
3946 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3949 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3950 ARMMMUIdxBit_S1SE1
|
3951 ARMMMUIdxBit_S1SE0
);
3952 } else if (has_el2
) {
3953 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3954 ARMMMUIdxBit_S12NSE1
|
3955 ARMMMUIdxBit_S12NSE0
|
3958 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3959 ARMMMUIdxBit_S12NSE1
|
3960 ARMMMUIdxBit_S12NSE0
);
3964 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3967 CPUState
*cs
= env_cpu(env
);
3969 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3972 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3975 CPUState
*cs
= env_cpu(env
);
3977 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3980 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3983 /* Invalidate by VA, EL2
3984 * Currently handles both VAE2 and VALE2, since we don't support
3985 * flush-last-level-only.
3987 ARMCPU
*cpu
= env_archcpu(env
);
3988 CPUState
*cs
= CPU(cpu
);
3989 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3991 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3994 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3997 /* Invalidate by VA, EL3
3998 * Currently handles both VAE3 and VALE3, since we don't support
3999 * flush-last-level-only.
4001 ARMCPU
*cpu
= env_archcpu(env
);
4002 CPUState
*cs
= CPU(cpu
);
4003 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4005 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
4008 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4011 ARMCPU
*cpu
= env_archcpu(env
);
4012 CPUState
*cs
= CPU(cpu
);
4013 bool sec
= arm_is_secure_below_el3(env
);
4014 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4017 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4018 ARMMMUIdxBit_S1SE1
|
4019 ARMMMUIdxBit_S1SE0
);
4021 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4022 ARMMMUIdxBit_S12NSE1
|
4023 ARMMMUIdxBit_S12NSE0
);
4027 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4030 /* Invalidate by VA, EL1&0 (AArch64 version).
4031 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4032 * since we don't support flush-for-specific-ASID-only or
4033 * flush-last-level-only.
4035 ARMCPU
*cpu
= env_archcpu(env
);
4036 CPUState
*cs
= CPU(cpu
);
4037 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4039 if (tlb_force_broadcast(env
)) {
4040 tlbi_aa64_vae1is_write(env
, NULL
, value
);
4044 if (arm_is_secure_below_el3(env
)) {
4045 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
4046 ARMMMUIdxBit_S1SE1
|
4047 ARMMMUIdxBit_S1SE0
);
4049 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
4050 ARMMMUIdxBit_S12NSE1
|
4051 ARMMMUIdxBit_S12NSE0
);
4055 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4058 CPUState
*cs
= env_cpu(env
);
4059 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4061 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4065 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4068 CPUState
*cs
= env_cpu(env
);
4069 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4071 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4075 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4078 /* Invalidate by IPA. This has to invalidate any structures that
4079 * contain only stage 2 translation information, but does not need
4080 * to apply to structures that contain combined stage 1 and stage 2
4081 * translation information.
4082 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
4084 ARMCPU
*cpu
= env_archcpu(env
);
4085 CPUState
*cs
= CPU(cpu
);
4088 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4092 pageaddr
= sextract64(value
<< 12, 0, 48);
4094 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
4097 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4100 CPUState
*cs
= env_cpu(env
);
4103 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4107 pageaddr
= sextract64(value
<< 12, 0, 48);
4109 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4113 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4116 /* We don't implement EL2, so the only control on DC ZVA is the
4117 * bit in the SCTLR which can prohibit access for EL0.
4119 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4120 return CP_ACCESS_TRAP
;
4122 return CP_ACCESS_OK
;
4125 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4127 ARMCPU
*cpu
= env_archcpu(env
);
4128 int dzp_bit
= 1 << 4;
4130 /* DZP indicates whether DC ZVA access is allowed */
4131 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4134 return cpu
->dcz_blocksize
| dzp_bit
;
4137 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4140 if (!(env
->pstate
& PSTATE_SP
)) {
4141 /* Access to SP_EL0 is undefined if it's being used as
4142 * the stack pointer.
4144 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4146 return CP_ACCESS_OK
;
4149 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4151 return env
->pstate
& PSTATE_SP
;
4154 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4156 update_spsel(env
, val
);
4159 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4162 ARMCPU
*cpu
= env_archcpu(env
);
4164 if (raw_read(env
, ri
) == value
) {
4165 /* Skip the TLB flush if nothing actually changed; Linux likes
4166 * to do a lot of pointless SCTLR writes.
4171 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4172 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4176 raw_write(env
, ri
, value
);
4177 /* ??? Lots of these bits are not implemented. */
4178 /* This may enable/disable the MMU, so do a TLB flush. */
4179 tlb_flush(CPU(cpu
));
4181 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4183 * Normally we would always end the TB on an SCTLR write; see the
4184 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4185 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4186 * of hflags from the translator, so do it here.
4188 arm_rebuild_hflags(env
);
4192 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4195 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4196 return CP_ACCESS_TRAP_FP_EL2
;
4198 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4199 return CP_ACCESS_TRAP_FP_EL3
;
4201 return CP_ACCESS_OK
;
4204 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4207 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4210 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4211 /* Minimal set of EL0-visible registers. This will need to be expanded
4212 * significantly for system emulation of AArch64 CPUs.
4214 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4215 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4216 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4217 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4218 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4219 .type
= ARM_CP_NO_RAW
,
4220 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4221 .fieldoffset
= offsetof(CPUARMState
, daif
),
4222 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4223 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4224 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4225 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4226 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4227 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4228 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4229 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4230 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4231 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4232 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4233 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4234 .readfn
= aa64_dczid_read
},
4235 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4236 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4237 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4238 #ifndef CONFIG_USER_ONLY
4239 /* Avoid overhead of an access check that always passes in user-mode */
4240 .accessfn
= aa64_zva_access
,
4243 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4244 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4245 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4246 /* Cache ops: all NOPs since we don't emulate caches */
4247 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4248 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4249 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4250 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4251 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4252 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4253 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4254 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4255 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4256 .accessfn
= aa64_cacheop_access
},
4257 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4258 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4259 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4260 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4261 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4262 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4263 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4264 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4265 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4266 .accessfn
= aa64_cacheop_access
},
4267 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4268 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4269 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4270 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4271 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4272 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4273 .accessfn
= aa64_cacheop_access
},
4274 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4275 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4276 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4277 .accessfn
= aa64_cacheop_access
},
4278 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4279 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4280 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4281 /* TLBI operations */
4282 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4283 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4284 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4285 .writefn
= tlbi_aa64_vmalle1is_write
},
4286 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4287 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4288 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4289 .writefn
= tlbi_aa64_vae1is_write
},
4290 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4291 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4292 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4293 .writefn
= tlbi_aa64_vmalle1is_write
},
4294 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4295 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4296 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4297 .writefn
= tlbi_aa64_vae1is_write
},
4298 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4299 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4300 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4301 .writefn
= tlbi_aa64_vae1is_write
},
4302 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4303 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4304 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4305 .writefn
= tlbi_aa64_vae1is_write
},
4306 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4307 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4308 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4309 .writefn
= tlbi_aa64_vmalle1_write
},
4310 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4311 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4312 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4313 .writefn
= tlbi_aa64_vae1_write
},
4314 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4315 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4316 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4317 .writefn
= tlbi_aa64_vmalle1_write
},
4318 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4319 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4320 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4321 .writefn
= tlbi_aa64_vae1_write
},
4322 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4323 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4324 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4325 .writefn
= tlbi_aa64_vae1_write
},
4326 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4327 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4328 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4329 .writefn
= tlbi_aa64_vae1_write
},
4330 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4331 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4332 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4333 .writefn
= tlbi_aa64_ipas2e1is_write
},
4334 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4335 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4336 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4337 .writefn
= tlbi_aa64_ipas2e1is_write
},
4338 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4339 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4340 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4341 .writefn
= tlbi_aa64_alle1is_write
},
4342 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4343 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4344 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4345 .writefn
= tlbi_aa64_alle1is_write
},
4346 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4347 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4348 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4349 .writefn
= tlbi_aa64_ipas2e1_write
},
4350 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4351 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4352 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4353 .writefn
= tlbi_aa64_ipas2e1_write
},
4354 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4355 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4356 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4357 .writefn
= tlbi_aa64_alle1_write
},
4358 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4359 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4360 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4361 .writefn
= tlbi_aa64_alle1is_write
},
4362 #ifndef CONFIG_USER_ONLY
4363 /* 64 bit address translation operations */
4364 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4365 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4366 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4367 .writefn
= ats_write64
},
4368 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4369 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4370 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4371 .writefn
= ats_write64
},
4372 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4373 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4374 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4375 .writefn
= ats_write64
},
4376 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4377 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4378 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4379 .writefn
= ats_write64
},
4380 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4381 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4382 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4383 .writefn
= ats_write64
},
4384 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4385 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4386 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4387 .writefn
= ats_write64
},
4388 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4389 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4390 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4391 .writefn
= ats_write64
},
4392 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4393 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4394 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4395 .writefn
= ats_write64
},
4396 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4397 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4398 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4399 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4400 .writefn
= ats_write64
},
4401 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4402 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4403 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4404 .writefn
= ats_write64
},
4405 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4406 .type
= ARM_CP_ALIAS
,
4407 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4408 .access
= PL1_RW
, .resetvalue
= 0,
4409 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4410 .writefn
= par_write
},
4412 /* TLB invalidate last level of translation table walk */
4413 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4414 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
4415 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4416 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
4417 .writefn
= tlbimvaa_is_write
},
4418 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4419 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
4420 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4421 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
4422 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4423 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4424 .writefn
= tlbimva_hyp_write
},
4425 { .name
= "TLBIMVALHIS",
4426 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4427 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4428 .writefn
= tlbimva_hyp_is_write
},
4429 { .name
= "TLBIIPAS2",
4430 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4431 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4432 .writefn
= tlbiipas2_write
},
4433 { .name
= "TLBIIPAS2IS",
4434 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4435 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4436 .writefn
= tlbiipas2_is_write
},
4437 { .name
= "TLBIIPAS2L",
4438 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4439 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4440 .writefn
= tlbiipas2_write
},
4441 { .name
= "TLBIIPAS2LIS",
4442 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4443 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4444 .writefn
= tlbiipas2_is_write
},
4445 /* 32 bit cache operations */
4446 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4447 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4448 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4449 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4450 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4451 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4452 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4453 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4454 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4455 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4456 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4457 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4458 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4459 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4460 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4461 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4462 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4463 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4464 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4465 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4466 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4467 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4468 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4469 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4470 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4471 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4472 /* MMU Domain access control / MPU write buffer control */
4473 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4474 .access
= PL1_RW
, .resetvalue
= 0,
4475 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4476 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4477 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4478 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4479 .type
= ARM_CP_ALIAS
,
4480 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4482 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4483 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4484 .type
= ARM_CP_ALIAS
,
4485 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4487 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4488 /* We rely on the access checks not allowing the guest to write to the
4489 * state field when SPSel indicates that it's being used as the stack
4492 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4493 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4494 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
4495 .type
= ARM_CP_ALIAS
,
4496 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
4497 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
4498 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
4499 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4500 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
4501 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
4502 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
4503 .type
= ARM_CP_NO_RAW
,
4504 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
4505 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
4506 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
4507 .type
= ARM_CP_ALIAS
,
4508 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
4509 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
4510 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
4511 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
4512 .access
= PL2_RW
, .resetvalue
= 0,
4513 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4514 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
4515 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
4516 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
4517 .access
= PL2_RW
, .resetvalue
= 0,
4518 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
4519 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
4520 .type
= ARM_CP_ALIAS
,
4521 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
4523 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
4524 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
4525 .type
= ARM_CP_ALIAS
,
4526 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
4528 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
4529 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
4530 .type
= ARM_CP_ALIAS
,
4531 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
4533 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
4534 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
4535 .type
= ARM_CP_ALIAS
,
4536 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
4538 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
4539 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
4540 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
4542 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
4543 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
4544 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
4545 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4546 .writefn
= sdcr_write
,
4547 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
4551 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4552 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
4553 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4554 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4556 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
4557 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4558 .type
= ARM_CP_NO_RAW
,
4559 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4561 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4562 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4563 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4564 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4565 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4566 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4568 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4569 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4570 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4571 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4572 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4573 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4574 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4576 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4577 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4578 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4579 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4580 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4581 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4583 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4584 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4585 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4587 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4588 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4589 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4591 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4592 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4593 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4595 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4596 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4597 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4598 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4599 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4600 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4601 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4602 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4603 .cp
= 15, .opc1
= 6, .crm
= 2,
4604 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4605 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
4606 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4607 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4608 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4609 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4610 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4611 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4612 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4613 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4614 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4615 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4616 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4617 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4618 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4619 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4621 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4622 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4623 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4624 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4625 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4626 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4627 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4628 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4630 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4631 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4632 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4633 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4634 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4636 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4637 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4638 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4639 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4640 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4641 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4642 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4643 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4644 .access
= PL2_RW
, .accessfn
= access_tda
,
4645 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4646 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4647 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4648 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4649 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4650 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4651 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4652 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4653 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4654 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4655 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4656 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4657 .type
= ARM_CP_CONST
,
4658 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4659 .access
= PL2_RW
, .resetvalue
= 0 },
4663 /* Ditto, but for registers which exist in ARMv8 but not v7 */
4664 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
4665 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4666 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4668 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4672 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
4674 ARMCPU
*cpu
= env_archcpu(env
);
4675 uint64_t valid_mask
= HCR_MASK
;
4677 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4678 valid_mask
&= ~HCR_HCD
;
4679 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
4680 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
4681 * However, if we're using the SMC PSCI conduit then QEMU is
4682 * effectively acting like EL3 firmware and so the guest at
4683 * EL2 should retain the ability to prevent EL1 from being
4684 * able to make SMC calls into the ersatz firmware, so in
4685 * that case HCR.TSC should be read/write.
4687 valid_mask
&= ~HCR_TSC
;
4689 if (cpu_isar_feature(aa64_lor
, cpu
)) {
4690 valid_mask
|= HCR_TLOR
;
4692 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
4693 valid_mask
|= HCR_API
| HCR_APK
;
4696 /* Clear RES0 bits. */
4697 value
&= valid_mask
;
4699 /* These bits change the MMU setup:
4700 * HCR_VM enables stage 2 translation
4701 * HCR_PTW forbids certain page-table setups
4702 * HCR_DC Disables stage1 and enables stage2 translation
4704 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
4705 tlb_flush(CPU(cpu
));
4707 env
->cp15
.hcr_el2
= value
;
4710 * Updates to VI and VF require us to update the status of
4711 * virtual interrupts, which are the logical OR of these bits
4712 * and the state of the input lines from the GIC. (This requires
4713 * that we have the iothread lock, which is done by marking the
4714 * reginfo structs as ARM_CP_IO.)
4715 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
4716 * possible for it to be taken immediately, because VIRQ and
4717 * VFIQ are masked unless running at EL0 or EL1, and HCR
4718 * can only be written at EL2.
4720 g_assert(qemu_mutex_iothread_locked());
4721 arm_cpu_update_virq(cpu
);
4722 arm_cpu_update_vfiq(cpu
);
4725 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4728 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
4729 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
4730 hcr_write(env
, NULL
, value
);
4733 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4736 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
4737 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
4738 hcr_write(env
, NULL
, value
);
4742 * Return the effective value of HCR_EL2.
4743 * Bits that are not included here:
4744 * RW (read from SCR_EL3.RW as needed)
4746 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
4748 uint64_t ret
= env
->cp15
.hcr_el2
;
4750 if (arm_is_secure_below_el3(env
)) {
4752 * "This register has no effect if EL2 is not enabled in the
4753 * current Security state". This is ARMv8.4-SecEL2 speak for
4754 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
4756 * Prior to that, the language was "In an implementation that
4757 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
4758 * as if this field is 0 for all purposes other than a direct
4759 * read or write access of HCR_EL2". With lots of enumeration
4760 * on a per-field basis. In current QEMU, this is condition
4761 * is arm_is_secure_below_el3.
4763 * Since the v8.4 language applies to the entire register, and
4764 * appears to be backward compatible, use that.
4767 } else if (ret
& HCR_TGE
) {
4768 /* These bits are up-to-date as of ARMv8.4. */
4769 if (ret
& HCR_E2H
) {
4770 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
4771 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
4772 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
4773 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
);
4775 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
4777 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
4778 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
4779 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
4786 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4790 * For A-profile AArch32 EL3, if NSACR.CP10
4791 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
4793 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
4794 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
4795 value
&= ~(0x3 << 10);
4796 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
4798 env
->cp15
.cptr_el
[2] = value
;
4801 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4804 * For A-profile AArch32 EL3, if NSACR.CP10
4805 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
4807 uint64_t value
= env
->cp15
.cptr_el
[2];
4809 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
4810 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
4816 static const ARMCPRegInfo el2_cp_reginfo
[] = {
4817 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
4819 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4820 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4821 .writefn
= hcr_write
},
4822 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
4823 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
4824 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4825 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4826 .writefn
= hcr_writelow
},
4827 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4828 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4829 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4830 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
4831 .type
= ARM_CP_ALIAS
,
4832 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
4834 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
4835 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4836 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4837 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
4838 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4839 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4840 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
4841 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4842 .type
= ARM_CP_ALIAS
,
4843 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4845 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
4846 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
4847 .type
= ARM_CP_ALIAS
,
4848 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
4850 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
4851 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4852 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4853 .access
= PL2_RW
, .writefn
= vbar_write
,
4854 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
4856 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
4857 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
4858 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
4859 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
4860 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4861 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4862 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4863 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
4864 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
4865 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4866 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4867 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
4869 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4870 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4871 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4872 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
4873 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4874 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4875 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4877 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
4878 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4879 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4880 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4882 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4883 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4884 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4886 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4887 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4888 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4890 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4891 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4893 /* no .writefn needed as this can't cause an ASID change;
4894 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4896 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
4897 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
4898 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4899 .type
= ARM_CP_ALIAS
,
4900 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4901 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4902 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
4903 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4905 /* no .writefn needed as this can't cause an ASID change;
4906 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4908 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4909 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4910 .cp
= 15, .opc1
= 6, .crm
= 2,
4911 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4912 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4913 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
4914 .writefn
= vttbr_write
},
4915 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4916 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4917 .access
= PL2_RW
, .writefn
= vttbr_write
,
4918 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
4919 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4920 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4921 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4922 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
4923 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4924 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4925 .access
= PL2_RW
, .resetvalue
= 0,
4926 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
4927 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4928 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4929 .access
= PL2_RW
, .resetvalue
= 0,
4930 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4931 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4932 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4933 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4934 { .name
= "TLBIALLNSNH",
4935 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4936 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4937 .writefn
= tlbiall_nsnh_write
},
4938 { .name
= "TLBIALLNSNHIS",
4939 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4940 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4941 .writefn
= tlbiall_nsnh_is_write
},
4942 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4943 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4944 .writefn
= tlbiall_hyp_write
},
4945 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4946 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4947 .writefn
= tlbiall_hyp_is_write
},
4948 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4949 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4950 .writefn
= tlbimva_hyp_write
},
4951 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4952 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4953 .writefn
= tlbimva_hyp_is_write
},
4954 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
4955 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4956 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4957 .writefn
= tlbi_aa64_alle2_write
},
4958 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
4959 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4960 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4961 .writefn
= tlbi_aa64_vae2_write
},
4962 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
4963 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4964 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4965 .writefn
= tlbi_aa64_vae2_write
},
4966 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
4967 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4968 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4969 .writefn
= tlbi_aa64_alle2is_write
},
4970 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
4971 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4972 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4973 .writefn
= tlbi_aa64_vae2is_write
},
4974 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
4975 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4976 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4977 .writefn
= tlbi_aa64_vae2is_write
},
4978 #ifndef CONFIG_USER_ONLY
4979 /* Unlike the other EL2-related AT operations, these must
4980 * UNDEF from EL3 if EL2 is not implemented, which is why we
4981 * define them here rather than with the rest of the AT ops.
4983 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
4984 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4985 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4986 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
4987 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4989 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4990 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
4991 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
4992 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
4993 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
4994 * to behave as if SCR.NS was 1.
4996 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4998 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
4999 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5001 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5002 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5003 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5004 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5005 * reset values as IMPDEF. We choose to reset to 3 to comply with
5006 * both ARMv7 and ARMv8.
5008 .access
= PL2_RW
, .resetvalue
= 3,
5009 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5010 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5011 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5012 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5013 .writefn
= gt_cntvoff_write
,
5014 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5015 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5016 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5017 .writefn
= gt_cntvoff_write
,
5018 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5019 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5020 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5021 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5022 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5023 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5024 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5025 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5026 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5027 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5028 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5029 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5030 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5031 .resetfn
= gt_hyp_timer_reset
,
5032 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5033 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5035 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5037 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5039 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5041 /* The only field of MDCR_EL2 that has a defined architectural reset value
5042 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5043 * don't implement any PMU event counters, so using zero as a reset
5044 * value for MDCR_EL2 is okay
5046 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5047 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5048 .access
= PL2_RW
, .resetvalue
= 0,
5049 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5050 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5051 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5052 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5053 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5054 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5055 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5057 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5058 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5059 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5061 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5065 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5066 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5067 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5068 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5070 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5071 .writefn
= hcr_writehigh
},
5075 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5078 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5079 * At Secure EL1 it traps to EL3.
5081 if (arm_current_el(env
) == 3) {
5082 return CP_ACCESS_OK
;
5084 if (arm_is_secure_below_el3(env
)) {
5085 return CP_ACCESS_TRAP_EL3
;
5087 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5089 return CP_ACCESS_OK
;
5091 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5094 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5095 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5096 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5097 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5098 .resetvalue
= 0, .writefn
= scr_write
},
5099 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
5100 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5101 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5102 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5103 .writefn
= scr_write
},
5104 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5105 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5106 .access
= PL3_RW
, .resetvalue
= 0,
5107 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5109 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5110 .access
= PL3_RW
, .resetvalue
= 0,
5111 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5112 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5113 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5114 .writefn
= vbar_write
, .resetvalue
= 0,
5115 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5116 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5117 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5118 .access
= PL3_RW
, .resetvalue
= 0,
5119 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5120 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5121 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5123 /* no .writefn needed as this can't cause an ASID change;
5124 * we must provide a .raw_writefn and .resetfn because we handle
5125 * reset and migration for the AArch32 TTBCR(S), which might be
5126 * using mask and base_mask.
5128 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5129 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5130 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5131 .type
= ARM_CP_ALIAS
,
5132 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5134 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5135 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5136 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5137 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5138 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5139 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5140 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5141 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5142 .type
= ARM_CP_ALIAS
,
5143 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5145 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5146 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5147 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5148 .access
= PL3_RW
, .writefn
= vbar_write
,
5149 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5151 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5152 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5153 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5154 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5155 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5156 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5157 .access
= PL3_RW
, .resetvalue
= 0,
5158 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5159 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5160 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5161 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5163 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5164 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5165 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5167 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5168 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5169 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5171 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5172 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5173 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5174 .writefn
= tlbi_aa64_alle3is_write
},
5175 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5176 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5177 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5178 .writefn
= tlbi_aa64_vae3is_write
},
5179 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5180 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5181 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5182 .writefn
= tlbi_aa64_vae3is_write
},
5183 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5184 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5185 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5186 .writefn
= tlbi_aa64_alle3_write
},
5187 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5188 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5189 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5190 .writefn
= tlbi_aa64_vae3_write
},
5191 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5192 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5193 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5194 .writefn
= tlbi_aa64_vae3_write
},
5198 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5201 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
5202 * but the AArch32 CTR has its own reginfo struct)
5204 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5205 return CP_ACCESS_TRAP
;
5207 return CP_ACCESS_OK
;
5210 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5213 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5214 * read via a bit in OSLSR_EL1.
5218 if (ri
->state
== ARM_CP_STATE_AA32
) {
5219 oslock
= (value
== 0xC5ACCE55);
5224 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5227 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5228 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5229 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5230 * unlike DBGDRAR it is never accessible from EL0.
5231 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5234 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5235 .access
= PL0_R
, .accessfn
= access_tdra
,
5236 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5237 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5238 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5239 .access
= PL1_R
, .accessfn
= access_tdra
,
5240 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5241 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5242 .access
= PL0_R
, .accessfn
= access_tdra
,
5243 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5244 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5245 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5246 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5247 .access
= PL1_RW
, .accessfn
= access_tda
,
5248 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5250 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5251 * We don't implement the configurable EL0 access.
5253 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
5254 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5255 .type
= ARM_CP_ALIAS
,
5256 .access
= PL1_R
, .accessfn
= access_tda
,
5257 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5258 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5259 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5260 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5261 .accessfn
= access_tdosa
,
5262 .writefn
= oslar_write
},
5263 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5264 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5265 .access
= PL1_R
, .resetvalue
= 10,
5266 .accessfn
= access_tdosa
,
5267 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5268 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5269 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5270 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5271 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5272 .type
= ARM_CP_NOP
},
5273 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5274 * implement vector catch debug events yet.
5277 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5278 .access
= PL1_RW
, .accessfn
= access_tda
,
5279 .type
= ARM_CP_NOP
},
5280 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5281 * to save and restore a 32-bit guest's DBGVCR)
5283 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5284 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5285 .access
= PL2_RW
, .accessfn
= access_tda
,
5286 .type
= ARM_CP_NOP
},
5287 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5288 * Channel but Linux may try to access this register. The 32-bit
5289 * alias is DBGDCCINT.
5291 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5292 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5293 .access
= PL1_RW
, .accessfn
= access_tda
,
5294 .type
= ARM_CP_NOP
},
5298 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
5299 /* 64 bit access versions of the (dummy) debug registers */
5300 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
5301 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5302 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
5303 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5307 /* Return the exception level to which exceptions should be taken
5308 * via SVEAccessTrap. If an exception should be routed through
5309 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5310 * take care of raising that exception.
5311 * C.f. the ARM pseudocode function CheckSVEEnabled.
5313 int sve_exception_el(CPUARMState
*env
, int el
)
5315 #ifndef CONFIG_USER_ONLY
5317 bool disabled
= false;
5319 /* The CPACR.ZEN controls traps to EL1:
5320 * 0, 2 : trap EL0 and EL1 accesses
5321 * 1 : trap only EL0 accesses
5322 * 3 : trap no accesses
5324 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
5326 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
5331 return (arm_feature(env
, ARM_FEATURE_EL2
)
5332 && (arm_hcr_el2_eff(env
) & HCR_TGE
) ? 2 : 1);
5335 /* Check CPACR.FPEN. */
5336 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
5338 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
5346 /* CPTR_EL2. Since TZ and TFP are positive,
5347 * they will be zero when EL2 is not present.
5349 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
5350 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
5353 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
5358 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5359 if (arm_feature(env
, ARM_FEATURE_EL3
)
5360 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
5367 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
5371 end_len
= start_len
&= 0xf;
5372 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
5373 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
5374 assert(end_len
< start_len
);
5380 * Given that SVE is enabled, return the vector length for EL.
5382 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
5384 ARMCPU
*cpu
= env_archcpu(env
);
5385 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
5388 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
5390 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
5391 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
5393 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5394 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
5397 return sve_zcr_get_valid_len(cpu
, zcr_len
);
5400 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5403 int cur_el
= arm_current_el(env
);
5404 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
5407 /* Bits other than [3:0] are RAZ/WI. */
5408 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
5409 raw_write(env
, ri
, value
& 0xf);
5412 * Because we arrived here, we know both FP and SVE are enabled;
5413 * otherwise we would have trapped access to the ZCR_ELn register.
5415 new_len
= sve_zcr_len_for_el(env
, cur_el
);
5416 if (new_len
< old_len
) {
5417 aarch64_sve_narrow_vq(env
, new_len
+ 1);
5421 static const ARMCPRegInfo zcr_el1_reginfo
= {
5422 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
5423 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
5424 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
5425 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
5426 .writefn
= zcr_write
, .raw_writefn
= raw_write
5429 static const ARMCPRegInfo zcr_el2_reginfo
= {
5430 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5431 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5432 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5433 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
5434 .writefn
= zcr_write
, .raw_writefn
= raw_write
5437 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
5438 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5439 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5440 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5441 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
5444 static const ARMCPRegInfo zcr_el3_reginfo
= {
5445 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
5446 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
5447 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
5448 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
5449 .writefn
= zcr_write
, .raw_writefn
= raw_write
5452 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
5454 CPUARMState
*env
= &cpu
->env
;
5456 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
5457 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
5459 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
5461 if (env
->cpu_watchpoint
[n
]) {
5462 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
5463 env
->cpu_watchpoint
[n
] = NULL
;
5466 if (!extract64(wcr
, 0, 1)) {
5467 /* E bit clear : watchpoint disabled */
5471 switch (extract64(wcr
, 3, 2)) {
5473 /* LSC 00 is reserved and must behave as if the wp is disabled */
5476 flags
|= BP_MEM_READ
;
5479 flags
|= BP_MEM_WRITE
;
5482 flags
|= BP_MEM_ACCESS
;
5486 /* Attempts to use both MASK and BAS fields simultaneously are
5487 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
5488 * thus generating a watchpoint for every byte in the masked region.
5490 mask
= extract64(wcr
, 24, 4);
5491 if (mask
== 1 || mask
== 2) {
5492 /* Reserved values of MASK; we must act as if the mask value was
5493 * some non-reserved value, or as if the watchpoint were disabled.
5494 * We choose the latter.
5498 /* Watchpoint covers an aligned area up to 2GB in size */
5500 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
5501 * whether the watchpoint fires when the unmasked bits match; we opt
5502 * to generate the exceptions.
5506 /* Watchpoint covers bytes defined by the byte address select bits */
5507 int bas
= extract64(wcr
, 5, 8);
5511 /* This must act as if the watchpoint is disabled */
5515 if (extract64(wvr
, 2, 1)) {
5516 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
5517 * ignored, and BAS[3:0] define which bytes to watch.
5521 /* The BAS bits are supposed to be programmed to indicate a contiguous
5522 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
5523 * we fire for each byte in the word/doubleword addressed by the WVR.
5524 * We choose to ignore any non-zero bits after the first range of 1s.
5526 basstart
= ctz32(bas
);
5527 len
= cto32(bas
>> basstart
);
5531 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
5532 &env
->cpu_watchpoint
[n
]);
5535 void hw_watchpoint_update_all(ARMCPU
*cpu
)
5538 CPUARMState
*env
= &cpu
->env
;
5540 /* Completely clear out existing QEMU watchpoints and our array, to
5541 * avoid possible stale entries following migration load.
5543 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
5544 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
5546 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
5547 hw_watchpoint_update(cpu
, i
);
5551 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5554 ARMCPU
*cpu
= env_archcpu(env
);
5557 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
5558 * register reads and behaves as if values written are sign extended.
5559 * Bits [1:0] are RES0.
5561 value
= sextract64(value
, 0, 49) & ~3ULL;
5563 raw_write(env
, ri
, value
);
5564 hw_watchpoint_update(cpu
, i
);
5567 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5570 ARMCPU
*cpu
= env_archcpu(env
);
5573 raw_write(env
, ri
, value
);
5574 hw_watchpoint_update(cpu
, i
);
5577 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
5579 CPUARMState
*env
= &cpu
->env
;
5580 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
5581 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
5586 if (env
->cpu_breakpoint
[n
]) {
5587 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
5588 env
->cpu_breakpoint
[n
] = NULL
;
5591 if (!extract64(bcr
, 0, 1)) {
5592 /* E bit clear : watchpoint disabled */
5596 bt
= extract64(bcr
, 20, 4);
5599 case 4: /* unlinked address mismatch (reserved if AArch64) */
5600 case 5: /* linked address mismatch (reserved if AArch64) */
5601 qemu_log_mask(LOG_UNIMP
,
5602 "arm: address mismatch breakpoint types not implemented\n");
5604 case 0: /* unlinked address match */
5605 case 1: /* linked address match */
5607 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
5608 * we behave as if the register was sign extended. Bits [1:0] are
5609 * RES0. The BAS field is used to allow setting breakpoints on 16
5610 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
5611 * a bp will fire if the addresses covered by the bp and the addresses
5612 * covered by the insn overlap but the insn doesn't start at the
5613 * start of the bp address range. We choose to require the insn and
5614 * the bp to have the same address. The constraints on writing to
5615 * BAS enforced in dbgbcr_write mean we have only four cases:
5616 * 0b0000 => no breakpoint
5617 * 0b0011 => breakpoint on addr
5618 * 0b1100 => breakpoint on addr + 2
5619 * 0b1111 => breakpoint on addr
5620 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
5622 int bas
= extract64(bcr
, 5, 4);
5623 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
5632 case 2: /* unlinked context ID match */
5633 case 8: /* unlinked VMID match (reserved if no EL2) */
5634 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
5635 qemu_log_mask(LOG_UNIMP
,
5636 "arm: unlinked context breakpoint types not implemented\n");
5638 case 9: /* linked VMID match (reserved if no EL2) */
5639 case 11: /* linked context ID and VMID match (reserved if no EL2) */
5640 case 3: /* linked context ID match */
5642 /* We must generate no events for Linked context matches (unless
5643 * they are linked to by some other bp/wp, which is handled in
5644 * updates for the linking bp/wp). We choose to also generate no events
5645 * for reserved values.
5650 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
5653 void hw_breakpoint_update_all(ARMCPU
*cpu
)
5656 CPUARMState
*env
= &cpu
->env
;
5658 /* Completely clear out existing QEMU breakpoints and our array, to
5659 * avoid possible stale entries following migration load.
5661 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
5662 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
5664 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
5665 hw_breakpoint_update(cpu
, i
);
5669 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5672 ARMCPU
*cpu
= env_archcpu(env
);
5675 raw_write(env
, ri
, value
);
5676 hw_breakpoint_update(cpu
, i
);
5679 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5682 ARMCPU
*cpu
= env_archcpu(env
);
5685 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
5688 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
5689 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
5691 raw_write(env
, ri
, value
);
5692 hw_breakpoint_update(cpu
, i
);
5695 static void define_debug_regs(ARMCPU
*cpu
)
5697 /* Define v7 and v8 architectural debug registers.
5698 * These are just dummy implementations for now.
5701 int wrps
, brps
, ctx_cmps
;
5702 ARMCPRegInfo dbgdidr
= {
5703 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
5704 .access
= PL0_R
, .accessfn
= access_tda
,
5705 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
5708 /* Note that all these register fields hold "number of Xs minus 1". */
5709 brps
= extract32(cpu
->dbgdidr
, 24, 4);
5710 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
5711 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
5713 assert(ctx_cmps
<= brps
);
5715 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
5716 * of the debug registers such as number of breakpoints;
5717 * check that if they both exist then they agree.
5719 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
5720 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
5721 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
5722 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
5725 define_one_arm_cp_reg(cpu
, &dbgdidr
);
5726 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
5728 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
5729 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
5732 for (i
= 0; i
< brps
+ 1; i
++) {
5733 ARMCPRegInfo dbgregs
[] = {
5734 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
5735 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
5736 .access
= PL1_RW
, .accessfn
= access_tda
,
5737 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
5738 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
5740 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
5741 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
5742 .access
= PL1_RW
, .accessfn
= access_tda
,
5743 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
5744 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
5748 define_arm_cp_regs(cpu
, dbgregs
);
5751 for (i
= 0; i
< wrps
+ 1; i
++) {
5752 ARMCPRegInfo dbgregs
[] = {
5753 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
5754 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
5755 .access
= PL1_RW
, .accessfn
= access_tda
,
5756 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
5757 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
5759 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
5760 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
5761 .access
= PL1_RW
, .accessfn
= access_tda
,
5762 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
5763 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
5767 define_arm_cp_regs(cpu
, dbgregs
);
5771 /* We don't know until after realize whether there's a GICv3
5772 * attached, and that is what registers the gicv3 sysregs.
5773 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
5776 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5778 ARMCPU
*cpu
= env_archcpu(env
);
5779 uint64_t pfr1
= cpu
->id_pfr1
;
5781 if (env
->gicv3state
) {
5787 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5789 ARMCPU
*cpu
= env_archcpu(env
);
5790 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
5792 if (env
->gicv3state
) {
5798 /* Shared logic between LORID and the rest of the LOR* registers.
5799 * Secure state has already been delt with.
5801 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
5803 int el
= arm_current_el(env
);
5805 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
5806 return CP_ACCESS_TRAP_EL2
;
5808 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
5809 return CP_ACCESS_TRAP_EL3
;
5811 return CP_ACCESS_OK
;
5814 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5817 if (arm_is_secure_below_el3(env
)) {
5818 /* Access ok in secure mode. */
5819 return CP_ACCESS_OK
;
5821 return access_lor_ns(env
);
5824 static CPAccessResult
access_lor_other(CPUARMState
*env
,
5825 const ARMCPRegInfo
*ri
, bool isread
)
5827 if (arm_is_secure_below_el3(env
)) {
5828 /* Access denied in secure mode. */
5829 return CP_ACCESS_TRAP
;
5831 return access_lor_ns(env
);
5834 #ifdef TARGET_AARCH64
5835 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5838 int el
= arm_current_el(env
);
5841 arm_feature(env
, ARM_FEATURE_EL2
) &&
5842 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
5843 return CP_ACCESS_TRAP_EL2
;
5846 arm_feature(env
, ARM_FEATURE_EL3
) &&
5847 !(env
->cp15
.scr_el3
& SCR_APK
)) {
5848 return CP_ACCESS_TRAP_EL3
;
5850 return CP_ACCESS_OK
;
5853 static const ARMCPRegInfo pauth_reginfo
[] = {
5854 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5855 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
5856 .access
= PL1_RW
, .accessfn
= access_pauth
,
5857 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
5858 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5859 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
5860 .access
= PL1_RW
, .accessfn
= access_pauth
,
5861 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
5862 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5863 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
5864 .access
= PL1_RW
, .accessfn
= access_pauth
,
5865 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
5866 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5867 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
5868 .access
= PL1_RW
, .accessfn
= access_pauth
,
5869 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
5870 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5871 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
5872 .access
= PL1_RW
, .accessfn
= access_pauth
,
5873 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
5874 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5875 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
5876 .access
= PL1_RW
, .accessfn
= access_pauth
,
5877 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
5878 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5879 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
5880 .access
= PL1_RW
, .accessfn
= access_pauth
,
5881 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
5882 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5883 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
5884 .access
= PL1_RW
, .accessfn
= access_pauth
,
5885 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
5886 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5887 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
5888 .access
= PL1_RW
, .accessfn
= access_pauth
,
5889 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
5890 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5891 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
5892 .access
= PL1_RW
, .accessfn
= access_pauth
,
5893 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
5897 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5902 /* Success sets NZCV = 0000. */
5903 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
5905 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
5907 * ??? Failed, for unknown reasons in the crypto subsystem.
5908 * The best we can do is log the reason and return the
5909 * timed-out indication to the guest. There is no reason
5910 * we know to expect this failure to be transitory, so the
5911 * guest may well hang retrying the operation.
5913 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
5914 ri
->name
, error_get_pretty(err
));
5917 env
->ZF
= 0; /* NZCF = 0100 */
5923 /* We do not support re-seeding, so the two registers operate the same. */
5924 static const ARMCPRegInfo rndr_reginfo
[] = {
5925 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
5926 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
5927 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
5928 .access
= PL0_R
, .readfn
= rndr_readfn
},
5929 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
5930 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
5931 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
5932 .access
= PL0_R
, .readfn
= rndr_readfn
},
5937 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5940 int el
= arm_current_el(env
);
5943 uint64_t sctlr
= arm_sctlr(env
, el
);
5944 if (!(sctlr
& SCTLR_EnRCTX
)) {
5945 return CP_ACCESS_TRAP
;
5947 } else if (el
== 1) {
5948 uint64_t hcr
= arm_hcr_el2_eff(env
);
5950 return CP_ACCESS_TRAP_EL2
;
5953 return CP_ACCESS_OK
;
5956 static const ARMCPRegInfo predinv_reginfo
[] = {
5957 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
5958 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
5959 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5960 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
5961 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
5962 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5963 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
5964 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
5965 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5967 * Note the AArch32 opcodes have a different OPC1.
5969 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
5970 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
5971 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5972 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
5973 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
5974 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5975 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
5976 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
5977 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
5981 void register_cp_regs_for_features(ARMCPU
*cpu
)
5983 /* Register all the coprocessor registers based on feature bits */
5984 CPUARMState
*env
= &cpu
->env
;
5985 if (arm_feature(env
, ARM_FEATURE_M
)) {
5986 /* M profile has no coprocessor registers */
5990 define_arm_cp_regs(cpu
, cp_reginfo
);
5991 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
5992 /* Must go early as it is full of wildcards that may be
5993 * overridden by later definitions.
5995 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
5998 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5999 /* The ID registers all have impdef reset values */
6000 ARMCPRegInfo v6_idregs
[] = {
6001 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
6002 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6003 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6004 .resetvalue
= cpu
->id_pfr0
},
6005 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
6006 * the value of the GIC field until after we define these regs.
6008 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
6009 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
6010 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6011 .readfn
= id_pfr1_read
,
6012 .writefn
= arm_cp_write_ignore
},
6013 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
6014 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
6015 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6016 .resetvalue
= cpu
->id_dfr0
},
6017 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
6018 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
6019 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6020 .resetvalue
= cpu
->id_afr0
},
6021 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
6022 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
6023 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6024 .resetvalue
= cpu
->id_mmfr0
},
6025 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
6026 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
6027 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6028 .resetvalue
= cpu
->id_mmfr1
},
6029 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
6030 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
6031 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6032 .resetvalue
= cpu
->id_mmfr2
},
6033 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
6034 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
6035 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6036 .resetvalue
= cpu
->id_mmfr3
},
6037 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
6038 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6039 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6040 .resetvalue
= cpu
->isar
.id_isar0
},
6041 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
6042 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
6043 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6044 .resetvalue
= cpu
->isar
.id_isar1
},
6045 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
6046 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6047 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6048 .resetvalue
= cpu
->isar
.id_isar2
},
6049 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
6050 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
6051 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6052 .resetvalue
= cpu
->isar
.id_isar3
},
6053 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
6054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
6055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6056 .resetvalue
= cpu
->isar
.id_isar4
},
6057 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
6058 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
6059 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6060 .resetvalue
= cpu
->isar
.id_isar5
},
6061 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
6062 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
6063 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6064 .resetvalue
= cpu
->id_mmfr4
},
6065 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
6066 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
6067 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6068 .resetvalue
= cpu
->isar
.id_isar6
},
6071 define_arm_cp_regs(cpu
, v6_idregs
);
6072 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
6074 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
6076 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
6077 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
6079 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
6080 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
6081 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
6083 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
6084 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
6086 if (arm_feature(env
, ARM_FEATURE_V7
)) {
6087 /* v7 performance monitor control register: same implementor
6088 * field as main ID register, and we implement four counters in
6089 * addition to the cycle count register.
6091 unsigned int i
, pmcrn
= 4;
6092 ARMCPRegInfo pmcr
= {
6093 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6095 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6096 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6097 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6098 .raw_writefn
= raw_write
,
6100 ARMCPRegInfo pmcr64
= {
6101 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6102 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6103 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6105 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6106 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
),
6107 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6109 define_one_arm_cp_reg(cpu
, &pmcr
);
6110 define_one_arm_cp_reg(cpu
, &pmcr64
);
6111 for (i
= 0; i
< pmcrn
; i
++) {
6112 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6113 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6114 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6115 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6116 ARMCPRegInfo pmev_regs
[] = {
6117 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6118 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6119 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6120 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6121 .accessfn
= pmreg_access
},
6122 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6123 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6124 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6126 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6127 .raw_readfn
= pmevcntr_rawread
,
6128 .raw_writefn
= pmevcntr_rawwrite
},
6129 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6130 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6131 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6132 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6133 .accessfn
= pmreg_access
},
6134 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6135 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6136 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6138 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6139 .raw_writefn
= pmevtyper_rawwrite
},
6142 define_arm_cp_regs(cpu
, pmev_regs
);
6143 g_free(pmevcntr_name
);
6144 g_free(pmevcntr_el0_name
);
6145 g_free(pmevtyper_name
);
6146 g_free(pmevtyper_el0_name
);
6148 ARMCPRegInfo clidr
= {
6149 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
6150 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
6151 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
6153 define_one_arm_cp_reg(cpu
, &clidr
);
6154 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
6155 define_debug_regs(cpu
);
6157 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
6159 if (FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) >= 4 &&
6160 FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf) {
6161 ARMCPRegInfo v81_pmu_regs
[] = {
6162 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6163 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6164 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6165 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6166 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6167 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6168 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6169 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6172 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6174 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6175 /* AArch64 ID registers, which all have impdef reset values.
6176 * Note that within the ID register ranges the unused slots
6177 * must all RAZ, not UNDEF; future architecture versions may
6178 * define new registers here.
6180 ARMCPRegInfo v8_idregs
[] = {
6181 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
6182 * know the right value for the GIC field until after we
6183 * define these regs.
6185 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6186 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
6187 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6188 .readfn
= id_aa64pfr0_read
,
6189 .writefn
= arm_cp_write_ignore
},
6190 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6191 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
6192 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6193 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
6194 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6195 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
6196 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6198 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6199 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
6200 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6202 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6203 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
6204 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6205 /* At present, only SVEver == 0 is defined anyway. */
6207 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6208 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
6209 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6211 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6212 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
6213 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6215 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6216 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
6217 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6219 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6220 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
6221 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6222 .resetvalue
= cpu
->id_aa64dfr0
},
6223 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6224 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
6225 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6226 .resetvalue
= cpu
->id_aa64dfr1
},
6227 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6228 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
6229 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6231 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6232 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
6233 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6235 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6236 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
6237 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6238 .resetvalue
= cpu
->id_aa64afr0
},
6239 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6240 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
6241 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6242 .resetvalue
= cpu
->id_aa64afr1
},
6243 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6244 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
6245 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6247 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6248 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
6249 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6251 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
6252 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
6253 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6254 .resetvalue
= cpu
->isar
.id_aa64isar0
},
6255 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
6256 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
6257 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6258 .resetvalue
= cpu
->isar
.id_aa64isar1
},
6259 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6260 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
6261 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6263 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6264 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
6265 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6267 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6268 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
6269 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6271 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6272 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
6273 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6275 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6276 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
6277 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6279 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6280 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
6281 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6283 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6284 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6285 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6286 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
6287 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6288 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
6289 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6290 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
6291 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6292 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
6293 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6295 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6296 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
6297 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6299 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6300 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
6301 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6303 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6304 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
6305 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6307 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6308 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
6309 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6311 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6312 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
6313 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6315 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6316 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
6317 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6318 .resetvalue
= cpu
->isar
.mvfr0
},
6319 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6320 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
6321 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6322 .resetvalue
= cpu
->isar
.mvfr1
},
6323 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
6324 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
6325 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6326 .resetvalue
= cpu
->isar
.mvfr2
},
6327 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6328 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
6329 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6331 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6332 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
6333 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6335 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6336 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
6337 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6339 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6340 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
6341 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6343 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6344 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
6345 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6347 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
6348 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
6349 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6350 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
6351 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
6352 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
6353 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6354 .resetvalue
= cpu
->pmceid0
},
6355 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
6356 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
6357 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6358 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
6359 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
6360 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
6361 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6362 .resetvalue
= cpu
->pmceid1
},
6365 #ifdef CONFIG_USER_ONLY
6366 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
6367 { .name
= "ID_AA64PFR0_EL1",
6368 .exported_bits
= 0x000f000f00ff0000,
6369 .fixed_bits
= 0x0000000000000011 },
6370 { .name
= "ID_AA64PFR1_EL1",
6371 .exported_bits
= 0x00000000000000f0 },
6372 { .name
= "ID_AA64PFR*_EL1_RESERVED",
6374 { .name
= "ID_AA64ZFR0_EL1" },
6375 { .name
= "ID_AA64MMFR0_EL1",
6376 .fixed_bits
= 0x00000000ff000000 },
6377 { .name
= "ID_AA64MMFR1_EL1" },
6378 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
6380 { .name
= "ID_AA64DFR0_EL1",
6381 .fixed_bits
= 0x0000000000000006 },
6382 { .name
= "ID_AA64DFR1_EL1" },
6383 { .name
= "ID_AA64DFR*_EL1_RESERVED",
6385 { .name
= "ID_AA64AFR*",
6387 { .name
= "ID_AA64ISAR0_EL1",
6388 .exported_bits
= 0x00fffffff0fffff0 },
6389 { .name
= "ID_AA64ISAR1_EL1",
6390 .exported_bits
= 0x000000f0ffffffff },
6391 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
6393 REGUSERINFO_SENTINEL
6395 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
6397 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
6398 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
6399 !arm_feature(env
, ARM_FEATURE_EL2
)) {
6400 ARMCPRegInfo rvbar
= {
6401 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6402 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6403 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
6405 define_one_arm_cp_reg(cpu
, &rvbar
);
6407 define_arm_cp_regs(cpu
, v8_idregs
);
6408 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
6410 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6411 uint64_t vmpidr_def
= mpidr_read_val(env
);
6412 ARMCPRegInfo vpidr_regs
[] = {
6413 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
6414 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6415 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6416 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
6417 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
6418 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6419 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6420 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
6421 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6422 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
6423 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6424 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6425 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
6426 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
6427 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6428 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6430 .resetvalue
= vmpidr_def
,
6431 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
6434 define_arm_cp_regs(cpu
, vpidr_regs
);
6435 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
6436 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6437 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
6439 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
6440 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
6441 ARMCPRegInfo rvbar
= {
6442 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
6443 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
6444 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
6446 define_one_arm_cp_reg(cpu
, &rvbar
);
6449 /* If EL2 is missing but higher ELs are enabled, we need to
6450 * register the no_el2 reginfos.
6452 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6453 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
6454 * of MIDR_EL1 and MPIDR_EL1.
6456 ARMCPRegInfo vpidr_regs
[] = {
6457 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6458 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6459 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6460 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
6461 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6462 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6463 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6464 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6465 .type
= ARM_CP_NO_RAW
,
6466 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
6469 define_arm_cp_regs(cpu
, vpidr_regs
);
6470 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
6471 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6472 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
6476 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6477 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
6478 ARMCPRegInfo el3_regs
[] = {
6479 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6480 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
6481 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
6482 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6483 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
6485 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6486 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
6487 .resetvalue
= cpu
->reset_sctlr
},
6491 define_arm_cp_regs(cpu
, el3_regs
);
6493 /* The behaviour of NSACR is sufficiently various that we don't
6494 * try to describe it in a single reginfo:
6495 * if EL3 is 64 bit, then trap to EL3 from S EL1,
6496 * reads as constant 0xc00 from NS EL1 and NS EL2
6497 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
6498 * if v7 without EL3, register doesn't exist
6499 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
6501 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6502 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6503 ARMCPRegInfo nsacr
= {
6504 .name
= "NSACR", .type
= ARM_CP_CONST
,
6505 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6506 .access
= PL1_RW
, .accessfn
= nsacr_access
,
6509 define_one_arm_cp_reg(cpu
, &nsacr
);
6511 ARMCPRegInfo nsacr
= {
6513 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6514 .access
= PL3_RW
| PL1_R
,
6516 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
6518 define_one_arm_cp_reg(cpu
, &nsacr
);
6521 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6522 ARMCPRegInfo nsacr
= {
6523 .name
= "NSACR", .type
= ARM_CP_CONST
,
6524 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6528 define_one_arm_cp_reg(cpu
, &nsacr
);
6532 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
6533 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6534 /* PMSAv6 not implemented */
6535 assert(arm_feature(env
, ARM_FEATURE_V7
));
6536 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6537 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
6539 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
6542 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6543 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
6544 /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
6545 if (FIELD_EX32(cpu
->id_mmfr4
, ID_MMFR4
, HPDS
) != 0) {
6546 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
6549 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
6550 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
6552 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
6553 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
6555 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
6556 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
6558 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
6559 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
6561 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
6562 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
6564 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
6565 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
6567 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
6568 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
6570 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6571 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
6573 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6574 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
6576 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
6577 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
6579 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
6580 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
6582 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
6583 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
6584 * be read-only (ie write causes UNDEF exception).
6587 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
6588 /* Pre-v8 MIDR space.
6589 * Note that the MIDR isn't a simple constant register because
6590 * of the TI925 behaviour where writes to another register can
6591 * cause the MIDR value to change.
6593 * Unimplemented registers in the c15 0 0 0 space default to
6594 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
6595 * and friends override accordingly.
6598 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
6599 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
6600 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
6601 .readfn
= midr_read
,
6602 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6603 .type
= ARM_CP_OVERRIDE
},
6604 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
6606 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
6607 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6609 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
6610 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6612 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
6613 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6615 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
6616 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6618 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
6619 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6622 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
6623 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6624 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
6625 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
6626 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6627 .readfn
= midr_read
},
6628 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
6629 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6630 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6631 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6632 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6633 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
6634 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6635 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6636 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
6637 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
6640 ARMCPRegInfo id_cp_reginfo
[] = {
6641 /* These are common to v8 and pre-v8 */
6643 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
6644 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6645 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
6646 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
6647 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
6648 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6649 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
6651 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
6652 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6655 /* TLBTR is specific to VMSA */
6656 ARMCPRegInfo id_tlbtr_reginfo
= {
6658 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
6659 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
6661 /* MPUIR is specific to PMSA V6+ */
6662 ARMCPRegInfo id_mpuir_reginfo
= {
6664 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6665 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6666 .resetvalue
= cpu
->pmsav7_dregion
<< 8
6668 ARMCPRegInfo crn0_wi_reginfo
= {
6669 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
6670 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
6671 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
6673 #ifdef CONFIG_USER_ONLY
6674 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
6675 { .name
= "MIDR_EL1",
6676 .exported_bits
= 0x00000000ffffffff },
6677 { .name
= "REVIDR_EL1" },
6678 REGUSERINFO_SENTINEL
6680 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
6682 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
6683 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6685 /* Register the blanket "writes ignored" value first to cover the
6686 * whole space. Then update the specific ID registers to allow write
6687 * access, so that they ignore writes rather than causing them to
6690 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
6691 for (r
= id_pre_v8_midr_cp_reginfo
;
6692 r
->type
!= ARM_CP_SENTINEL
; r
++) {
6695 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
6698 id_mpuir_reginfo
.access
= PL1_RW
;
6699 id_tlbtr_reginfo
.access
= PL1_RW
;
6701 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6702 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
6704 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
6706 define_arm_cp_regs(cpu
, id_cp_reginfo
);
6707 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
6708 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
6709 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
6710 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
6714 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
6715 ARMCPRegInfo mpidr_cp_reginfo
[] = {
6716 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6717 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
6718 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
6721 #ifdef CONFIG_USER_ONLY
6722 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
6723 { .name
= "MPIDR_EL1",
6724 .fixed_bits
= 0x0000000080000000 },
6725 REGUSERINFO_SENTINEL
6727 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
6729 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
6732 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
6733 ARMCPRegInfo auxcr_reginfo
[] = {
6734 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6735 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
6736 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
6737 .resetvalue
= cpu
->reset_auxcr
},
6738 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6739 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
6740 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6742 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6743 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
6744 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6748 define_arm_cp_regs(cpu
, auxcr_reginfo
);
6749 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6750 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
6751 ARMCPRegInfo hactlr2_reginfo
= {
6752 .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
6753 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
6754 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6757 define_one_arm_cp_reg(cpu
, &hactlr2_reginfo
);
6761 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
6763 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
6764 * There are two flavours:
6765 * (1) older 32-bit only cores have a simple 32-bit CBAR
6766 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
6767 * 32-bit register visible to AArch32 at a different encoding
6768 * to the "flavour 1" register and with the bits rearranged to
6769 * be able to squash a 64-bit address into the 32-bit view.
6770 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
6771 * in future if we support AArch32-only configs of some of the
6772 * AArch64 cores we might need to add a specific feature flag
6773 * to indicate cores with "flavour 2" CBAR.
6775 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6776 /* 32 bit view is [31:18] 0...0 [43:32]. */
6777 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
6778 | extract64(cpu
->reset_cbar
, 32, 12);
6779 ARMCPRegInfo cbar_reginfo
[] = {
6781 .type
= ARM_CP_CONST
,
6782 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
6783 .access
= PL1_R
, .resetvalue
= cbar32
},
6784 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6785 .type
= ARM_CP_CONST
,
6786 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
6787 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
6790 /* We don't implement a r/w 64 bit CBAR currently */
6791 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
6792 define_arm_cp_regs(cpu
, cbar_reginfo
);
6794 ARMCPRegInfo cbar
= {
6796 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
6797 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
6798 .fieldoffset
= offsetof(CPUARMState
,
6799 cp15
.c15_config_base_address
)
6801 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
6802 cbar
.access
= PL1_R
;
6803 cbar
.fieldoffset
= 0;
6804 cbar
.type
= ARM_CP_CONST
;
6806 define_one_arm_cp_reg(cpu
, &cbar
);
6810 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
6811 ARMCPRegInfo vbar_cp_reginfo
[] = {
6812 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
6813 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
6814 .access
= PL1_RW
, .writefn
= vbar_write
,
6815 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
6816 offsetof(CPUARMState
, cp15
.vbar_ns
) },
6820 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
6823 /* Generic registers whose values depend on the implementation */
6825 ARMCPRegInfo sctlr
= {
6826 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
6827 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6829 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
6830 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
6831 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
6832 .raw_writefn
= raw_write
,
6834 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6835 /* Normally we would always end the TB on an SCTLR write, but Linux
6836 * arch/arm/mach-pxa/sleep.S expects two instructions following
6837 * an MMU enable to execute from cache. Imitate this behaviour.
6839 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
6841 define_one_arm_cp_reg(cpu
, &sctlr
);
6844 if (cpu_isar_feature(aa64_lor
, cpu
)) {
6846 * A trivial implementation of ARMv8.1-LOR leaves all of these
6847 * registers fixed at 0, which indicates that there are zero
6848 * supported Limited Ordering regions.
6850 static const ARMCPRegInfo lor_reginfo
[] = {
6851 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6852 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6853 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6854 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6855 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6856 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6857 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6858 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6859 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6860 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6861 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6862 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6863 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6864 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6865 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6866 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6867 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6868 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6869 .access
= PL1_R
, .accessfn
= access_lorid
,
6870 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6873 define_arm_cp_regs(cpu
, lor_reginfo
);
6876 if (cpu_isar_feature(aa64_sve
, cpu
)) {
6877 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
6878 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6879 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
6881 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
6883 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6884 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
6888 #ifdef TARGET_AARCH64
6889 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
6890 define_arm_cp_regs(cpu
, pauth_reginfo
);
6892 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
6893 define_arm_cp_regs(cpu
, rndr_reginfo
);
6898 * While all v8.0 cpus support aarch64, QEMU does have configurations
6899 * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
6900 * which will set ID_ISAR6.
6902 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
6903 ? cpu_isar_feature(aa64_predinv
, cpu
)
6904 : cpu_isar_feature(aa32_predinv
, cpu
)) {
6905 define_arm_cp_regs(cpu
, predinv_reginfo
);
6909 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
6911 CPUState
*cs
= CPU(cpu
);
6912 CPUARMState
*env
= &cpu
->env
;
6914 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6915 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
6916 aarch64_fpu_gdb_set_reg
,
6917 34, "aarch64-fpu.xml", 0);
6918 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
6919 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6920 51, "arm-neon.xml", 0);
6921 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
6922 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6923 35, "arm-vfp3.xml", 0);
6924 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
6925 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
6926 19, "arm-vfp.xml", 0);
6928 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
6929 arm_gen_dynamic_xml(cs
),
6930 "system-registers.xml", 0);
6933 /* Sort alphabetically by type name, except for "any". */
6934 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
6936 ObjectClass
*class_a
= (ObjectClass
*)a
;
6937 ObjectClass
*class_b
= (ObjectClass
*)b
;
6938 const char *name_a
, *name_b
;
6940 name_a
= object_class_get_name(class_a
);
6941 name_b
= object_class_get_name(class_b
);
6942 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
6944 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
6947 return strcmp(name_a
, name_b
);
6951 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
6953 ObjectClass
*oc
= data
;
6954 const char *typename
;
6957 typename
= object_class_get_name(oc
);
6958 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
6959 qemu_printf(" %s\n", name
);
6963 void arm_cpu_list(void)
6967 list
= object_class_get_list(TYPE_ARM_CPU
, false);
6968 list
= g_slist_sort(list
, arm_cpu_list_compare
);
6969 qemu_printf("Available CPUs:\n");
6970 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
6974 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
6976 ObjectClass
*oc
= data
;
6977 CpuDefinitionInfoList
**cpu_list
= user_data
;
6978 CpuDefinitionInfoList
*entry
;
6979 CpuDefinitionInfo
*info
;
6980 const char *typename
;
6982 typename
= object_class_get_name(oc
);
6983 info
= g_malloc0(sizeof(*info
));
6984 info
->name
= g_strndup(typename
,
6985 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
6986 info
->q_typename
= g_strdup(typename
);
6988 entry
= g_malloc0(sizeof(*entry
));
6989 entry
->value
= info
;
6990 entry
->next
= *cpu_list
;
6994 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
6996 CpuDefinitionInfoList
*cpu_list
= NULL
;
6999 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7000 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
7006 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
7007 void *opaque
, int state
, int secstate
,
7008 int crm
, int opc1
, int opc2
,
7011 /* Private utility function for define_one_arm_cp_reg_with_opaque():
7012 * add a single reginfo struct to the hash table.
7014 uint32_t *key
= g_new(uint32_t, 1);
7015 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
7016 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
7017 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
7019 r2
->name
= g_strdup(name
);
7020 /* Reset the secure state to the specific incoming state. This is
7021 * necessary as the register may have been defined with both states.
7023 r2
->secure
= secstate
;
7025 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7026 /* Register is banked (using both entries in array).
7027 * Overwriting fieldoffset as the array is only used to define
7028 * banked registers but later only fieldoffset is used.
7030 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
7033 if (state
== ARM_CP_STATE_AA32
) {
7034 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7035 /* If the register is banked then we don't need to migrate or
7036 * reset the 32-bit instance in certain cases:
7038 * 1) If the register has both 32-bit and 64-bit instances then we
7039 * can count on the 64-bit instance taking care of the
7041 * 2) If ARMv8 is enabled then we can count on a 64-bit version
7042 * taking care of the secure bank. This requires that separate
7043 * 32 and 64-bit definitions are provided.
7045 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
7046 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
7047 r2
->type
|= ARM_CP_ALIAS
;
7049 } else if ((secstate
!= r
->secure
) && !ns
) {
7050 /* The register is not banked so we only want to allow migration of
7051 * the non-secure instance.
7053 r2
->type
|= ARM_CP_ALIAS
;
7056 if (r
->state
== ARM_CP_STATE_BOTH
) {
7057 /* We assume it is a cp15 register if the .cp field is left unset.
7063 #ifdef HOST_WORDS_BIGENDIAN
7064 if (r2
->fieldoffset
) {
7065 r2
->fieldoffset
+= sizeof(uint32_t);
7070 if (state
== ARM_CP_STATE_AA64
) {
7071 /* To allow abbreviation of ARMCPRegInfo
7072 * definitions, we treat cp == 0 as equivalent to
7073 * the value for "standard guest-visible sysreg".
7074 * STATE_BOTH definitions are also always "standard
7075 * sysreg" in their AArch64 view (the .cp value may
7076 * be non-zero for the benefit of the AArch32 view).
7078 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
7079 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
7081 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
7082 r2
->opc0
, opc1
, opc2
);
7084 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
7087 r2
->opaque
= opaque
;
7089 /* reginfo passed to helpers is correct for the actual access,
7090 * and is never ARM_CP_STATE_BOTH:
7093 /* Make sure reginfo passed to helpers for wildcarded regs
7094 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
7099 /* By convention, for wildcarded registers only the first
7100 * entry is used for migration; the others are marked as
7101 * ALIAS so we don't try to transfer the register
7102 * multiple times. Special registers (ie NOP/WFI) are
7103 * never migratable and not even raw-accessible.
7105 if ((r
->type
& ARM_CP_SPECIAL
)) {
7106 r2
->type
|= ARM_CP_NO_RAW
;
7108 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
7109 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
7110 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
7111 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
7114 /* Check that raw accesses are either forbidden or handled. Note that
7115 * we can't assert this earlier because the setup of fieldoffset for
7116 * banked registers has to be done first.
7118 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
7119 assert(!raw_accessors_invalid(r2
));
7122 /* Overriding of an existing definition must be explicitly
7125 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
7126 ARMCPRegInfo
*oldreg
;
7127 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
7128 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
7129 fprintf(stderr
, "Register redefined: cp=%d %d bit "
7130 "crn=%d crm=%d opc1=%d opc2=%d, "
7131 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
7132 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
7133 oldreg
->name
, r2
->name
);
7134 g_assert_not_reached();
7137 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
7141 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
7142 const ARMCPRegInfo
*r
, void *opaque
)
7144 /* Define implementations of coprocessor registers.
7145 * We store these in a hashtable because typically
7146 * there are less than 150 registers in a space which
7147 * is 16*16*16*8*8 = 262144 in size.
7148 * Wildcarding is supported for the crm, opc1 and opc2 fields.
7149 * If a register is defined twice then the second definition is
7150 * used, so this can be used to define some generic registers and
7151 * then override them with implementation specific variations.
7152 * At least one of the original and the second definition should
7153 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
7154 * against accidental use.
7156 * The state field defines whether the register is to be
7157 * visible in the AArch32 or AArch64 execution state. If the
7158 * state is set to ARM_CP_STATE_BOTH then we synthesise a
7159 * reginfo structure for the AArch32 view, which sees the lower
7160 * 32 bits of the 64 bit register.
7162 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
7163 * be wildcarded. AArch64 registers are always considered to be 64
7164 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
7165 * the register, if any.
7167 int crm
, opc1
, opc2
, state
;
7168 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
7169 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
7170 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
7171 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
7172 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
7173 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
7174 /* 64 bit registers have only CRm and Opc1 fields */
7175 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
7176 /* op0 only exists in the AArch64 encodings */
7177 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
7178 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
7179 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
7180 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
7181 * encodes a minimum access level for the register. We roll this
7182 * runtime check into our general permission check code, so check
7183 * here that the reginfo's specified permissions are strict enough
7184 * to encompass the generic architectural permission check.
7186 if (r
->state
!= ARM_CP_STATE_AA32
) {
7190 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
7191 mask
= PL0U_R
| PL1_RW
;
7206 /* unallocated encoding, so not possible */
7214 /* min_EL EL1, secure mode only (we don't check the latter) */
7218 /* broken reginfo with out-of-range opc1 */
7222 /* assert our permissions are not too lax (stricter is fine) */
7223 assert((r
->access
& ~mask
) == 0);
7226 /* Check that the register definition has enough info to handle
7227 * reads and writes if they are permitted.
7229 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
7230 if (r
->access
& PL3_R
) {
7231 assert((r
->fieldoffset
||
7232 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
7235 if (r
->access
& PL3_W
) {
7236 assert((r
->fieldoffset
||
7237 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
7241 /* Bad type field probably means missing sentinel at end of reg list */
7242 assert(cptype_valid(r
->type
));
7243 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
7244 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
7245 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
7246 for (state
= ARM_CP_STATE_AA32
;
7247 state
<= ARM_CP_STATE_AA64
; state
++) {
7248 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
7251 if (state
== ARM_CP_STATE_AA32
) {
7252 /* Under AArch32 CP registers can be common
7253 * (same for secure and non-secure world) or banked.
7257 switch (r
->secure
) {
7258 case ARM_CP_SECSTATE_S
:
7259 case ARM_CP_SECSTATE_NS
:
7260 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7261 r
->secure
, crm
, opc1
, opc2
,
7265 name
= g_strdup_printf("%s_S", r
->name
);
7266 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7268 crm
, opc1
, opc2
, name
);
7270 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7272 crm
, opc1
, opc2
, r
->name
);
7276 /* AArch64 registers get mapped to non-secure instance
7278 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7280 crm
, opc1
, opc2
, r
->name
);
7288 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
7289 const ARMCPRegInfo
*regs
, void *opaque
)
7291 /* Define a whole list of registers */
7292 const ARMCPRegInfo
*r
;
7293 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7294 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
7299 * Modify ARMCPRegInfo for access from userspace.
7301 * This is a data driven modification directed by
7302 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
7303 * user-space cannot alter any values and dynamic values pertaining to
7304 * execution state are hidden from user space view anyway.
7306 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
7308 const ARMCPRegUserSpaceInfo
*m
;
7311 for (m
= mods
; m
->name
; m
++) {
7312 GPatternSpec
*pat
= NULL
;
7314 pat
= g_pattern_spec_new(m
->name
);
7316 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7317 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
7318 r
->type
= ARM_CP_CONST
;
7322 } else if (strcmp(r
->name
, m
->name
) == 0) {
7323 r
->type
= ARM_CP_CONST
;
7325 r
->resetvalue
&= m
->exported_bits
;
7326 r
->resetvalue
|= m
->fixed_bits
;
7331 g_pattern_spec_free(pat
);
7336 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
7338 return g_hash_table_lookup(cpregs
, &encoded_cp
);
7341 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7344 /* Helper coprocessor write function for write-ignore registers */
7347 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7349 /* Helper coprocessor write function for read-as-zero registers */
7353 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
7355 /* Helper coprocessor reset function for do-nothing-on-reset registers */
7358 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
7360 /* Return true if it is not valid for us to switch to
7361 * this CPU mode (ie all the UNPREDICTABLE cases in
7362 * the ARM ARM CPSRWriteByInstr pseudocode).
7365 /* Changes to or from Hyp via MSR and CPS are illegal. */
7366 if (write_type
== CPSRWriteByInstr
&&
7367 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
7368 mode
== ARM_CPU_MODE_HYP
)) {
7373 case ARM_CPU_MODE_USR
:
7375 case ARM_CPU_MODE_SYS
:
7376 case ARM_CPU_MODE_SVC
:
7377 case ARM_CPU_MODE_ABT
:
7378 case ARM_CPU_MODE_UND
:
7379 case ARM_CPU_MODE_IRQ
:
7380 case ARM_CPU_MODE_FIQ
:
7381 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
7382 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
7384 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
7385 * and CPS are treated as illegal mode changes.
7387 if (write_type
== CPSRWriteByInstr
&&
7388 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
7389 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
7393 case ARM_CPU_MODE_HYP
:
7394 return !arm_feature(env
, ARM_FEATURE_EL2
)
7395 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
7396 case ARM_CPU_MODE_MON
:
7397 return arm_current_el(env
) < 3;
7403 uint32_t cpsr_read(CPUARMState
*env
)
7406 ZF
= (env
->ZF
== 0);
7407 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
7408 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
7409 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
7410 | ((env
->condexec_bits
& 0xfc) << 8)
7411 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
7414 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
7415 CPSRWriteType write_type
)
7417 uint32_t changed_daif
;
7419 if (mask
& CPSR_NZCV
) {
7420 env
->ZF
= (~val
) & CPSR_Z
;
7422 env
->CF
= (val
>> 29) & 1;
7423 env
->VF
= (val
<< 3) & 0x80000000;
7426 env
->QF
= ((val
& CPSR_Q
) != 0);
7428 env
->thumb
= ((val
& CPSR_T
) != 0);
7429 if (mask
& CPSR_IT_0_1
) {
7430 env
->condexec_bits
&= ~3;
7431 env
->condexec_bits
|= (val
>> 25) & 3;
7433 if (mask
& CPSR_IT_2_7
) {
7434 env
->condexec_bits
&= 3;
7435 env
->condexec_bits
|= (val
>> 8) & 0xfc;
7437 if (mask
& CPSR_GE
) {
7438 env
->GE
= (val
>> 16) & 0xf;
7441 /* In a V7 implementation that includes the security extensions but does
7442 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
7443 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
7444 * bits respectively.
7446 * In a V8 implementation, it is permitted for privileged software to
7447 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
7449 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
7450 arm_feature(env
, ARM_FEATURE_EL3
) &&
7451 !arm_feature(env
, ARM_FEATURE_EL2
) &&
7452 !arm_is_secure(env
)) {
7454 changed_daif
= (env
->daif
^ val
) & mask
;
7456 if (changed_daif
& CPSR_A
) {
7457 /* Check to see if we are allowed to change the masking of async
7458 * abort exceptions from a non-secure state.
7460 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
7461 qemu_log_mask(LOG_GUEST_ERROR
,
7462 "Ignoring attempt to switch CPSR_A flag from "
7463 "non-secure world with SCR.AW bit clear\n");
7468 if (changed_daif
& CPSR_F
) {
7469 /* Check to see if we are allowed to change the masking of FIQ
7470 * exceptions from a non-secure state.
7472 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
7473 qemu_log_mask(LOG_GUEST_ERROR
,
7474 "Ignoring attempt to switch CPSR_F flag from "
7475 "non-secure world with SCR.FW bit clear\n");
7479 /* Check whether non-maskable FIQ (NMFI) support is enabled.
7480 * If this bit is set software is not allowed to mask
7481 * FIQs, but is allowed to set CPSR_F to 0.
7483 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
7485 qemu_log_mask(LOG_GUEST_ERROR
,
7486 "Ignoring attempt to enable CPSR_F flag "
7487 "(non-maskable FIQ [NMFI] support enabled)\n");
7493 env
->daif
&= ~(CPSR_AIF
& mask
);
7494 env
->daif
|= val
& CPSR_AIF
& mask
;
7496 if (write_type
!= CPSRWriteRaw
&&
7497 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
7498 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
7499 /* Note that we can only get here in USR mode if this is a
7500 * gdb stub write; for this case we follow the architectural
7501 * behaviour for guest writes in USR mode of ignoring an attempt
7502 * to switch mode. (Those are caught by translate.c for writes
7503 * triggered by guest instructions.)
7506 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
7507 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
7508 * v7, and has defined behaviour in v8:
7509 * + leave CPSR.M untouched
7510 * + allow changes to the other CPSR fields
7512 * For user changes via the GDB stub, we don't set PSTATE.IL,
7513 * as this would be unnecessarily harsh for a user error.
7516 if (write_type
!= CPSRWriteByGDBStub
&&
7517 arm_feature(env
, ARM_FEATURE_V8
)) {
7521 qemu_log_mask(LOG_GUEST_ERROR
,
7522 "Illegal AArch32 mode switch attempt from %s to %s\n",
7523 aarch32_mode_name(env
->uncached_cpsr
),
7524 aarch32_mode_name(val
));
7526 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
7527 write_type
== CPSRWriteExceptionReturn
?
7528 "Exception return from AArch32" :
7529 "AArch32 mode switch from",
7530 aarch32_mode_name(env
->uncached_cpsr
),
7531 aarch32_mode_name(val
), env
->regs
[15]);
7532 switch_mode(env
, val
& CPSR_M
);
7535 mask
&= ~CACHED_CPSR_BITS
;
7536 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
7539 /* Sign/zero extend */
7540 uint32_t HELPER(sxtb16
)(uint32_t x
)
7543 res
= (uint16_t)(int8_t)x
;
7544 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
7548 uint32_t HELPER(uxtb16
)(uint32_t x
)
7551 res
= (uint16_t)(uint8_t)x
;
7552 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
7556 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
7560 if (num
== INT_MIN
&& den
== -1)
7565 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
7572 uint32_t HELPER(rbit
)(uint32_t x
)
7577 #ifdef CONFIG_USER_ONLY
7579 static void switch_mode(CPUARMState
*env
, int mode
)
7581 ARMCPU
*cpu
= env_archcpu(env
);
7583 if (mode
!= ARM_CPU_MODE_USR
) {
7584 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
7588 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7589 uint32_t cur_el
, bool secure
)
7594 void aarch64_sync_64_to_32(CPUARMState
*env
)
7596 g_assert_not_reached();
7601 static void switch_mode(CPUARMState
*env
, int mode
)
7606 old_mode
= env
->uncached_cpsr
& CPSR_M
;
7607 if (mode
== old_mode
)
7610 if (old_mode
== ARM_CPU_MODE_FIQ
) {
7611 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7612 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
7613 } else if (mode
== ARM_CPU_MODE_FIQ
) {
7614 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7615 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
7618 i
= bank_number(old_mode
);
7619 env
->banked_r13
[i
] = env
->regs
[13];
7620 env
->banked_spsr
[i
] = env
->spsr
;
7622 i
= bank_number(mode
);
7623 env
->regs
[13] = env
->banked_r13
[i
];
7624 env
->spsr
= env
->banked_spsr
[i
];
7626 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
7627 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
7630 /* Physical Interrupt Target EL Lookup Table
7632 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
7634 * The below multi-dimensional table is used for looking up the target
7635 * exception level given numerous condition criteria. Specifically, the
7636 * target EL is based on SCR and HCR routing controls as well as the
7637 * currently executing EL and secure state.
7640 * target_el_table[2][2][2][2][2][4]
7641 * | | | | | +--- Current EL
7642 * | | | | +------ Non-secure(0)/Secure(1)
7643 * | | | +--------- HCR mask override
7644 * | | +------------ SCR exec state control
7645 * | +--------------- SCR mask override
7646 * +------------------ 32-bit(0)/64-bit(1) EL3
7648 * The table values are as such:
7652 * The ARM ARM target EL table includes entries indicating that an "exception
7653 * is not taken". The two cases where this is applicable are:
7654 * 1) An exception is taken from EL3 but the SCR does not have the exception
7656 * 2) An exception is taken from EL2 but the HCR does not have the exception
7658 * In these two cases, the below table contain a target of EL1. This value is
7659 * returned as it is expected that the consumer of the table data will check
7660 * for "target EL >= current EL" to ensure the exception is not taken.
7664 * BIT IRQ IMO Non-secure Secure
7665 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
7667 static const int8_t target_el_table
[2][2][2][2][2][4] = {
7668 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7669 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
7670 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7671 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
7672 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7673 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
7674 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7675 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
7676 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
7677 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
7678 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
7679 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
7680 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7681 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
7682 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7683 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
7687 * Determine the target EL for physical exceptions
7689 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7690 uint32_t cur_el
, bool secure
)
7692 CPUARMState
*env
= cs
->env_ptr
;
7697 /* Is the highest EL AArch64? */
7698 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
7701 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7702 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
7704 /* Either EL2 is the highest EL (and so the EL2 register width
7705 * is given by is64); or there is no EL2 or EL3, in which case
7706 * the value of 'rw' does not affect the table lookup anyway.
7711 hcr_el2
= arm_hcr_el2_eff(env
);
7714 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
7715 hcr
= hcr_el2
& HCR_IMO
;
7718 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
7719 hcr
= hcr_el2
& HCR_FMO
;
7722 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
7723 hcr
= hcr_el2
& HCR_AMO
;
7727 /* Perform a table-lookup for the target EL given the current state */
7728 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
7730 assert(target_el
> 0);
7735 void arm_log_exception(int idx
)
7737 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
7738 const char *exc
= NULL
;
7739 static const char * const excnames
[] = {
7740 [EXCP_UDEF
] = "Undefined Instruction",
7742 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
7743 [EXCP_DATA_ABORT
] = "Data Abort",
7746 [EXCP_BKPT
] = "Breakpoint",
7747 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
7748 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
7749 [EXCP_HVC
] = "Hypervisor Call",
7750 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
7751 [EXCP_SMC
] = "Secure Monitor Call",
7752 [EXCP_VIRQ
] = "Virtual IRQ",
7753 [EXCP_VFIQ
] = "Virtual FIQ",
7754 [EXCP_SEMIHOST
] = "Semihosting call",
7755 [EXCP_NOCP
] = "v7M NOCP UsageFault",
7756 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
7757 [EXCP_STKOF
] = "v8M STKOF UsageFault",
7758 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
7759 [EXCP_LSERR
] = "v8M LSERR UsageFault",
7760 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
7763 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
7764 exc
= excnames
[idx
];
7769 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
7774 * Function used to synchronize QEMU's AArch64 register set with AArch32
7775 * register set. This is necessary when switching between AArch32 and AArch64
7778 void aarch64_sync_32_to_64(CPUARMState
*env
)
7781 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7783 /* We can blanket copy R[0:7] to X[0:7] */
7784 for (i
= 0; i
< 8; i
++) {
7785 env
->xregs
[i
] = env
->regs
[i
];
7789 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7790 * Otherwise, they come from the banked user regs.
7792 if (mode
== ARM_CPU_MODE_FIQ
) {
7793 for (i
= 8; i
< 13; i
++) {
7794 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7797 for (i
= 8; i
< 13; i
++) {
7798 env
->xregs
[i
] = env
->regs
[i
];
7803 * Registers x13-x23 are the various mode SP and FP registers. Registers
7804 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7805 * from the mode banked register.
7807 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7808 env
->xregs
[13] = env
->regs
[13];
7809 env
->xregs
[14] = env
->regs
[14];
7811 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7812 /* HYP is an exception in that it is copied from r14 */
7813 if (mode
== ARM_CPU_MODE_HYP
) {
7814 env
->xregs
[14] = env
->regs
[14];
7816 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
7820 if (mode
== ARM_CPU_MODE_HYP
) {
7821 env
->xregs
[15] = env
->regs
[13];
7823 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7826 if (mode
== ARM_CPU_MODE_IRQ
) {
7827 env
->xregs
[16] = env
->regs
[14];
7828 env
->xregs
[17] = env
->regs
[13];
7830 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
7831 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7834 if (mode
== ARM_CPU_MODE_SVC
) {
7835 env
->xregs
[18] = env
->regs
[14];
7836 env
->xregs
[19] = env
->regs
[13];
7838 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
7839 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7842 if (mode
== ARM_CPU_MODE_ABT
) {
7843 env
->xregs
[20] = env
->regs
[14];
7844 env
->xregs
[21] = env
->regs
[13];
7846 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
7847 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
7850 if (mode
== ARM_CPU_MODE_UND
) {
7851 env
->xregs
[22] = env
->regs
[14];
7852 env
->xregs
[23] = env
->regs
[13];
7854 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
7855 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
7859 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7860 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7861 * FIQ bank for r8-r14.
7863 if (mode
== ARM_CPU_MODE_FIQ
) {
7864 for (i
= 24; i
< 31; i
++) {
7865 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
7868 for (i
= 24; i
< 29; i
++) {
7869 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
7871 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
7872 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
7875 env
->pc
= env
->regs
[15];
7879 * Function used to synchronize QEMU's AArch32 register set with AArch64
7880 * register set. This is necessary when switching between AArch32 and AArch64
7883 void aarch64_sync_64_to_32(CPUARMState
*env
)
7886 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7888 /* We can blanket copy X[0:7] to R[0:7] */
7889 for (i
= 0; i
< 8; i
++) {
7890 env
->regs
[i
] = env
->xregs
[i
];
7894 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
7895 * Otherwise, we copy x8-x12 into the banked user regs.
7897 if (mode
== ARM_CPU_MODE_FIQ
) {
7898 for (i
= 8; i
< 13; i
++) {
7899 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
7902 for (i
= 8; i
< 13; i
++) {
7903 env
->regs
[i
] = env
->xregs
[i
];
7908 * Registers r13 & r14 depend on the current mode.
7909 * If we are in a given mode, we copy the corresponding x registers to r13
7910 * and r14. Otherwise, we copy the x register to the banked r13 and r14
7913 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7914 env
->regs
[13] = env
->xregs
[13];
7915 env
->regs
[14] = env
->xregs
[14];
7917 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
7920 * HYP is an exception in that it does not have its own banked r14 but
7921 * shares the USR r14
7923 if (mode
== ARM_CPU_MODE_HYP
) {
7924 env
->regs
[14] = env
->xregs
[14];
7926 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
7930 if (mode
== ARM_CPU_MODE_HYP
) {
7931 env
->regs
[13] = env
->xregs
[15];
7933 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
7936 if (mode
== ARM_CPU_MODE_IRQ
) {
7937 env
->regs
[14] = env
->xregs
[16];
7938 env
->regs
[13] = env
->xregs
[17];
7940 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
7941 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
7944 if (mode
== ARM_CPU_MODE_SVC
) {
7945 env
->regs
[14] = env
->xregs
[18];
7946 env
->regs
[13] = env
->xregs
[19];
7948 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
7949 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
7952 if (mode
== ARM_CPU_MODE_ABT
) {
7953 env
->regs
[14] = env
->xregs
[20];
7954 env
->regs
[13] = env
->xregs
[21];
7956 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
7957 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
7960 if (mode
== ARM_CPU_MODE_UND
) {
7961 env
->regs
[14] = env
->xregs
[22];
7962 env
->regs
[13] = env
->xregs
[23];
7964 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
7965 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
7968 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7969 * mode, then we can copy to r8-r14. Otherwise, we copy to the
7970 * FIQ bank for r8-r14.
7972 if (mode
== ARM_CPU_MODE_FIQ
) {
7973 for (i
= 24; i
< 31; i
++) {
7974 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
7977 for (i
= 24; i
< 29; i
++) {
7978 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
7980 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
7981 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
7984 env
->regs
[15] = env
->pc
;
7987 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
7988 uint32_t mask
, uint32_t offset
,
7991 /* Change the CPU state so as to actually take the exception. */
7992 switch_mode(env
, new_mode
);
7994 * For exceptions taken to AArch32 we must clear the SS bit in both
7995 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
7997 env
->uncached_cpsr
&= ~PSTATE_SS
;
7998 env
->spsr
= cpsr_read(env
);
7999 /* Clear IT bits. */
8000 env
->condexec_bits
= 0;
8001 /* Switch to the new mode, and to the correct instruction set. */
8002 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8003 /* Set new mode endianness */
8004 env
->uncached_cpsr
&= ~CPSR_E
;
8005 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
8006 env
->uncached_cpsr
|= CPSR_E
;
8008 /* J and IL must always be cleared for exception entry */
8009 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
8012 if (new_mode
== ARM_CPU_MODE_HYP
) {
8013 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
8014 env
->elr_el
[2] = env
->regs
[15];
8017 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8018 * and we should just guard the thumb mode on V4
8020 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8022 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8024 env
->regs
[14] = env
->regs
[15] + offset
;
8026 env
->regs
[15] = newpc
;
8027 arm_rebuild_hflags(env
);
8030 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
8033 * Handle exception entry to Hyp mode; this is sufficiently
8034 * different to entry to other AArch32 modes that we handle it
8037 * The vector table entry used is always the 0x14 Hyp mode entry point,
8038 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8039 * The offset applied to the preferred return address is always zero
8040 * (see DDI0487C.a section G1.12.3).
8041 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8043 uint32_t addr
, mask
;
8044 ARMCPU
*cpu
= ARM_CPU(cs
);
8045 CPUARMState
*env
= &cpu
->env
;
8047 switch (cs
->exception_index
) {
8055 /* Fall through to prefetch abort. */
8056 case EXCP_PREFETCH_ABORT
:
8057 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
8058 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
8059 (uint32_t)env
->exception
.vaddress
);
8062 case EXCP_DATA_ABORT
:
8063 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
8064 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
8065 (uint32_t)env
->exception
.vaddress
);
8081 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8084 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
8085 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8087 * QEMU syndrome values are v8-style. v7 has the IL bit
8088 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
8089 * If this is a v7 CPU, squash the IL bit in those cases.
8091 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
8092 (cs
->exception_index
== EXCP_DATA_ABORT
&&
8093 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
8094 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
8095 env
->exception
.syndrome
&= ~ARM_EL_IL
;
8098 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
8101 if (arm_current_el(env
) != 2 && addr
< 0x14) {
8106 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
8109 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
8112 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
8116 addr
+= env
->cp15
.hvbar
;
8118 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
8121 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
8123 ARMCPU
*cpu
= ARM_CPU(cs
);
8124 CPUARMState
*env
= &cpu
->env
;
8131 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
8132 switch (syn_get_ec(env
->exception
.syndrome
)) {
8134 case EC_BREAKPOINT_SAME_EL
:
8138 case EC_WATCHPOINT_SAME_EL
:
8144 case EC_VECTORCATCH
:
8153 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
8156 if (env
->exception
.target_el
== 2) {
8157 arm_cpu_do_interrupt_aarch32_hyp(cs
);
8161 switch (cs
->exception_index
) {
8163 new_mode
= ARM_CPU_MODE_UND
;
8172 new_mode
= ARM_CPU_MODE_SVC
;
8175 /* The PC already points to the next instruction. */
8179 /* Fall through to prefetch abort. */
8180 case EXCP_PREFETCH_ABORT
:
8181 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
8182 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
8183 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
8184 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
8185 new_mode
= ARM_CPU_MODE_ABT
;
8187 mask
= CPSR_A
| CPSR_I
;
8190 case EXCP_DATA_ABORT
:
8191 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
8192 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
8193 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
8195 (uint32_t)env
->exception
.vaddress
);
8196 new_mode
= ARM_CPU_MODE_ABT
;
8198 mask
= CPSR_A
| CPSR_I
;
8202 new_mode
= ARM_CPU_MODE_IRQ
;
8204 /* Disable IRQ and imprecise data aborts. */
8205 mask
= CPSR_A
| CPSR_I
;
8207 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
8208 /* IRQ routed to monitor mode */
8209 new_mode
= ARM_CPU_MODE_MON
;
8214 new_mode
= ARM_CPU_MODE_FIQ
;
8216 /* Disable FIQ, IRQ and imprecise data aborts. */
8217 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8218 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
8219 /* FIQ routed to monitor mode */
8220 new_mode
= ARM_CPU_MODE_MON
;
8225 new_mode
= ARM_CPU_MODE_IRQ
;
8227 /* Disable IRQ and imprecise data aborts. */
8228 mask
= CPSR_A
| CPSR_I
;
8232 new_mode
= ARM_CPU_MODE_FIQ
;
8234 /* Disable FIQ, IRQ and imprecise data aborts. */
8235 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8239 new_mode
= ARM_CPU_MODE_MON
;
8241 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8245 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8246 return; /* Never happens. Keep compiler happy. */
8249 if (new_mode
== ARM_CPU_MODE_MON
) {
8250 addr
+= env
->cp15
.mvbar
;
8251 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
8252 /* High vectors. When enabled, base address cannot be remapped. */
8255 /* ARM v7 architectures provide a vector base address register to remap
8256 * the interrupt vector table.
8257 * This register is only followed in non-monitor mode, and is banked.
8258 * Note: only bits 31:5 are valid.
8260 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
8263 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
8264 env
->cp15
.scr_el3
&= ~SCR_NS
;
8267 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
8270 /* Handle exception entry to a target EL which is using AArch64 */
8271 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
8273 ARMCPU
*cpu
= ARM_CPU(cs
);
8274 CPUARMState
*env
= &cpu
->env
;
8275 unsigned int new_el
= env
->exception
.target_el
;
8276 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
8277 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
8278 unsigned int cur_el
= arm_current_el(env
);
8281 * Note that new_el can never be 0. If cur_el is 0, then
8282 * el0_a64 is is_a64(), else el0_a64 is ignored.
8284 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
8286 if (cur_el
< new_el
) {
8287 /* Entry vector offset depends on whether the implemented EL
8288 * immediately lower than the target level is using AArch32 or AArch64
8294 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
8297 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
8300 is_aa64
= is_a64(env
);
8303 g_assert_not_reached();
8311 } else if (pstate_read(env
) & PSTATE_SP
) {
8315 switch (cs
->exception_index
) {
8316 case EXCP_PREFETCH_ABORT
:
8317 case EXCP_DATA_ABORT
:
8318 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
8319 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
8320 env
->cp15
.far_el
[new_el
]);
8328 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
8330 * QEMU internal FP/SIMD syndromes from AArch32 include the
8331 * TA and coproc fields which are only exposed if the exception
8332 * is taken to AArch32 Hyp mode. Mask them out to get a valid
8333 * AArch64 format syndrome.
8335 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
8337 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
8348 qemu_log_mask(CPU_LOG_INT
,
8349 "...handling as semihosting call 0x%" PRIx64
"\n",
8351 env
->xregs
[0] = do_arm_semihosting(env
);
8354 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8358 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
8359 aarch64_save_sp(env
, arm_current_el(env
));
8360 env
->elr_el
[new_el
] = env
->pc
;
8362 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
8363 env
->elr_el
[new_el
] = env
->regs
[15];
8365 aarch64_sync_32_to_64(env
);
8367 env
->condexec_bits
= 0;
8369 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
8370 env
->elr_el
[new_el
]);
8372 pstate_write(env
, PSTATE_DAIF
| new_mode
);
8374 aarch64_restore_sp(env
, new_el
);
8375 helper_rebuild_hflags_a64(env
, new_el
);
8379 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
8380 new_el
, env
->pc
, pstate_read(env
));
8384 * Do semihosting call and set the appropriate return value. All the
8385 * permission and validity checks have been done at translate time.
8387 * We only see semihosting exceptions in TCG only as they are not
8388 * trapped to the hypervisor in KVM.
8391 static void handle_semihosting(CPUState
*cs
)
8393 ARMCPU
*cpu
= ARM_CPU(cs
);
8394 CPUARMState
*env
= &cpu
->env
;
8397 qemu_log_mask(CPU_LOG_INT
,
8398 "...handling as semihosting call 0x%" PRIx64
"\n",
8400 env
->xregs
[0] = do_arm_semihosting(env
);
8402 qemu_log_mask(CPU_LOG_INT
,
8403 "...handling as semihosting call 0x%x\n",
8405 env
->regs
[0] = do_arm_semihosting(env
);
8410 /* Handle a CPU exception for A and R profile CPUs.
8411 * Do any appropriate logging, handle PSCI calls, and then hand off
8412 * to the AArch64-entry or AArch32-entry function depending on the
8413 * target exception level's register width.
8415 void arm_cpu_do_interrupt(CPUState
*cs
)
8417 ARMCPU
*cpu
= ARM_CPU(cs
);
8418 CPUARMState
*env
= &cpu
->env
;
8419 unsigned int new_el
= env
->exception
.target_el
;
8421 assert(!arm_feature(env
, ARM_FEATURE_M
));
8423 arm_log_exception(cs
->exception_index
);
8424 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
8426 if (qemu_loglevel_mask(CPU_LOG_INT
)
8427 && !excp_is_internal(cs
->exception_index
)) {
8428 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
8429 syn_get_ec(env
->exception
.syndrome
),
8430 env
->exception
.syndrome
);
8433 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
8434 arm_handle_psci_call(cpu
);
8435 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
8440 * Semihosting semantics depend on the register width of the code
8441 * that caused the exception, not the target exception level, so
8442 * must be handled here.
8445 if (cs
->exception_index
== EXCP_SEMIHOST
) {
8446 handle_semihosting(cs
);
8451 /* Hooks may change global state so BQL should be held, also the
8452 * BQL needs to be held for any modification of
8453 * cs->interrupt_request.
8455 g_assert(qemu_mutex_iothread_locked());
8457 arm_call_pre_el_change_hook(cpu
);
8459 assert(!excp_is_internal(cs
->exception_index
));
8460 if (arm_el_is_aa64(env
, new_el
)) {
8461 arm_cpu_do_interrupt_aarch64(cs
);
8463 arm_cpu_do_interrupt_aarch32(cs
);
8466 arm_call_el_change_hook(cpu
);
8468 if (!kvm_enabled()) {
8469 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
8472 #endif /* !CONFIG_USER_ONLY */
8474 /* Return the exception level which controls this address translation regime */
8475 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8478 case ARMMMUIdx_S2NS
:
8479 case ARMMMUIdx_S1E2
:
8481 case ARMMMUIdx_S1E3
:
8483 case ARMMMUIdx_S1SE0
:
8484 return arm_el_is_aa64(env
, 3) ? 1 : 3;
8485 case ARMMMUIdx_S1SE1
:
8486 case ARMMMUIdx_S1NSE0
:
8487 case ARMMMUIdx_S1NSE1
:
8488 case ARMMMUIdx_MPrivNegPri
:
8489 case ARMMMUIdx_MUserNegPri
:
8490 case ARMMMUIdx_MPriv
:
8491 case ARMMMUIdx_MUser
:
8492 case ARMMMUIdx_MSPrivNegPri
:
8493 case ARMMMUIdx_MSUserNegPri
:
8494 case ARMMMUIdx_MSPriv
:
8495 case ARMMMUIdx_MSUser
:
8498 g_assert_not_reached();
8502 #ifndef CONFIG_USER_ONLY
8504 /* Return the SCTLR value which controls this address translation regime */
8505 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8507 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
8510 /* Return true if the specified stage of address translation is disabled */
8511 static inline bool regime_translation_disabled(CPUARMState
*env
,
8514 if (arm_feature(env
, ARM_FEATURE_M
)) {
8515 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
8516 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
8517 case R_V7M_MPU_CTRL_ENABLE_MASK
:
8518 /* Enabled, but not for HardFault and NMI */
8519 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
8520 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
8521 /* Enabled for all cases */
8525 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
8526 * we warned about that in armv7m_nvic.c when the guest set it.
8532 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8533 /* HCR.DC means HCR.VM behaves as 1 */
8534 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
8537 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
8538 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
8539 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
8544 if ((env
->cp15
.hcr_el2
& HCR_DC
) &&
8545 (mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
)) {
8546 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
8550 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
8553 static inline bool regime_translation_big_endian(CPUARMState
*env
,
8556 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
8559 /* Return the TTBR associated with this translation regime */
8560 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8563 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8564 return env
->cp15
.vttbr_el2
;
8567 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
8569 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
8573 #endif /* !CONFIG_USER_ONLY */
8575 /* Return the TCR controlling this translation regime */
8576 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8578 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8579 return &env
->cp15
.vtcr_el2
;
8581 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
8584 /* Convert a possible stage1+2 MMU index into the appropriate
8587 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
8589 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8590 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
8595 /* Return true if the translation regime is using LPAE format page tables */
8596 static inline bool regime_using_lpae_format(CPUARMState
*env
,
8599 int el
= regime_el(env
, mmu_idx
);
8600 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
8603 if (arm_feature(env
, ARM_FEATURE_LPAE
)
8604 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
8610 /* Returns true if the stage 1 translation regime is using LPAE format page
8611 * tables. Used when raising alignment exceptions, whose FSR changes depending
8612 * on whether the long or short descriptor format is in use. */
8613 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8615 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8617 return regime_using_lpae_format(env
, mmu_idx
);
8620 #ifndef CONFIG_USER_ONLY
8621 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8624 case ARMMMUIdx_S1SE0
:
8625 case ARMMMUIdx_S1NSE0
:
8626 case ARMMMUIdx_MUser
:
8627 case ARMMMUIdx_MSUser
:
8628 case ARMMMUIdx_MUserNegPri
:
8629 case ARMMMUIdx_MSUserNegPri
:
8633 case ARMMMUIdx_S12NSE0
:
8634 case ARMMMUIdx_S12NSE1
:
8635 g_assert_not_reached();
8639 /* Translate section/page access permissions to page
8640 * R/W protection flags
8643 * @mmu_idx: MMU index indicating required translation regime
8644 * @ap: The 3-bit access permissions (AP[2:0])
8645 * @domain_prot: The 2-bit domain access permissions
8647 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8648 int ap
, int domain_prot
)
8650 bool is_user
= regime_is_user(env
, mmu_idx
);
8652 if (domain_prot
== 3) {
8653 return PAGE_READ
| PAGE_WRITE
;
8658 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8661 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8663 return is_user
? 0 : PAGE_READ
;
8670 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8675 return PAGE_READ
| PAGE_WRITE
;
8678 return PAGE_READ
| PAGE_WRITE
;
8679 case 4: /* Reserved. */
8682 return is_user
? 0 : PAGE_READ
;
8686 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8691 g_assert_not_reached();
8695 /* Translate section/page access permissions to page
8696 * R/W protection flags.
8698 * @ap: The 2-bit simple AP (AP[2:1])
8699 * @is_user: TRUE if accessing from PL0
8701 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8705 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8707 return PAGE_READ
| PAGE_WRITE
;
8709 return is_user
? 0 : PAGE_READ
;
8713 g_assert_not_reached();
8718 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8720 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8723 /* Translate S2 section/page access permissions to protection flags
8726 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8727 * @xn: XN (execute-never) bit
8729 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8740 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8747 /* Translate section/page access permissions to protection flags
8750 * @mmu_idx: MMU index indicating required translation regime
8751 * @is_aa64: TRUE if AArch64
8752 * @ap: The 2-bit simple AP (AP[2:1])
8753 * @ns: NS (non-secure) bit
8754 * @xn: XN (execute-never) bit
8755 * @pxn: PXN (privileged execute-never) bit
8757 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8758 int ap
, int ns
, int xn
, int pxn
)
8760 bool is_user
= regime_is_user(env
, mmu_idx
);
8761 int prot_rw
, user_rw
;
8765 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8767 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8771 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8774 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8778 /* TODO have_wxn should be replaced with
8779 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8780 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8781 * compatible processors have EL2, which is required for [U]WXN.
8783 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8786 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8790 switch (regime_el(env
, mmu_idx
)) {
8793 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8800 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8801 switch (regime_el(env
, mmu_idx
)) {
8805 xn
= xn
|| !(user_rw
& PAGE_READ
);
8809 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8811 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8812 (uwxn
&& (user_rw
& PAGE_WRITE
));
8822 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8825 return prot_rw
| PAGE_EXEC
;
8828 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8829 uint32_t *table
, uint32_t address
)
8831 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8832 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8834 if (address
& tcr
->mask
) {
8835 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8836 /* Translation table walk disabled for TTBR1 */
8839 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8841 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8842 /* Translation table walk disabled for TTBR0 */
8845 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
8847 *table
|= (address
>> 18) & 0x3ffc;
8851 /* Translate a S1 pagetable walk through S2 if needed. */
8852 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8853 hwaddr addr
, MemTxAttrs txattrs
,
8854 ARMMMUFaultInfo
*fi
)
8856 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
8857 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8858 target_ulong s2size
;
8862 ARMCacheAttrs cacheattrs
= {};
8863 ARMCacheAttrs
*pcacheattrs
= NULL
;
8865 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
8867 * PTW means we must fault if this S1 walk touches S2 Device
8868 * memory; otherwise we don't care about the attributes and can
8869 * save the S2 translation the effort of computing them.
8871 pcacheattrs
= &cacheattrs
;
8874 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
8875 &txattrs
, &s2prot
, &s2size
, fi
, pcacheattrs
);
8877 assert(fi
->type
!= ARMFault_None
);
8883 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
8884 /* Access was to Device memory: generate Permission fault */
8885 fi
->type
= ARMFault_Permission
;
8896 /* All loads done in the course of a page table walk go through here. */
8897 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8898 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8900 ARMCPU
*cpu
= ARM_CPU(cs
);
8901 CPUARMState
*env
= &cpu
->env
;
8902 MemTxAttrs attrs
= {};
8903 MemTxResult result
= MEMTX_OK
;
8907 attrs
.secure
= is_secure
;
8908 as
= arm_addressspace(cs
, attrs
);
8909 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8913 if (regime_translation_big_endian(env
, mmu_idx
)) {
8914 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
8916 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
8918 if (result
== MEMTX_OK
) {
8921 fi
->type
= ARMFault_SyncExternalOnWalk
;
8922 fi
->ea
= arm_extabort_type(result
);
8926 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8927 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8929 ARMCPU
*cpu
= ARM_CPU(cs
);
8930 CPUARMState
*env
= &cpu
->env
;
8931 MemTxAttrs attrs
= {};
8932 MemTxResult result
= MEMTX_OK
;
8936 attrs
.secure
= is_secure
;
8937 as
= arm_addressspace(cs
, attrs
);
8938 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8942 if (regime_translation_big_endian(env
, mmu_idx
)) {
8943 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
8945 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
8947 if (result
== MEMTX_OK
) {
8950 fi
->type
= ARMFault_SyncExternalOnWalk
;
8951 fi
->ea
= arm_extabort_type(result
);
8955 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
8956 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8957 hwaddr
*phys_ptr
, int *prot
,
8958 target_ulong
*page_size
,
8959 ARMMMUFaultInfo
*fi
)
8961 CPUState
*cs
= env_cpu(env
);
8972 /* Pagetable walk. */
8973 /* Lookup l1 descriptor. */
8974 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8975 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8976 fi
->type
= ARMFault_Translation
;
8979 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8981 if (fi
->type
!= ARMFault_None
) {
8985 domain
= (desc
>> 5) & 0x0f;
8986 if (regime_el(env
, mmu_idx
) == 1) {
8987 dacr
= env
->cp15
.dacr_ns
;
8989 dacr
= env
->cp15
.dacr_s
;
8991 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8993 /* Section translation fault. */
8994 fi
->type
= ARMFault_Translation
;
9000 if (domain_prot
== 0 || domain_prot
== 2) {
9001 fi
->type
= ARMFault_Domain
;
9006 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9007 ap
= (desc
>> 10) & 3;
9008 *page_size
= 1024 * 1024;
9010 /* Lookup l2 entry. */
9012 /* Coarse pagetable. */
9013 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9015 /* Fine pagetable. */
9016 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
9018 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9020 if (fi
->type
!= ARMFault_None
) {
9024 case 0: /* Page translation fault. */
9025 fi
->type
= ARMFault_Translation
;
9027 case 1: /* 64k page. */
9028 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9029 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
9030 *page_size
= 0x10000;
9032 case 2: /* 4k page. */
9033 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9034 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
9035 *page_size
= 0x1000;
9037 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
9039 /* ARMv6/XScale extended small page format */
9040 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
9041 || arm_feature(env
, ARM_FEATURE_V6
)) {
9042 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9043 *page_size
= 0x1000;
9045 /* UNPREDICTABLE in ARMv5; we choose to take a
9046 * page translation fault.
9048 fi
->type
= ARMFault_Translation
;
9052 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
9055 ap
= (desc
>> 4) & 3;
9058 /* Never happens, but compiler isn't smart enough to tell. */
9062 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9063 *prot
|= *prot
? PAGE_EXEC
: 0;
9064 if (!(*prot
& (1 << access_type
))) {
9065 /* Access permission fault. */
9066 fi
->type
= ARMFault_Permission
;
9069 *phys_ptr
= phys_addr
;
9072 fi
->domain
= domain
;
9077 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
9078 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9079 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
9080 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
9082 CPUState
*cs
= env_cpu(env
);
9096 /* Pagetable walk. */
9097 /* Lookup l1 descriptor. */
9098 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9099 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9100 fi
->type
= ARMFault_Translation
;
9103 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9105 if (fi
->type
!= ARMFault_None
) {
9109 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
9110 /* Section translation fault, or attempt to use the encoding
9111 * which is Reserved on implementations without PXN.
9113 fi
->type
= ARMFault_Translation
;
9116 if ((type
== 1) || !(desc
& (1 << 18))) {
9117 /* Page or Section. */
9118 domain
= (desc
>> 5) & 0x0f;
9120 if (regime_el(env
, mmu_idx
) == 1) {
9121 dacr
= env
->cp15
.dacr_ns
;
9123 dacr
= env
->cp15
.dacr_s
;
9128 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9129 if (domain_prot
== 0 || domain_prot
== 2) {
9130 /* Section or Page domain fault */
9131 fi
->type
= ARMFault_Domain
;
9135 if (desc
& (1 << 18)) {
9137 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
9138 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
9139 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
9140 *page_size
= 0x1000000;
9143 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9144 *page_size
= 0x100000;
9146 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
9147 xn
= desc
& (1 << 4);
9149 ns
= extract32(desc
, 19, 1);
9151 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
9152 pxn
= (desc
>> 2) & 1;
9154 ns
= extract32(desc
, 3, 1);
9155 /* Lookup l2 entry. */
9156 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9157 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9159 if (fi
->type
!= ARMFault_None
) {
9162 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
9164 case 0: /* Page translation fault. */
9165 fi
->type
= ARMFault_Translation
;
9167 case 1: /* 64k page. */
9168 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9169 xn
= desc
& (1 << 15);
9170 *page_size
= 0x10000;
9172 case 2: case 3: /* 4k page. */
9173 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9175 *page_size
= 0x1000;
9178 /* Never happens, but compiler isn't smart enough to tell. */
9182 if (domain_prot
== 3) {
9183 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9185 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
9188 if (xn
&& access_type
== MMU_INST_FETCH
) {
9189 fi
->type
= ARMFault_Permission
;
9193 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
9194 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
9195 /* The simplified model uses AP[0] as an access control bit. */
9196 if ((ap
& 1) == 0) {
9197 /* Access flag fault. */
9198 fi
->type
= ARMFault_AccessFlag
;
9201 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
9203 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9208 if (!(*prot
& (1 << access_type
))) {
9209 /* Access permission fault. */
9210 fi
->type
= ARMFault_Permission
;
9215 /* The NS bit will (as required by the architecture) have no effect if
9216 * the CPU doesn't support TZ or this is a non-secure translation
9217 * regime, because the attribute will already be non-secure.
9219 attrs
->secure
= false;
9221 *phys_ptr
= phys_addr
;
9224 fi
->domain
= domain
;
9230 * check_s2_mmu_setup
9232 * @is_aa64: True if the translation regime is in AArch64 state
9233 * @startlevel: Suggested starting level
9234 * @inputsize: Bitsize of IPAs
9235 * @stride: Page-table stride (See the ARM ARM)
9237 * Returns true if the suggested S2 translation parameters are OK and
9240 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
9241 int inputsize
, int stride
)
9243 const int grainsize
= stride
+ 3;
9246 /* Negative levels are never allowed. */
9251 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
9252 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
9257 CPUARMState
*env
= &cpu
->env
;
9258 unsigned int pamax
= arm_pamax(cpu
);
9261 case 13: /* 64KB Pages. */
9262 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
9266 case 11: /* 16KB Pages. */
9267 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
9271 case 9: /* 4KB Pages. */
9272 if (level
== 0 && pamax
<= 42) {
9277 g_assert_not_reached();
9280 /* Inputsize checks. */
9281 if (inputsize
> pamax
&&
9282 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
9283 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
9287 /* AArch32 only supports 4KB pages. Assert on that. */
9288 assert(stride
== 9);
9297 /* Translate from the 4-bit stage 2 representation of
9298 * memory attributes (without cache-allocation hints) to
9299 * the 8-bit representation of the stage 1 MAIR registers
9300 * (which includes allocation hints).
9302 * ref: shared/translation/attrs/S2AttrDecode()
9303 * .../S2ConvertAttrsHints()
9305 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
9307 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
9308 uint8_t loattr
= extract32(s2attrs
, 0, 2);
9309 uint8_t hihint
= 0, lohint
= 0;
9311 if (hiattr
!= 0) { /* normal memory */
9312 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
9313 hiattr
= loattr
= 1; /* non-cacheable */
9315 if (hiattr
!= 1) { /* Write-through or write-back */
9316 hihint
= 3; /* RW allocate */
9318 if (loattr
!= 1) { /* Write-through or write-back */
9319 lohint
= 3; /* RW allocate */
9324 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
9326 #endif /* !CONFIG_USER_ONLY */
9328 ARMVAParameters
aa64_va_parameters_both(CPUARMState
*env
, uint64_t va
,
9331 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
9332 uint32_t el
= regime_el(env
, mmu_idx
);
9333 bool tbi
, tbid
, epd
, hpd
, using16k
, using64k
;
9337 * Bit 55 is always between the two regions, and is canonical for
9338 * determining if address tagging is enabled.
9340 select
= extract64(va
, 55, 1);
9343 tsz
= extract32(tcr
, 0, 6);
9344 using64k
= extract32(tcr
, 14, 1);
9345 using16k
= extract32(tcr
, 15, 1);
9346 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9348 tbi
= tbid
= hpd
= false;
9350 tbi
= extract32(tcr
, 20, 1);
9351 hpd
= extract32(tcr
, 24, 1);
9352 tbid
= extract32(tcr
, 29, 1);
9355 } else if (!select
) {
9356 tsz
= extract32(tcr
, 0, 6);
9357 epd
= extract32(tcr
, 7, 1);
9358 using64k
= extract32(tcr
, 14, 1);
9359 using16k
= extract32(tcr
, 15, 1);
9360 tbi
= extract64(tcr
, 37, 1);
9361 hpd
= extract64(tcr
, 41, 1);
9362 tbid
= extract64(tcr
, 51, 1);
9364 int tg
= extract32(tcr
, 30, 2);
9367 tsz
= extract32(tcr
, 16, 6);
9368 epd
= extract32(tcr
, 23, 1);
9369 tbi
= extract64(tcr
, 38, 1);
9370 hpd
= extract64(tcr
, 42, 1);
9371 tbid
= extract64(tcr
, 52, 1);
9373 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
9374 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
9376 return (ARMVAParameters
) {
9383 .using16k
= using16k
,
9384 .using64k
= using64k
,
9388 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
9389 ARMMMUIdx mmu_idx
, bool data
)
9391 ARMVAParameters ret
= aa64_va_parameters_both(env
, va
, mmu_idx
);
9393 /* Present TBI as a composite with TBID. */
9394 ret
.tbi
&= (data
|| !ret
.tbid
);
9398 #ifndef CONFIG_USER_ONLY
9399 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
9402 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
9403 uint32_t el
= regime_el(env
, mmu_idx
);
9407 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9409 bool sext
= extract32(tcr
, 4, 1);
9410 bool sign
= extract32(tcr
, 3, 1);
9413 * If the sign-extend bit is not the same as t0sz[3], the result
9414 * is unpredictable. Flag this as a guest error.
9417 qemu_log_mask(LOG_GUEST_ERROR
,
9418 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
9420 tsz
= sextract32(tcr
, 0, 4) + 8;
9424 } else if (el
== 2) {
9426 tsz
= extract32(tcr
, 0, 3);
9428 hpd
= extract64(tcr
, 24, 1);
9431 int t0sz
= extract32(tcr
, 0, 3);
9432 int t1sz
= extract32(tcr
, 16, 3);
9435 select
= va
> (0xffffffffu
>> t0sz
);
9437 /* Note that we will detect errors later. */
9438 select
= va
>= ~(0xffffffffu
>> t1sz
);
9442 epd
= extract32(tcr
, 7, 1);
9443 hpd
= extract64(tcr
, 41, 1);
9446 epd
= extract32(tcr
, 23, 1);
9447 hpd
= extract64(tcr
, 42, 1);
9449 /* For aarch32, hpd0 is not enabled without t2e as well. */
9450 hpd
&= extract32(tcr
, 6, 1);
9453 return (ARMVAParameters
) {
9461 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
9462 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9463 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
9464 target_ulong
*page_size_ptr
,
9465 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
9467 ARMCPU
*cpu
= env_archcpu(env
);
9468 CPUState
*cs
= CPU(cpu
);
9469 /* Read an LPAE long-descriptor translation table. */
9470 ARMFaultType fault_type
= ARMFault_Translation
;
9472 ARMVAParameters param
;
9474 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
9475 uint32_t tableattrs
;
9476 target_ulong page_size
;
9479 int addrsize
, inputsize
;
9480 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9481 int ap
, ns
, xn
, pxn
;
9482 uint32_t el
= regime_el(env
, mmu_idx
);
9484 uint64_t descaddrmask
;
9485 bool aarch64
= arm_el_is_aa64(env
, el
);
9486 bool guarded
= false;
9489 * This code does not handle the different format TCR for VTCR_EL2.
9490 * This code also does not support shareability levels.
9491 * Attribute and permission bit handling should also be checked when adding
9492 * support for those page table walks.
9495 param
= aa64_va_parameters(env
, address
, mmu_idx
,
9496 access_type
!= MMU_INST_FETCH
);
9498 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9501 ttbr1_valid
= (el
< 2);
9502 addrsize
= 64 - 8 * param
.tbi
;
9503 inputsize
= 64 - param
.tsz
;
9505 param
= aa32_va_parameters(env
, address
, mmu_idx
);
9507 /* There is no TTBR1 for EL2 */
9508 ttbr1_valid
= (el
!= 2);
9509 addrsize
= (mmu_idx
== ARMMMUIdx_S2NS
? 40 : 32);
9510 inputsize
= addrsize
- param
.tsz
;
9514 * We determined the region when collecting the parameters, but we
9515 * have not yet validated that the address is valid for the region.
9516 * Extract the top bits and verify that they all match select.
9518 * For aa32, if inputsize == addrsize, then we have selected the
9519 * region by exclusion in aa32_va_parameters and there is no more
9520 * validation to do here.
9522 if (inputsize
< addrsize
) {
9523 target_ulong top_bits
= sextract64(address
, inputsize
,
9524 addrsize
- inputsize
);
9525 if (-top_bits
!= param
.select
|| (param
.select
&& !ttbr1_valid
)) {
9526 /* The gap between the two regions is a Translation fault */
9527 fault_type
= ARMFault_Translation
;
9532 if (param
.using64k
) {
9534 } else if (param
.using16k
) {
9540 /* Note that QEMU ignores shareability and cacheability attributes,
9541 * so we don't need to do anything with the SH, ORGN, IRGN fields
9542 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
9543 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
9544 * implement any ASID-like capability so we can ignore it (instead
9545 * we will always flush the TLB any time the ASID is changed).
9547 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
9549 /* Here we should have set up all the parameters for the translation:
9550 * inputsize, ttbr, epd, stride, tbi
9554 /* Translation table walk disabled => Translation fault on TLB miss
9555 * Note: This is always 0 on 64-bit EL2 and EL3.
9560 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9561 /* The starting level depends on the virtual address size (which can
9562 * be up to 48 bits) and the translation granule size. It indicates
9563 * the number of strides (stride bits at a time) needed to
9564 * consume the bits of the input address. In the pseudocode this is:
9565 * level = 4 - RoundUp((inputsize - grainsize) / stride)
9566 * where their 'inputsize' is our 'inputsize', 'grainsize' is
9567 * our 'stride + 3' and 'stride' is our 'stride'.
9568 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
9569 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
9570 * = 4 - (inputsize - 4) / stride;
9572 level
= 4 - (inputsize
- 4) / stride
;
9574 /* For stage 2 translations the starting level is specified by the
9575 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
9577 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
9578 uint32_t startlevel
;
9581 if (!aarch64
|| stride
== 9) {
9582 /* AArch32 or 4KB pages */
9583 startlevel
= 2 - sl0
;
9585 /* 16KB or 64KB pages */
9586 startlevel
= 3 - sl0
;
9589 /* Check that the starting level is valid. */
9590 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
9593 fault_type
= ARMFault_Translation
;
9599 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
9600 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
9602 /* Now we can extract the actual base address from the TTBR */
9603 descaddr
= extract64(ttbr
, 0, 48);
9604 descaddr
&= ~indexmask
;
9606 /* The address field in the descriptor goes up to bit 39 for ARMv7
9607 * but up to bit 47 for ARMv8, but we use the descaddrmask
9608 * up to bit 39 for AArch32, because we don't need other bits in that case
9609 * to construct next descriptor address (anyway they should be all zeroes).
9611 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
9612 ~indexmask_grainsize
;
9614 /* Secure accesses start with the page table in secure memory and
9615 * can be downgraded to non-secure at any step. Non-secure accesses
9616 * remain non-secure. We implement this by just ORing in the NSTable/NS
9617 * bits at each step.
9619 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
9621 uint64_t descriptor
;
9624 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
9626 nstable
= extract32(tableattrs
, 4, 1);
9627 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
9628 if (fi
->type
!= ARMFault_None
) {
9632 if (!(descriptor
& 1) ||
9633 (!(descriptor
& 2) && (level
== 3))) {
9634 /* Invalid, or the Reserved level 3 encoding */
9637 descaddr
= descriptor
& descaddrmask
;
9639 if ((descriptor
& 2) && (level
< 3)) {
9640 /* Table entry. The top five bits are attributes which may
9641 * propagate down through lower levels of the table (and
9642 * which are all arranged so that 0 means "no effect", so
9643 * we can gather them up by ORing in the bits at each level).
9645 tableattrs
|= extract64(descriptor
, 59, 5);
9647 indexmask
= indexmask_grainsize
;
9650 /* Block entry at level 1 or 2, or page entry at level 3.
9651 * These are basically the same thing, although the number
9652 * of bits we pull in from the vaddr varies.
9654 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
9655 descaddr
|= (address
& (page_size
- 1));
9656 /* Extract attributes from the descriptor */
9657 attrs
= extract64(descriptor
, 2, 10)
9658 | (extract64(descriptor
, 52, 12) << 10);
9660 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9661 /* Stage 2 table descriptors do not include any attribute fields */
9664 /* Merge in attributes from table descriptors */
9665 attrs
|= nstable
<< 3; /* NS */
9666 guarded
= extract64(descriptor
, 50, 1); /* GP */
9668 /* HPD disables all the table attributes except NSTable. */
9671 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
9672 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9673 * means "force PL1 access only", which means forcing AP[1] to 0.
9675 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
9676 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
9679 /* Here descaddr is the final physical address, and attributes
9682 fault_type
= ARMFault_AccessFlag
;
9683 if ((attrs
& (1 << 8)) == 0) {
9688 ap
= extract32(attrs
, 4, 2);
9689 xn
= extract32(attrs
, 12, 1);
9691 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9693 *prot
= get_S2prot(env
, ap
, xn
);
9695 ns
= extract32(attrs
, 3, 1);
9696 pxn
= extract32(attrs
, 11, 1);
9697 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
9700 fault_type
= ARMFault_Permission
;
9701 if (!(*prot
& (1 << access_type
))) {
9706 /* The NS bit will (as required by the architecture) have no effect if
9707 * the CPU doesn't support TZ or this is a non-secure translation
9708 * regime, because the attribute will already be non-secure.
9710 txattrs
->secure
= false;
9712 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
9713 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
9714 txattrs
->target_tlb_bit0
= true;
9717 if (cacheattrs
!= NULL
) {
9718 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9719 cacheattrs
->attrs
= convert_stage2_attrs(env
,
9720 extract32(attrs
, 0, 4));
9722 /* Index into MAIR registers for cache attributes */
9723 uint8_t attrindx
= extract32(attrs
, 0, 3);
9724 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
9725 assert(attrindx
<= 7);
9726 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
9728 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
9731 *phys_ptr
= descaddr
;
9732 *page_size_ptr
= page_size
;
9736 fi
->type
= fault_type
;
9738 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9739 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
9743 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
9745 int32_t address
, int *prot
)
9747 if (!arm_feature(env
, ARM_FEATURE_M
)) {
9748 *prot
= PAGE_READ
| PAGE_WRITE
;
9750 case 0xF0000000 ... 0xFFFFFFFF:
9751 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
9752 /* hivecs execing is ok */
9756 case 0x00000000 ... 0x7FFFFFFF:
9761 /* Default system address map for M profile cores.
9762 * The architecture specifies which regions are execute-never;
9763 * at the MPU level no other checks are defined.
9766 case 0x00000000 ... 0x1fffffff: /* ROM */
9767 case 0x20000000 ... 0x3fffffff: /* SRAM */
9768 case 0x60000000 ... 0x7fffffff: /* RAM */
9769 case 0x80000000 ... 0x9fffffff: /* RAM */
9770 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9772 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9773 case 0xa0000000 ... 0xbfffffff: /* Device */
9774 case 0xc0000000 ... 0xdfffffff: /* Device */
9775 case 0xe0000000 ... 0xffffffff: /* System */
9776 *prot
= PAGE_READ
| PAGE_WRITE
;
9779 g_assert_not_reached();
9784 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
9785 ARMMMUIdx mmu_idx
, bool is_user
)
9787 /* Return true if we should use the default memory map as a
9788 * "background" region if there are no hits against any MPU regions.
9790 CPUARMState
*env
= &cpu
->env
;
9796 if (arm_feature(env
, ARM_FEATURE_M
)) {
9797 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
9798 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9800 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9804 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9806 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9807 return arm_feature(env
, ARM_FEATURE_M
) &&
9808 extract32(address
, 20, 12) == 0xe00;
9811 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9813 /* True if address is in the M profile system region
9814 * 0xe0000000 - 0xffffffff
9816 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9819 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9820 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9821 hwaddr
*phys_ptr
, int *prot
,
9822 target_ulong
*page_size
,
9823 ARMMMUFaultInfo
*fi
)
9825 ARMCPU
*cpu
= env_archcpu(env
);
9827 bool is_user
= regime_is_user(env
, mmu_idx
);
9829 *phys_ptr
= address
;
9830 *page_size
= TARGET_PAGE_SIZE
;
9833 if (regime_translation_disabled(env
, mmu_idx
) ||
9834 m_is_ppb_region(env
, address
)) {
9835 /* MPU disabled or M profile PPB access: use default memory map.
9836 * The other case which uses the default memory map in the
9837 * v7M ARM ARM pseudocode is exception vector reads from the vector
9838 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9839 * which always does a direct read using address_space_ldl(), rather
9840 * than going via this function, so we don't need to check that here.
9842 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9843 } else { /* MPU enabled */
9844 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9846 uint32_t base
= env
->pmsav7
.drbar
[n
];
9847 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
9851 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
9856 qemu_log_mask(LOG_GUEST_ERROR
,
9857 "DRSR[%d]: Rsize field cannot be 0\n", n
);
9861 rmask
= (1ull << rsize
) - 1;
9864 qemu_log_mask(LOG_GUEST_ERROR
,
9865 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
9866 "to DRSR region size, mask = 0x%" PRIx32
"\n",
9871 if (address
< base
|| address
> base
+ rmask
) {
9873 * Address not in this region. We must check whether the
9874 * region covers addresses in the same page as our address.
9875 * In that case we must not report a size that covers the
9876 * whole page for a subsequent hit against a different MPU
9877 * region or the background region, because it would result in
9878 * incorrect TLB hits for subsequent accesses to addresses that
9879 * are in this MPU region.
9881 if (ranges_overlap(base
, rmask
,
9882 address
& TARGET_PAGE_MASK
,
9883 TARGET_PAGE_SIZE
)) {
9889 /* Region matched */
9891 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
9893 uint32_t srdis_mask
;
9895 rsize
-= 3; /* sub region size (power of 2) */
9896 snd
= ((address
- base
) >> rsize
) & 0x7;
9897 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
9899 srdis_mask
= srdis
? 0x3 : 0x0;
9900 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
9901 /* This will check in groups of 2, 4 and then 8, whether
9902 * the subregion bits are consistent. rsize is incremented
9903 * back up to give the region size, considering consistent
9904 * adjacent subregions as one region. Stop testing if rsize
9905 * is already big enough for an entire QEMU page.
9907 int snd_rounded
= snd
& ~(i
- 1);
9908 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
9909 snd_rounded
+ 8, i
);
9910 if (srdis_mask
^ srdis_multi
) {
9913 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
9920 if (rsize
< TARGET_PAGE_BITS
) {
9921 *page_size
= 1 << rsize
;
9926 if (n
== -1) { /* no hits */
9927 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9928 /* background fault */
9929 fi
->type
= ARMFault_Background
;
9932 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9933 } else { /* a MPU hit! */
9934 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
9935 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
9937 if (m_is_system_region(env
, address
)) {
9938 /* System space is always execute never */
9942 if (is_user
) { /* User mode AP bit decoding */
9947 break; /* no access */
9949 *prot
|= PAGE_WRITE
;
9953 *prot
|= PAGE_READ
| PAGE_EXEC
;
9956 /* for v7M, same as 6; for R profile a reserved value */
9957 if (arm_feature(env
, ARM_FEATURE_M
)) {
9958 *prot
|= PAGE_READ
| PAGE_EXEC
;
9963 qemu_log_mask(LOG_GUEST_ERROR
,
9964 "DRACR[%d]: Bad value for AP bits: 0x%"
9965 PRIx32
"\n", n
, ap
);
9967 } else { /* Priv. mode AP bits decoding */
9970 break; /* no access */
9974 *prot
|= PAGE_WRITE
;
9978 *prot
|= PAGE_READ
| PAGE_EXEC
;
9981 /* for v7M, same as 6; for R profile a reserved value */
9982 if (arm_feature(env
, ARM_FEATURE_M
)) {
9983 *prot
|= PAGE_READ
| PAGE_EXEC
;
9988 qemu_log_mask(LOG_GUEST_ERROR
,
9989 "DRACR[%d]: Bad value for AP bits: 0x%"
9990 PRIx32
"\n", n
, ap
);
9996 *prot
&= ~PAGE_EXEC
;
10001 fi
->type
= ARMFault_Permission
;
10003 return !(*prot
& (1 << access_type
));
10006 static bool v8m_is_sau_exempt(CPUARMState
*env
,
10007 uint32_t address
, MMUAccessType access_type
)
10009 /* The architecture specifies that certain address ranges are
10010 * exempt from v8M SAU/IDAU checks.
10013 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
10014 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
10015 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
10016 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
10017 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
10018 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
10021 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
10022 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10023 V8M_SAttributes
*sattrs
)
10025 /* Look up the security attributes for this address. Compare the
10026 * pseudocode SecurityCheck() function.
10027 * We assume the caller has zero-initialized *sattrs.
10029 ARMCPU
*cpu
= env_archcpu(env
);
10031 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
10032 int idau_region
= IREGION_NOTVALID
;
10033 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10034 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10037 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
10038 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
10040 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
10044 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
10045 /* 0xf0000000..0xffffffff is always S for insn fetches */
10049 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
10050 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
10054 if (idau_region
!= IREGION_NOTVALID
) {
10055 sattrs
->irvalid
= true;
10056 sattrs
->iregion
= idau_region
;
10059 switch (env
->sau
.ctrl
& 3) {
10060 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
10062 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
10065 default: /* SAU.ENABLE == 1 */
10066 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
10067 if (env
->sau
.rlar
[r
] & 1) {
10068 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
10069 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
10071 if (base
<= address
&& limit
>= address
) {
10072 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10073 sattrs
->subpage
= true;
10075 if (sattrs
->srvalid
) {
10076 /* If we hit in more than one region then we must report
10077 * as Secure, not NS-Callable, with no valid region
10080 sattrs
->ns
= false;
10081 sattrs
->nsc
= false;
10082 sattrs
->sregion
= 0;
10083 sattrs
->srvalid
= false;
10086 if (env
->sau
.rlar
[r
] & 2) {
10087 sattrs
->nsc
= true;
10091 sattrs
->srvalid
= true;
10092 sattrs
->sregion
= r
;
10096 * Address not in this region. We must check whether the
10097 * region covers addresses in the same page as our address.
10098 * In that case we must not report a size that covers the
10099 * whole page for a subsequent hit against a different MPU
10100 * region or the background region, because it would result
10101 * in incorrect TLB hits for subsequent accesses to
10102 * addresses that are in this MPU region.
10104 if (limit
>= base
&&
10105 ranges_overlap(base
, limit
- base
+ 1,
10107 TARGET_PAGE_SIZE
)) {
10108 sattrs
->subpage
= true;
10117 * The IDAU will override the SAU lookup results if it specifies
10118 * higher security than the SAU does.
10121 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
10122 sattrs
->ns
= false;
10123 sattrs
->nsc
= idau_nsc
;
10128 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
10129 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10130 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10131 int *prot
, bool *is_subpage
,
10132 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
10134 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
10135 * that a full phys-to-virt translation does).
10136 * mregion is (if not NULL) set to the region number which matched,
10137 * or -1 if no region number is returned (MPU off, address did not
10138 * hit a region, address hit in multiple regions).
10139 * We set is_subpage to true if the region hit doesn't cover the
10140 * entire TARGET_PAGE the address is within.
10142 ARMCPU
*cpu
= env_archcpu(env
);
10143 bool is_user
= regime_is_user(env
, mmu_idx
);
10144 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10146 int matchregion
= -1;
10148 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10149 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10151 *is_subpage
= false;
10152 *phys_ptr
= address
;
10158 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
10159 * was an exception vector read from the vector table (which is always
10160 * done using the default system address map), because those accesses
10161 * are done in arm_v7m_load_vector(), which always does a direct
10162 * read using address_space_ldl(), rather than going via this function.
10164 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
10166 } else if (m_is_ppb_region(env
, address
)) {
10169 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10173 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10174 /* region search */
10175 /* Note that the base address is bits [31:5] from the register
10176 * with bits [4:0] all zeroes, but the limit address is bits
10177 * [31:5] from the register with bits [4:0] all ones.
10179 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
10180 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
10182 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
10183 /* Region disabled */
10187 if (address
< base
|| address
> limit
) {
10189 * Address not in this region. We must check whether the
10190 * region covers addresses in the same page as our address.
10191 * In that case we must not report a size that covers the
10192 * whole page for a subsequent hit against a different MPU
10193 * region or the background region, because it would result in
10194 * incorrect TLB hits for subsequent accesses to addresses that
10195 * are in this MPU region.
10197 if (limit
>= base
&&
10198 ranges_overlap(base
, limit
- base
+ 1,
10200 TARGET_PAGE_SIZE
)) {
10201 *is_subpage
= true;
10206 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10207 *is_subpage
= true;
10210 if (matchregion
!= -1) {
10211 /* Multiple regions match -- always a failure (unlike
10212 * PMSAv7 where highest-numbered-region wins)
10214 fi
->type
= ARMFault_Permission
;
10225 /* background fault */
10226 fi
->type
= ARMFault_Background
;
10230 if (matchregion
== -1) {
10231 /* hit using the background region */
10232 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10234 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
10235 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
10237 if (m_is_system_region(env
, address
)) {
10238 /* System space is always execute never */
10242 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
10243 if (*prot
&& !xn
) {
10244 *prot
|= PAGE_EXEC
;
10246 /* We don't need to look the attribute up in the MAIR0/MAIR1
10247 * registers because that only tells us about cacheability.
10250 *mregion
= matchregion
;
10254 fi
->type
= ARMFault_Permission
;
10256 return !(*prot
& (1 << access_type
));
10260 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
10261 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10262 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10263 int *prot
, target_ulong
*page_size
,
10264 ARMMMUFaultInfo
*fi
)
10266 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10267 V8M_SAttributes sattrs
= {};
10269 bool mpu_is_subpage
;
10271 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10272 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
10273 if (access_type
== MMU_INST_FETCH
) {
10274 /* Instruction fetches always use the MMU bank and the
10275 * transaction attribute determined by the fetch address,
10276 * regardless of CPU state. This is painful for QEMU
10277 * to handle, because it would mean we need to encode
10278 * into the mmu_idx not just the (user, negpri) information
10279 * for the current security state but also that for the
10280 * other security state, which would balloon the number
10281 * of mmu_idx values needed alarmingly.
10282 * Fortunately we can avoid this because it's not actually
10283 * possible to arbitrarily execute code from memory with
10284 * the wrong security attribute: it will always generate
10285 * an exception of some kind or another, apart from the
10286 * special case of an NS CPU executing an SG instruction
10287 * in S&NSC memory. So we always just fail the translation
10288 * here and sort things out in the exception handler
10289 * (including possibly emulating an SG instruction).
10291 if (sattrs
.ns
!= !secure
) {
10293 fi
->type
= ARMFault_QEMU_NSCExec
;
10295 fi
->type
= ARMFault_QEMU_SFault
;
10297 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10298 *phys_ptr
= address
;
10303 /* For data accesses we always use the MMU bank indicated
10304 * by the current CPU state, but the security attributes
10305 * might downgrade a secure access to nonsecure.
10308 txattrs
->secure
= false;
10309 } else if (!secure
) {
10310 /* NS access to S memory must fault.
10311 * Architecturally we should first check whether the
10312 * MPU information for this address indicates that we
10313 * are doing an unaligned access to Device memory, which
10314 * should generate a UsageFault instead. QEMU does not
10315 * currently check for that kind of unaligned access though.
10316 * If we added it we would need to do so as a special case
10317 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
10319 fi
->type
= ARMFault_QEMU_SFault
;
10320 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10321 *phys_ptr
= address
;
10328 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
10329 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
10330 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
10334 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
10335 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10336 hwaddr
*phys_ptr
, int *prot
,
10337 ARMMMUFaultInfo
*fi
)
10342 bool is_user
= regime_is_user(env
, mmu_idx
);
10344 if (regime_translation_disabled(env
, mmu_idx
)) {
10345 /* MPU disabled. */
10346 *phys_ptr
= address
;
10347 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10351 *phys_ptr
= address
;
10352 for (n
= 7; n
>= 0; n
--) {
10353 base
= env
->cp15
.c6_region
[n
];
10354 if ((base
& 1) == 0) {
10357 mask
= 1 << ((base
>> 1) & 0x1f);
10358 /* Keep this shift separate from the above to avoid an
10359 (undefined) << 32. */
10360 mask
= (mask
<< 1) - 1;
10361 if (((base
^ address
) & ~mask
) == 0) {
10366 fi
->type
= ARMFault_Background
;
10370 if (access_type
== MMU_INST_FETCH
) {
10371 mask
= env
->cp15
.pmsav5_insn_ap
;
10373 mask
= env
->cp15
.pmsav5_data_ap
;
10375 mask
= (mask
>> (n
* 4)) & 0xf;
10378 fi
->type
= ARMFault_Permission
;
10383 fi
->type
= ARMFault_Permission
;
10387 *prot
= PAGE_READ
| PAGE_WRITE
;
10392 *prot
|= PAGE_WRITE
;
10396 *prot
= PAGE_READ
| PAGE_WRITE
;
10400 fi
->type
= ARMFault_Permission
;
10410 /* Bad permission. */
10411 fi
->type
= ARMFault_Permission
;
10415 *prot
|= PAGE_EXEC
;
10419 /* Combine either inner or outer cacheability attributes for normal
10420 * memory, according to table D4-42 and pseudocode procedure
10421 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
10423 * NB: only stage 1 includes allocation hints (RW bits), leading to
10426 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
10428 if (s1
== 4 || s2
== 4) {
10429 /* non-cacheable has precedence */
10431 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
10432 /* stage 1 write-through takes precedence */
10434 } else if (extract32(s2
, 2, 2) == 2) {
10435 /* stage 2 write-through takes precedence, but the allocation hint
10436 * is still taken from stage 1
10438 return (2 << 2) | extract32(s1
, 0, 2);
10439 } else { /* write-back */
10444 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
10445 * and CombineS1S2Desc()
10447 * @s1: Attributes from stage 1 walk
10448 * @s2: Attributes from stage 2 walk
10450 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
10452 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
10453 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
10456 /* Combine shareability attributes (table D4-43) */
10457 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
10458 /* if either are outer-shareable, the result is outer-shareable */
10459 ret
.shareability
= 2;
10460 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
10461 /* if either are inner-shareable, the result is inner-shareable */
10462 ret
.shareability
= 3;
10464 /* both non-shareable */
10465 ret
.shareability
= 0;
10468 /* Combine memory type and cacheability attributes */
10469 if (s1hi
== 0 || s2hi
== 0) {
10470 /* Device has precedence over normal */
10471 if (s1lo
== 0 || s2lo
== 0) {
10472 /* nGnRnE has precedence over anything */
10474 } else if (s1lo
== 4 || s2lo
== 4) {
10475 /* non-Reordering has precedence over Reordering */
10476 ret
.attrs
= 4; /* nGnRE */
10477 } else if (s1lo
== 8 || s2lo
== 8) {
10478 /* non-Gathering has precedence over Gathering */
10479 ret
.attrs
= 8; /* nGRE */
10481 ret
.attrs
= 0xc; /* GRE */
10484 /* Any location for which the resultant memory type is any
10485 * type of Device memory is always treated as Outer Shareable.
10487 ret
.shareability
= 2;
10488 } else { /* Normal memory */
10489 /* Outer/inner cacheability combine independently */
10490 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
10491 | combine_cacheattr_nibble(s1lo
, s2lo
);
10493 if (ret
.attrs
== 0x44) {
10494 /* Any location for which the resultant memory type is Normal
10495 * Inner Non-cacheable, Outer Non-cacheable is always treated
10496 * as Outer Shareable.
10498 ret
.shareability
= 2;
10506 /* get_phys_addr - get the physical address for this virtual address
10508 * Find the physical address corresponding to the given virtual address,
10509 * by doing a translation table walk on MMU based systems or using the
10510 * MPU state on MPU based systems.
10512 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10513 * prot and page_size may not be filled in, and the populated fsr value provides
10514 * information on why the translation aborted, in the format of a
10515 * DFSR/IFSR fault register, with the following caveats:
10516 * * we honour the short vs long DFSR format differences.
10517 * * the WnR bit is never set (the caller must do this).
10518 * * for PSMAv5 based systems we don't bother to return a full FSR format
10521 * @env: CPUARMState
10522 * @address: virtual address to get physical address for
10523 * @access_type: 0 for read, 1 for write, 2 for execute
10524 * @mmu_idx: MMU index indicating required translation regime
10525 * @phys_ptr: set to the physical address corresponding to the virtual address
10526 * @attrs: set to the memory transaction attributes to use
10527 * @prot: set to the permissions for the page containing phys_ptr
10528 * @page_size: set to the size of the page containing phys_ptr
10529 * @fi: set to fault info if the translation fails
10530 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10532 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
10533 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10534 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10535 target_ulong
*page_size
,
10536 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10538 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
10539 /* Call ourselves recursively to do the stage 1 and then stage 2
10542 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
10546 ARMCacheAttrs cacheattrs2
= {};
10548 ret
= get_phys_addr(env
, address
, access_type
,
10549 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
10550 prot
, page_size
, fi
, cacheattrs
);
10552 /* If S1 fails or S2 is disabled, return early. */
10553 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
10558 /* S1 is done. Now do S2 translation. */
10559 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
10560 phys_ptr
, attrs
, &s2_prot
,
10562 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
10564 /* Combine the S1 and S2 perms. */
10567 /* Combine the S1 and S2 cache attributes, if needed */
10568 if (!ret
&& cacheattrs
!= NULL
) {
10569 if (env
->cp15
.hcr_el2
& HCR_DC
) {
10571 * HCR.DC forces the first stage attributes to
10572 * Normal Non-Shareable,
10573 * Inner Write-Back Read-Allocate Write-Allocate,
10574 * Outer Write-Back Read-Allocate Write-Allocate.
10576 cacheattrs
->attrs
= 0xff;
10577 cacheattrs
->shareability
= 0;
10579 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
10585 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
10587 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10591 /* The page table entries may downgrade secure to non-secure, but
10592 * cannot upgrade an non-secure translation regime's attributes
10595 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
10596 attrs
->user
= regime_is_user(env
, mmu_idx
);
10598 /* Fast Context Switch Extension. This doesn't exist at all in v8.
10599 * In v7 and earlier it affects all stage 1 translations.
10601 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
10602 && !arm_feature(env
, ARM_FEATURE_V8
)) {
10603 if (regime_el(env
, mmu_idx
) == 3) {
10604 address
+= env
->cp15
.fcseidr_s
;
10606 address
+= env
->cp15
.fcseidr_ns
;
10610 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
10612 *page_size
= TARGET_PAGE_SIZE
;
10614 if (arm_feature(env
, ARM_FEATURE_V8
)) {
10616 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
10617 phys_ptr
, attrs
, prot
, page_size
, fi
);
10618 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10620 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
10621 phys_ptr
, prot
, page_size
, fi
);
10624 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
10625 phys_ptr
, prot
, fi
);
10627 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
10628 " mmu_idx %u -> %s (prot %c%c%c)\n",
10629 access_type
== MMU_DATA_LOAD
? "reading" :
10630 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
10631 (uint32_t)address
, mmu_idx
,
10632 ret
? "Miss" : "Hit",
10633 *prot
& PAGE_READ
? 'r' : '-',
10634 *prot
& PAGE_WRITE
? 'w' : '-',
10635 *prot
& PAGE_EXEC
? 'x' : '-');
10640 /* Definitely a real MMU, not an MPU */
10642 if (regime_translation_disabled(env
, mmu_idx
)) {
10643 /* MMU disabled. */
10644 *phys_ptr
= address
;
10645 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10646 *page_size
= TARGET_PAGE_SIZE
;
10650 if (regime_using_lpae_format(env
, mmu_idx
)) {
10651 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
10652 phys_ptr
, attrs
, prot
, page_size
,
10654 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
10655 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
10656 phys_ptr
, attrs
, prot
, page_size
, fi
);
10658 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
10659 phys_ptr
, prot
, page_size
, fi
);
10663 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
10666 ARMCPU
*cpu
= ARM_CPU(cs
);
10667 CPUARMState
*env
= &cpu
->env
;
10669 target_ulong page_size
;
10672 ARMMMUFaultInfo fi
= {};
10673 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
10675 *attrs
= (MemTxAttrs
) {};
10677 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
10678 attrs
, &prot
, &page_size
, &fi
, NULL
);
10688 /* Note that signed overflow is undefined in C. The following routines are
10689 careful to use unsigned types where modulo arithmetic is required.
10690 Failure to do so _will_ break on newer gcc. */
10692 /* Signed saturating arithmetic. */
10694 /* Perform 16-bit signed saturating addition. */
10695 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10700 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10709 /* Perform 8-bit signed saturating addition. */
10710 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10715 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10724 /* Perform 16-bit signed saturating subtraction. */
10725 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10730 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10739 /* Perform 8-bit signed saturating subtraction. */
10740 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10745 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10754 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10755 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10756 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10757 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10760 #include "op_addsub.h"
10762 /* Unsigned saturating arithmetic. */
10763 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10772 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10780 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10789 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10797 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10798 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10799 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10800 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10803 #include "op_addsub.h"
10805 /* Signed modulo arithmetic. */
10806 #define SARITH16(a, b, n, op) do { \
10808 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10809 RESULT(sum, n, 16); \
10811 ge |= 3 << (n * 2); \
10814 #define SARITH8(a, b, n, op) do { \
10816 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10817 RESULT(sum, n, 8); \
10823 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10824 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10825 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10826 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10830 #include "op_addsub.h"
10832 /* Unsigned modulo arithmetic. */
10833 #define ADD16(a, b, n) do { \
10835 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10836 RESULT(sum, n, 16); \
10837 if ((sum >> 16) == 1) \
10838 ge |= 3 << (n * 2); \
10841 #define ADD8(a, b, n) do { \
10843 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10844 RESULT(sum, n, 8); \
10845 if ((sum >> 8) == 1) \
10849 #define SUB16(a, b, n) do { \
10851 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10852 RESULT(sum, n, 16); \
10853 if ((sum >> 16) == 0) \
10854 ge |= 3 << (n * 2); \
10857 #define SUB8(a, b, n) do { \
10859 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10860 RESULT(sum, n, 8); \
10861 if ((sum >> 8) == 0) \
10868 #include "op_addsub.h"
10870 /* Halved signed arithmetic. */
10871 #define ADD16(a, b, n) \
10872 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10873 #define SUB16(a, b, n) \
10874 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10875 #define ADD8(a, b, n) \
10876 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10877 #define SUB8(a, b, n) \
10878 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10881 #include "op_addsub.h"
10883 /* Halved unsigned arithmetic. */
10884 #define ADD16(a, b, n) \
10885 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10886 #define SUB16(a, b, n) \
10887 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10888 #define ADD8(a, b, n) \
10889 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10890 #define SUB8(a, b, n) \
10891 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10894 #include "op_addsub.h"
10896 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10904 /* Unsigned sum of absolute byte differences. */
10905 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10908 sum
= do_usad(a
, b
);
10909 sum
+= do_usad(a
>> 8, b
>> 8);
10910 sum
+= do_usad(a
>> 16, b
>>16);
10911 sum
+= do_usad(a
>> 24, b
>> 24);
10915 /* For ARMv6 SEL instruction. */
10916 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10928 mask
|= 0xff000000;
10929 return (a
& mask
) | (b
& ~mask
);
10933 * The upper bytes of val (above the number specified by 'bytes') must have
10934 * been zeroed out by the caller.
10936 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10940 stl_le_p(buf
, val
);
10942 /* zlib crc32 converts the accumulator and output to one's complement. */
10943 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
10946 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10950 stl_le_p(buf
, val
);
10952 /* Linux crc32c converts the output to one's complement. */
10953 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
10956 /* Return the exception level to which FP-disabled exceptions should
10957 * be taken, or 0 if FP is enabled.
10959 int fp_exception_el(CPUARMState
*env
, int cur_el
)
10961 #ifndef CONFIG_USER_ONLY
10964 /* CPACR and the CPTR registers don't exist before v6, so FP is
10965 * always accessible
10967 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
10971 if (arm_feature(env
, ARM_FEATURE_M
)) {
10972 /* CPACR can cause a NOCP UsageFault taken to current security state */
10973 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
10977 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
10978 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
10979 /* FP insns cause a NOCP UsageFault taken to Secure */
10987 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
10988 * 0, 2 : trap EL0 and EL1/PL1 accesses
10989 * 1 : trap only EL0 accesses
10990 * 3 : trap no accesses
10992 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
10996 if (cur_el
== 0 || cur_el
== 1) {
10997 /* Trap to PL1, which might be EL1 or EL3 */
10998 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
11003 if (cur_el
== 3 && !is_a64(env
)) {
11004 /* Secure PL1 running at EL3 */
11018 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11019 * to control non-secure access to the FPU. It doesn't have any
11020 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11022 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11023 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11024 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11025 /* FP insns act as UNDEF */
11026 return cur_el
== 2 ? 2 : 1;
11030 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
11031 * check because zero bits in the registers mean "don't trap".
11034 /* CPTR_EL2 : present in v7VE or v8 */
11035 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
11036 && !arm_is_secure_below_el3(env
)) {
11037 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
11041 /* CPTR_EL3 : present in v8 */
11042 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
11043 /* Trap all FP ops to EL3 */
11051 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11053 g_assert_not_reached();
11057 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11059 if (arm_feature(env
, ARM_FEATURE_M
)) {
11060 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11063 if (el
< 2 && arm_is_secure_below_el3(env
)) {
11064 return ARMMMUIdx_S1SE0
+ el
;
11066 return ARMMMUIdx_S12NSE0
+ el
;
11070 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11072 return arm_mmu_idx_el(env
, arm_current_el(env
));
11075 int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
11077 return arm_to_core_mmu_idx(arm_mmu_idx(env
));
11080 #ifndef CONFIG_USER_ONLY
11081 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
11083 return stage_1_mmu_idx(arm_mmu_idx(env
));
11087 static uint32_t rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11088 ARMMMUIdx mmu_idx
, uint32_t flags
)
11090 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
11091 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
,
11092 arm_to_core_mmu_idx(mmu_idx
));
11094 if (arm_singlestep_active(env
)) {
11095 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
11100 static uint32_t rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11101 ARMMMUIdx mmu_idx
, uint32_t flags
)
11103 bool sctlr_b
= arm_sctlr_b(env
);
11106 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, 1);
11108 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11109 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
11111 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
11113 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11116 static uint32_t rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11119 uint32_t flags
= 0;
11121 /* v8M always enables the fpu. */
11122 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
11124 if (arm_v7m_is_handler_mode(env
)) {
11125 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HANDLER
, 1);
11129 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11130 * is suppressing them because the requested execution priority
11133 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11134 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11135 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11136 flags
= FIELD_DP32(flags
, TBFLAG_A32
, STACKCHECK
, 1);
11139 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11142 static uint32_t rebuild_hflags_aprofile(CPUARMState
*env
)
11146 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
,
11147 arm_debug_target_el(env
));
11151 static uint32_t rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11154 uint32_t flags
= rebuild_hflags_aprofile(env
);
11156 if (arm_el_is_aa64(env
, 1)) {
11157 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
11159 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11162 static uint32_t rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11165 uint32_t flags
= rebuild_hflags_aprofile(env
);
11166 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11167 ARMVAParameters p0
= aa64_va_parameters_both(env
, 0, stage1
);
11171 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
11173 /* FIXME: ARMv8.1-VHE S2 translation regime. */
11174 if (regime_el(env
, stage1
) < 2) {
11175 ARMVAParameters p1
= aa64_va_parameters_both(env
, -1, stage1
);
11176 tbid
= (p1
.tbi
<< 1) | p0
.tbi
;
11177 tbii
= tbid
& ~((p1
.tbid
<< 1) | p0
.tbid
);
11180 tbii
= tbid
& !p0
.tbid
;
11183 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
11184 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
11186 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11187 int sve_el
= sve_exception_el(env
, el
);
11191 * If SVE is disabled, but FP is enabled,
11192 * then the effective len is 0.
11194 if (sve_el
!= 0 && fp_el
== 0) {
11197 zcr_len
= sve_zcr_len_for_el(env
, el
);
11199 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
11200 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
11203 sctlr
= arm_sctlr(env
, el
);
11205 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
11206 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
11209 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
11211 * In order to save space in flags, we record only whether
11212 * pauth is "inactive", meaning all insns are implemented as
11213 * a nop, or "active" when some action must be performed.
11214 * The decision of which action to take is left to a helper.
11216 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
11217 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
11221 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11222 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
11223 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
11224 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
11228 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11231 static uint32_t rebuild_hflags_internal(CPUARMState
*env
)
11233 int el
= arm_current_el(env
);
11234 int fp_el
= fp_exception_el(env
, el
);
11235 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11238 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11239 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
11240 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11242 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11246 void arm_rebuild_hflags(CPUARMState
*env
)
11248 env
->hflags
= rebuild_hflags_internal(env
);
11251 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
11253 int fp_el
= fp_exception_el(env
, el
);
11254 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11256 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11259 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
11261 int fp_el
= fp_exception_el(env
, el
);
11262 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11264 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11267 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
11269 int fp_el
= fp_exception_el(env
, el
);
11270 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11272 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11275 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11276 target_ulong
*cs_base
, uint32_t *pflags
)
11278 uint32_t flags
= env
->hflags
;
11279 uint32_t pstate_for_ss
;
11282 #ifdef CONFIG_DEBUG_TCG
11283 assert(flags
== rebuild_hflags_internal(env
));
11286 if (FIELD_EX32(flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
11288 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11289 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
11291 pstate_for_ss
= env
->pstate
;
11293 *pc
= env
->regs
[15];
11295 if (arm_feature(env
, ARM_FEATURE_M
)) {
11296 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11297 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
11298 != env
->v7m
.secure
) {
11299 flags
= FIELD_DP32(flags
, TBFLAG_A32
, FPCCR_S_WRONG
, 1);
11302 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
11303 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
11304 (env
->v7m
.secure
&&
11305 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
11307 * ASPEN is set, but FPCA/SFPA indicate that there is no
11308 * active FP context; we must create a new FP context before
11309 * executing any FP insn.
11311 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NEW_FP_CTXT_NEEDED
, 1);
11314 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
11315 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
11316 flags
= FIELD_DP32(flags
, TBFLAG_A32
, LSPACT
, 1);
11320 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
11321 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
11323 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11324 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
11325 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
11327 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
,
11329 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
,
11330 env
->vfp
.vec_stride
);
11332 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
11333 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
11337 flags
= FIELD_DP32(flags
, TBFLAG_A32
, THUMB
, env
->thumb
);
11338 flags
= FIELD_DP32(flags
, TBFLAG_A32
, CONDEXEC
, env
->condexec_bits
);
11339 pstate_for_ss
= env
->uncached_cpsr
;
11343 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11344 * states defined in the ARM ARM for software singlestep:
11345 * SS_ACTIVE PSTATE.SS State
11346 * 0 x Inactive (the TB flag for SS is always 0)
11347 * 1 0 Active-pending
11348 * 1 1 Active-not-pending
11349 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
11351 if (FIELD_EX32(flags
, TBFLAG_ANY
, SS_ACTIVE
) &&
11352 (pstate_for_ss
& PSTATE_SS
)) {
11353 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
11359 #ifdef TARGET_AARCH64
11361 * The manual says that when SVE is enabled and VQ is widened the
11362 * implementation is allowed to zero the previously inaccessible
11363 * portion of the registers. The corollary to that is that when
11364 * SVE is enabled and VQ is narrowed we are also allowed to zero
11365 * the now inaccessible portion of the registers.
11367 * The intent of this is that no predicate bit beyond VQ is ever set.
11368 * Which means that some operations on predicate registers themselves
11369 * may operate on full uint64_t or even unrolled across the maximum
11370 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
11371 * may well be cheaper than conditionals to restrict the operation
11372 * to the relevant portion of a uint16_t[16].
11374 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
11379 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
11380 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
11382 /* Zap the high bits of the zregs. */
11383 for (i
= 0; i
< 32; i
++) {
11384 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
11387 /* Zap the high bits of the pregs and ffr. */
11390 pmask
= ~(-1ULL << (16 * (vq
& 3)));
11392 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
11393 for (i
= 0; i
< 17; ++i
) {
11394 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
11401 * Notice a change in SVE vector size when changing EL.
11403 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
11404 int new_el
, bool el0_a64
)
11406 ARMCPU
*cpu
= env_archcpu(env
);
11407 int old_len
, new_len
;
11408 bool old_a64
, new_a64
;
11410 /* Nothing to do if no SVE. */
11411 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
11415 /* Nothing to do if FP is disabled in either EL. */
11416 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
11421 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
11422 * at ELx, or not available because the EL is in AArch32 state, then
11423 * for all purposes other than a direct read, the ZCR_ELx.LEN field
11424 * has an effective value of 0".
11426 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
11427 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
11428 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
11429 * we already have the correct register contents when encountering the
11430 * vq0->vq0 transition between EL0->EL1.
11432 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
11433 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
11434 ? sve_zcr_len_for_el(env
, old_el
) : 0);
11435 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
11436 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
11437 ? sve_zcr_len_for_el(env
, new_el
) : 0);
11439 /* When changing vector length, clear inaccessible state. */
11440 if (new_len
< old_len
) {
11441 aarch64_sve_narrow_vq(env
, new_len
+ 1);