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failover: simplify virtio_net_find_primary()
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob76e27f8fad319adc4b64c4347fbf27e8b2826e4f
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/rtc/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "hw/mem/nvdimm.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "hw/hyperv/vmbus-bridge.h"
55
56 /* Supported chipsets: */
57 #include "hw/southbridge/piix.h"
58 #include "hw/acpi/pcihp.h"
59 #include "hw/i386/fw_cfg.h"
60 #include "hw/i386/ich9.h"
61 #include "hw/pci/pci_bus.h"
62 #include "hw/pci-host/q35.h"
63 #include "hw/i386/x86-iommu.h"
64
65 #include "hw/acpi/aml-build.h"
66 #include "hw/acpi/utils.h"
67 #include "hw/acpi/pci.h"
68
69 #include "qom/qom-qobject.h"
70 #include "hw/i386/amd_iommu.h"
71 #include "hw/i386/intel_iommu.h"
72
73 #include "hw/acpi/ipmi.h"
74 #include "hw/acpi/hmat.h"
75
76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
78 * a little bit, there should be plenty of free space since the DSDT
79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
80 */
81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
82 #define ACPI_BUILD_ALIGN_SIZE 0x1000
83
84 #define ACPI_BUILD_TABLE_SIZE 0x20000
85
86 /* #define DEBUG_ACPI_BUILD */
87 #ifdef DEBUG_ACPI_BUILD
88 #define ACPI_BUILD_DPRINTF(fmt, ...) \
89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
90 #else
91 #define ACPI_BUILD_DPRINTF(fmt, ...)
92 #endif
93
94 typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 bool smi_on_cpuhp;
99 bool pcihp_root_en;
100 uint8_t s4_val;
101 AcpiFadtData fadt;
102 uint16_t cpu_hp_io_base;
103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106
107 typedef struct AcpiMiscInfo {
108 bool is_piix4;
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 typedef struct FwCfgTPMConfig {
125 uint32_t tpmppi_address;
126 uint8_t tpm_version;
127 uint8_t tpmppi_version;
128 } QEMU_PACKED FwCfgTPMConfig;
129
130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
131
132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
133 .space_id = AML_AS_SYSTEM_IO,
134 .address = NVDIMM_ACPI_IO_BASE,
135 .bit_width = NVDIMM_ACPI_IO_LEN << 3
136 };
137
138 static void init_common_fadt_data(MachineState *ms, Object *o,
139 AcpiFadtData *data)
140 {
141 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
142 AmlAddressSpace as = AML_AS_SYSTEM_IO;
143 AcpiFadtData fadt = {
144 .rev = 3,
145 .flags =
146 (1 << ACPI_FADT_F_WBINVD) |
147 (1 << ACPI_FADT_F_PROC_C1) |
148 (1 << ACPI_FADT_F_SLP_BUTTON) |
149 (1 << ACPI_FADT_F_RTC_S4) |
150 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
151 /* APIC destination mode ("Flat Logical") has an upper limit of 8
152 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
153 * used
154 */
155 ((ms->smp.max_cpus > 8) ?
156 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
157 .int_model = 1 /* Multiple APIC */,
158 .rtc_century = RTC_CENTURY,
159 .plvl2_lat = 0xfff /* C2 state not supported */,
160 .plvl3_lat = 0xfff /* C3 state not supported */,
161 .smi_cmd = ACPI_PORT_SMI_CMD,
162 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
163 .acpi_enable_cmd =
164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
165 .acpi_disable_cmd =
166 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
167 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
168 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
169 .address = io + 0x04 },
170 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
171 .gpe0_blk = { .space_id = as, .bit_width =
172 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
173 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
174 },
175 };
176 *data = fadt;
177 }
178
179 static Object *object_resolve_type_unambiguous(const char *typename)
180 {
181 bool ambig;
182 Object *o = object_resolve_path_type("", typename, &ambig);
183
184 if (ambig || !o) {
185 return NULL;
186 }
187 return o;
188 }
189
190 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
191 {
192 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
193 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
194 Object *obj = piix ? piix : lpc;
195 QObject *o;
196 pm->cpu_hp_io_base = 0;
197 pm->pcihp_io_base = 0;
198 pm->pcihp_io_len = 0;
199 pm->smi_on_cpuhp = false;
200
201 assert(obj);
202 init_common_fadt_data(machine, obj, &pm->fadt);
203 if (piix) {
204 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
205 pm->fadt.rev = 1;
206 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
207 pm->pcihp_io_base =
208 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
209 pm->pcihp_io_len =
210 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
211 }
212 if (lpc) {
213 uint64_t smi_features = object_property_get_uint(lpc,
214 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
215 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
216 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
217 pm->fadt.reset_reg = r;
218 pm->fadt.reset_val = 0xf;
219 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
220 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
221 pm->smi_on_cpuhp =
222 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
223 }
224
225 /* The above need not be conditional on machine type because the reset port
226 * happens to be the same on PIIX (pc) and ICH9 (q35). */
227 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
228
229 /* Fill in optional s3/s4 related properties */
230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
231 if (o) {
232 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
233 } else {
234 pm->s3_disabled = false;
235 }
236 qobject_unref(o);
237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
238 if (o) {
239 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
240 } else {
241 pm->s4_disabled = false;
242 }
243 qobject_unref(o);
244 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
245 if (o) {
246 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
247 } else {
248 pm->s4_val = false;
249 }
250 qobject_unref(o);
251
252 pm->pcihp_bridge_en =
253 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
254 NULL);
255 pm->pcihp_root_en =
256 object_property_get_bool(obj, "acpi-root-pci-hotplug",
257 NULL);
258 }
259
260 static void acpi_get_misc_info(AcpiMiscInfo *info)
261 {
262 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
263 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
264 assert(!!piix != !!lpc);
265
266 if (piix) {
267 info->is_piix4 = true;
268 }
269 if (lpc) {
270 info->is_piix4 = false;
271 }
272
273 info->has_hpet = hpet_find();
274 info->tpm_version = tpm_get_version(tpm_find());
275 info->pvpanic_port = pvpanic_port();
276 info->applesmc_io_base = applesmc_port();
277 }
278
279 /*
280 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
281 * On i386 arch we only have two pci hosts, so we can look only for them.
282 */
283 static Object *acpi_get_i386_pci_host(void)
284 {
285 PCIHostState *host;
286
287 host = OBJECT_CHECK(PCIHostState,
288 object_resolve_path("/machine/i440fx", NULL),
289 TYPE_PCI_HOST_BRIDGE);
290 if (!host) {
291 host = OBJECT_CHECK(PCIHostState,
292 object_resolve_path("/machine/q35", NULL),
293 TYPE_PCI_HOST_BRIDGE);
294 }
295
296 return OBJECT(host);
297 }
298
299 static void acpi_get_pci_holes(Range *hole, Range *hole64)
300 {
301 Object *pci_host;
302
303 pci_host = acpi_get_i386_pci_host();
304 g_assert(pci_host);
305
306 range_set_bounds1(hole,
307 object_property_get_uint(pci_host,
308 PCI_HOST_PROP_PCI_HOLE_START,
309 NULL),
310 object_property_get_uint(pci_host,
311 PCI_HOST_PROP_PCI_HOLE_END,
312 NULL));
313 range_set_bounds1(hole64,
314 object_property_get_uint(pci_host,
315 PCI_HOST_PROP_PCI_HOLE64_START,
316 NULL),
317 object_property_get_uint(pci_host,
318 PCI_HOST_PROP_PCI_HOLE64_END,
319 NULL));
320 }
321
322 static void acpi_align_size(GArray *blob, unsigned align)
323 {
324 /* Align size to multiple of given size. This reduces the chance
325 * we need to change size in the future (breaking cross version migration).
326 */
327 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
328 }
329
330 /* FACS */
331 static void
332 build_facs(GArray *table_data)
333 {
334 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
335 memcpy(&facs->signature, "FACS", 4);
336 facs->length = cpu_to_le32(sizeof(*facs));
337 }
338
339 static void build_append_pcihp_notify_entry(Aml *method, int slot)
340 {
341 Aml *if_ctx;
342 int32_t devfn = PCI_DEVFN(slot, 0);
343
344 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
345 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
346 aml_append(method, if_ctx);
347 }
348
349 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
350 bool pcihp_bridge_en)
351 {
352 Aml *dev, *notify_method = NULL, *method;
353 QObject *bsel;
354 PCIBus *sec;
355 int i;
356
357 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
358 if (bsel) {
359 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
360
361 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
362 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
363 }
364
365 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
366 DeviceClass *dc;
367 PCIDeviceClass *pc;
368 PCIDevice *pdev = bus->devices[i];
369 int slot = PCI_SLOT(i);
370 bool hotplug_enabled_dev;
371 bool bridge_in_acpi;
372 bool cold_plugged_bridge;
373
374 if (!pdev) {
375 if (bsel) { /* add hotplug slots for non present devices */
376 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
377 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
378 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
379 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
380 aml_append(method,
381 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
382 );
383 aml_append(dev, method);
384 aml_append(parent_scope, dev);
385
386 build_append_pcihp_notify_entry(notify_method, slot);
387 }
388 continue;
389 }
390
391 pc = PCI_DEVICE_GET_CLASS(pdev);
392 dc = DEVICE_GET_CLASS(pdev);
393
394 /*
395 * Cold plugged bridges aren't themselves hot-pluggable.
396 * Hotplugged bridges *are* hot-pluggable.
397 */
398 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
399 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
400
401 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
402
403 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
404 continue;
405 }
406
407 /* start to compose PCI slot descriptor */
408 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
409 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
410
411 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
412 /* add VGA specific AML methods */
413 int s3d;
414
415 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
416 s3d = 3;
417 } else {
418 s3d = 0;
419 }
420
421 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
422 aml_append(method, aml_return(aml_int(0)));
423 aml_append(dev, method);
424
425 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
426 aml_append(method, aml_return(aml_int(0)));
427 aml_append(dev, method);
428
429 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
430 aml_append(method, aml_return(aml_int(s3d)));
431 aml_append(dev, method);
432 } else if (hotplug_enabled_dev) {
433 /* add _SUN/_EJ0 to make slot hotpluggable */
434 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
435
436 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
437 aml_append(method,
438 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
439 );
440 aml_append(dev, method);
441
442 if (bsel) {
443 build_append_pcihp_notify_entry(notify_method, slot);
444 }
445 } else if (bridge_in_acpi) {
446 /*
447 * device is coldplugged bridge,
448 * add child device descriptions into its scope
449 */
450 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
451
452 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
453 }
454 /* slot descriptor has been composed, add it into parent context */
455 aml_append(parent_scope, dev);
456 }
457
458 if (bsel) {
459 aml_append(parent_scope, notify_method);
460 }
461
462 /* Append PCNT method to notify about events on local and child buses.
463 * Add this method for root bus only when hotplug is enabled since DSDT
464 * expects it.
465 */
466 if (bsel || pcihp_bridge_en) {
467 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
468
469 /* If bus supports hotplug select it and notify about local events */
470 if (bsel) {
471 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
472
473 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
474 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
475 aml_int(1))); /* Device Check */
476 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
477 aml_int(3))); /* Eject Request */
478 }
479
480 /* Notify about child bus events in any case */
481 if (pcihp_bridge_en) {
482 QLIST_FOREACH(sec, &bus->child, sibling) {
483 int32_t devfn = sec->parent_dev->devfn;
484
485 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
486 continue;
487 }
488
489 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
490 }
491 }
492
493 aml_append(parent_scope, method);
494 }
495 qobject_unref(bsel);
496 }
497
498 /**
499 * build_prt_entry:
500 * @link_name: link name for PCI route entry
501 *
502 * build AML package containing a PCI route entry for @link_name
503 */
504 static Aml *build_prt_entry(const char *link_name)
505 {
506 Aml *a_zero = aml_int(0);
507 Aml *pkg = aml_package(4);
508 aml_append(pkg, a_zero);
509 aml_append(pkg, a_zero);
510 aml_append(pkg, aml_name("%s", link_name));
511 aml_append(pkg, a_zero);
512 return pkg;
513 }
514
515 /*
516 * initialize_route - Initialize the interrupt routing rule
517 * through a specific LINK:
518 * if (lnk_idx == idx)
519 * route using link 'link_name'
520 */
521 static Aml *initialize_route(Aml *route, const char *link_name,
522 Aml *lnk_idx, int idx)
523 {
524 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
525 Aml *pkg = build_prt_entry(link_name);
526
527 aml_append(if_ctx, aml_store(pkg, route));
528
529 return if_ctx;
530 }
531
532 /*
533 * build_prt - Define interrupt rounting rules
534 *
535 * Returns an array of 128 routes, one for each device,
536 * based on device location.
537 * The main goal is to equaly distribute the interrupts
538 * over the 4 existing ACPI links (works only for i440fx).
539 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
540 *
541 */
542 static Aml *build_prt(bool is_pci0_prt)
543 {
544 Aml *method, *while_ctx, *pin, *res;
545
546 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
547 res = aml_local(0);
548 pin = aml_local(1);
549 aml_append(method, aml_store(aml_package(128), res));
550 aml_append(method, aml_store(aml_int(0), pin));
551
552 /* while (pin < 128) */
553 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
554 {
555 Aml *slot = aml_local(2);
556 Aml *lnk_idx = aml_local(3);
557 Aml *route = aml_local(4);
558
559 /* slot = pin >> 2 */
560 aml_append(while_ctx,
561 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
562 /* lnk_idx = (slot + pin) & 3 */
563 aml_append(while_ctx,
564 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
565 lnk_idx));
566
567 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
568 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
569 if (is_pci0_prt) {
570 Aml *if_device_1, *if_pin_4, *else_pin_4;
571
572 /* device 1 is the power-management device, needs SCI */
573 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
574 {
575 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
576 {
577 aml_append(if_pin_4,
578 aml_store(build_prt_entry("LNKS"), route));
579 }
580 aml_append(if_device_1, if_pin_4);
581 else_pin_4 = aml_else();
582 {
583 aml_append(else_pin_4,
584 aml_store(build_prt_entry("LNKA"), route));
585 }
586 aml_append(if_device_1, else_pin_4);
587 }
588 aml_append(while_ctx, if_device_1);
589 } else {
590 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
591 }
592 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
593 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
594
595 /* route[0] = 0x[slot]FFFF */
596 aml_append(while_ctx,
597 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
598 NULL),
599 aml_index(route, aml_int(0))));
600 /* route[1] = pin & 3 */
601 aml_append(while_ctx,
602 aml_store(aml_and(pin, aml_int(3), NULL),
603 aml_index(route, aml_int(1))));
604 /* res[pin] = route */
605 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
606 /* pin++ */
607 aml_append(while_ctx, aml_increment(pin));
608 }
609 aml_append(method, while_ctx);
610 /* return res*/
611 aml_append(method, aml_return(res));
612
613 return method;
614 }
615
616 static void build_hpet_aml(Aml *table)
617 {
618 Aml *crs;
619 Aml *field;
620 Aml *method;
621 Aml *if_ctx;
622 Aml *scope = aml_scope("_SB");
623 Aml *dev = aml_device("HPET");
624 Aml *zero = aml_int(0);
625 Aml *id = aml_local(0);
626 Aml *period = aml_local(1);
627
628 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
629 aml_append(dev, aml_name_decl("_UID", zero));
630
631 aml_append(dev,
632 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
633 HPET_LEN));
634 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
635 aml_append(field, aml_named_field("VEND", 32));
636 aml_append(field, aml_named_field("PRD", 32));
637 aml_append(dev, field);
638
639 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
640 aml_append(method, aml_store(aml_name("VEND"), id));
641 aml_append(method, aml_store(aml_name("PRD"), period));
642 aml_append(method, aml_shiftright(id, aml_int(16), id));
643 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
644 aml_equal(id, aml_int(0xffff))));
645 {
646 aml_append(if_ctx, aml_return(zero));
647 }
648 aml_append(method, if_ctx);
649
650 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
651 aml_lgreater(period, aml_int(100000000))));
652 {
653 aml_append(if_ctx, aml_return(zero));
654 }
655 aml_append(method, if_ctx);
656
657 aml_append(method, aml_return(aml_int(0x0F)));
658 aml_append(dev, method);
659
660 crs = aml_resource_template();
661 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
662 aml_append(dev, aml_name_decl("_CRS", crs));
663
664 aml_append(scope, dev);
665 aml_append(table, scope);
666 }
667
668 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
669 {
670 Aml *dev;
671 Aml *method;
672 Aml *crs;
673
674 dev = aml_device("VMBS");
675 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
676 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
677 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
678 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
679
680 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
681 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
682 aml_name("STA")));
683 aml_append(dev, method);
684
685 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
686 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
687 aml_name("STA")));
688 aml_append(dev, method);
689
690 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
691 aml_append(method, aml_return(aml_name("STA")));
692 aml_append(dev, method);
693
694 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
695
696 crs = aml_resource_template();
697 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
698 aml_append(dev, aml_name_decl("_CRS", crs));
699
700 return dev;
701 }
702
703 static void build_isa_devices_aml(Aml *table)
704 {
705 bool ambiguous;
706 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
707 Aml *scope;
708
709 assert(obj && !ambiguous);
710
711 scope = aml_scope("_SB.PCI0.ISA");
712 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
713 isa_build_aml(ISA_BUS(obj), scope);
714
715 aml_append(table, scope);
716 }
717
718 static void build_dbg_aml(Aml *table)
719 {
720 Aml *field;
721 Aml *method;
722 Aml *while_ctx;
723 Aml *scope = aml_scope("\\");
724 Aml *buf = aml_local(0);
725 Aml *len = aml_local(1);
726 Aml *idx = aml_local(2);
727
728 aml_append(scope,
729 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
730 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
731 aml_append(field, aml_named_field("DBGB", 8));
732 aml_append(scope, field);
733
734 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
735
736 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
737 aml_append(method, aml_to_buffer(buf, buf));
738 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
739 aml_append(method, aml_store(aml_int(0), idx));
740
741 while_ctx = aml_while(aml_lless(idx, len));
742 aml_append(while_ctx,
743 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
744 aml_append(while_ctx, aml_increment(idx));
745 aml_append(method, while_ctx);
746
747 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
748 aml_append(scope, method);
749
750 aml_append(table, scope);
751 }
752
753 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
754 {
755 Aml *dev;
756 Aml *crs;
757 Aml *method;
758 uint32_t irqs[] = {5, 10, 11};
759
760 dev = aml_device("%s", name);
761 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
762 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
763
764 crs = aml_resource_template();
765 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
766 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
767 aml_append(dev, aml_name_decl("_PRS", crs));
768
769 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
770 aml_append(method, aml_return(aml_call1("IQST", reg)));
771 aml_append(dev, method);
772
773 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
774 aml_append(method, aml_or(reg, aml_int(0x80), reg));
775 aml_append(dev, method);
776
777 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
778 aml_append(method, aml_return(aml_call1("IQCR", reg)));
779 aml_append(dev, method);
780
781 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
782 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
783 aml_append(method, aml_store(aml_name("PRRI"), reg));
784 aml_append(dev, method);
785
786 return dev;
787 }
788
789 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
790 {
791 Aml *dev;
792 Aml *crs;
793 Aml *method;
794 uint32_t irqs;
795
796 dev = aml_device("%s", name);
797 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
798 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
799
800 crs = aml_resource_template();
801 irqs = gsi;
802 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
803 AML_SHARED, &irqs, 1));
804 aml_append(dev, aml_name_decl("_PRS", crs));
805
806 aml_append(dev, aml_name_decl("_CRS", crs));
807
808 /*
809 * _DIS can be no-op because the interrupt cannot be disabled.
810 */
811 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
812 aml_append(dev, method);
813
814 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
815 aml_append(dev, method);
816
817 return dev;
818 }
819
820 /* _CRS method - get current settings */
821 static Aml *build_iqcr_method(bool is_piix4)
822 {
823 Aml *if_ctx;
824 uint32_t irqs;
825 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
826 Aml *crs = aml_resource_template();
827
828 irqs = 0;
829 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
830 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
831 aml_append(method, aml_name_decl("PRR0", crs));
832
833 aml_append(method,
834 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
835
836 if (is_piix4) {
837 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
838 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
839 aml_append(method, if_ctx);
840 } else {
841 aml_append(method,
842 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
843 aml_name("PRRI")));
844 }
845
846 aml_append(method, aml_return(aml_name("PRR0")));
847 return method;
848 }
849
850 /* _STA method - get status */
851 static Aml *build_irq_status_method(void)
852 {
853 Aml *if_ctx;
854 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
855
856 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
857 aml_append(if_ctx, aml_return(aml_int(0x09)));
858 aml_append(method, if_ctx);
859 aml_append(method, aml_return(aml_int(0x0B)));
860 return method;
861 }
862
863 static void build_piix4_pci0_int(Aml *table)
864 {
865 Aml *dev;
866 Aml *crs;
867 Aml *field;
868 Aml *method;
869 uint32_t irqs;
870 Aml *sb_scope = aml_scope("_SB");
871 Aml *pci0_scope = aml_scope("PCI0");
872
873 aml_append(pci0_scope, build_prt(true));
874 aml_append(sb_scope, pci0_scope);
875
876 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
877 aml_append(field, aml_named_field("PRQ0", 8));
878 aml_append(field, aml_named_field("PRQ1", 8));
879 aml_append(field, aml_named_field("PRQ2", 8));
880 aml_append(field, aml_named_field("PRQ3", 8));
881 aml_append(sb_scope, field);
882
883 aml_append(sb_scope, build_irq_status_method());
884 aml_append(sb_scope, build_iqcr_method(true));
885
886 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
887 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
888 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
889 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
890
891 dev = aml_device("LNKS");
892 {
893 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
894 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
895
896 crs = aml_resource_template();
897 irqs = 9;
898 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
899 AML_ACTIVE_HIGH, AML_SHARED,
900 &irqs, 1));
901 aml_append(dev, aml_name_decl("_PRS", crs));
902
903 /* The SCI cannot be disabled and is always attached to GSI 9,
904 * so these are no-ops. We only need this link to override the
905 * polarity to active high and match the content of the MADT.
906 */
907 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
908 aml_append(method, aml_return(aml_int(0x0b)));
909 aml_append(dev, method);
910
911 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
912 aml_append(dev, method);
913
914 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
915 aml_append(method, aml_return(aml_name("_PRS")));
916 aml_append(dev, method);
917
918 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
919 aml_append(dev, method);
920 }
921 aml_append(sb_scope, dev);
922
923 aml_append(table, sb_scope);
924 }
925
926 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
927 {
928 int i;
929 int head;
930 Aml *pkg;
931 char base = name[3] < 'E' ? 'A' : 'E';
932 char *s = g_strdup(name);
933 Aml *a_nr = aml_int((nr << 16) | 0xffff);
934
935 assert(strlen(s) == 4);
936
937 head = name[3] - base;
938 for (i = 0; i < 4; i++) {
939 if (head + i > 3) {
940 head = i * -1;
941 }
942 s[3] = base + head + i;
943 pkg = aml_package(4);
944 aml_append(pkg, a_nr);
945 aml_append(pkg, aml_int(i));
946 aml_append(pkg, aml_name("%s", s));
947 aml_append(pkg, aml_int(0));
948 aml_append(ctx, pkg);
949 }
950 g_free(s);
951 }
952
953 static Aml *build_q35_routing_table(const char *str)
954 {
955 int i;
956 Aml *pkg;
957 char *name = g_strdup_printf("%s ", str);
958
959 pkg = aml_package(128);
960 for (i = 0; i < 0x18; i++) {
961 name[3] = 'E' + (i & 0x3);
962 append_q35_prt_entry(pkg, i, name);
963 }
964
965 name[3] = 'E';
966 append_q35_prt_entry(pkg, 0x18, name);
967
968 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
969 for (i = 0x0019; i < 0x1e; i++) {
970 name[3] = 'A';
971 append_q35_prt_entry(pkg, i, name);
972 }
973
974 /* PCIe->PCI bridge. use PIRQ[E-H] */
975 name[3] = 'E';
976 append_q35_prt_entry(pkg, 0x1e, name);
977 name[3] = 'A';
978 append_q35_prt_entry(pkg, 0x1f, name);
979
980 g_free(name);
981 return pkg;
982 }
983
984 static void build_q35_pci0_int(Aml *table)
985 {
986 Aml *field;
987 Aml *method;
988 Aml *sb_scope = aml_scope("_SB");
989 Aml *pci0_scope = aml_scope("PCI0");
990
991 /* Zero => PIC mode, One => APIC Mode */
992 aml_append(table, aml_name_decl("PICF", aml_int(0)));
993 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
994 {
995 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
996 }
997 aml_append(table, method);
998
999 aml_append(pci0_scope,
1000 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1001 aml_append(pci0_scope,
1002 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1003
1004 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1005 {
1006 Aml *if_ctx;
1007 Aml *else_ctx;
1008
1009 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1010 section 6.2.8.1 */
1011 /* Note: we provide the same info as the PCI routing
1012 table of the Bochs BIOS */
1013 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1014 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1015 aml_append(method, if_ctx);
1016 else_ctx = aml_else();
1017 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1018 aml_append(method, else_ctx);
1019 }
1020 aml_append(pci0_scope, method);
1021 aml_append(sb_scope, pci0_scope);
1022
1023 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1024 aml_append(field, aml_named_field("PRQA", 8));
1025 aml_append(field, aml_named_field("PRQB", 8));
1026 aml_append(field, aml_named_field("PRQC", 8));
1027 aml_append(field, aml_named_field("PRQD", 8));
1028 aml_append(field, aml_reserved_field(0x20));
1029 aml_append(field, aml_named_field("PRQE", 8));
1030 aml_append(field, aml_named_field("PRQF", 8));
1031 aml_append(field, aml_named_field("PRQG", 8));
1032 aml_append(field, aml_named_field("PRQH", 8));
1033 aml_append(sb_scope, field);
1034
1035 aml_append(sb_scope, build_irq_status_method());
1036 aml_append(sb_scope, build_iqcr_method(false));
1037
1038 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1039 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1040 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1041 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1042 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1043 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1044 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1045 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1046
1047 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1048 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1049 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1050 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1051 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1052 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1053 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1054 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1055
1056 aml_append(table, sb_scope);
1057 }
1058
1059 static void build_q35_isa_bridge(Aml *table)
1060 {
1061 Aml *dev;
1062 Aml *scope;
1063
1064 scope = aml_scope("_SB.PCI0");
1065 dev = aml_device("ISA");
1066 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1067
1068 /* ICH9 PCI to ISA irq remapping */
1069 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1070 aml_int(0x60), 0x0C));
1071
1072 aml_append(scope, dev);
1073 aml_append(table, scope);
1074 }
1075
1076 static void build_piix4_isa_bridge(Aml *table)
1077 {
1078 Aml *dev;
1079 Aml *scope;
1080
1081 scope = aml_scope("_SB.PCI0");
1082 dev = aml_device("ISA");
1083 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1084
1085 /* PIIX PCI to ISA irq remapping */
1086 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1087 aml_int(0x60), 0x04));
1088
1089 aml_append(scope, dev);
1090 aml_append(table, scope);
1091 }
1092
1093 static void build_piix4_pci_hotplug(Aml *table)
1094 {
1095 Aml *scope;
1096 Aml *field;
1097 Aml *method;
1098
1099 scope = aml_scope("_SB.PCI0");
1100
1101 aml_append(scope,
1102 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1103 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1104 aml_append(field, aml_named_field("PCIU", 32));
1105 aml_append(field, aml_named_field("PCID", 32));
1106 aml_append(scope, field);
1107
1108 aml_append(scope,
1109 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1110 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1111 aml_append(field, aml_named_field("B0EJ", 32));
1112 aml_append(scope, field);
1113
1114 aml_append(scope,
1115 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1116 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1117 aml_append(field, aml_named_field("BNUM", 32));
1118 aml_append(scope, field);
1119
1120 aml_append(scope, aml_mutex("BLCK", 0));
1121
1122 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1123 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1124 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1125 aml_append(method,
1126 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1127 aml_append(method, aml_release(aml_name("BLCK")));
1128 aml_append(method, aml_return(aml_int(0)));
1129 aml_append(scope, method);
1130
1131 aml_append(table, scope);
1132 }
1133
1134 static Aml *build_q35_osc_method(void)
1135 {
1136 Aml *if_ctx;
1137 Aml *if_ctx2;
1138 Aml *else_ctx;
1139 Aml *method;
1140 Aml *a_cwd1 = aml_name("CDW1");
1141 Aml *a_ctrl = aml_local(0);
1142
1143 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1144 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1145
1146 if_ctx = aml_if(aml_equal(
1147 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1148 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1149 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1150
1151 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1152
1153 /*
1154 * Always allow native PME, AER (no dependencies)
1155 * Allow SHPC (PCI bridges can have SHPC controller)
1156 */
1157 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1158
1159 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1160 /* Unknown revision */
1161 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1162 aml_append(if_ctx, if_ctx2);
1163
1164 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1165 /* Capabilities bits were masked */
1166 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1167 aml_append(if_ctx, if_ctx2);
1168
1169 /* Update DWORD3 in the buffer */
1170 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1171 aml_append(method, if_ctx);
1172
1173 else_ctx = aml_else();
1174 /* Unrecognized UUID */
1175 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1176 aml_append(method, else_ctx);
1177
1178 aml_append(method, aml_return(aml_arg(3)));
1179 return method;
1180 }
1181
1182 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1183 {
1184 Aml *scope = aml_scope("_SB.PCI0");
1185 Aml *dev = aml_device("SMB0");
1186
1187 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1188 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1189 aml_append(scope, dev);
1190 aml_append(table, scope);
1191 }
1192
1193 static void
1194 build_dsdt(GArray *table_data, BIOSLinker *linker,
1195 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1196 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1197 {
1198 CrsRangeEntry *entry;
1199 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1200 CrsRangeSet crs_range_set;
1201 PCMachineState *pcms = PC_MACHINE(machine);
1202 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1203 X86MachineState *x86ms = X86_MACHINE(machine);
1204 AcpiMcfgInfo mcfg;
1205 uint32_t nr_mem = machine->ram_slots;
1206 int root_bus_limit = 0xFF;
1207 PCIBus *bus = NULL;
1208 TPMIf *tpm = tpm_find();
1209 int i;
1210 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1211
1212 dsdt = init_aml_allocator();
1213
1214 /* Reserve space for header */
1215 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1216
1217 build_dbg_aml(dsdt);
1218 if (misc->is_piix4) {
1219 sb_scope = aml_scope("_SB");
1220 dev = aml_device("PCI0");
1221 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1222 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1223 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1224 aml_append(sb_scope, dev);
1225 aml_append(dsdt, sb_scope);
1226
1227 build_hpet_aml(dsdt);
1228 build_piix4_isa_bridge(dsdt);
1229 build_isa_devices_aml(dsdt);
1230 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1231 build_piix4_pci_hotplug(dsdt);
1232 }
1233 build_piix4_pci0_int(dsdt);
1234 } else {
1235 sb_scope = aml_scope("_SB");
1236 dev = aml_device("PCI0");
1237 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1238 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1239 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1240 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1241 aml_append(dev, build_q35_osc_method());
1242 aml_append(sb_scope, dev);
1243
1244 if (pm->smi_on_cpuhp) {
1245 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1246 dev = aml_device("PCI0.SMI0");
1247 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1248 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1249 crs = aml_resource_template();
1250 aml_append(crs,
1251 aml_io(
1252 AML_DECODE16,
1253 ACPI_PORT_SMI_CMD,
1254 ACPI_PORT_SMI_CMD,
1255 1,
1256 2)
1257 );
1258 aml_append(dev, aml_name_decl("_CRS", crs));
1259 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1260 aml_int(ACPI_PORT_SMI_CMD), 2));
1261 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1262 AML_WRITE_AS_ZEROS);
1263 aml_append(field, aml_named_field("SMIC", 8));
1264 aml_append(field, aml_reserved_field(8));
1265 aml_append(dev, field);
1266 aml_append(sb_scope, dev);
1267 }
1268
1269 aml_append(dsdt, sb_scope);
1270
1271 build_hpet_aml(dsdt);
1272 build_q35_isa_bridge(dsdt);
1273 build_isa_devices_aml(dsdt);
1274 build_q35_pci0_int(dsdt);
1275 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1276 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1277 }
1278 }
1279
1280 if (vmbus_bridge) {
1281 sb_scope = aml_scope("_SB");
1282 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1283 aml_append(dsdt, sb_scope);
1284 }
1285
1286 if (pcmc->legacy_cpu_hotplug) {
1287 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1288 } else {
1289 CPUHotplugFeatures opts = {
1290 .acpi_1_compatible = true, .has_legacy_cphp = true,
1291 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1292 };
1293 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1294 "\\_SB.PCI0", "\\_GPE._E02");
1295 }
1296
1297 if (pcms->memhp_io_base && nr_mem) {
1298 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1299 "\\_GPE._E03", AML_SYSTEM_IO,
1300 pcms->memhp_io_base);
1301 }
1302
1303 scope = aml_scope("_GPE");
1304 {
1305 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1306
1307 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1308 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1309 aml_append(method,
1310 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1311 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1312 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1313 aml_append(scope, method);
1314 }
1315
1316 if (machine->nvdimms_state->is_enabled) {
1317 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1318 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1319 aml_int(0x80)));
1320 aml_append(scope, method);
1321 }
1322 }
1323 aml_append(dsdt, scope);
1324
1325 crs_range_set_init(&crs_range_set);
1326 bus = PC_MACHINE(machine)->bus;
1327 if (bus) {
1328 QLIST_FOREACH(bus, &bus->child, sibling) {
1329 uint8_t bus_num = pci_bus_num(bus);
1330 uint8_t numa_node = pci_bus_numa_node(bus);
1331
1332 /* look only for expander root buses */
1333 if (!pci_bus_is_root(bus)) {
1334 continue;
1335 }
1336
1337 if (bus_num < root_bus_limit) {
1338 root_bus_limit = bus_num - 1;
1339 }
1340
1341 scope = aml_scope("\\_SB");
1342 dev = aml_device("PC%.02X", bus_num);
1343 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1344 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1345 if (pci_bus_is_express(bus)) {
1346 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1347 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1348 aml_append(dev, build_q35_osc_method());
1349 } else {
1350 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1351 }
1352
1353 if (numa_node != NUMA_NODE_UNASSIGNED) {
1354 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1355 }
1356
1357 aml_append(dev, build_prt(false));
1358 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1359 aml_append(dev, aml_name_decl("_CRS", crs));
1360 aml_append(scope, dev);
1361 aml_append(dsdt, scope);
1362 }
1363 }
1364
1365 /*
1366 * At this point crs_range_set has all the ranges used by pci
1367 * busses *other* than PCI0. These ranges will be excluded from
1368 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1369 * too.
1370 */
1371 if (acpi_get_mcfg(&mcfg)) {
1372 crs_range_insert(crs_range_set.mem_ranges,
1373 mcfg.base, mcfg.base + mcfg.size - 1);
1374 }
1375
1376 scope = aml_scope("\\_SB.PCI0");
1377 /* build PCI0._CRS */
1378 crs = aml_resource_template();
1379 aml_append(crs,
1380 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1381 0x0000, 0x0, root_bus_limit,
1382 0x0000, root_bus_limit + 1));
1383 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1384
1385 aml_append(crs,
1386 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1387 AML_POS_DECODE, AML_ENTIRE_RANGE,
1388 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1389
1390 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1391 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1392 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1393 aml_append(crs,
1394 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1395 AML_POS_DECODE, AML_ENTIRE_RANGE,
1396 0x0000, entry->base, entry->limit,
1397 0x0000, entry->limit - entry->base + 1));
1398 }
1399
1400 aml_append(crs,
1401 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1402 AML_CACHEABLE, AML_READ_WRITE,
1403 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1404
1405 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1406 range_lob(pci_hole),
1407 range_upb(pci_hole));
1408 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1409 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1410 aml_append(crs,
1411 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1412 AML_NON_CACHEABLE, AML_READ_WRITE,
1413 0, entry->base, entry->limit,
1414 0, entry->limit - entry->base + 1));
1415 }
1416
1417 if (!range_is_empty(pci_hole64)) {
1418 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1419 range_lob(pci_hole64),
1420 range_upb(pci_hole64));
1421 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1422 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1423 aml_append(crs,
1424 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1425 AML_MAX_FIXED,
1426 AML_CACHEABLE, AML_READ_WRITE,
1427 0, entry->base, entry->limit,
1428 0, entry->limit - entry->base + 1));
1429 }
1430 }
1431
1432 if (TPM_IS_TIS_ISA(tpm_find())) {
1433 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1434 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1435 }
1436 aml_append(scope, aml_name_decl("_CRS", crs));
1437
1438 /* reserve GPE0 block resources */
1439 dev = aml_device("GPE0");
1440 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1441 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1442 /* device present, functioning, decoding, not shown in UI */
1443 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1444 crs = aml_resource_template();
1445 aml_append(crs,
1446 aml_io(
1447 AML_DECODE16,
1448 pm->fadt.gpe0_blk.address,
1449 pm->fadt.gpe0_blk.address,
1450 1,
1451 pm->fadt.gpe0_blk.bit_width / 8)
1452 );
1453 aml_append(dev, aml_name_decl("_CRS", crs));
1454 aml_append(scope, dev);
1455
1456 crs_range_set_free(&crs_range_set);
1457
1458 /* reserve PCIHP resources */
1459 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1460 dev = aml_device("PHPR");
1461 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1462 aml_append(dev,
1463 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1464 /* device present, functioning, decoding, not shown in UI */
1465 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1466 crs = aml_resource_template();
1467 aml_append(crs,
1468 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1469 pm->pcihp_io_len)
1470 );
1471 aml_append(dev, aml_name_decl("_CRS", crs));
1472 aml_append(scope, dev);
1473 }
1474 aml_append(dsdt, scope);
1475
1476 /* create S3_ / S4_ / S5_ packages if necessary */
1477 scope = aml_scope("\\");
1478 if (!pm->s3_disabled) {
1479 pkg = aml_package(4);
1480 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1481 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1482 aml_append(pkg, aml_int(0)); /* reserved */
1483 aml_append(pkg, aml_int(0)); /* reserved */
1484 aml_append(scope, aml_name_decl("_S3", pkg));
1485 }
1486
1487 if (!pm->s4_disabled) {
1488 pkg = aml_package(4);
1489 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1490 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1491 aml_append(pkg, aml_int(pm->s4_val));
1492 aml_append(pkg, aml_int(0)); /* reserved */
1493 aml_append(pkg, aml_int(0)); /* reserved */
1494 aml_append(scope, aml_name_decl("_S4", pkg));
1495 }
1496
1497 pkg = aml_package(4);
1498 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1499 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1500 aml_append(pkg, aml_int(0)); /* reserved */
1501 aml_append(pkg, aml_int(0)); /* reserved */
1502 aml_append(scope, aml_name_decl("_S5", pkg));
1503 aml_append(dsdt, scope);
1504
1505 /* create fw_cfg node, unconditionally */
1506 {
1507 scope = aml_scope("\\_SB.PCI0");
1508 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1509 aml_append(dsdt, scope);
1510 }
1511
1512 if (misc->applesmc_io_base) {
1513 scope = aml_scope("\\_SB.PCI0.ISA");
1514 dev = aml_device("SMC");
1515
1516 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1517 /* device present, functioning, decoding, not shown in UI */
1518 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1519
1520 crs = aml_resource_template();
1521 aml_append(crs,
1522 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1523 0x01, APPLESMC_MAX_DATA_LENGTH)
1524 );
1525 aml_append(crs, aml_irq_no_flags(6));
1526 aml_append(dev, aml_name_decl("_CRS", crs));
1527
1528 aml_append(scope, dev);
1529 aml_append(dsdt, scope);
1530 }
1531
1532 if (misc->pvpanic_port) {
1533 scope = aml_scope("\\_SB.PCI0.ISA");
1534
1535 dev = aml_device("PEVT");
1536 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1537
1538 crs = aml_resource_template();
1539 aml_append(crs,
1540 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1541 );
1542 aml_append(dev, aml_name_decl("_CRS", crs));
1543
1544 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1545 aml_int(misc->pvpanic_port), 1));
1546 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1547 aml_append(field, aml_named_field("PEPT", 8));
1548 aml_append(dev, field);
1549
1550 /* device present, functioning, decoding, shown in UI */
1551 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1552
1553 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1554 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1555 aml_append(method, aml_return(aml_local(0)));
1556 aml_append(dev, method);
1557
1558 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1559 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1560 aml_append(dev, method);
1561
1562 aml_append(scope, dev);
1563 aml_append(dsdt, scope);
1564 }
1565
1566 sb_scope = aml_scope("\\_SB");
1567 {
1568 Object *pci_host;
1569 PCIBus *bus = NULL;
1570
1571 pci_host = acpi_get_i386_pci_host();
1572 if (pci_host) {
1573 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1574 }
1575
1576 if (bus) {
1577 Aml *scope = aml_scope("PCI0");
1578 /* Scan all PCI buses. Generate tables to support hotplug. */
1579 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1580
1581 if (TPM_IS_TIS_ISA(tpm)) {
1582 if (misc->tpm_version == TPM_VERSION_2_0) {
1583 dev = aml_device("TPM");
1584 aml_append(dev, aml_name_decl("_HID",
1585 aml_string("MSFT0101")));
1586 } else {
1587 dev = aml_device("ISA.TPM");
1588 aml_append(dev, aml_name_decl("_HID",
1589 aml_eisaid("PNP0C31")));
1590 }
1591
1592 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1593 crs = aml_resource_template();
1594 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1595 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1596 /*
1597 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1598 Rewrite to take IRQ from TPM device model and
1599 fix default IRQ value there to use some unused IRQ
1600 */
1601 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1602 aml_append(dev, aml_name_decl("_CRS", crs));
1603
1604 tpm_build_ppi_acpi(tpm, dev);
1605
1606 aml_append(scope, dev);
1607 }
1608
1609 aml_append(sb_scope, scope);
1610 }
1611 }
1612
1613 if (TPM_IS_CRB(tpm)) {
1614 dev = aml_device("TPM");
1615 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1616 crs = aml_resource_template();
1617 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1618 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1619 aml_append(dev, aml_name_decl("_CRS", crs));
1620
1621 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1622
1623 tpm_build_ppi_acpi(tpm, dev);
1624
1625 aml_append(sb_scope, dev);
1626 }
1627
1628 aml_append(dsdt, sb_scope);
1629
1630 /* copy AML table into ACPI tables blob and patch header there */
1631 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1632 build_header(linker, table_data,
1633 (void *)(table_data->data + table_data->len - dsdt->buf->len),
1634 "DSDT", dsdt->buf->len, 1, NULL, NULL);
1635 free_aml_allocator();
1636 }
1637
1638 static void
1639 build_hpet(GArray *table_data, BIOSLinker *linker)
1640 {
1641 Acpi20Hpet *hpet;
1642
1643 hpet = acpi_data_push(table_data, sizeof(*hpet));
1644 /* Note timer_block_id value must be kept in sync with value advertised by
1645 * emulated hpet
1646 */
1647 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1648 hpet->addr.address = cpu_to_le64(HPET_BASE);
1649 build_header(linker, table_data,
1650 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
1651 }
1652
1653 static void
1654 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
1655 {
1656 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1657 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1658 unsigned log_addr_offset =
1659 (char *)&tcpa->log_area_start_address - table_data->data;
1660
1661 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1662 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1663 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1664
1665 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1666 false /* high memory */);
1667
1668 /* log area start address to be filled by Guest linker */
1669 bios_linker_loader_add_pointer(linker,
1670 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1671 ACPI_BUILD_TPMLOG_FILE, 0);
1672
1673 build_header(linker, table_data,
1674 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
1675 }
1676
1677 #define HOLE_640K_START (640 * KiB)
1678 #define HOLE_640K_END (1 * MiB)
1679
1680 static void
1681 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1682 {
1683 AcpiSystemResourceAffinityTable *srat;
1684 AcpiSratMemoryAffinity *numamem;
1685
1686 int i;
1687 int srat_start, numa_start, slots;
1688 uint64_t mem_len, mem_base, next_base;
1689 MachineClass *mc = MACHINE_GET_CLASS(machine);
1690 X86MachineState *x86ms = X86_MACHINE(machine);
1691 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1692 PCMachineState *pcms = PC_MACHINE(machine);
1693 ram_addr_t hotplugabble_address_space_size =
1694 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1695 NULL);
1696
1697 srat_start = table_data->len;
1698
1699 srat = acpi_data_push(table_data, sizeof *srat);
1700 srat->reserved1 = cpu_to_le32(1);
1701
1702 for (i = 0; i < apic_ids->len; i++) {
1703 int node_id = apic_ids->cpus[i].props.node_id;
1704 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1705
1706 if (apic_id < 255) {
1707 AcpiSratProcessorAffinity *core;
1708
1709 core = acpi_data_push(table_data, sizeof *core);
1710 core->type = ACPI_SRAT_PROCESSOR_APIC;
1711 core->length = sizeof(*core);
1712 core->local_apic_id = apic_id;
1713 core->proximity_lo = node_id;
1714 memset(core->proximity_hi, 0, 3);
1715 core->local_sapic_eid = 0;
1716 core->flags = cpu_to_le32(1);
1717 } else {
1718 AcpiSratProcessorX2ApicAffinity *core;
1719
1720 core = acpi_data_push(table_data, sizeof *core);
1721 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
1722 core->length = sizeof(*core);
1723 core->x2apic_id = cpu_to_le32(apic_id);
1724 core->proximity_domain = cpu_to_le32(node_id);
1725 core->flags = cpu_to_le32(1);
1726 }
1727 }
1728
1729
1730 /* the memory map is a bit tricky, it contains at least one hole
1731 * from 640k-1M and possibly another one from 3.5G-4G.
1732 */
1733 next_base = 0;
1734 numa_start = table_data->len;
1735
1736 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
1737 mem_base = next_base;
1738 mem_len = pcms->node_mem[i - 1];
1739 next_base = mem_base + mem_len;
1740
1741 /* Cut out the 640K hole */
1742 if (mem_base <= HOLE_640K_START &&
1743 next_base > HOLE_640K_START) {
1744 mem_len -= next_base - HOLE_640K_START;
1745 if (mem_len > 0) {
1746 numamem = acpi_data_push(table_data, sizeof *numamem);
1747 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1748 MEM_AFFINITY_ENABLED);
1749 }
1750
1751 /* Check for the rare case: 640K < RAM < 1M */
1752 if (next_base <= HOLE_640K_END) {
1753 next_base = HOLE_640K_END;
1754 continue;
1755 }
1756 mem_base = HOLE_640K_END;
1757 mem_len = next_base - HOLE_640K_END;
1758 }
1759
1760 /* Cut out the ACPI_PCI hole */
1761 if (mem_base <= x86ms->below_4g_mem_size &&
1762 next_base > x86ms->below_4g_mem_size) {
1763 mem_len -= next_base - x86ms->below_4g_mem_size;
1764 if (mem_len > 0) {
1765 numamem = acpi_data_push(table_data, sizeof *numamem);
1766 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1767 MEM_AFFINITY_ENABLED);
1768 }
1769 mem_base = 1ULL << 32;
1770 mem_len = next_base - x86ms->below_4g_mem_size;
1771 next_base = mem_base + mem_len;
1772 }
1773
1774 if (mem_len > 0) {
1775 numamem = acpi_data_push(table_data, sizeof *numamem);
1776 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1777 MEM_AFFINITY_ENABLED);
1778 }
1779 }
1780
1781 if (machine->nvdimms_state->is_enabled) {
1782 nvdimm_build_srat(table_data);
1783 }
1784
1785 slots = (table_data->len - numa_start) / sizeof *numamem;
1786 for (; slots < pcms->numa_nodes + 2; slots++) {
1787 numamem = acpi_data_push(table_data, sizeof *numamem);
1788 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1789 }
1790
1791 /*
1792 * Entry is required for Windows to enable memory hotplug in OS
1793 * and for Linux to enable SWIOTLB when booted with less than
1794 * 4G of RAM. Windows works better if the entry sets proximity
1795 * to the highest NUMA node in the machine.
1796 * Memory devices may override proximity set by this entry,
1797 * providing _PXM method if necessary.
1798 */
1799 if (hotplugabble_address_space_size) {
1800 numamem = acpi_data_push(table_data, sizeof *numamem);
1801 build_srat_memory(numamem, machine->device_memory->base,
1802 hotplugabble_address_space_size, pcms->numa_nodes - 1,
1803 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
1804 }
1805
1806 build_header(linker, table_data,
1807 (void *)(table_data->data + srat_start),
1808 "SRAT",
1809 table_data->len - srat_start, 1, NULL, NULL);
1810 }
1811
1812 /*
1813 * VT-d spec 8.1 DMA Remapping Reporting Structure
1814 * (version Oct. 2014 or later)
1815 */
1816 static void
1817 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
1818 {
1819 int dmar_start = table_data->len;
1820
1821 AcpiTableDmar *dmar;
1822 AcpiDmarHardwareUnit *drhd;
1823 AcpiDmarRootPortATS *atsr;
1824 uint8_t dmar_flags = 0;
1825 X86IOMMUState *iommu = x86_iommu_get_default();
1826 AcpiDmarDeviceScope *scope = NULL;
1827 /* Root complex IOAPIC use one path[0] only */
1828 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
1829 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1830
1831 assert(iommu);
1832 if (x86_iommu_ir_supported(iommu)) {
1833 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
1834 }
1835
1836 dmar = acpi_data_push(table_data, sizeof(*dmar));
1837 dmar->host_address_width = intel_iommu->aw_bits - 1;
1838 dmar->flags = dmar_flags;
1839
1840 /* DMAR Remapping Hardware Unit Definition structure */
1841 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
1842 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1843 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
1844 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1845 drhd->pci_segment = cpu_to_le16(0);
1846 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1847
1848 /* Scope definition for the root-complex IOAPIC. See VT-d spec
1849 * 8.3.1 (version Oct. 2014 or later). */
1850 scope = &drhd->scope[0];
1851 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
1852 scope->length = ioapic_scope_size;
1853 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
1854 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
1855 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
1856 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
1857
1858 if (iommu->dt_supported) {
1859 atsr = acpi_data_push(table_data, sizeof(*atsr));
1860 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
1861 atsr->length = cpu_to_le16(sizeof(*atsr));
1862 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
1863 atsr->pci_segment = cpu_to_le16(0);
1864 }
1865
1866 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1867 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
1868 }
1869
1870 /*
1871 * Windows ACPI Emulated Devices Table
1872 * (Version 1.0 - April 6, 2009)
1873 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1874 *
1875 * Helpful to speedup Windows guests and ignored by others.
1876 */
1877 static void
1878 build_waet(GArray *table_data, BIOSLinker *linker)
1879 {
1880 int waet_start = table_data->len;
1881
1882 /* WAET header */
1883 acpi_data_push(table_data, sizeof(AcpiTableHeader));
1884 /*
1885 * Set "ACPI PM timer good" flag.
1886 *
1887 * Tells Windows guests that our ACPI PM timer is reliable in the
1888 * sense that guest can read it only once to obtain a reliable value.
1889 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
1890 */
1891 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
1892
1893 build_header(linker, table_data, (void *)(table_data->data + waet_start),
1894 "WAET", table_data->len - waet_start, 1, NULL, NULL);
1895 }
1896
1897 /*
1898 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
1899 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
1900 */
1901 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
1902
1903 /*
1904 * Insert IVHD entry for device and recurse, insert alias, or insert range as
1905 * necessary for the PCI topology.
1906 */
1907 static void
1908 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
1909 {
1910 GArray *table_data = opaque;
1911 uint32_t entry;
1912
1913 /* "Select" IVHD entry, type 0x2 */
1914 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
1915 build_append_int_noprefix(table_data, entry, 4);
1916
1917 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1918 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1919 uint8_t sec = pci_bus_num(sec_bus);
1920 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
1921
1922 if (pci_bus_is_express(sec_bus)) {
1923 /*
1924 * Walk the bus if there are subordinates, otherwise use a range
1925 * to cover an entire leaf bus. We could potentially also use a
1926 * range for traversed buses, but we'd need to take care not to
1927 * create both Select and Range entries covering the same device.
1928 * This is easier and potentially more compact.
1929 *
1930 * An example bare metal system seems to use Select entries for
1931 * root ports without a slot (ie. built-ins) and Range entries
1932 * when there is a slot. The same system also only hard-codes
1933 * the alias range for an onboard PCIe-to-PCI bridge, apparently
1934 * making no effort to support nested bridges. We attempt to
1935 * be more thorough here.
1936 */
1937 if (sec == sub) { /* leaf bus */
1938 /* "Start of Range" IVHD entry, type 0x3 */
1939 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
1940 build_append_int_noprefix(table_data, entry, 4);
1941 /* "End of Range" IVHD entry, type 0x4 */
1942 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1943 build_append_int_noprefix(table_data, entry, 4);
1944 } else {
1945 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
1946 }
1947 } else {
1948 /*
1949 * If the secondary bus is conventional, then we need to create an
1950 * Alias range for everything downstream. The range covers the
1951 * first devfn on the secondary bus to the last devfn on the
1952 * subordinate bus. The alias target depends on legacy versus
1953 * express bridges, just as in pci_device_iommu_address_space().
1954 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
1955 */
1956 uint16_t dev_id_a, dev_id_b;
1957
1958 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
1959
1960 if (pci_is_express(dev) &&
1961 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
1962 dev_id_b = dev_id_a;
1963 } else {
1964 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
1965 }
1966
1967 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
1968 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
1969 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
1970
1971 /* "End of Range" IVHD entry, type 0x4 */
1972 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1973 build_append_int_noprefix(table_data, entry, 4);
1974 }
1975 }
1976 }
1977
1978 /* For all PCI host bridges, walk and insert IVHD entries */
1979 static int
1980 ivrs_host_bridges(Object *obj, void *opaque)
1981 {
1982 GArray *ivhd_blob = opaque;
1983
1984 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
1985 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
1986
1987 if (bus) {
1988 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
1989 }
1990 }
1991
1992 return 0;
1993 }
1994
1995 static void
1996 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
1997 {
1998 int ivhd_table_len = 24;
1999 int iommu_start = table_data->len;
2000 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2001 GArray *ivhd_blob = g_array_new(false, true, 1);
2002
2003 /* IVRS header */
2004 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2005 /* IVinfo - IO virtualization information common to all
2006 * IOMMU units in a system
2007 */
2008 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2009 /* reserved */
2010 build_append_int_noprefix(table_data, 0, 8);
2011
2012 /* IVHD definition - type 10h */
2013 build_append_int_noprefix(table_data, 0x10, 1);
2014 /* virtualization flags */
2015 build_append_int_noprefix(table_data,
2016 (1UL << 0) | /* HtTunEn */
2017 (1UL << 4) | /* iotblSup */
2018 (1UL << 6) | /* PrefSup */
2019 (1UL << 7), /* PPRSup */
2020 1);
2021
2022 /*
2023 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2024 * complete set of IVHD entries. Do this into a separate blob so that we
2025 * can calculate the total IVRS table length here and then append the new
2026 * blob further below. Fall back to an entry covering all devices, which
2027 * is sufficient when no aliases are present.
2028 */
2029 object_child_foreach_recursive(object_get_root(),
2030 ivrs_host_bridges, ivhd_blob);
2031
2032 if (!ivhd_blob->len) {
2033 /*
2034 * Type 1 device entry reporting all devices
2035 * These are 4-byte device entries currently reporting the range of
2036 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2037 */
2038 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2039 }
2040
2041 ivhd_table_len += ivhd_blob->len;
2042
2043 /*
2044 * When interrupt remapping is supported, we add a special IVHD device
2045 * for type IO-APIC.
2046 */
2047 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2048 ivhd_table_len += 8;
2049 }
2050
2051 /* IVHD length */
2052 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2053 /* DeviceID */
2054 build_append_int_noprefix(table_data, s->devid, 2);
2055 /* Capability offset */
2056 build_append_int_noprefix(table_data, s->capab_offset, 2);
2057 /* IOMMU base address */
2058 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2059 /* PCI Segment Group */
2060 build_append_int_noprefix(table_data, 0, 2);
2061 /* IOMMU info */
2062 build_append_int_noprefix(table_data, 0, 2);
2063 /* IOMMU Feature Reporting */
2064 build_append_int_noprefix(table_data,
2065 (48UL << 30) | /* HATS */
2066 (48UL << 28) | /* GATS */
2067 (1UL << 2) | /* GTSup */
2068 (1UL << 6), /* GASup */
2069 4);
2070
2071 /* IVHD entries as found above */
2072 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2073 g_array_free(ivhd_blob, TRUE);
2074
2075 /*
2076 * Add a special IVHD device type.
2077 * Refer to spec - Table 95: IVHD device entry type codes
2078 *
2079 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2080 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2081 */
2082 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2083 build_append_int_noprefix(table_data,
2084 (0x1ull << 56) | /* type IOAPIC */
2085 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2086 0x48, /* special device */
2087 8);
2088 }
2089
2090 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2091 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2092 }
2093
2094 typedef
2095 struct AcpiBuildState {
2096 /* Copy of table in RAM (for patching). */
2097 MemoryRegion *table_mr;
2098 /* Is table patched? */
2099 uint8_t patched;
2100 void *rsdp;
2101 MemoryRegion *rsdp_mr;
2102 MemoryRegion *linker_mr;
2103 } AcpiBuildState;
2104
2105 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2106 {
2107 Object *pci_host;
2108 QObject *o;
2109
2110 pci_host = acpi_get_i386_pci_host();
2111 g_assert(pci_host);
2112
2113 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2114 if (!o) {
2115 return false;
2116 }
2117 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2118 qobject_unref(o);
2119 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2120 return false;
2121 }
2122
2123 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2124 assert(o);
2125 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2126 qobject_unref(o);
2127 return true;
2128 }
2129
2130 static
2131 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2132 {
2133 PCMachineState *pcms = PC_MACHINE(machine);
2134 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2135 X86MachineState *x86ms = X86_MACHINE(machine);
2136 GArray *table_offsets;
2137 unsigned facs, dsdt, rsdt, fadt;
2138 AcpiPmInfo pm;
2139 AcpiMiscInfo misc;
2140 AcpiMcfgInfo mcfg;
2141 Range pci_hole, pci_hole64;
2142 uint8_t *u;
2143 size_t aml_len = 0;
2144 GArray *tables_blob = tables->table_data;
2145 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2146 Object *vmgenid_dev;
2147
2148 acpi_get_pm_info(machine, &pm);
2149 acpi_get_misc_info(&misc);
2150 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2151 acpi_get_slic_oem(&slic_oem);
2152
2153 table_offsets = g_array_new(false, true /* clear */,
2154 sizeof(uint32_t));
2155 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2156
2157 bios_linker_loader_alloc(tables->linker,
2158 ACPI_BUILD_TABLE_FILE, tables_blob,
2159 64 /* Ensure FACS is aligned */,
2160 false /* high memory */);
2161
2162 /*
2163 * FACS is pointed to by FADT.
2164 * We place it first since it's the only table that has alignment
2165 * requirements.
2166 */
2167 facs = tables_blob->len;
2168 build_facs(tables_blob);
2169
2170 /* DSDT is pointed to by FADT */
2171 dsdt = tables_blob->len;
2172 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2173 &pci_hole, &pci_hole64, machine);
2174
2175 /* Count the size of the DSDT and SSDT, we will need it for legacy
2176 * sizing of ACPI tables.
2177 */
2178 aml_len += tables_blob->len - dsdt;
2179
2180 /* ACPI tables pointed to by RSDT */
2181 fadt = tables_blob->len;
2182 acpi_add_table(table_offsets, tables_blob);
2183 pm.fadt.facs_tbl_offset = &facs;
2184 pm.fadt.dsdt_tbl_offset = &dsdt;
2185 pm.fadt.xdsdt_tbl_offset = &dsdt;
2186 build_fadt(tables_blob, tables->linker, &pm.fadt,
2187 slic_oem.id, slic_oem.table_id);
2188 aml_len += tables_blob->len - fadt;
2189
2190 acpi_add_table(table_offsets, tables_blob);
2191 acpi_build_madt(tables_blob, tables->linker, x86ms,
2192 ACPI_DEVICE_IF(x86ms->acpi_dev));
2193
2194 vmgenid_dev = find_vmgenid_dev();
2195 if (vmgenid_dev) {
2196 acpi_add_table(table_offsets, tables_blob);
2197 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2198 tables->vmgenid, tables->linker);
2199 }
2200
2201 if (misc.has_hpet) {
2202 acpi_add_table(table_offsets, tables_blob);
2203 build_hpet(tables_blob, tables->linker);
2204 }
2205 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2206 if (misc.tpm_version == TPM_VERSION_1_2) {
2207 acpi_add_table(table_offsets, tables_blob);
2208 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2209 } else { /* TPM_VERSION_2_0 */
2210 acpi_add_table(table_offsets, tables_blob);
2211 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2212 }
2213 }
2214 if (pcms->numa_nodes) {
2215 acpi_add_table(table_offsets, tables_blob);
2216 build_srat(tables_blob, tables->linker, machine);
2217 if (machine->numa_state->have_numa_distance) {
2218 acpi_add_table(table_offsets, tables_blob);
2219 build_slit(tables_blob, tables->linker, machine);
2220 }
2221 if (machine->numa_state->hmat_enabled) {
2222 acpi_add_table(table_offsets, tables_blob);
2223 build_hmat(tables_blob, tables->linker, machine->numa_state);
2224 }
2225 }
2226 if (acpi_get_mcfg(&mcfg)) {
2227 acpi_add_table(table_offsets, tables_blob);
2228 build_mcfg(tables_blob, tables->linker, &mcfg);
2229 }
2230 if (x86_iommu_get_default()) {
2231 IommuType IOMMUType = x86_iommu_get_type();
2232 if (IOMMUType == TYPE_AMD) {
2233 acpi_add_table(table_offsets, tables_blob);
2234 build_amd_iommu(tables_blob, tables->linker);
2235 } else if (IOMMUType == TYPE_INTEL) {
2236 acpi_add_table(table_offsets, tables_blob);
2237 build_dmar_q35(tables_blob, tables->linker);
2238 }
2239 }
2240 if (machine->nvdimms_state->is_enabled) {
2241 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2242 machine->nvdimms_state, machine->ram_slots);
2243 }
2244
2245 acpi_add_table(table_offsets, tables_blob);
2246 build_waet(tables_blob, tables->linker);
2247
2248 /* Add tables supplied by user (if any) */
2249 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2250 unsigned len = acpi_table_len(u);
2251
2252 acpi_add_table(table_offsets, tables_blob);
2253 g_array_append_vals(tables_blob, u, len);
2254 }
2255
2256 /* RSDT is pointed to by RSDP */
2257 rsdt = tables_blob->len;
2258 build_rsdt(tables_blob, tables->linker, table_offsets,
2259 slic_oem.id, slic_oem.table_id);
2260
2261 /* RSDP is in FSEG memory, so allocate it separately */
2262 {
2263 AcpiRsdpData rsdp_data = {
2264 .revision = 0,
2265 .oem_id = ACPI_BUILD_APPNAME6,
2266 .xsdt_tbl_offset = NULL,
2267 .rsdt_tbl_offset = &rsdt,
2268 };
2269 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2270 if (!pcmc->rsdp_in_ram) {
2271 /* We used to allocate some extra space for RSDP revision 2 but
2272 * only used the RSDP revision 0 space. The extra bytes were
2273 * zeroed out and not used.
2274 * Here we continue wasting those extra 16 bytes to make sure we
2275 * don't break migration for machine types 2.2 and older due to
2276 * RSDP blob size mismatch.
2277 */
2278 build_append_int_noprefix(tables->rsdp, 0, 16);
2279 }
2280 }
2281
2282 /* We'll expose it all to Guest so we want to reduce
2283 * chance of size changes.
2284 *
2285 * We used to align the tables to 4k, but of course this would
2286 * too simple to be enough. 4k turned out to be too small an
2287 * alignment very soon, and in fact it is almost impossible to
2288 * keep the table size stable for all (max_cpus, max_memory_slots)
2289 * combinations. So the table size is always 64k for pc-i440fx-2.1
2290 * and we give an error if the table grows beyond that limit.
2291 *
2292 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2293 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2294 * than 2.0 and we can always pad the smaller tables with zeros. We can
2295 * then use the exact size of the 2.0 tables.
2296 *
2297 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2298 */
2299 if (pcmc->legacy_acpi_table_size) {
2300 /* Subtracting aml_len gives the size of fixed tables. Then add the
2301 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2302 */
2303 int legacy_aml_len =
2304 pcmc->legacy_acpi_table_size +
2305 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2306 int legacy_table_size =
2307 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2308 ACPI_BUILD_ALIGN_SIZE);
2309 if (tables_blob->len > legacy_table_size) {
2310 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2311 warn_report("ACPI table size %u exceeds %d bytes,"
2312 " migration may not work",
2313 tables_blob->len, legacy_table_size);
2314 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2315 " or PCI bridges.");
2316 }
2317 g_array_set_size(tables_blob, legacy_table_size);
2318 } else {
2319 /* Make sure we have a buffer in case we need to resize the tables. */
2320 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2321 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2322 warn_report("ACPI table size %u exceeds %d bytes,"
2323 " migration may not work",
2324 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2325 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2326 " or PCI bridges.");
2327 }
2328 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2329 }
2330
2331 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2332
2333 /* Cleanup memory that's no longer used. */
2334 g_array_free(table_offsets, true);
2335 }
2336
2337 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2338 {
2339 uint32_t size = acpi_data_len(data);
2340
2341 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2342 memory_region_ram_resize(mr, size, &error_abort);
2343
2344 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2345 memory_region_set_dirty(mr, 0, size);
2346 }
2347
2348 static void acpi_build_update(void *build_opaque)
2349 {
2350 AcpiBuildState *build_state = build_opaque;
2351 AcpiBuildTables tables;
2352
2353 /* No state to update or already patched? Nothing to do. */
2354 if (!build_state || build_state->patched) {
2355 return;
2356 }
2357 build_state->patched = 1;
2358
2359 acpi_build_tables_init(&tables);
2360
2361 acpi_build(&tables, MACHINE(qdev_get_machine()));
2362
2363 acpi_ram_update(build_state->table_mr, tables.table_data);
2364
2365 if (build_state->rsdp) {
2366 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2367 } else {
2368 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2369 }
2370
2371 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2372 acpi_build_tables_cleanup(&tables, true);
2373 }
2374
2375 static void acpi_build_reset(void *build_opaque)
2376 {
2377 AcpiBuildState *build_state = build_opaque;
2378 build_state->patched = 0;
2379 }
2380
2381 static const VMStateDescription vmstate_acpi_build = {
2382 .name = "acpi_build",
2383 .version_id = 1,
2384 .minimum_version_id = 1,
2385 .fields = (VMStateField[]) {
2386 VMSTATE_UINT8(patched, AcpiBuildState),
2387 VMSTATE_END_OF_LIST()
2388 },
2389 };
2390
2391 void acpi_setup(void)
2392 {
2393 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2394 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2395 X86MachineState *x86ms = X86_MACHINE(pcms);
2396 AcpiBuildTables tables;
2397 AcpiBuildState *build_state;
2398 Object *vmgenid_dev;
2399 TPMIf *tpm;
2400 static FwCfgTPMConfig tpm_config;
2401
2402 if (!x86ms->fw_cfg) {
2403 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2404 return;
2405 }
2406
2407 if (!pcms->acpi_build_enabled) {
2408 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2409 return;
2410 }
2411
2412 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2413 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2414 return;
2415 }
2416
2417 build_state = g_malloc0(sizeof *build_state);
2418
2419 acpi_build_tables_init(&tables);
2420 acpi_build(&tables, MACHINE(pcms));
2421
2422 /* Now expose it all to Guest */
2423 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2424 build_state, tables.table_data,
2425 ACPI_BUILD_TABLE_FILE,
2426 ACPI_BUILD_TABLE_MAX_SIZE);
2427 assert(build_state->table_mr != NULL);
2428
2429 build_state->linker_mr =
2430 acpi_add_rom_blob(acpi_build_update, build_state,
2431 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
2432
2433 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2434 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2435
2436 tpm = tpm_find();
2437 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2438 tpm_config = (FwCfgTPMConfig) {
2439 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2440 .tpm_version = tpm_get_version(tpm),
2441 .tpmppi_version = TPM_PPI_VERSION_1_30
2442 };
2443 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2444 &tpm_config, sizeof tpm_config);
2445 }
2446
2447 vmgenid_dev = find_vmgenid_dev();
2448 if (vmgenid_dev) {
2449 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2450 tables.vmgenid);
2451 }
2452
2453 if (!pcmc->rsdp_in_ram) {
2454 /*
2455 * Keep for compatibility with old machine types.
2456 * Though RSDP is small, its contents isn't immutable, so
2457 * we'll update it along with the rest of tables on guest access.
2458 */
2459 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2460
2461 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2462 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2463 acpi_build_update, NULL, build_state,
2464 build_state->rsdp, rsdp_size, true);
2465 build_state->rsdp_mr = NULL;
2466 } else {
2467 build_state->rsdp = NULL;
2468 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2469 build_state, tables.rsdp,
2470 ACPI_BUILD_RSDP_FILE, 0);
2471 }
2472
2473 qemu_register_reset(acpi_build_reset, build_state);
2474 acpi_build_reset(build_state);
2475 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2476
2477 /* Cleanup tables but don't free the memory: we track it
2478 * in build_state.
2479 */
2480 acpi_build_tables_cleanup(&tables, false);
2481 }
AR7 emulation for QEMU