target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/qemu-print.h"
  23 #include "cpu.h"
  24
  25 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  26 {
  27     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  28
  29     cpu->env.pc = value;
  30     cpu->env.dflag = 0;
  31 }
  32
  33 static bool openrisc_cpu_has_work(CPUState *cs)
  34 {
  35     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  36                                     CPU_INTERRUPT_TIMER);
  37 }
  38
  39 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
  40 {
  41     info->print_insn = print_insn_or1k;
  42 }
  43
  44 static void openrisc_cpu_reset(DeviceState *dev)
  45 {
  46     CPUState *s = CPU(dev);
  47     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  48     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  49
  50     occ->parent_reset(dev);
  51
  52     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  53
  54     cpu->env.pc = 0x100;
  55     cpu->env.sr = SR_FO | SR_SM;
  56     cpu->env.lock_addr = -1;
  57     s->exception_index = -1;
  58     cpu_set_fpcsr(&cpu->env, 0);
  59
  60 #ifndef CONFIG_USER_ONLY
  61     cpu->env.picmr = 0x00000000;
  62     cpu->env.picsr = 0x00000000;
  63
  64     cpu->env.ttmr = 0x00000000;
  65 #endif
  66 }
  67
  68 #ifndef CONFIG_USER_ONLY
  69 static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
  70 {
  71     OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
  72     CPUState *cs = CPU(cpu);
  73     uint32_t irq_bit;
  74
  75     if (irq > 31 || irq < 0) {
  76         return;
  77     }
  78
  79     irq_bit = 1U << irq;
  80
  81     if (level) {
  82         cpu->env.picsr |= irq_bit;
  83     } else {
  84         cpu->env.picsr &= ~irq_bit;
  85     }
  86
  87     if (cpu->env.picsr & cpu->env.picmr) {
  88         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  89     } else {
  90         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  91         cpu->env.picsr = 0;
  92     }
  93 }
  94 #endif
  95
  96 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  97 {
  98     CPUState *cs = CPU(dev);
  99     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
 100     Error *local_err = NULL;
 101
 102     cpu_exec_realizefn(cs, &local_err);
 103     if (local_err != NULL) {
 104         error_propagate(errp, local_err);
 105         return;
 106     }
 107
 108     qemu_init_vcpu(cs);
 109     cpu_reset(cs);
 110
 111     occ->parent_realize(dev, errp);
 112 }
 113
 114 static void openrisc_cpu_initfn(Object *obj)
 115 {
 116     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 117
 118     cpu_set_cpustate_pointers(cpu);
 119
 120 #ifndef CONFIG_USER_ONLY
 121     qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
 122 #endif
 123 }
 124
 125 /* CPU models */
 126
 127 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 128 {
 129     ObjectClass *oc;
 130     char *typename;
 131
 132     typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
 133     oc = object_class_by_name(typename);
 134     g_free(typename);
 135     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 136                        object_class_is_abstract(oc))) {
 137         return NULL;
 138     }
 139     return oc;
 140 }
 141
 142 static void or1200_initfn(Object *obj)
 143 {
 144     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 145
 146     cpu->env.vr = 0x13000008;
 147     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
 148     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 149                        CPUCFGR_EVBARP;
 150
 151     /* 1Way, TLB_SIZE entries.  */
 152     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
 153                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 154     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
 155                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 156 }
 157
 158 static void openrisc_any_initfn(Object *obj)
 159 {
 160     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 161
 162     cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */
 163     cpu->env.vr2 = 0;           /* No version specific id */
 164     cpu->env.avr = 0x01030000;  /* Architecture v1.3 */
 165
 166     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
 167     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 168                        CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
 169
 170     /* 1Way, TLB_SIZE entries.  */
 171     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
 172                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 173     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
 174                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 175 }
 176
 177 #include "hw/core/tcg-cpu-ops.h"
 178
 179 static struct TCGCPUOps openrisc_tcg_ops = {
 180     .initialize = openrisc_translate_init,
 181     .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
 182     .tlb_fill = openrisc_cpu_tlb_fill,
 183
 184 #ifndef CONFIG_USER_ONLY
 185     .do_interrupt = openrisc_cpu_do_interrupt,
 186 #endif /* !CONFIG_USER_ONLY */
 187 };
 188
 189 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 190 {
 191     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 192     CPUClass *cc = CPU_CLASS(occ);
 193     DeviceClass *dc = DEVICE_CLASS(oc);
 194
 195     device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 196                                     &occ->parent_realize);
 197     device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
 198
 199     cc->class_by_name = openrisc_cpu_class_by_name;
 200     cc->has_work = openrisc_cpu_has_work;
 201     cc->dump_state = openrisc_cpu_dump_state;
 202     cc->set_pc = openrisc_cpu_set_pc;
 203     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 204     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 205 #ifndef CONFIG_USER_ONLY
 206     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 207     dc->vmsd = &vmstate_openrisc_cpu;
 208 #endif
 209     cc->gdb_num_core_regs = 32 + 3;
 210     cc->disas_set_info = openrisc_disas_set_info;
 211     cc->tcg_ops = &openrisc_tcg_ops;
 212 }
 213
 214 /* Sort alphabetically by type name, except for "any". */
 215 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 216 {
 217     ObjectClass *class_a = (ObjectClass *)a;
 218     ObjectClass *class_b = (ObjectClass *)b;
 219     const char *name_a, *name_b;
 220
 221     name_a = object_class_get_name(class_a);
 222     name_b = object_class_get_name(class_b);
 223     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 224         return 1;
 225     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 226         return -1;
 227     } else {
 228         return strcmp(name_a, name_b);
 229     }
 230 }
 231
 232 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 233 {
 234     ObjectClass *oc = data;
 235     const char *typename;
 236     char *name;
 237
 238     typename = object_class_get_name(oc);
 239     name = g_strndup(typename,
 240                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 241     qemu_printf("  %s\n", name);
 242     g_free(name);
 243 }
 244
 245 void cpu_openrisc_list(void)
 246 {
 247     GSList *list;
 248
 249     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 250     list = g_slist_sort(list, openrisc_cpu_list_compare);
 251     qemu_printf("Available CPUs:\n");
 252     g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
 253     g_slist_free(list);
 254 }
 255
 256 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
 257     {                                               \
 258         .parent = TYPE_OPENRISC_CPU,                \
 259         .instance_init = initfn,                    \
 260         .name = OPENRISC_CPU_TYPE_NAME(cpu_model),  \
 261     }
 262
 263 static const TypeInfo openrisc_cpus_type_infos[] = {
 264     { /* base class should be registered first */
 265         .name = TYPE_OPENRISC_CPU,
 266         .parent = TYPE_CPU,
 267         .instance_size = sizeof(OpenRISCCPU),
 268         .instance_init = openrisc_cpu_initfn,
 269         .abstract = true,
 270         .class_size = sizeof(OpenRISCCPUClass),
 271         .class_init = openrisc_cpu_class_init,
 272     },
 273     DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
 274     DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
 275 };
 276
 277 DEFINE_TYPES(openrisc_cpus_type_infos)