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[qemu/ar7.git] / target-arm / op_helper.c
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1 /*
2 * ARM helper routines
4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "cpu.h"
20 #include "helper.h"
22 #define SIGNBIT (uint32_t)0x80000000
23 #define SIGNBIT64 ((uint64_t)1 << 63)
25 static void raise_exception(CPUARMState *env, int tt)
27 env->exception_index = tt;
28 cpu_loop_exit(env);
31 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
32 uint32_t rn, uint32_t maxindex)
34 uint32_t val;
35 uint32_t tmp;
36 int index;
37 int shift;
38 uint64_t *table;
39 table = (uint64_t *)&env->vfp.regs[rn];
40 val = 0;
41 for (shift = 0; shift < 32; shift += 8) {
42 index = (ireg >> shift) & 0xff;
43 if (index < maxindex) {
44 tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
45 val |= tmp << shift;
46 } else {
47 val |= def & (0xff << shift);
50 return val;
53 #if !defined(CONFIG_USER_ONLY)
55 #include "exec/softmmu_exec.h"
57 #define MMUSUFFIX _mmu
59 #define SHIFT 0
60 #include "exec/softmmu_template.h"
62 #define SHIFT 1
63 #include "exec/softmmu_template.h"
65 #define SHIFT 2
66 #include "exec/softmmu_template.h"
68 #define SHIFT 3
69 #include "exec/softmmu_template.h"
71 /* try to fill the TLB and return an exception if error. If retaddr is
72 NULL, it means that the function was called in C code (i.e. not
73 from generated code or from helper.c) */
74 void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
75 uintptr_t retaddr)
77 int ret;
79 ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
80 if (unlikely(ret)) {
81 if (retaddr) {
82 /* now we have a real cpu fault */
83 cpu_restore_state(env, retaddr);
85 raise_exception(env, env->exception_index);
88 #endif
90 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
92 uint32_t res = a + b;
93 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
94 env->QF = 1;
95 return res;
98 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
100 uint32_t res = a + b;
101 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
102 env->QF = 1;
103 res = ~(((int32_t)a >> 31) ^ SIGNBIT);
105 return res;
108 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
110 uint32_t res = a - b;
111 if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
112 env->QF = 1;
113 res = ~(((int32_t)a >> 31) ^ SIGNBIT);
115 return res;
118 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
120 uint32_t res;
121 if (val >= 0x40000000) {
122 res = ~SIGNBIT;
123 env->QF = 1;
124 } else if (val <= (int32_t)0xc0000000) {
125 res = SIGNBIT;
126 env->QF = 1;
127 } else {
128 res = val << 1;
130 return res;
133 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
135 uint32_t res = a + b;
136 if (res < a) {
137 env->QF = 1;
138 res = ~0;
140 return res;
143 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
145 uint32_t res = a - b;
146 if (res > a) {
147 env->QF = 1;
148 res = 0;
150 return res;
153 /* Signed saturation. */
154 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
156 int32_t top;
157 uint32_t mask;
159 top = val >> shift;
160 mask = (1u << shift) - 1;
161 if (top > 0) {
162 env->QF = 1;
163 return mask;
164 } else if (top < -1) {
165 env->QF = 1;
166 return ~mask;
168 return val;
171 /* Unsigned saturation. */
172 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
174 uint32_t max;
176 max = (1u << shift) - 1;
177 if (val < 0) {
178 env->QF = 1;
179 return 0;
180 } else if (val > max) {
181 env->QF = 1;
182 return max;
184 return val;
187 /* Signed saturate. */
188 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
190 return do_ssat(env, x, shift);
193 /* Dual halfword signed saturate. */
194 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
196 uint32_t res;
198 res = (uint16_t)do_ssat(env, (int16_t)x, shift);
199 res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
200 return res;
203 /* Unsigned saturate. */
204 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
206 return do_usat(env, x, shift);
209 /* Dual halfword unsigned saturate. */
210 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
212 uint32_t res;
214 res = (uint16_t)do_usat(env, (int16_t)x, shift);
215 res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
216 return res;
219 void HELPER(wfi)(CPUARMState *env)
221 CPUState *cs = CPU(arm_env_get_cpu(env));
223 env->exception_index = EXCP_HLT;
224 cs->halted = 1;
225 cpu_loop_exit(env);
228 void HELPER(exception)(CPUARMState *env, uint32_t excp)
230 env->exception_index = excp;
231 cpu_loop_exit(env);
234 uint32_t HELPER(cpsr_read)(CPUARMState *env)
236 return cpsr_read(env) & ~CPSR_EXEC;
239 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
241 cpsr_write(env, val, mask);
244 /* Access to user mode registers from privileged modes. */
245 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
247 uint32_t val;
249 if (regno == 13) {
250 val = env->banked_r13[0];
251 } else if (regno == 14) {
252 val = env->banked_r14[0];
253 } else if (regno >= 8
254 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
255 val = env->usr_regs[regno - 8];
256 } else {
257 val = env->regs[regno];
259 return val;
262 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
264 if (regno == 13) {
265 env->banked_r13[0] = val;
266 } else if (regno == 14) {
267 env->banked_r14[0] = val;
268 } else if (regno >= 8
269 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
270 env->usr_regs[regno - 8] = val;
271 } else {
272 env->regs[regno] = val;
276 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
278 const ARMCPRegInfo *ri = rip;
279 int excp = ri->writefn(env, ri, value);
280 if (excp) {
281 raise_exception(env, excp);
285 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
287 const ARMCPRegInfo *ri = rip;
288 uint64_t value;
289 int excp = ri->readfn(env, ri, &value);
290 if (excp) {
291 raise_exception(env, excp);
293 return value;
296 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
298 const ARMCPRegInfo *ri = rip;
299 int excp = ri->writefn(env, ri, value);
300 if (excp) {
301 raise_exception(env, excp);
305 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
307 const ARMCPRegInfo *ri = rip;
308 uint64_t value;
309 int excp = ri->readfn(env, ri, &value);
310 if (excp) {
311 raise_exception(env, excp);
313 return value;
316 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
317 The only way to do that in TCG is a conditional branch, which clobbers
318 all our temporaries. For now implement these as helper functions. */
320 /* Similarly for variable shift instructions. */
322 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
324 int shift = i & 0xff;
325 if (shift >= 32) {
326 if (shift == 32)
327 env->CF = x & 1;
328 else
329 env->CF = 0;
330 return 0;
331 } else if (shift != 0) {
332 env->CF = (x >> (32 - shift)) & 1;
333 return x << shift;
335 return x;
338 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
340 int shift = i & 0xff;
341 if (shift >= 32) {
342 if (shift == 32)
343 env->CF = (x >> 31) & 1;
344 else
345 env->CF = 0;
346 return 0;
347 } else if (shift != 0) {
348 env->CF = (x >> (shift - 1)) & 1;
349 return x >> shift;
351 return x;
354 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
356 int shift = i & 0xff;
357 if (shift >= 32) {
358 env->CF = (x >> 31) & 1;
359 return (int32_t)x >> 31;
360 } else if (shift != 0) {
361 env->CF = (x >> (shift - 1)) & 1;
362 return (int32_t)x >> shift;
364 return x;
367 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
369 int shift1, shift;
370 shift1 = i & 0xff;
371 shift = shift1 & 0x1f;
372 if (shift == 0) {
373 if (shift1 != 0)
374 env->CF = (x >> 31) & 1;
375 return x;
376 } else {
377 env->CF = (x >> (shift - 1)) & 1;
378 return ((uint32_t)x >> shift) | (x << (32 - shift));