hw/i386/kvmvapic.c

   1 /*
   2  * TPR optimization for 32-bit Windows guests (XP and Server 2003)
   3  *
   4  * Copyright (C) 2007-2008 Qumranet Technologies
   5  * Copyright (C) 2012      Jan Kiszka, Siemens AG
   6  *
   7  * This work is licensed under the terms of the GNU GPL version 2, or
   8  * (at your option) any later version. See the COPYING file in the
   9  * top-level directory.
  10  */
  11 #include "sysemu/sysemu.h"
  12 #include "sysemu/cpus.h"
  13 #include "sysemu/kvm.h"
  14 #include "hw/i386/apic_internal.h"
  15 #include "hw/sysbus.h"
  16
  17 #define VAPIC_IO_PORT           0x7e
  18
  19 #define VAPIC_CPU_SHIFT         7
  20
  21 #define ROM_BLOCK_SIZE          512
  22 #define ROM_BLOCK_MASK          (~(ROM_BLOCK_SIZE - 1))
  23
  24 typedef enum VAPICMode {
  25     VAPIC_INACTIVE = 0,
  26     VAPIC_ACTIVE   = 1,
  27     VAPIC_STANDBY  = 2,
  28 } VAPICMode;
  29
  30 typedef struct VAPICHandlers {
  31     uint32_t set_tpr;
  32     uint32_t set_tpr_eax;
  33     uint32_t get_tpr[8];
  34     uint32_t get_tpr_stack;
  35 } QEMU_PACKED VAPICHandlers;
  36
  37 typedef struct GuestROMState {
  38     char signature[8];
  39     uint32_t vaddr;
  40     uint32_t fixup_start;
  41     uint32_t fixup_end;
  42     uint32_t vapic_vaddr;
  43     uint32_t vapic_size;
  44     uint32_t vcpu_shift;
  45     uint32_t real_tpr_addr;
  46     VAPICHandlers up;
  47     VAPICHandlers mp;
  48 } QEMU_PACKED GuestROMState;
  49
  50 typedef struct VAPICROMState {
  51     SysBusDevice busdev;
  52     MemoryRegion io;
  53     MemoryRegion rom;
  54     uint32_t state;
  55     uint32_t rom_state_paddr;
  56     uint32_t rom_state_vaddr;
  57     uint32_t vapic_paddr;
  58     uint32_t real_tpr_addr;
  59     GuestROMState rom_state;
  60     size_t rom_size;
  61     bool rom_mapped_writable;
  62     VMChangeStateEntry *vmsentry;
  63 } VAPICROMState;
  64
  65 #define TYPE_VAPIC "kvmvapic"
  66 #define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC)
  67
  68 #define TPR_INSTR_ABS_MODRM             0x1
  69 #define TPR_INSTR_MATCH_MODRM_REG       0x2
  70
  71 typedef struct TPRInstruction {
  72     uint8_t opcode;
  73     uint8_t modrm_reg;
  74     unsigned int flags;
  75     TPRAccess access;
  76     size_t length;
  77     off_t addr_offset;
  78 } TPRInstruction;
  79
  80 /* must be sorted by length, shortest first */
  81 static const TPRInstruction tpr_instr[] = {
  82     { /* mov abs to eax */
  83         .opcode = 0xa1,
  84         .access = TPR_ACCESS_READ,
  85         .length = 5,
  86         .addr_offset = 1,
  87     },
  88     { /* mov eax to abs */
  89         .opcode = 0xa3,
  90         .access = TPR_ACCESS_WRITE,
  91         .length = 5,
  92         .addr_offset = 1,
  93     },
  94     { /* mov r32 to r/m32 */
  95         .opcode = 0x89,
  96         .flags = TPR_INSTR_ABS_MODRM,
  97         .access = TPR_ACCESS_WRITE,
  98         .length = 6,
  99         .addr_offset = 2,
 100     },
 101     { /* mov r/m32 to r32 */
 102         .opcode = 0x8b,
 103         .flags = TPR_INSTR_ABS_MODRM,
 104         .access = TPR_ACCESS_READ,
 105         .length = 6,
 106         .addr_offset = 2,
 107     },
 108     { /* push r/m32 */
 109         .opcode = 0xff,
 110         .modrm_reg = 6,
 111         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 112         .access = TPR_ACCESS_READ,
 113         .length = 6,
 114         .addr_offset = 2,
 115     },
 116     { /* mov imm32, r/m32 (c7/0) */
 117         .opcode = 0xc7,
 118         .modrm_reg = 0,
 119         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 120         .access = TPR_ACCESS_WRITE,
 121         .length = 10,
 122         .addr_offset = 2,
 123     },
 124 };
 125
 126 static void read_guest_rom_state(VAPICROMState *s)
 127 {
 128     cpu_physical_memory_read(s->rom_state_paddr, &s->rom_state,
 129                              sizeof(GuestROMState));
 130 }
 131
 132 static void write_guest_rom_state(VAPICROMState *s)
 133 {
 134     cpu_physical_memory_write(s->rom_state_paddr, &s->rom_state,
 135                               sizeof(GuestROMState));
 136 }
 137
 138 static void update_guest_rom_state(VAPICROMState *s)
 139 {
 140     read_guest_rom_state(s);
 141
 142     s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr);
 143     s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT);
 144
 145     write_guest_rom_state(s);
 146 }
 147
 148 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
 149 {
 150     CPUState *cs = CPU(x86_env_get_cpu(env));
 151     hwaddr paddr;
 152     target_ulong addr;
 153
 154     if (s->state == VAPIC_ACTIVE) {
 155         return 0;
 156     }
 157     /*
 158      * If there is no prior TPR access instruction we could analyze (which is
 159      * the case after resume from hibernation), we need to scan the possible
 160      * virtual address space for the APIC mapping.
 161      */
 162     for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
 163         paddr = cpu_get_phys_page_debug(cs, addr);
 164         if (paddr != APIC_DEFAULT_ADDRESS) {
 165             continue;
 166         }
 167         s->real_tpr_addr = addr + 0x80;
 168         update_guest_rom_state(s);
 169         return 0;
 170     }
 171     return -1;
 172 }
 173
 174 static uint8_t modrm_reg(uint8_t modrm)
 175 {
 176     return (modrm >> 3) & 7;
 177 }
 178
 179 static bool is_abs_modrm(uint8_t modrm)
 180 {
 181     return (modrm & 0xc7) == 0x05;
 182 }
 183
 184 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
 185 {
 186     return opcode[0] == instr->opcode &&
 187         (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) &&
 188         (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) ||
 189          modrm_reg(opcode[1]) == instr->modrm_reg);
 190 }
 191
 192 static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
 193                                     target_ulong *pip, TPRAccess access)
 194 {
 195     CPUState *cs = CPU(cpu);
 196     const TPRInstruction *instr;
 197     target_ulong ip = *pip;
 198     uint8_t opcode[2];
 199     uint32_t real_tpr_addr;
 200     int i;
 201
 202     if ((ip & 0xf0000000ULL) != 0x80000000ULL &&
 203         (ip & 0xf0000000ULL) != 0xe0000000ULL) {
 204         return -1;
 205     }
 206
 207     /*
 208      * Early Windows 2003 SMP initialization contains a
 209      *
 210      *   mov imm32, r/m32
 211      *
 212      * instruction that is patched by TPR optimization. The problem is that
 213      * RSP, used by the patched instruction, is zero, so the guest gets a
 214      * double fault and dies.
 215      */
 216     if (cpu->env.regs[R_ESP] == 0) {
 217         return -1;
 218     }
 219
 220     if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
 221         /*
 222          * KVM without kernel-based TPR access reporting will pass an IP that
 223          * points after the accessing instruction. So we need to look backward
 224          * to find the reason.
 225          */
 226         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 227             instr = &tpr_instr[i];
 228             if (instr->access != access) {
 229                 continue;
 230             }
 231             if (cpu_memory_rw_debug(cs, ip - instr->length, opcode,
 232                                     sizeof(opcode), 0) < 0) {
 233                 return -1;
 234             }
 235             if (opcode_matches(opcode, instr)) {
 236                 ip -= instr->length;
 237                 goto instruction_ok;
 238             }
 239         }
 240         return -1;
 241     } else {
 242         if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) {
 243             return -1;
 244         }
 245         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 246             instr = &tpr_instr[i];
 247             if (opcode_matches(opcode, instr)) {
 248                 goto instruction_ok;
 249             }
 250         }
 251         return -1;
 252     }
 253
 254 instruction_ok:
 255     /*
 256      * Grab the virtual TPR address from the instruction
 257      * and update the cached values.
 258      */
 259     if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
 260                             (void *)&real_tpr_addr,
 261                             sizeof(real_tpr_addr), 0) < 0) {
 262         return -1;
 263     }
 264     real_tpr_addr = le32_to_cpu(real_tpr_addr);
 265     if ((real_tpr_addr & 0xfff) != 0x80) {
 266         return -1;
 267     }
 268     s->real_tpr_addr = real_tpr_addr;
 269     update_guest_rom_state(s);
 270
 271     *pip = ip;
 272     return 0;
 273 }
 274
 275 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
 276 {
 277     CPUState *cs = CPU(x86_env_get_cpu(env));
 278     hwaddr paddr;
 279     uint32_t rom_state_vaddr;
 280     uint32_t pos, patch, offset;
 281
 282     /* nothing to do if already activated */
 283     if (s->state == VAPIC_ACTIVE) {
 284         return 0;
 285     }
 286
 287     /* bail out if ROM init code was not executed (missing ROM?) */
 288     if (s->state == VAPIC_INACTIVE) {
 289         return -1;
 290     }
 291
 292     /* find out virtual address of the ROM */
 293     rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
 294     paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr);
 295     if (paddr == -1) {
 296         return -1;
 297     }
 298     paddr += rom_state_vaddr & ~TARGET_PAGE_MASK;
 299     if (paddr != s->rom_state_paddr) {
 300         return -1;
 301     }
 302     read_guest_rom_state(s);
 303     if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) {
 304         return -1;
 305     }
 306     s->rom_state_vaddr = rom_state_vaddr;
 307
 308     /* fixup addresses in ROM if needed */
 309     if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) {
 310         return 0;
 311     }
 312     for (pos = le32_to_cpu(s->rom_state.fixup_start);
 313          pos < le32_to_cpu(s->rom_state.fixup_end);
 314          pos += 4) {
 315         cpu_physical_memory_read(paddr + pos - s->rom_state.vaddr,
 316                                  &offset, sizeof(offset));
 317         offset = le32_to_cpu(offset);
 318         cpu_physical_memory_read(paddr + offset, &patch, sizeof(patch));
 319         patch = le32_to_cpu(patch);
 320         patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr);
 321         patch = cpu_to_le32(patch);
 322         cpu_physical_memory_write(paddr + offset, &patch, sizeof(patch));
 323     }
 324     read_guest_rom_state(s);
 325     s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) -
 326         le32_to_cpu(s->rom_state.vaddr);
 327
 328     return 0;
 329 }
 330
 331 /*
 332  * Tries to read the unique processor number from the Kernel Processor Control
 333  * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR
 334  * cannot be accessed or is considered invalid. This also ensures that we are
 335  * not patching the wrong guest.
 336  */
 337 static int get_kpcr_number(X86CPU *cpu)
 338 {
 339     CPUX86State *env = &cpu->env;
 340     struct kpcr {
 341         uint8_t  fill1[0x1c];
 342         uint32_t self;
 343         uint8_t  fill2[0x31];
 344         uint8_t  number;
 345     } QEMU_PACKED kpcr;
 346
 347     if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
 348                             (void *)&kpcr, sizeof(kpcr), 0) < 0 ||
 349         kpcr.self != env->segs[R_FS].base) {
 350         return -1;
 351     }
 352     return kpcr.number;
 353 }
 354
 355 static int vapic_enable(VAPICROMState *s, X86CPU *cpu)
 356 {
 357     int cpu_number = get_kpcr_number(cpu);
 358     hwaddr vapic_paddr;
 359     static const uint8_t enabled = 1;
 360
 361     if (cpu_number < 0) {
 362         return -1;
 363     }
 364     vapic_paddr = s->vapic_paddr +
 365         (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
 366     cpu_physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled),
 367                               &enabled, sizeof(enabled));
 368     apic_enable_vapic(cpu->apic_state, vapic_paddr);
 369
 370     s->state = VAPIC_ACTIVE;
 371
 372     return 0;
 373 }
 374
 375 static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte)
 376 {
 377     cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1);
 378 }
 379
 380 static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
 381                        uint32_t target)
 382 {
 383     uint32_t offset;
 384
 385     offset = cpu_to_le32(target - ip - 5);
 386     patch_byte(cpu, ip, 0xe8); /* call near */
 387     cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1);
 388 }
 389
 390 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
 391 {
 392     CPUState *cs = CPU(cpu);
 393     CPUX86State *env = &cpu->env;
 394     VAPICHandlers *handlers;
 395     uint8_t opcode[2];
 396     uint32_t imm32;
 397     target_ulong current_pc = 0;
 398     target_ulong current_cs_base = 0;
 399     int current_flags = 0;
 400
 401     if (smp_cpus == 1) {
 402         handlers = &s->rom_state.up;
 403     } else {
 404         handlers = &s->rom_state.mp;
 405     }
 406
 407     if (!kvm_enabled()) {
 408         cpu_restore_state(cs, cs->mem_io_pc);
 409         cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
 410                              &current_flags);
 411     }
 412
 413     pause_all_vcpus();
 414
 415     cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0);
 416
 417     switch (opcode[0]) {
 418     case 0x89: /* mov r32 to r/m32 */
 419         patch_byte(cpu, ip, 0x50 + modrm_reg(opcode[1]));  /* push reg */
 420         patch_call(s, cpu, ip + 1, handlers->set_tpr);
 421         break;
 422     case 0x8b: /* mov r/m32 to r32 */
 423         patch_byte(cpu, ip, 0x90);
 424         patch_call(s, cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
 425         break;
 426     case 0xa1: /* mov abs to eax */
 427         patch_call(s, cpu, ip, handlers->get_tpr[0]);
 428         break;
 429     case 0xa3: /* mov eax to abs */
 430         patch_call(s, cpu, ip, handlers->set_tpr_eax);
 431         break;
 432     case 0xc7: /* mov imm32, r/m32 (c7/0) */
 433         patch_byte(cpu, ip, 0x68);  /* push imm32 */
 434         cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0);
 435         cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1);
 436         patch_call(s, cpu, ip + 5, handlers->set_tpr);
 437         break;
 438     case 0xff: /* push r/m32 */
 439         patch_byte(cpu, ip, 0x50); /* push eax */
 440         patch_call(s, cpu, ip + 1, handlers->get_tpr_stack);
 441         break;
 442     default:
 443         abort();
 444     }
 445
 446     resume_all_vcpus();
 447
 448     if (!kvm_enabled()) {
 449         cs->current_tb = NULL;
 450         tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
 451         cpu_resume_from_signal(cs, NULL);
 452     }
 453 }
 454
 455 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
 456                              TPRAccess access)
 457 {
 458     VAPICROMState *s = VAPIC(dev);
 459     X86CPU *cpu = X86_CPU(cs);
 460     CPUX86State *env = &cpu->env;
 461
 462     cpu_synchronize_state(cs);
 463
 464     if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) {
 465         if (s->state == VAPIC_ACTIVE) {
 466             vapic_enable(s, cpu);
 467         }
 468         return;
 469     }
 470     if (update_rom_mapping(s, env, ip) < 0) {
 471         return;
 472     }
 473     if (vapic_enable(s, cpu) < 0) {
 474         return;
 475     }
 476     patch_instruction(s, cpu, ip);
 477 }
 478
 479 typedef struct VAPICEnableTPRReporting {
 480     DeviceState *apic;
 481     bool enable;
 482 } VAPICEnableTPRReporting;
 483
 484 static void vapic_do_enable_tpr_reporting(void *data)
 485 {
 486     VAPICEnableTPRReporting *info = data;
 487
 488     apic_enable_tpr_access_reporting(info->apic, info->enable);
 489 }
 490
 491 static void vapic_enable_tpr_reporting(bool enable)
 492 {
 493     VAPICEnableTPRReporting info = {
 494         .enable = enable,
 495     };
 496     CPUState *cs;
 497     X86CPU *cpu;
 498
 499     CPU_FOREACH(cs) {
 500         cpu = X86_CPU(cs);
 501         info.apic = cpu->apic_state;
 502         run_on_cpu(cs, vapic_do_enable_tpr_reporting, &info);
 503     }
 504 }
 505
 506 static void vapic_reset(DeviceState *dev)
 507 {
 508     VAPICROMState *s = VAPIC(dev);
 509
 510     s->state = VAPIC_INACTIVE;
 511     s->rom_state_paddr = 0;
 512     vapic_enable_tpr_reporting(false);
 513 }
 514
 515 /*
 516  * Set the IRQ polling hypercalls to the supported variant:
 517  *  - vmcall if using KVM in-kernel irqchip
 518  *  - 32-bit VAPIC port write otherwise
 519  */
 520 static int patch_hypercalls(VAPICROMState *s)
 521 {
 522     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 523     static const uint8_t vmcall_pattern[] = { /* vmcall */
 524         0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
 525     };
 526     static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */
 527         0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e
 528     };
 529     uint8_t alternates[2];
 530     const uint8_t *pattern;
 531     const uint8_t *patch;
 532     int patches = 0;
 533     off_t pos;
 534     uint8_t *rom;
 535
 536     rom = g_malloc(s->rom_size);
 537     cpu_physical_memory_read(rom_paddr, rom, s->rom_size);
 538
 539     for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) {
 540         if (kvm_irqchip_in_kernel()) {
 541             pattern = outl_pattern;
 542             alternates[0] = outl_pattern[7];
 543             alternates[1] = outl_pattern[7];
 544             patch = &vmcall_pattern[5];
 545         } else {
 546             pattern = vmcall_pattern;
 547             alternates[0] = vmcall_pattern[7];
 548             alternates[1] = 0xd9; /* AMD's VMMCALL */
 549             patch = &outl_pattern[5];
 550         }
 551         if (memcmp(rom + pos, pattern, 7) == 0 &&
 552             (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) {
 553             cpu_physical_memory_write(rom_paddr + pos + 5, patch, 3);
 554             /*
 555              * Don't flush the tb here. Under ordinary conditions, the patched
 556              * calls are miles away from the current IP. Under malicious
 557              * conditions, the guest could trick us to crash.
 558              */
 559         }
 560     }
 561
 562     g_free(rom);
 563
 564     if (patches != 0 && patches != 2) {
 565         return -1;
 566     }
 567
 568     return 0;
 569 }
 570
 571 /*
 572  * For TCG mode or the time KVM honors read-only memory regions, we need to
 573  * enable write access to the option ROM so that variables can be updated by
 574  * the guest.
 575  */
 576 static int vapic_map_rom_writable(VAPICROMState *s)
 577 {
 578     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 579     MemoryRegionSection section;
 580     MemoryRegion *as;
 581     size_t rom_size;
 582     uint8_t *ram;
 583
 584     as = sysbus_address_space(&s->busdev);
 585
 586     if (s->rom_mapped_writable) {
 587         memory_region_del_subregion(as, &s->rom);
 588         object_unparent(OBJECT(&s->rom));
 589     }
 590
 591     /* grab RAM memory region (region @rom_paddr may still be pc.rom) */
 592     section = memory_region_find(as, 0, 1);
 593
 594     /* read ROM size from RAM region */
 595     if (rom_paddr + 2 >= memory_region_size(section.mr)) {
 596         return -1;
 597     }
 598     ram = memory_region_get_ram_ptr(section.mr);
 599     rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE;
 600     if (rom_size == 0) {
 601         return -1;
 602     }
 603     s->rom_size = rom_size;
 604
 605     /* We need to round to avoid creating subpages
 606      * from which we cannot run code. */
 607     rom_size += rom_paddr & ~TARGET_PAGE_MASK;
 608     rom_paddr &= TARGET_PAGE_MASK;
 609     rom_size = TARGET_PAGE_ALIGN(rom_size);
 610
 611     memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr,
 612                              rom_paddr, rom_size);
 613     memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
 614     s->rom_mapped_writable = true;
 615     memory_region_unref(section.mr);
 616
 617     return 0;
 618 }
 619
 620 static int vapic_prepare(VAPICROMState *s)
 621 {
 622     if (vapic_map_rom_writable(s) < 0) {
 623         return -1;
 624     }
 625
 626     if (patch_hypercalls(s) < 0) {
 627         return -1;
 628     }
 629
 630     vapic_enable_tpr_reporting(true);
 631
 632     return 0;
 633 }
 634
 635 static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
 636                         unsigned int size)
 637 {
 638     CPUState *cs = current_cpu;
 639     X86CPU *cpu = X86_CPU(cs);
 640     CPUX86State *env = &cpu->env;
 641     hwaddr rom_paddr;
 642     VAPICROMState *s = opaque;
 643
 644     cpu_synchronize_state(cs);
 645
 646     /*
 647      * The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
 648      *  o 16-bit write access:
 649      *    Reports the option ROM initialization to the hypervisor. Written
 650      *    value is the offset of the state structure in the ROM.
 651      *  o 8-bit write access:
 652      *    Reactivates the VAPIC after a guest hibernation, i.e. after the
 653      *    option ROM content has been re-initialized by a guest power cycle.
 654      *  o 32-bit write access:
 655      *    Poll for pending IRQs, considering the current VAPIC state.
 656      */
 657     switch (size) {
 658     case 2:
 659         if (s->state == VAPIC_INACTIVE) {
 660             rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK;
 661             s->rom_state_paddr = rom_paddr + data;
 662
 663             s->state = VAPIC_STANDBY;
 664         }
 665         if (vapic_prepare(s) < 0) {
 666             s->state = VAPIC_INACTIVE;
 667             s->rom_state_paddr = 0;
 668             break;
 669         }
 670         break;
 671     case 1:
 672         if (kvm_enabled()) {
 673             /*
 674              * Disable triggering instruction in ROM by writing a NOP.
 675              *
 676              * We cannot do this in TCG mode as the reported IP is not
 677              * accurate.
 678              */
 679             pause_all_vcpus();
 680             patch_byte(cpu, env->eip - 2, 0x66);
 681             patch_byte(cpu, env->eip - 1, 0x90);
 682             resume_all_vcpus();
 683         }
 684
 685         if (s->state == VAPIC_ACTIVE) {
 686             break;
 687         }
 688         if (update_rom_mapping(s, env, env->eip) < 0) {
 689             break;
 690         }
 691         if (find_real_tpr_addr(s, env) < 0) {
 692             break;
 693         }
 694         vapic_enable(s, cpu);
 695         break;
 696     default:
 697     case 4:
 698         if (!kvm_irqchip_in_kernel()) {
 699             apic_poll_irq(cpu->apic_state);
 700         }
 701         break;
 702     }
 703 }
 704
 705 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
 706 {
 707     return 0xffffffff;
 708 }
 709
 710 static const MemoryRegionOps vapic_ops = {
 711     .write = vapic_write,
 712     .read = vapic_read,
 713     .endianness = DEVICE_NATIVE_ENDIAN,
 714 };
 715
 716 static void vapic_realize(DeviceState *dev, Error **errp)
 717 {
 718     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 719     VAPICROMState *s = VAPIC(dev);
 720
 721     memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2);
 722     sysbus_add_io(sbd, VAPIC_IO_PORT, &s->io);
 723     sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2);
 724
 725     option_rom[nb_option_roms].name = "kvmvapic.bin";
 726     option_rom[nb_option_roms].bootindex = -1;
 727     nb_option_roms++;
 728 }
 729
 730 static void do_vapic_enable(void *data)
 731 {
 732     VAPICROMState *s = data;
 733     X86CPU *cpu = X86_CPU(first_cpu);
 734
 735     static const uint8_t enabled = 1;
 736     cpu_physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled),
 737                               &enabled, sizeof(enabled));
 738     apic_enable_vapic(cpu->apic_state, s->vapic_paddr);
 739     s->state = VAPIC_ACTIVE;
 740 }
 741
 742 static void kvmvapic_vm_state_change(void *opaque, int running,
 743                                      RunState state)
 744 {
 745     VAPICROMState *s = opaque;
 746     uint8_t *zero;
 747
 748     if (!running) {
 749         return;
 750     }
 751
 752     if (s->state == VAPIC_ACTIVE) {
 753         if (smp_cpus == 1) {
 754             run_on_cpu(first_cpu, do_vapic_enable, s);
 755         } else {
 756             zero = g_malloc0(s->rom_state.vapic_size);
 757             cpu_physical_memory_write(s->vapic_paddr, zero,
 758                                       s->rom_state.vapic_size);
 759             g_free(zero);
 760         }
 761     }
 762
 763     qemu_del_vm_change_state_handler(s->vmsentry);
 764 }
 765
 766 static int vapic_post_load(void *opaque, int version_id)
 767 {
 768     VAPICROMState *s = opaque;
 769
 770     /*
 771      * The old implementation of qemu-kvm did not provide the state
 772      * VAPIC_STANDBY. Reconstruct it.
 773      */
 774     if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) {
 775         s->state = VAPIC_STANDBY;
 776     }
 777
 778     if (s->state != VAPIC_INACTIVE) {
 779         if (vapic_prepare(s) < 0) {
 780             return -1;
 781         }
 782     }
 783
 784     if (!s->vmsentry) {
 785         s->vmsentry =
 786             qemu_add_vm_change_state_handler(kvmvapic_vm_state_change, s);
 787     }
 788     return 0;
 789 }
 790
 791 static const VMStateDescription vmstate_handlers = {
 792     .name = "kvmvapic-handlers",
 793     .version_id = 1,
 794     .minimum_version_id = 1,
 795     .fields = (VMStateField[]) {
 796         VMSTATE_UINT32(set_tpr, VAPICHandlers),
 797         VMSTATE_UINT32(set_tpr_eax, VAPICHandlers),
 798         VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8),
 799         VMSTATE_UINT32(get_tpr_stack, VAPICHandlers),
 800         VMSTATE_END_OF_LIST()
 801     }
 802 };
 803
 804 static const VMStateDescription vmstate_guest_rom = {
 805     .name = "kvmvapic-guest-rom",
 806     .version_id = 1,
 807     .minimum_version_id = 1,
 808     .fields = (VMStateField[]) {
 809         VMSTATE_UNUSED(8),     /* signature */
 810         VMSTATE_UINT32(vaddr, GuestROMState),
 811         VMSTATE_UINT32(fixup_start, GuestROMState),
 812         VMSTATE_UINT32(fixup_end, GuestROMState),
 813         VMSTATE_UINT32(vapic_vaddr, GuestROMState),
 814         VMSTATE_UINT32(vapic_size, GuestROMState),
 815         VMSTATE_UINT32(vcpu_shift, GuestROMState),
 816         VMSTATE_UINT32(real_tpr_addr, GuestROMState),
 817         VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 818         VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 819         VMSTATE_END_OF_LIST()
 820     }
 821 };
 822
 823 static const VMStateDescription vmstate_vapic = {
 824     .name = "kvm-tpr-opt",      /* compatible with qemu-kvm VAPIC */
 825     .version_id = 1,
 826     .minimum_version_id = 1,
 827     .post_load = vapic_post_load,
 828     .fields = (VMStateField[]) {
 829         VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom,
 830                        GuestROMState),
 831         VMSTATE_UINT32(state, VAPICROMState),
 832         VMSTATE_UINT32(real_tpr_addr, VAPICROMState),
 833         VMSTATE_UINT32(rom_state_vaddr, VAPICROMState),
 834         VMSTATE_UINT32(vapic_paddr, VAPICROMState),
 835         VMSTATE_UINT32(rom_state_paddr, VAPICROMState),
 836         VMSTATE_END_OF_LIST()
 837     }
 838 };
 839
 840 static void vapic_class_init(ObjectClass *klass, void *data)
 841 {
 842     DeviceClass *dc = DEVICE_CLASS(klass);
 843
 844     dc->reset   = vapic_reset;
 845     dc->vmsd    = &vmstate_vapic;
 846     dc->realize = vapic_realize;
 847 }
 848
 849 static const TypeInfo vapic_type = {
 850     .name          = TYPE_VAPIC,
 851     .parent        = TYPE_SYS_BUS_DEVICE,
 852     .instance_size = sizeof(VAPICROMState),
 853     .class_init    = vapic_class_init,
 854 };
 855
 856 static void vapic_register(void)
 857 {
 858     type_register_static(&vapic_type);
 859 }
 860
 861 type_init(vapic_register);