2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 static const TypeInfo spapr_intc_info
= {
27 .name
= TYPE_SPAPR_INTC
,
28 .parent
= TYPE_INTERFACE
,
29 .class_size
= sizeof(SpaprInterruptControllerClass
),
32 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
34 spapr
->irq_map_nr
= nr_msis
;
35 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
38 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
44 * The 'align_mask' parameter of bitmap_find_next_zero_area()
45 * should be one less than a power of 2; 0 means no
46 * alignment. Adapt the 'align' value of the former allocator
47 * to fit the requirements of bitmap_find_next_zero_area()
51 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
53 if (irq
== spapr
->irq_map_nr
) {
54 error_setg(errp
, "can't find a free %d-IRQ block", num
);
58 bitmap_set(spapr
->irq_map
, irq
, num
);
60 return irq
+ SPAPR_IRQ_MSI
;
63 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
65 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
68 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
69 SpaprIrq
*irq
, Error
**errp
)
71 MachineState
*machine
= MACHINE(spapr
);
72 Error
*local_err
= NULL
;
74 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
75 irq
->init_kvm(spapr
, &local_err
);
76 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
77 error_prepend(&local_err
,
78 "kernel_irqchip requested but unavailable: ");
79 error_propagate(errp
, local_err
);
88 * We failed to initialize the KVM device, fallback to
91 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
92 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
93 warn_report_err(local_err
);
101 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
106 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
108 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
111 ics_pic_print_info(spapr
->ics
, mon
);
114 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
116 if (!kvm_irqchip_in_kernel()) {
119 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
120 icp_resend(spapr_cpu_state(cpu
)->icp
);
126 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
128 Error
*local_err
= NULL
;
130 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
132 error_propagate(errp
, local_err
);
137 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
140 xics_kvm_connect(spapr
, errp
);
144 SpaprIrq spapr_irq_xics
= {
145 .nr_xirqs
= SPAPR_NR_XIRQS
,
146 .nr_msis
= SPAPR_NR_MSIS
,
150 .print_info
= spapr_irq_print_info_xics
,
151 .dt_populate
= spapr_dt_xics
,
152 .post_load
= spapr_irq_post_load_xics
,
153 .reset
= spapr_irq_reset_xics
,
154 .init_kvm
= spapr_irq_init_kvm_xics
,
161 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
167 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
169 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
172 spapr_xive_pic_print_info(spapr
->xive
, mon
);
175 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
177 return spapr_xive_post_load(spapr
->xive
, version_id
);
180 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
183 Error
*local_err
= NULL
;
186 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
188 /* (TCG) Set the OS CAM line of the thread interrupt context. */
189 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
192 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
194 error_propagate(errp
, local_err
);
198 /* Activate the XIVE MMIOs */
199 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
202 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
205 kvmppc_xive_connect(spapr
->xive
, errp
);
209 SpaprIrq spapr_irq_xive
= {
210 .nr_xirqs
= SPAPR_NR_XIRQS
,
211 .nr_msis
= SPAPR_NR_MSIS
,
215 .print_info
= spapr_irq_print_info_xive
,
216 .dt_populate
= spapr_dt_xive
,
217 .post_load
= spapr_irq_post_load_xive
,
218 .reset
= spapr_irq_reset_xive
,
219 .init_kvm
= spapr_irq_init_kvm_xive
,
223 * Dual XIVE and XICS IRQ backend.
225 * Both interrupt mode, XIVE and XICS, objects are created but the
226 * machine starts in legacy interrupt mode (XICS). It can be changed
227 * by the CAS negotiation process and, in that case, the new mode is
228 * activated after an extra machine reset.
232 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
235 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
237 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
238 &spapr_irq_xive
: &spapr_irq_xics
;
241 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
243 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
246 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
247 uint32_t nr_servers
, void *fdt
,
250 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
253 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
256 * Force a reset of the XIVE backend after migration. The machine
257 * defaults to XICS at startup.
259 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
260 if (kvm_irqchip_in_kernel()) {
261 xics_kvm_disconnect(spapr
, &error_fatal
);
263 spapr_irq_xive
.reset(spapr
, &error_fatal
);
266 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
269 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
271 Error
*local_err
= NULL
;
274 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
277 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
279 /* Destroy all KVM devices */
280 if (kvm_irqchip_in_kernel()) {
281 xics_kvm_disconnect(spapr
, &local_err
);
283 error_propagate(errp
, local_err
);
284 error_prepend(errp
, "KVM XICS disconnect failed: ");
287 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
289 error_propagate(errp
, local_err
);
290 error_prepend(errp
, "KVM XIVE disconnect failed: ");
295 spapr_irq_current(spapr
)->reset(spapr
, errp
);
299 * Define values in sync with the XIVE and XICS backend
301 SpaprIrq spapr_irq_dual
= {
302 .nr_xirqs
= SPAPR_NR_XIRQS
,
303 .nr_msis
= SPAPR_NR_MSIS
,
307 .print_info
= spapr_irq_print_info_dual
,
308 .dt_populate
= spapr_irq_dt_populate_dual
,
309 .post_load
= spapr_irq_post_load_dual
,
310 .reset
= spapr_irq_reset_dual
,
311 .init_kvm
= NULL
, /* should not be used */
315 static int spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
317 MachineState
*machine
= MACHINE(spapr
);
320 * Sanity checks on non-P9 machines. On these, XIVE is not
321 * advertised, see spapr_dt_ov5_platform_support()
323 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
324 0, spapr
->max_compat_pvr
)) {
326 * If the 'dual' interrupt mode is selected, force XICS as CAS
327 * negotiation is useless.
329 if (spapr
->irq
== &spapr_irq_dual
) {
330 spapr
->irq
= &spapr_irq_xics
;
335 * Non-P9 machines using only XIVE is a bogus setup. We have two
336 * scenarios to take into account because of the compat mode:
338 * 1. POWER7/8 machines should fail to init later on when creating
339 * the XIVE interrupt presenters because a POWER9 exception
342 * 2. POWER9 machines using the POWER8 compat mode won't fail and
343 * will let the OS boot with a partial XIVE setup : DT
344 * properties but no hcalls.
346 * To cover both and not confuse the OS, add an early failure in
349 if (spapr
->irq
== &spapr_irq_xive
) {
350 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
356 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
357 * re-created. Detect that early to avoid QEMU to exit later when the
361 spapr
->irq
== &spapr_irq_dual
&&
362 machine_kernel_irqchip_required(machine
) &&
363 xics_kvm_has_broken_disconnect(spapr
)) {
364 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
372 * sPAPR IRQ frontend routines for devices
374 #define ALL_INTCS(spapr_) \
375 { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
377 int spapr_irq_cpu_intc_create(SpaprMachineState
*spapr
,
378 PowerPCCPU
*cpu
, Error
**errp
)
380 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
384 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
385 SpaprInterruptController
*intc
= intcs
[i
];
387 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
388 rc
= sicc
->cpu_intc_create(intc
, cpu
, errp
);
398 static void spapr_set_irq(void *opaque
, int irq
, int level
)
400 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
401 SpaprInterruptControllerClass
*sicc
402 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
404 sicc
->set_irq(spapr
->active_intc
, irq
, level
);
407 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
409 MachineState
*machine
= MACHINE(spapr
);
411 if (machine_kernel_irqchip_split(machine
)) {
412 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
416 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
418 "kernel_irqchip requested but only available with KVM");
422 if (spapr_irq_check(spapr
, errp
) < 0) {
426 /* Initialize the MSI IRQ allocator. */
427 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
428 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
431 if (spapr
->irq
->xics
) {
432 Error
*local_err
= NULL
;
435 obj
= object_new(TYPE_ICS_SPAPR
);
436 object_property_add_child(OBJECT(spapr
), "ics", obj
, &local_err
);
438 error_propagate(errp
, local_err
);
442 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
445 error_propagate(errp
, local_err
);
449 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
, "nr-irqs",
452 error_propagate(errp
, local_err
);
456 object_property_set_bool(obj
, true, "realized", &local_err
);
458 error_propagate(errp
, local_err
);
462 spapr
->ics
= ICS_SPAPR(obj
);
465 if (spapr
->irq
->xive
) {
466 uint32_t nr_servers
= spapr_max_server_number(spapr
);
470 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
471 qdev_prop_set_uint32(dev
, "nr-irqs",
472 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
474 * 8 XIVE END structures per CPU. One for each available
477 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
478 qdev_init_nofail(dev
);
480 spapr
->xive
= SPAPR_XIVE(dev
);
482 /* Enable the CPU IPIs */
483 for (i
= 0; i
< nr_servers
; ++i
) {
484 SpaprInterruptControllerClass
*sicc
485 = SPAPR_INTC_GET_CLASS(spapr
->xive
);
487 if (sicc
->claim_irq(SPAPR_INTC(spapr
->xive
), SPAPR_IRQ_IPI
+ i
,
493 spapr_xive_hcall_init(spapr
);
496 spapr
->qirqs
= qemu_allocate_irqs(spapr_set_irq
, spapr
,
497 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
500 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
502 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
506 assert(irq
>= SPAPR_XIRQ_BASE
);
507 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
509 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
510 SpaprInterruptController
*intc
= intcs
[i
];
512 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
513 rc
= sicc
->claim_irq(intc
, irq
, lsi
, errp
);
523 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
525 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
528 assert(irq
>= SPAPR_XIRQ_BASE
);
529 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
531 for (i
= irq
; i
< (irq
+ num
); i
++) {
532 for (j
= 0; j
< ARRAY_SIZE(intcs
); j
++) {
533 SpaprInterruptController
*intc
= intcs
[j
];
536 SpaprInterruptControllerClass
*sicc
537 = SPAPR_INTC_GET_CLASS(intc
);
538 sicc
->free_irq(intc
, i
);
544 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
547 * This interface is basically for VIO and PHB devices to find the
548 * right qemu_irq to manipulate, so we only allow access to the
549 * external irqs for now. Currently anything which needs to
550 * access the IPIs most naturally gets there via the guest side
551 * interfaces, we can change this if we need to in future.
553 assert(irq
>= SPAPR_XIRQ_BASE
);
554 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
557 assert(ics_valid_irq(spapr
->ics
, irq
));
560 assert(irq
< spapr
->xive
->nr_irqs
);
561 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
564 return spapr
->qirqs
[irq
];
567 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
569 spapr_irq_update_active_intc(spapr
);
570 return spapr
->irq
->post_load(spapr
, version_id
);
573 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
575 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
577 spapr_irq_update_active_intc(spapr
);
579 if (spapr
->irq
->reset
) {
580 spapr
->irq
->reset(spapr
, errp
);
584 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
586 const char *nodename
= "interrupt-controller";
589 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
591 error_setg(errp
, "Can't find node \"%s\": %s",
592 nodename
, fdt_strerror(offset
));
596 phandle
= fdt_get_phandle(fdt
, offset
);
598 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
605 static void set_active_intc(SpaprMachineState
*spapr
,
606 SpaprInterruptController
*new_intc
)
608 SpaprInterruptControllerClass
*sicc
;
612 if (new_intc
== spapr
->active_intc
) {
617 if (spapr
->active_intc
) {
618 sicc
= SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
619 if (sicc
->deactivate
) {
620 sicc
->deactivate(spapr
->active_intc
);
624 sicc
= SPAPR_INTC_GET_CLASS(new_intc
);
625 if (sicc
->activate
) {
626 sicc
->activate(new_intc
, &error_fatal
);
629 spapr
->active_intc
= new_intc
;
632 void spapr_irq_update_active_intc(SpaprMachineState
*spapr
)
634 SpaprInterruptController
*new_intc
;
638 * XXX before we run CAS, ov5_cas is initialized empty, which
639 * indicates XICS, even if we have ic-mode=xive. TODO: clean
640 * up the CAS path so that we have a clearer way of handling
643 new_intc
= SPAPR_INTC(spapr
->xive
);
644 } else if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
645 new_intc
= SPAPR_INTC(spapr
->xive
);
647 new_intc
= SPAPR_INTC(spapr
->ics
);
650 set_active_intc(spapr
, new_intc
);
654 * XICS legacy routines - to deprecate one day
657 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
661 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
662 if (num
> (ics
->nr_irqs
- first
)) {
665 for (i
= first
; i
< first
+ num
; ++i
) {
666 if (!ics_irq_free(ics
, i
)) {
670 if (i
== (first
+ num
)) {
678 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
680 ICSState
*ics
= spapr
->ics
;
686 * MSIMesage::data is used for storing VIRQ so
687 * it has to be aligned to num to support multiple
688 * MSI vectors. MSI-X is not affected by this.
689 * The hint is used for the first IRQ, the rest should
690 * be allocated continuously.
693 assert((num
== 1) || (num
== 2) || (num
== 4) ||
694 (num
== 8) || (num
== 16) || (num
== 32));
695 first
= ics_find_free_block(ics
, num
, num
);
697 first
= ics_find_free_block(ics
, num
, 1);
701 error_setg(errp
, "can't find a free %d-IRQ block", num
);
705 return first
+ ics
->offset
;
708 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
710 SpaprIrq spapr_irq_xics_legacy
= {
711 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
712 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
716 .print_info
= spapr_irq_print_info_xics
,
717 .dt_populate
= spapr_dt_xics
,
718 .post_load
= spapr_irq_post_load_xics
,
719 .reset
= spapr_irq_reset_xics
,
720 .init_kvm
= spapr_irq_init_kvm_xics
,
723 static void spapr_irq_register_types(void)
725 type_register_static(&spapr_intc_info
);
728 type_init(spapr_irq_register_types
)