target-sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "cpu.h"
  24 #include "qemu-common.h"
  25 #include "migration/vmstate.h"
  26
  27
  28 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     SuperHCPU *cpu = SUPERH_CPU(cs);
  31
  32     cpu->env.pc = value;
  33 }
  34
  35 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  36 {
  37     SuperHCPU *cpu = SUPERH_CPU(cs);
  38
  39     cpu->env.pc = tb->pc;
  40     cpu->env.flags = tb->flags;
  41 }
  42
  43 static bool superh_cpu_has_work(CPUState *cs)
  44 {
  45     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  46 }
  47
  48 /* CPUClass::reset() */
  49 static void superh_cpu_reset(CPUState *s)
  50 {
  51     SuperHCPU *cpu = SUPERH_CPU(s);
  52     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  53     CPUSH4State *env = &cpu->env;
  54
  55     scc->parent_reset(s);
  56
  57     memset(env, 0, offsetof(CPUSH4State, id));
  58     tlb_flush(s, 1);
  59
  60     env->pc = 0xA0000000;
  61 #if defined(CONFIG_USER_ONLY)
  62     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  63     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  64 #else
  65     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  66               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  67     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  68     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  69     set_flush_to_zero(1, &env->fp_status);
  70 #endif
  71     set_default_nan_mode(1, &env->fp_status);
  72 }
  73
  74 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  75 {
  76     info->mach = bfd_mach_sh4;
  77     info->print_insn = print_insn_sh;
  78 }
  79
  80 typedef struct SuperHCPUListState {
  81     fprintf_function cpu_fprintf;
  82     FILE *file;
  83 } SuperHCPUListState;
  84
  85 /* Sort alphabetically by type name. */
  86 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
  87 {
  88     ObjectClass *class_a = (ObjectClass *)a;
  89     ObjectClass *class_b = (ObjectClass *)b;
  90     const char *name_a, *name_b;
  91
  92     name_a = object_class_get_name(class_a);
  93     name_b = object_class_get_name(class_b);
  94     return strcmp(name_a, name_b);
  95 }
  96
  97 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
  98 {
  99     ObjectClass *oc = data;
 100     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 101     SuperHCPUListState *s = user_data;
 102
 103     (*s->cpu_fprintf)(s->file, "%s\n",
 104                       scc->name);
 105 }
 106
 107 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 108 {
 109     SuperHCPUListState s = {
 110         .cpu_fprintf = cpu_fprintf,
 111         .file = f,
 112     };
 113     GSList *list;
 114
 115     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 116     list = g_slist_sort(list, superh_cpu_list_compare);
 117     g_slist_foreach(list, superh_cpu_list_entry, &s);
 118     g_slist_free(list);
 119 }
 120
 121 static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
 122 {
 123     const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
 124     const char *name = b;
 125
 126     return strcasecmp(scc->name, name);
 127 }
 128
 129 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 130 {
 131     ObjectClass *oc;
 132     GSList *list, *item;
 133
 134     if (cpu_model == NULL) {
 135         return NULL;
 136     }
 137     if (strcasecmp(cpu_model, "any") == 0) {
 138         return object_class_by_name(TYPE_SH7750R_CPU);
 139     }
 140
 141     oc = object_class_by_name(cpu_model);
 142     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
 143         && !object_class_is_abstract(oc)) {
 144         return oc;
 145     }
 146
 147     oc = NULL;
 148     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 149     item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
 150     if (item != NULL) {
 151         oc = item->data;
 152     }
 153     g_slist_free(list);
 154     return oc;
 155 }
 156
 157 SuperHCPU *cpu_sh4_init(const char *cpu_model)
 158 {
 159     return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
 160 }
 161
 162 static void sh7750r_cpu_initfn(Object *obj)
 163 {
 164     SuperHCPU *cpu = SUPERH_CPU(obj);
 165     CPUSH4State *env = &cpu->env;
 166
 167     env->id = SH_CPU_SH7750R;
 168     env->features = SH_FEATURE_BCR3_AND_BCR4;
 169 }
 170
 171 static void sh7750r_class_init(ObjectClass *oc, void *data)
 172 {
 173     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 174
 175     scc->name = "SH7750R";
 176     scc->pvr = 0x00050000;
 177     scc->prr = 0x00000100;
 178     scc->cvr = 0x00110000;
 179 }
 180
 181 static const TypeInfo sh7750r_type_info = {
 182     .name = TYPE_SH7750R_CPU,
 183     .parent = TYPE_SUPERH_CPU,
 184     .class_init = sh7750r_class_init,
 185     .instance_init = sh7750r_cpu_initfn,
 186 };
 187
 188 static void sh7751r_cpu_initfn(Object *obj)
 189 {
 190     SuperHCPU *cpu = SUPERH_CPU(obj);
 191     CPUSH4State *env = &cpu->env;
 192
 193     env->id = SH_CPU_SH7751R;
 194     env->features = SH_FEATURE_BCR3_AND_BCR4;
 195 }
 196
 197 static void sh7751r_class_init(ObjectClass *oc, void *data)
 198 {
 199     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 200
 201     scc->name = "SH7751R";
 202     scc->pvr = 0x04050005;
 203     scc->prr = 0x00000113;
 204     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 205 }
 206
 207 static const TypeInfo sh7751r_type_info = {
 208     .name = TYPE_SH7751R_CPU,
 209     .parent = TYPE_SUPERH_CPU,
 210     .class_init = sh7751r_class_init,
 211     .instance_init = sh7751r_cpu_initfn,
 212 };
 213
 214 static void sh7785_cpu_initfn(Object *obj)
 215 {
 216     SuperHCPU *cpu = SUPERH_CPU(obj);
 217     CPUSH4State *env = &cpu->env;
 218
 219     env->id = SH_CPU_SH7785;
 220     env->features = SH_FEATURE_SH4A;
 221 }
 222
 223 static void sh7785_class_init(ObjectClass *oc, void *data)
 224 {
 225     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 226
 227     scc->name = "SH7785";
 228     scc->pvr = 0x10300700;
 229     scc->prr = 0x00000200;
 230     scc->cvr = 0x71440211;
 231 }
 232
 233 static const TypeInfo sh7785_type_info = {
 234     .name = TYPE_SH7785_CPU,
 235     .parent = TYPE_SUPERH_CPU,
 236     .class_init = sh7785_class_init,
 237     .instance_init = sh7785_cpu_initfn,
 238 };
 239
 240 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 241 {
 242     CPUState *cs = CPU(dev);
 243     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 244
 245     cpu_reset(cs);
 246     qemu_init_vcpu(cs);
 247
 248     scc->parent_realize(dev, errp);
 249 }
 250
 251 static void superh_cpu_initfn(Object *obj)
 252 {
 253     CPUState *cs = CPU(obj);
 254     SuperHCPU *cpu = SUPERH_CPU(obj);
 255     CPUSH4State *env = &cpu->env;
 256
 257     cs->env_ptr = env;
 258     cpu_exec_init(cs, &error_abort);
 259
 260     env->movcal_backup_tail = &(env->movcal_backup);
 261
 262     if (tcg_enabled()) {
 263         sh4_translate_init();
 264     }
 265 }
 266
 267 static const VMStateDescription vmstate_sh_cpu = {
 268     .name = "cpu",
 269     .unmigratable = 1,
 270 };
 271
 272 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 273 {
 274     DeviceClass *dc = DEVICE_CLASS(oc);
 275     CPUClass *cc = CPU_CLASS(oc);
 276     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 277
 278     scc->parent_realize = dc->realize;
 279     dc->realize = superh_cpu_realizefn;
 280
 281     scc->parent_reset = cc->reset;
 282     cc->reset = superh_cpu_reset;
 283
 284     cc->class_by_name = superh_cpu_class_by_name;
 285     cc->has_work = superh_cpu_has_work;
 286     cc->do_interrupt = superh_cpu_do_interrupt;
 287     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 288     cc->dump_state = superh_cpu_dump_state;
 289     cc->set_pc = superh_cpu_set_pc;
 290     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 291     cc->gdb_read_register = superh_cpu_gdb_read_register;
 292     cc->gdb_write_register = superh_cpu_gdb_write_register;
 293 #ifdef CONFIG_USER_ONLY
 294     cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
 295 #else
 296     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 297 #endif
 298     cc->disas_set_info = superh_cpu_disas_set_info;
 299
 300     cc->gdb_num_core_regs = 59;
 301
 302     dc->vmsd = &vmstate_sh_cpu;
 303
 304     /*
 305      * Reason: superh_cpu_initfn() calls cpu_exec_init(), which saves
 306      * the object in cpus -> dangling pointer after final
 307      * object_unref().
 308      */
 309     dc->cannot_destroy_with_object_finalize_yet = true;
 310 }
 311
 312 static const TypeInfo superh_cpu_type_info = {
 313     .name = TYPE_SUPERH_CPU,
 314     .parent = TYPE_CPU,
 315     .instance_size = sizeof(SuperHCPU),
 316     .instance_init = superh_cpu_initfn,
 317     .abstract = true,
 318     .class_size = sizeof(SuperHCPUClass),
 319     .class_init = superh_cpu_class_init,
 320 };
 321
 322 static void superh_cpu_register_types(void)
 323 {
 324     type_register_static(&superh_cpu_type_info);
 325     type_register_static(&sh7750r_type_info);
 326     type_register_static(&sh7751r_type_info);
 327     type_register_static(&sh7785_type_info);
 328 }
 329
 330 type_init(superh_cpu_register_types)