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target-ppc: Use the new deposit and extract ops
[qemu/ar7.git] / target / ppc / translate.c
blob435c6f0c637e5c8fe657a50e22e1683551f6d036
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
75 static TCGv cpu_reserve;
76 static TCGv cpu_fpscr;
77 static TCGv_i32 cpu_access_type;
78
79 #include "exec/gen-icount.h"
80
81 void ppc_translate_init(void)
82 {
83 int i;
84 char* p;
85 size_t cpu_reg_names_size;
86 static int done_init = 0;
87
88 if (done_init)
89 return;
90
91 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
92 tcg_ctx.tcg_env = cpu_env;
93
94 p = cpu_reg_names;
95 cpu_reg_names_size = sizeof(cpu_reg_names);
96
97 for (i = 0; i < 8; i++) {
98 snprintf(p, cpu_reg_names_size, "crf%d", i);
99 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
100 offsetof(CPUPPCState, crf[i]), p);
101 p += 5;
102 cpu_reg_names_size -= 5;
103 }
104
105 for (i = 0; i < 32; i++) {
106 snprintf(p, cpu_reg_names_size, "r%d", i);
107 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
108 offsetof(CPUPPCState, gpr[i]), p);
109 p += (i < 10) ? 3 : 4;
110 cpu_reg_names_size -= (i < 10) ? 3 : 4;
111 snprintf(p, cpu_reg_names_size, "r%dH", i);
112 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
113 offsetof(CPUPPCState, gprh[i]), p);
114 p += (i < 10) ? 4 : 5;
115 cpu_reg_names_size -= (i < 10) ? 4 : 5;
116
117 snprintf(p, cpu_reg_names_size, "fp%d", i);
118 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
119 offsetof(CPUPPCState, fpr[i]), p);
120 p += (i < 10) ? 4 : 5;
121 cpu_reg_names_size -= (i < 10) ? 4 : 5;
122
123 snprintf(p, cpu_reg_names_size, "avr%dH", i);
124 #ifdef HOST_WORDS_BIGENDIAN
125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
126 offsetof(CPUPPCState, avr[i].u64[0]), p);
127 #else
128 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
129 offsetof(CPUPPCState, avr[i].u64[1]), p);
130 #endif
131 p += (i < 10) ? 6 : 7;
132 cpu_reg_names_size -= (i < 10) ? 6 : 7;
133
134 snprintf(p, cpu_reg_names_size, "avr%dL", i);
135 #ifdef HOST_WORDS_BIGENDIAN
136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
137 offsetof(CPUPPCState, avr[i].u64[1]), p);
138 #else
139 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
140 offsetof(CPUPPCState, avr[i].u64[0]), p);
141 #endif
142 p += (i < 10) ? 6 : 7;
143 cpu_reg_names_size -= (i < 10) ? 6 : 7;
144 snprintf(p, cpu_reg_names_size, "vsr%d", i);
145 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
146 offsetof(CPUPPCState, vsr[i]), p);
147 p += (i < 10) ? 5 : 6;
148 cpu_reg_names_size -= (i < 10) ? 5 : 6;
149 }
150
151 cpu_nip = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, nip), "nip");
153
154 cpu_msr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, msr), "msr");
156
157 cpu_ctr = tcg_global_mem_new(cpu_env,
158 offsetof(CPUPPCState, ctr), "ctr");
159
160 cpu_lr = tcg_global_mem_new(cpu_env,
161 offsetof(CPUPPCState, lr), "lr");
162
163 #if defined(TARGET_PPC64)
164 cpu_cfar = tcg_global_mem_new(cpu_env,
165 offsetof(CPUPPCState, cfar), "cfar");
166 #endif
167
168 cpu_xer = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, xer), "xer");
170 cpu_so = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, so), "SO");
172 cpu_ov = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ov), "OV");
174 cpu_ca = tcg_global_mem_new(cpu_env,
175 offsetof(CPUPPCState, ca), "CA");
176
177 cpu_reserve = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, reserve_addr),
179 "reserve_addr");
180
181 cpu_fpscr = tcg_global_mem_new(cpu_env,
182 offsetof(CPUPPCState, fpscr), "fpscr");
183
184 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
185 offsetof(CPUPPCState, access_type), "access_type");
186
187 done_init = 1;
188 }
189
190 /* internal defines */
191 struct DisasContext {
192 struct TranslationBlock *tb;
193 target_ulong nip;
194 uint32_t opcode;
195 uint32_t exception;
196 /* Routine used to access memory */
197 bool pr, hv, dr, le_mode;
198 bool lazy_tlb_flush;
199 bool need_access_type;
200 int mem_idx;
201 int access_type;
202 /* Translation flags */
203 TCGMemOp default_tcg_memop_mask;
204 #if defined(TARGET_PPC64)
205 bool sf_mode;
206 bool has_cfar;
207 #endif
208 bool fpu_enabled;
209 bool altivec_enabled;
210 bool vsx_enabled;
211 bool spe_enabled;
212 bool tm_enabled;
213 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
214 int singlestep_enabled;
215 uint64_t insns_flags;
216 uint64_t insns_flags2;
217 };
218
219 /* Return true iff byteswap is needed in a scalar memop */
220 static inline bool need_byteswap(const DisasContext *ctx)
221 {
222 #if defined(TARGET_WORDS_BIGENDIAN)
223 return ctx->le_mode;
224 #else
225 return !ctx->le_mode;
226 #endif
227 }
228
229 /* True when active word size < size of target_long. */
230 #ifdef TARGET_PPC64
231 # define NARROW_MODE(C) (!(C)->sf_mode)
232 #else
233 # define NARROW_MODE(C) 0
234 #endif
235
236 struct opc_handler_t {
237 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238 uint32_t inval1;
239 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240 uint32_t inval2;
241 /* instruction type */
242 uint64_t type;
243 /* extended instruction type */
244 uint64_t type2;
245 /* handler */
246 void (*handler)(DisasContext *ctx);
247 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248 const char *oname;
249 #endif
250 #if defined(DO_PPC_STATISTICS)
251 uint64_t count;
252 #endif
253 };
254
255 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
256 {
257 if (ctx->need_access_type && ctx->access_type != access_type) {
258 tcg_gen_movi_i32(cpu_access_type, access_type);
259 ctx->access_type = access_type;
260 }
261 }
262
263 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
264 {
265 if (NARROW_MODE(ctx)) {
266 nip = (uint32_t)nip;
267 }
268 tcg_gen_movi_tl(cpu_nip, nip);
269 }
270
271 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274
275 /* These are all synchronous exceptions, we set the PC back to
276 * the faulting instruction
277 */
278 if (ctx->exception == POWERPC_EXCP_NONE) {
279 gen_update_nip(ctx, ctx->nip - 4);
280 }
281 t0 = tcg_const_i32(excp);
282 t1 = tcg_const_i32(error);
283 gen_helper_raise_exception_err(cpu_env, t0, t1);
284 tcg_temp_free_i32(t0);
285 tcg_temp_free_i32(t1);
286 ctx->exception = (excp);
287 }
288
289 static void gen_exception(DisasContext *ctx, uint32_t excp)
290 {
291 TCGv_i32 t0;
292
293 /* These are all synchronous exceptions, we set the PC back to
294 * the faulting instruction
295 */
296 if (ctx->exception == POWERPC_EXCP_NONE) {
297 gen_update_nip(ctx, ctx->nip - 4);
298 }
299 t0 = tcg_const_i32(excp);
300 gen_helper_raise_exception(cpu_env, t0);
301 tcg_temp_free_i32(t0);
302 ctx->exception = (excp);
303 }
304
305 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
306 target_ulong nip)
307 {
308 TCGv_i32 t0;
309
310 gen_update_nip(ctx, nip);
311 t0 = tcg_const_i32(excp);
312 gen_helper_raise_exception(cpu_env, t0);
313 tcg_temp_free_i32(t0);
314 ctx->exception = (excp);
315 }
316
317 static void gen_debug_exception(DisasContext *ctx)
318 {
319 TCGv_i32 t0;
320
321 /* These are all synchronous exceptions, we set the PC back to
322 * the faulting instruction
323 */
324 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
325 (ctx->exception != POWERPC_EXCP_SYNC)) {
326 gen_update_nip(ctx, ctx->nip);
327 }
328 t0 = tcg_const_i32(EXCP_DEBUG);
329 gen_helper_raise_exception(cpu_env, t0);
330 tcg_temp_free_i32(t0);
331 }
332
333 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
334 {
335 /* Will be converted to program check if needed */
336 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
337 }
338
339 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
340 {
341 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
342 }
343
344 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
345 {
346 /* Will be converted to program check if needed */
347 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
348 }
349
350 /* Stop translation */
351 static inline void gen_stop_exception(DisasContext *ctx)
352 {
353 gen_update_nip(ctx, ctx->nip);
354 ctx->exception = POWERPC_EXCP_STOP;
355 }
356
357 #ifndef CONFIG_USER_ONLY
358 /* No need to update nip here, as execution flow will change */
359 static inline void gen_sync_exception(DisasContext *ctx)
360 {
361 ctx->exception = POWERPC_EXCP_SYNC;
362 }
363 #endif
364
365 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
366 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
367
368 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
369 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
370
371 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
372 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
373
374 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
375 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
376
377 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
378 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
379
380 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
381 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
382
383 typedef struct opcode_t {
384 unsigned char opc1, opc2, opc3, opc4;
385 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
386 unsigned char pad[4];
387 #endif
388 opc_handler_t handler;
389 const char *oname;
390 } opcode_t;
391
392 /* Helpers for priv. check */
393 #define GEN_PRIV \
394 do { \
395 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
396 } while (0)
397
398 #if defined(CONFIG_USER_ONLY)
399 #define CHK_HV GEN_PRIV
400 #define CHK_SV GEN_PRIV
401 #define CHK_HVRM GEN_PRIV
402 #else
403 #define CHK_HV \
404 do { \
405 if (unlikely(ctx->pr || !ctx->hv)) { \
406 GEN_PRIV; \
407 } \
408 } while (0)
409 #define CHK_SV \
410 do { \
411 if (unlikely(ctx->pr)) { \
412 GEN_PRIV; \
413 } \
414 } while (0)
415 #define CHK_HVRM \
416 do { \
417 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
418 GEN_PRIV; \
419 } \
420 } while (0)
421 #endif
422
423 #define CHK_NONE
424
425
426 /*****************************************************************************/
427 /*** Instruction decoding ***/
428 #define EXTRACT_HELPER(name, shift, nb) \
429 static inline uint32_t name(uint32_t opcode) \
430 { \
431 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
432 }
433
434 #define EXTRACT_SHELPER(name, shift, nb) \
435 static inline int32_t name(uint32_t opcode) \
436 { \
437 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
438 }
439
440 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
441 static inline uint32_t name(uint32_t opcode) \
442 { \
443 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
444 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
445 }
446
447 #define EXTRACT_HELPER_DXFORM(name, \
448 d0_bits, shift_op_d0, shift_d0, \
449 d1_bits, shift_op_d1, shift_d1, \
450 d2_bits, shift_op_d2, shift_d2) \
451 static inline int16_t name(uint32_t opcode) \
452 { \
453 return \
454 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
455 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
456 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
457 }
458
459
460 /* Opcode part 1 */
461 EXTRACT_HELPER(opc1, 26, 6);
462 /* Opcode part 2 */
463 EXTRACT_HELPER(opc2, 1, 5);
464 /* Opcode part 3 */
465 EXTRACT_HELPER(opc3, 6, 5);
466 /* Opcode part 4 */
467 EXTRACT_HELPER(opc4, 16, 5);
468 /* Update Cr0 flags */
469 EXTRACT_HELPER(Rc, 0, 1);
470 /* Update Cr6 flags (Altivec) */
471 EXTRACT_HELPER(Rc21, 10, 1);
472 /* Destination */
473 EXTRACT_HELPER(rD, 21, 5);
474 /* Source */
475 EXTRACT_HELPER(rS, 21, 5);
476 /* First operand */
477 EXTRACT_HELPER(rA, 16, 5);
478 /* Second operand */
479 EXTRACT_HELPER(rB, 11, 5);
480 /* Third operand */
481 EXTRACT_HELPER(rC, 6, 5);
482 /*** Get CRn ***/
483 EXTRACT_HELPER(crfD, 23, 3);
484 EXTRACT_HELPER(crfS, 18, 3);
485 EXTRACT_HELPER(crbD, 21, 5);
486 EXTRACT_HELPER(crbA, 16, 5);
487 EXTRACT_HELPER(crbB, 11, 5);
488 /* SPR / TBL */
489 EXTRACT_HELPER(_SPR, 11, 10);
490 static inline uint32_t SPR(uint32_t opcode)
491 {
492 uint32_t sprn = _SPR(opcode);
493
494 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
495 }
496 /*** Get constants ***/
497 /* 16 bits signed immediate value */
498 EXTRACT_SHELPER(SIMM, 0, 16);
499 /* 16 bits unsigned immediate value */
500 EXTRACT_HELPER(UIMM, 0, 16);
501 /* 5 bits signed immediate value */
502 EXTRACT_HELPER(SIMM5, 16, 5);
503 /* 5 bits signed immediate value */
504 EXTRACT_HELPER(UIMM5, 16, 5);
505 /* 4 bits unsigned immediate value */
506 EXTRACT_HELPER(UIMM4, 16, 4);
507 /* Bit count */
508 EXTRACT_HELPER(NB, 11, 5);
509 /* Shift count */
510 EXTRACT_HELPER(SH, 11, 5);
511 /* Vector shift count */
512 EXTRACT_HELPER(VSH, 6, 4);
513 /* Mask start */
514 EXTRACT_HELPER(MB, 6, 5);
515 /* Mask end */
516 EXTRACT_HELPER(ME, 1, 5);
517 /* Trap operand */
518 EXTRACT_HELPER(TO, 21, 5);
519
520 EXTRACT_HELPER(CRM, 12, 8);
521
522 #ifndef CONFIG_USER_ONLY
523 EXTRACT_HELPER(SR, 16, 4);
524 #endif
525
526 /* mtfsf/mtfsfi */
527 EXTRACT_HELPER(FPBF, 23, 3);
528 EXTRACT_HELPER(FPIMM, 12, 4);
529 EXTRACT_HELPER(FPL, 25, 1);
530 EXTRACT_HELPER(FPFLM, 17, 8);
531 EXTRACT_HELPER(FPW, 16, 1);
532
533 /* addpcis */
534 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
535 #if defined(TARGET_PPC64)
536 /* darn */
537 EXTRACT_HELPER(L, 16, 2);
538 #endif
539
540 /*** Jump target decoding ***/
541 /* Immediate address */
542 static inline target_ulong LI(uint32_t opcode)
543 {
544 return (opcode >> 0) & 0x03FFFFFC;
545 }
546
547 static inline uint32_t BD(uint32_t opcode)
548 {
549 return (opcode >> 0) & 0xFFFC;
550 }
551
552 EXTRACT_HELPER(BO, 21, 5);
553 EXTRACT_HELPER(BI, 16, 5);
554 /* Absolute/relative address */
555 EXTRACT_HELPER(AA, 1, 1);
556 /* Link */
557 EXTRACT_HELPER(LK, 0, 1);
558
559 /* DFP Z22-form */
560 EXTRACT_HELPER(DCM, 10, 6)
561
562 /* DFP Z23-form */
563 EXTRACT_HELPER(RMC, 9, 2)
564
565 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
566 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
567 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
568 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
569 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
570 EXTRACT_HELPER(DM, 8, 2);
571 EXTRACT_HELPER(UIM, 16, 2);
572 EXTRACT_HELPER(SHW, 8, 2);
573 EXTRACT_HELPER(SP, 19, 2);
574 EXTRACT_HELPER(IMM8, 11, 8);
575
576 /*****************************************************************************/
577 /* PowerPC instructions table */
578
579 #if defined(DO_PPC_STATISTICS)
580 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
581 { \
582 .opc1 = op1, \
583 .opc2 = op2, \
584 .opc3 = op3, \
585 .opc4 = 0xff, \
586 .handler = { \
587 .inval1 = invl, \
588 .type = _typ, \
589 .type2 = _typ2, \
590 .handler = &gen_##name, \
591 .oname = stringify(name), \
592 }, \
593 .oname = stringify(name), \
594 }
595 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
596 { \
597 .opc1 = op1, \
598 .opc2 = op2, \
599 .opc3 = op3, \
600 .opc4 = 0xff, \
601 .handler = { \
602 .inval1 = invl1, \
603 .inval2 = invl2, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 .oname = stringify(name), \
608 }, \
609 .oname = stringify(name), \
610 }
611 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
612 { \
613 .opc1 = op1, \
614 .opc2 = op2, \
615 .opc3 = op3, \
616 .opc4 = 0xff, \
617 .handler = { \
618 .inval1 = invl, \
619 .type = _typ, \
620 .type2 = _typ2, \
621 .handler = &gen_##name, \
622 .oname = onam, \
623 }, \
624 .oname = onam, \
625 }
626 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
627 { \
628 .opc1 = op1, \
629 .opc2 = op2, \
630 .opc3 = op3, \
631 .opc4 = op4, \
632 .handler = { \
633 .inval1 = invl, \
634 .type = _typ, \
635 .type2 = _typ2, \
636 .handler = &gen_##name, \
637 .oname = stringify(name), \
638 }, \
639 .oname = stringify(name), \
640 }
641 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
642 { \
643 .opc1 = op1, \
644 .opc2 = op2, \
645 .opc3 = op3, \
646 .opc4 = op4, \
647 .handler = { \
648 .inval1 = invl, \
649 .type = _typ, \
650 .type2 = _typ2, \
651 .handler = &gen_##name, \
652 .oname = onam, \
653 }, \
654 .oname = onam, \
655 }
656 #else
657 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
658 { \
659 .opc1 = op1, \
660 .opc2 = op2, \
661 .opc3 = op3, \
662 .opc4 = 0xff, \
663 .handler = { \
664 .inval1 = invl, \
665 .type = _typ, \
666 .type2 = _typ2, \
667 .handler = &gen_##name, \
668 }, \
669 .oname = stringify(name), \
670 }
671 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
672 { \
673 .opc1 = op1, \
674 .opc2 = op2, \
675 .opc3 = op3, \
676 .opc4 = 0xff, \
677 .handler = { \
678 .inval1 = invl1, \
679 .inval2 = invl2, \
680 .type = _typ, \
681 .type2 = _typ2, \
682 .handler = &gen_##name, \
683 }, \
684 .oname = stringify(name), \
685 }
686 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
687 { \
688 .opc1 = op1, \
689 .opc2 = op2, \
690 .opc3 = op3, \
691 .opc4 = 0xff, \
692 .handler = { \
693 .inval1 = invl, \
694 .type = _typ, \
695 .type2 = _typ2, \
696 .handler = &gen_##name, \
697 }, \
698 .oname = onam, \
699 }
700 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
701 { \
702 .opc1 = op1, \
703 .opc2 = op2, \
704 .opc3 = op3, \
705 .opc4 = op4, \
706 .handler = { \
707 .inval1 = invl, \
708 .type = _typ, \
709 .type2 = _typ2, \
710 .handler = &gen_##name, \
711 }, \
712 .oname = stringify(name), \
713 }
714 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
715 { \
716 .opc1 = op1, \
717 .opc2 = op2, \
718 .opc3 = op3, \
719 .opc4 = op4, \
720 .handler = { \
721 .inval1 = invl, \
722 .type = _typ, \
723 .type2 = _typ2, \
724 .handler = &gen_##name, \
725 }, \
726 .oname = onam, \
727 }
728 #endif
729
730 /* SPR load/store helpers */
731 static inline void gen_load_spr(TCGv t, int reg)
732 {
733 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
734 }
735
736 static inline void gen_store_spr(int reg, TCGv t)
737 {
738 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
739 }
740
741 /* Invalid instruction */
742 static void gen_invalid(DisasContext *ctx)
743 {
744 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
745 }
746
747 static opc_handler_t invalid_handler = {
748 .inval1 = 0xFFFFFFFF,
749 .inval2 = 0xFFFFFFFF,
750 .type = PPC_NONE,
751 .type2 = PPC_NONE,
752 .handler = gen_invalid,
753 };
754
755 /*** Integer comparison ***/
756
757 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
758 {
759 TCGv t0 = tcg_temp_new();
760 TCGv_i32 t1 = tcg_temp_new_i32();
761
762 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
763
764 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
765 tcg_gen_trunc_tl_i32(t1, t0);
766 tcg_gen_shli_i32(t1, t1, CRF_LT);
767 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
768
769 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
770 tcg_gen_trunc_tl_i32(t1, t0);
771 tcg_gen_shli_i32(t1, t1, CRF_GT);
772 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
773
774 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
775 tcg_gen_trunc_tl_i32(t1, t0);
776 tcg_gen_shli_i32(t1, t1, CRF_EQ);
777 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
778
779 tcg_temp_free(t0);
780 tcg_temp_free_i32(t1);
781 }
782
783 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
784 {
785 TCGv t0 = tcg_const_tl(arg1);
786 gen_op_cmp(arg0, t0, s, crf);
787 tcg_temp_free(t0);
788 }
789
790 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
791 {
792 TCGv t0, t1;
793 t0 = tcg_temp_new();
794 t1 = tcg_temp_new();
795 if (s) {
796 tcg_gen_ext32s_tl(t0, arg0);
797 tcg_gen_ext32s_tl(t1, arg1);
798 } else {
799 tcg_gen_ext32u_tl(t0, arg0);
800 tcg_gen_ext32u_tl(t1, arg1);
801 }
802 gen_op_cmp(t0, t1, s, crf);
803 tcg_temp_free(t1);
804 tcg_temp_free(t0);
805 }
806
807 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
808 {
809 TCGv t0 = tcg_const_tl(arg1);
810 gen_op_cmp32(arg0, t0, s, crf);
811 tcg_temp_free(t0);
812 }
813
814 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
815 {
816 if (NARROW_MODE(ctx)) {
817 gen_op_cmpi32(reg, 0, 1, 0);
818 } else {
819 gen_op_cmpi(reg, 0, 1, 0);
820 }
821 }
822
823 /* cmp */
824 static void gen_cmp(DisasContext *ctx)
825 {
826 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
827 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
828 1, crfD(ctx->opcode));
829 } else {
830 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
831 1, crfD(ctx->opcode));
832 }
833 }
834
835 /* cmpi */
836 static void gen_cmpi(DisasContext *ctx)
837 {
838 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
839 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
840 1, crfD(ctx->opcode));
841 } else {
842 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
843 1, crfD(ctx->opcode));
844 }
845 }
846
847 /* cmpl */
848 static void gen_cmpl(DisasContext *ctx)
849 {
850 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
851 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
852 0, crfD(ctx->opcode));
853 } else {
854 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
855 0, crfD(ctx->opcode));
856 }
857 }
858
859 /* cmpli */
860 static void gen_cmpli(DisasContext *ctx)
861 {
862 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
863 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
864 0, crfD(ctx->opcode));
865 } else {
866 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
867 0, crfD(ctx->opcode));
868 }
869 }
870
871 /* cmprb - range comparison: isupper, isaplha, islower*/
872 static void gen_cmprb(DisasContext *ctx)
873 {
874 TCGv_i32 src1 = tcg_temp_new_i32();
875 TCGv_i32 src2 = tcg_temp_new_i32();
876 TCGv_i32 src2lo = tcg_temp_new_i32();
877 TCGv_i32 src2hi = tcg_temp_new_i32();
878 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
879
880 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
881 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
882
883 tcg_gen_andi_i32(src1, src1, 0xFF);
884 tcg_gen_ext8u_i32(src2lo, src2);
885 tcg_gen_shri_i32(src2, src2, 8);
886 tcg_gen_ext8u_i32(src2hi, src2);
887
888 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
889 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
890 tcg_gen_and_i32(crf, src2lo, src2hi);
891
892 if (ctx->opcode & 0x00200000) {
893 tcg_gen_shri_i32(src2, src2, 8);
894 tcg_gen_ext8u_i32(src2lo, src2);
895 tcg_gen_shri_i32(src2, src2, 8);
896 tcg_gen_ext8u_i32(src2hi, src2);
897 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
898 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
899 tcg_gen_and_i32(src2lo, src2lo, src2hi);
900 tcg_gen_or_i32(crf, crf, src2lo);
901 }
902 tcg_gen_shli_i32(crf, crf, CRF_GT);
903 tcg_temp_free_i32(src1);
904 tcg_temp_free_i32(src2);
905 tcg_temp_free_i32(src2lo);
906 tcg_temp_free_i32(src2hi);
907 }
908
909 #if defined(TARGET_PPC64)
910 /* cmpeqb */
911 static void gen_cmpeqb(DisasContext *ctx)
912 {
913 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
914 cpu_gpr[rB(ctx->opcode)]);
915 }
916 #endif
917
918 /* isel (PowerPC 2.03 specification) */
919 static void gen_isel(DisasContext *ctx)
920 {
921 uint32_t bi = rC(ctx->opcode);
922 uint32_t mask = 0x08 >> (bi & 0x03);
923 TCGv t0 = tcg_temp_new();
924 TCGv zr;
925
926 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
927 tcg_gen_andi_tl(t0, t0, mask);
928
929 zr = tcg_const_tl(0);
930 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
931 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
932 cpu_gpr[rB(ctx->opcode)]);
933 tcg_temp_free(zr);
934 tcg_temp_free(t0);
935 }
936
937 /* cmpb: PowerPC 2.05 specification */
938 static void gen_cmpb(DisasContext *ctx)
939 {
940 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
941 cpu_gpr[rB(ctx->opcode)]);
942 }
943
944 /*** Integer arithmetic ***/
945
946 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
947 TCGv arg1, TCGv arg2, int sub)
948 {
949 TCGv t0 = tcg_temp_new();
950
951 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
952 tcg_gen_xor_tl(t0, arg1, arg2);
953 if (sub) {
954 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
955 } else {
956 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
957 }
958 tcg_temp_free(t0);
959 if (NARROW_MODE(ctx)) {
960 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
961 }
962 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
963 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
964 }
965
966 /* Common add function */
967 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
968 TCGv arg2, bool add_ca, bool compute_ca,
969 bool compute_ov, bool compute_rc0)
970 {
971 TCGv t0 = ret;
972
973 if (compute_ca || compute_ov) {
974 t0 = tcg_temp_new();
975 }
976
977 if (compute_ca) {
978 if (NARROW_MODE(ctx)) {
979 /* Caution: a non-obvious corner case of the spec is that we
980 must produce the *entire* 64-bit addition, but produce the
981 carry into bit 32. */
982 TCGv t1 = tcg_temp_new();
983 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
984 tcg_gen_add_tl(t0, arg1, arg2);
985 if (add_ca) {
986 tcg_gen_add_tl(t0, t0, cpu_ca);
987 }
988 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
989 tcg_temp_free(t1);
990 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
991 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
992 } else {
993 TCGv zero = tcg_const_tl(0);
994 if (add_ca) {
995 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
996 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
997 } else {
998 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
999 }
1000 tcg_temp_free(zero);
1001 }
1002 } else {
1003 tcg_gen_add_tl(t0, arg1, arg2);
1004 if (add_ca) {
1005 tcg_gen_add_tl(t0, t0, cpu_ca);
1006 }
1007 }
1008
1009 if (compute_ov) {
1010 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1011 }
1012 if (unlikely(compute_rc0)) {
1013 gen_set_Rc0(ctx, t0);
1014 }
1015
1016 if (!TCGV_EQUAL(t0, ret)) {
1017 tcg_gen_mov_tl(ret, t0);
1018 tcg_temp_free(t0);
1019 }
1020 }
1021 /* Add functions with two operands */
1022 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1023 static void glue(gen_, name)(DisasContext *ctx) \
1024 { \
1025 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1026 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1027 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1028 }
1029 /* Add functions with one operand and one immediate */
1030 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1031 add_ca, compute_ca, compute_ov) \
1032 static void glue(gen_, name)(DisasContext *ctx) \
1033 { \
1034 TCGv t0 = tcg_const_tl(const_val); \
1035 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1036 cpu_gpr[rA(ctx->opcode)], t0, \
1037 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1038 tcg_temp_free(t0); \
1039 }
1040
1041 /* add add. addo addo. */
1042 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1043 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1044 /* addc addc. addco addco. */
1045 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1046 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1047 /* adde adde. addeo addeo. */
1048 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1049 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1050 /* addme addme. addmeo addmeo. */
1051 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1052 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1053 /* addze addze. addzeo addzeo.*/
1054 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1055 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1056 /* addi */
1057 static void gen_addi(DisasContext *ctx)
1058 {
1059 target_long simm = SIMM(ctx->opcode);
1060
1061 if (rA(ctx->opcode) == 0) {
1062 /* li case */
1063 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1064 } else {
1065 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1066 cpu_gpr[rA(ctx->opcode)], simm);
1067 }
1068 }
1069 /* addic addic.*/
1070 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1071 {
1072 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1073 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1074 c, 0, 1, 0, compute_rc0);
1075 tcg_temp_free(c);
1076 }
1077
1078 static void gen_addic(DisasContext *ctx)
1079 {
1080 gen_op_addic(ctx, 0);
1081 }
1082
1083 static void gen_addic_(DisasContext *ctx)
1084 {
1085 gen_op_addic(ctx, 1);
1086 }
1087
1088 /* addis */
1089 static void gen_addis(DisasContext *ctx)
1090 {
1091 target_long simm = SIMM(ctx->opcode);
1092
1093 if (rA(ctx->opcode) == 0) {
1094 /* lis case */
1095 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1096 } else {
1097 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1098 cpu_gpr[rA(ctx->opcode)], simm << 16);
1099 }
1100 }
1101
1102 /* addpcis */
1103 static void gen_addpcis(DisasContext *ctx)
1104 {
1105 target_long d = DX(ctx->opcode);
1106
1107 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1108 }
1109
1110 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1111 TCGv arg2, int sign, int compute_ov)
1112 {
1113 TCGv_i32 t0 = tcg_temp_new_i32();
1114 TCGv_i32 t1 = tcg_temp_new_i32();
1115 TCGv_i32 t2 = tcg_temp_new_i32();
1116 TCGv_i32 t3 = tcg_temp_new_i32();
1117
1118 tcg_gen_trunc_tl_i32(t0, arg1);
1119 tcg_gen_trunc_tl_i32(t1, arg2);
1120 if (sign) {
1121 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1122 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1123 tcg_gen_and_i32(t2, t2, t3);
1124 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1125 tcg_gen_or_i32(t2, t2, t3);
1126 tcg_gen_movi_i32(t3, 0);
1127 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1128 tcg_gen_div_i32(t3, t0, t1);
1129 tcg_gen_extu_i32_tl(ret, t3);
1130 } else {
1131 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1132 tcg_gen_movi_i32(t3, 0);
1133 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1134 tcg_gen_divu_i32(t3, t0, t1);
1135 tcg_gen_extu_i32_tl(ret, t3);
1136 }
1137 if (compute_ov) {
1138 tcg_gen_extu_i32_tl(cpu_ov, t2);
1139 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1140 }
1141 tcg_temp_free_i32(t0);
1142 tcg_temp_free_i32(t1);
1143 tcg_temp_free_i32(t2);
1144 tcg_temp_free_i32(t3);
1145
1146 if (unlikely(Rc(ctx->opcode) != 0))
1147 gen_set_Rc0(ctx, ret);
1148 }
1149 /* Div functions */
1150 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1151 static void glue(gen_, name)(DisasContext *ctx) \
1152 { \
1153 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1154 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1155 sign, compute_ov); \
1156 }
1157 /* divwu divwu. divwuo divwuo. */
1158 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1159 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1160 /* divw divw. divwo divwo. */
1161 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1162 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1163
1164 /* div[wd]eu[o][.] */
1165 #define GEN_DIVE(name, hlpr, compute_ov) \
1166 static void gen_##name(DisasContext *ctx) \
1167 { \
1168 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1169 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1171 tcg_temp_free_i32(t0); \
1172 if (unlikely(Rc(ctx->opcode) != 0)) { \
1173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1174 } \
1175 }
1176
1177 GEN_DIVE(divweu, divweu, 0);
1178 GEN_DIVE(divweuo, divweu, 1);
1179 GEN_DIVE(divwe, divwe, 0);
1180 GEN_DIVE(divweo, divwe, 1);
1181
1182 #if defined(TARGET_PPC64)
1183 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1184 TCGv arg2, int sign, int compute_ov)
1185 {
1186 TCGv_i64 t0 = tcg_temp_new_i64();
1187 TCGv_i64 t1 = tcg_temp_new_i64();
1188 TCGv_i64 t2 = tcg_temp_new_i64();
1189 TCGv_i64 t3 = tcg_temp_new_i64();
1190
1191 tcg_gen_mov_i64(t0, arg1);
1192 tcg_gen_mov_i64(t1, arg2);
1193 if (sign) {
1194 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1195 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1196 tcg_gen_and_i64(t2, t2, t3);
1197 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1198 tcg_gen_or_i64(t2, t2, t3);
1199 tcg_gen_movi_i64(t3, 0);
1200 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1201 tcg_gen_div_i64(ret, t0, t1);
1202 } else {
1203 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1204 tcg_gen_movi_i64(t3, 0);
1205 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1206 tcg_gen_divu_i64(ret, t0, t1);
1207 }
1208 if (compute_ov) {
1209 tcg_gen_mov_tl(cpu_ov, t2);
1210 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1211 }
1212 tcg_temp_free_i64(t0);
1213 tcg_temp_free_i64(t1);
1214 tcg_temp_free_i64(t2);
1215 tcg_temp_free_i64(t3);
1216
1217 if (unlikely(Rc(ctx->opcode) != 0))
1218 gen_set_Rc0(ctx, ret);
1219 }
1220
1221 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1222 static void glue(gen_, name)(DisasContext *ctx) \
1223 { \
1224 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1225 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1226 sign, compute_ov); \
1227 }
1228 /* divwu divwu. divwuo divwuo. */
1229 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1230 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1231 /* divw divw. divwo divwo. */
1232 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1233 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1234
1235 GEN_DIVE(divdeu, divdeu, 0);
1236 GEN_DIVE(divdeuo, divdeu, 1);
1237 GEN_DIVE(divde, divde, 0);
1238 GEN_DIVE(divdeo, divde, 1);
1239 #endif
1240
1241 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1242 TCGv arg2, int sign)
1243 {
1244 TCGv_i32 t0 = tcg_temp_new_i32();
1245 TCGv_i32 t1 = tcg_temp_new_i32();
1246
1247 tcg_gen_trunc_tl_i32(t0, arg1);
1248 tcg_gen_trunc_tl_i32(t1, arg2);
1249 if (sign) {
1250 TCGv_i32 t2 = tcg_temp_new_i32();
1251 TCGv_i32 t3 = tcg_temp_new_i32();
1252 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1253 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1254 tcg_gen_and_i32(t2, t2, t3);
1255 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1256 tcg_gen_or_i32(t2, t2, t3);
1257 tcg_gen_movi_i32(t3, 0);
1258 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1259 tcg_gen_rem_i32(t3, t0, t1);
1260 tcg_gen_ext_i32_tl(ret, t3);
1261 tcg_temp_free_i32(t2);
1262 tcg_temp_free_i32(t3);
1263 } else {
1264 TCGv_i32 t2 = tcg_const_i32(1);
1265 TCGv_i32 t3 = tcg_const_i32(0);
1266 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1267 tcg_gen_remu_i32(t3, t0, t1);
1268 tcg_gen_extu_i32_tl(ret, t3);
1269 tcg_temp_free_i32(t2);
1270 tcg_temp_free_i32(t3);
1271 }
1272 tcg_temp_free_i32(t0);
1273 tcg_temp_free_i32(t1);
1274 }
1275
1276 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1277 static void glue(gen_, name)(DisasContext *ctx) \
1278 { \
1279 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1280 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1281 sign); \
1282 }
1283
1284 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1285 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1286
1287 #if defined(TARGET_PPC64)
1288 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1289 TCGv arg2, int sign)
1290 {
1291 TCGv_i64 t0 = tcg_temp_new_i64();
1292 TCGv_i64 t1 = tcg_temp_new_i64();
1293
1294 tcg_gen_mov_i64(t0, arg1);
1295 tcg_gen_mov_i64(t1, arg2);
1296 if (sign) {
1297 TCGv_i64 t2 = tcg_temp_new_i64();
1298 TCGv_i64 t3 = tcg_temp_new_i64();
1299 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1300 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1301 tcg_gen_and_i64(t2, t2, t3);
1302 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1303 tcg_gen_or_i64(t2, t2, t3);
1304 tcg_gen_movi_i64(t3, 0);
1305 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1306 tcg_gen_rem_i64(ret, t0, t1);
1307 tcg_temp_free_i64(t2);
1308 tcg_temp_free_i64(t3);
1309 } else {
1310 TCGv_i64 t2 = tcg_const_i64(1);
1311 TCGv_i64 t3 = tcg_const_i64(0);
1312 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1313 tcg_gen_remu_i64(ret, t0, t1);
1314 tcg_temp_free_i64(t2);
1315 tcg_temp_free_i64(t3);
1316 }
1317 tcg_temp_free_i64(t0);
1318 tcg_temp_free_i64(t1);
1319 }
1320
1321 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1322 static void glue(gen_, name)(DisasContext *ctx) \
1323 { \
1324 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1325 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1326 sign); \
1327 }
1328
1329 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1330 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1331 #endif
1332
1333 /* mulhw mulhw. */
1334 static void gen_mulhw(DisasContext *ctx)
1335 {
1336 TCGv_i32 t0 = tcg_temp_new_i32();
1337 TCGv_i32 t1 = tcg_temp_new_i32();
1338
1339 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1340 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1341 tcg_gen_muls2_i32(t0, t1, t0, t1);
1342 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1343 tcg_temp_free_i32(t0);
1344 tcg_temp_free_i32(t1);
1345 if (unlikely(Rc(ctx->opcode) != 0))
1346 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1347 }
1348
1349 /* mulhwu mulhwu. */
1350 static void gen_mulhwu(DisasContext *ctx)
1351 {
1352 TCGv_i32 t0 = tcg_temp_new_i32();
1353 TCGv_i32 t1 = tcg_temp_new_i32();
1354
1355 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1356 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1357 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1358 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1359 tcg_temp_free_i32(t0);
1360 tcg_temp_free_i32(t1);
1361 if (unlikely(Rc(ctx->opcode) != 0))
1362 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1363 }
1364
1365 /* mullw mullw. */
1366 static void gen_mullw(DisasContext *ctx)
1367 {
1368 #if defined(TARGET_PPC64)
1369 TCGv_i64 t0, t1;
1370 t0 = tcg_temp_new_i64();
1371 t1 = tcg_temp_new_i64();
1372 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1373 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1374 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1375 tcg_temp_free(t0);
1376 tcg_temp_free(t1);
1377 #else
1378 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1379 cpu_gpr[rB(ctx->opcode)]);
1380 #endif
1381 if (unlikely(Rc(ctx->opcode) != 0))
1382 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1383 }
1384
1385 /* mullwo mullwo. */
1386 static void gen_mullwo(DisasContext *ctx)
1387 {
1388 TCGv_i32 t0 = tcg_temp_new_i32();
1389 TCGv_i32 t1 = tcg_temp_new_i32();
1390
1391 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1392 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1393 tcg_gen_muls2_i32(t0, t1, t0, t1);
1394 #if defined(TARGET_PPC64)
1395 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1396 #else
1397 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1398 #endif
1399
1400 tcg_gen_sari_i32(t0, t0, 31);
1401 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1402 tcg_gen_extu_i32_tl(cpu_ov, t0);
1403 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1404
1405 tcg_temp_free_i32(t0);
1406 tcg_temp_free_i32(t1);
1407 if (unlikely(Rc(ctx->opcode) != 0))
1408 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1409 }
1410
1411 /* mulli */
1412 static void gen_mulli(DisasContext *ctx)
1413 {
1414 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1415 SIMM(ctx->opcode));
1416 }
1417
1418 #if defined(TARGET_PPC64)
1419 /* mulhd mulhd. */
1420 static void gen_mulhd(DisasContext *ctx)
1421 {
1422 TCGv lo = tcg_temp_new();
1423 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1424 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1425 tcg_temp_free(lo);
1426 if (unlikely(Rc(ctx->opcode) != 0)) {
1427 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1428 }
1429 }
1430
1431 /* mulhdu mulhdu. */
1432 static void gen_mulhdu(DisasContext *ctx)
1433 {
1434 TCGv lo = tcg_temp_new();
1435 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1436 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1437 tcg_temp_free(lo);
1438 if (unlikely(Rc(ctx->opcode) != 0)) {
1439 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1440 }
1441 }
1442
1443 /* mulld mulld. */
1444 static void gen_mulld(DisasContext *ctx)
1445 {
1446 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1447 cpu_gpr[rB(ctx->opcode)]);
1448 if (unlikely(Rc(ctx->opcode) != 0))
1449 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1450 }
1451
1452 /* mulldo mulldo. */
1453 static void gen_mulldo(DisasContext *ctx)
1454 {
1455 TCGv_i64 t0 = tcg_temp_new_i64();
1456 TCGv_i64 t1 = tcg_temp_new_i64();
1457
1458 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1459 cpu_gpr[rB(ctx->opcode)]);
1460 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1461
1462 tcg_gen_sari_i64(t0, t0, 63);
1463 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1464 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1465
1466 tcg_temp_free_i64(t0);
1467 tcg_temp_free_i64(t1);
1468
1469 if (unlikely(Rc(ctx->opcode) != 0)) {
1470 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1471 }
1472 }
1473 #endif
1474
1475 /* Common subf function */
1476 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1477 TCGv arg2, bool add_ca, bool compute_ca,
1478 bool compute_ov, bool compute_rc0)
1479 {
1480 TCGv t0 = ret;
1481
1482 if (compute_ca || compute_ov) {
1483 t0 = tcg_temp_new();
1484 }
1485
1486 if (compute_ca) {
1487 /* dest = ~arg1 + arg2 [+ ca]. */
1488 if (NARROW_MODE(ctx)) {
1489 /* Caution: a non-obvious corner case of the spec is that we
1490 must produce the *entire* 64-bit addition, but produce the
1491 carry into bit 32. */
1492 TCGv inv1 = tcg_temp_new();
1493 TCGv t1 = tcg_temp_new();
1494 tcg_gen_not_tl(inv1, arg1);
1495 if (add_ca) {
1496 tcg_gen_add_tl(t0, arg2, cpu_ca);
1497 } else {
1498 tcg_gen_addi_tl(t0, arg2, 1);
1499 }
1500 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1501 tcg_gen_add_tl(t0, t0, inv1);
1502 tcg_temp_free(inv1);
1503 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1504 tcg_temp_free(t1);
1505 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1506 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1507 } else if (add_ca) {
1508 TCGv zero, inv1 = tcg_temp_new();
1509 tcg_gen_not_tl(inv1, arg1);
1510 zero = tcg_const_tl(0);
1511 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1512 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1513 tcg_temp_free(zero);
1514 tcg_temp_free(inv1);
1515 } else {
1516 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1517 tcg_gen_sub_tl(t0, arg2, arg1);
1518 }
1519 } else if (add_ca) {
1520 /* Since we're ignoring carry-out, we can simplify the
1521 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1522 tcg_gen_sub_tl(t0, arg2, arg1);
1523 tcg_gen_add_tl(t0, t0, cpu_ca);
1524 tcg_gen_subi_tl(t0, t0, 1);
1525 } else {
1526 tcg_gen_sub_tl(t0, arg2, arg1);
1527 }
1528
1529 if (compute_ov) {
1530 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1531 }
1532 if (unlikely(compute_rc0)) {
1533 gen_set_Rc0(ctx, t0);
1534 }
1535
1536 if (!TCGV_EQUAL(t0, ret)) {
1537 tcg_gen_mov_tl(ret, t0);
1538 tcg_temp_free(t0);
1539 }
1540 }
1541 /* Sub functions with Two operands functions */
1542 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1543 static void glue(gen_, name)(DisasContext *ctx) \
1544 { \
1545 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1546 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1547 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1548 }
1549 /* Sub functions with one operand and one immediate */
1550 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1551 add_ca, compute_ca, compute_ov) \
1552 static void glue(gen_, name)(DisasContext *ctx) \
1553 { \
1554 TCGv t0 = tcg_const_tl(const_val); \
1555 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1556 cpu_gpr[rA(ctx->opcode)], t0, \
1557 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1558 tcg_temp_free(t0); \
1559 }
1560 /* subf subf. subfo subfo. */
1561 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1562 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1563 /* subfc subfc. subfco subfco. */
1564 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1565 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1566 /* subfe subfe. subfeo subfo. */
1567 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1568 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1569 /* subfme subfme. subfmeo subfmeo. */
1570 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1571 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1572 /* subfze subfze. subfzeo subfzeo.*/
1573 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1574 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1575
1576 /* subfic */
1577 static void gen_subfic(DisasContext *ctx)
1578 {
1579 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1580 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1581 c, 0, 1, 0, 0);
1582 tcg_temp_free(c);
1583 }
1584
1585 /* neg neg. nego nego. */
1586 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1587 {
1588 TCGv zero = tcg_const_tl(0);
1589 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1590 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1591 tcg_temp_free(zero);
1592 }
1593
1594 static void gen_neg(DisasContext *ctx)
1595 {
1596 gen_op_arith_neg(ctx, 0);
1597 }
1598
1599 static void gen_nego(DisasContext *ctx)
1600 {
1601 gen_op_arith_neg(ctx, 1);
1602 }
1603
1604 /*** Integer logical ***/
1605 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1606 static void glue(gen_, name)(DisasContext *ctx) \
1607 { \
1608 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1609 cpu_gpr[rB(ctx->opcode)]); \
1610 if (unlikely(Rc(ctx->opcode) != 0)) \
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1612 }
1613
1614 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1615 static void glue(gen_, name)(DisasContext *ctx) \
1616 { \
1617 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1618 if (unlikely(Rc(ctx->opcode) != 0)) \
1619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1620 }
1621
1622 /* and & and. */
1623 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1624 /* andc & andc. */
1625 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1626
1627 /* andi. */
1628 static void gen_andi_(DisasContext *ctx)
1629 {
1630 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1631 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632 }
1633
1634 /* andis. */
1635 static void gen_andis_(DisasContext *ctx)
1636 {
1637 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1639 }
1640
1641 /* cntlzw */
1642 static void gen_cntlzw(DisasContext *ctx)
1643 {
1644 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1645 if (unlikely(Rc(ctx->opcode) != 0))
1646 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1647 }
1648
1649 /* cnttzw */
1650 static void gen_cnttzw(DisasContext *ctx)
1651 {
1652 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1653 if (unlikely(Rc(ctx->opcode) != 0)) {
1654 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1655 }
1656 }
1657
1658 /* eqv & eqv. */
1659 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1660 /* extsb & extsb. */
1661 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1662 /* extsh & extsh. */
1663 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1664 /* nand & nand. */
1665 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1666 /* nor & nor. */
1667 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1668
1669 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1670 static void gen_pause(DisasContext *ctx)
1671 {
1672 TCGv_i32 t0 = tcg_const_i32(0);
1673 tcg_gen_st_i32(t0, cpu_env,
1674 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1675 tcg_temp_free_i32(t0);
1676
1677 /* Stop translation, this gives other CPUs a chance to run */
1678 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1679 }
1680 #endif /* defined(TARGET_PPC64) */
1681
1682 /* or & or. */
1683 static void gen_or(DisasContext *ctx)
1684 {
1685 int rs, ra, rb;
1686
1687 rs = rS(ctx->opcode);
1688 ra = rA(ctx->opcode);
1689 rb = rB(ctx->opcode);
1690 /* Optimisation for mr. ri case */
1691 if (rs != ra || rs != rb) {
1692 if (rs != rb)
1693 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1694 else
1695 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[ra]);
1698 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1699 gen_set_Rc0(ctx, cpu_gpr[rs]);
1700 #if defined(TARGET_PPC64)
1701 } else if (rs != 0) { /* 0 is nop */
1702 int prio = 0;
1703
1704 switch (rs) {
1705 case 1:
1706 /* Set process priority to low */
1707 prio = 2;
1708 break;
1709 case 6:
1710 /* Set process priority to medium-low */
1711 prio = 3;
1712 break;
1713 case 2:
1714 /* Set process priority to normal */
1715 prio = 4;
1716 break;
1717 #if !defined(CONFIG_USER_ONLY)
1718 case 31:
1719 if (!ctx->pr) {
1720 /* Set process priority to very low */
1721 prio = 1;
1722 }
1723 break;
1724 case 5:
1725 if (!ctx->pr) {
1726 /* Set process priority to medium-hight */
1727 prio = 5;
1728 }
1729 break;
1730 case 3:
1731 if (!ctx->pr) {
1732 /* Set process priority to high */
1733 prio = 6;
1734 }
1735 break;
1736 case 7:
1737 if (ctx->hv && !ctx->pr) {
1738 /* Set process priority to very high */
1739 prio = 7;
1740 }
1741 break;
1742 #endif
1743 default:
1744 break;
1745 }
1746 if (prio) {
1747 TCGv t0 = tcg_temp_new();
1748 gen_load_spr(t0, SPR_PPR);
1749 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1750 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1751 gen_store_spr(SPR_PPR, t0);
1752 tcg_temp_free(t0);
1753 }
1754 #if !defined(CONFIG_USER_ONLY)
1755 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1756 * CPU and the kernel hangs. This applies to all encodings other
1757 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1758 * and all currently undefined.
1759 */
1760 gen_pause(ctx);
1761 #endif
1762 #endif
1763 }
1764 }
1765 /* orc & orc. */
1766 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1767
1768 /* xor & xor. */
1769 static void gen_xor(DisasContext *ctx)
1770 {
1771 /* Optimisation for "set to zero" case */
1772 if (rS(ctx->opcode) != rB(ctx->opcode))
1773 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1774 else
1775 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1776 if (unlikely(Rc(ctx->opcode) != 0))
1777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1778 }
1779
1780 /* ori */
1781 static void gen_ori(DisasContext *ctx)
1782 {
1783 target_ulong uimm = UIMM(ctx->opcode);
1784
1785 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1786 return;
1787 }
1788 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1789 }
1790
1791 /* oris */
1792 static void gen_oris(DisasContext *ctx)
1793 {
1794 target_ulong uimm = UIMM(ctx->opcode);
1795
1796 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1797 /* NOP */
1798 return;
1799 }
1800 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1801 }
1802
1803 /* xori */
1804 static void gen_xori(DisasContext *ctx)
1805 {
1806 target_ulong uimm = UIMM(ctx->opcode);
1807
1808 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1809 /* NOP */
1810 return;
1811 }
1812 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1813 }
1814
1815 /* xoris */
1816 static void gen_xoris(DisasContext *ctx)
1817 {
1818 target_ulong uimm = UIMM(ctx->opcode);
1819
1820 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1821 /* NOP */
1822 return;
1823 }
1824 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1825 }
1826
1827 /* popcntb : PowerPC 2.03 specification */
1828 static void gen_popcntb(DisasContext *ctx)
1829 {
1830 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1831 }
1832
1833 static void gen_popcntw(DisasContext *ctx)
1834 {
1835 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1836 }
1837
1838 #if defined(TARGET_PPC64)
1839 /* popcntd: PowerPC 2.06 specification */
1840 static void gen_popcntd(DisasContext *ctx)
1841 {
1842 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1843 }
1844 #endif
1845
1846 /* prtyw: PowerPC 2.05 specification */
1847 static void gen_prtyw(DisasContext *ctx)
1848 {
1849 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1850 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1851 TCGv t0 = tcg_temp_new();
1852 tcg_gen_shri_tl(t0, rs, 16);
1853 tcg_gen_xor_tl(ra, rs, t0);
1854 tcg_gen_shri_tl(t0, ra, 8);
1855 tcg_gen_xor_tl(ra, ra, t0);
1856 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1857 tcg_temp_free(t0);
1858 }
1859
1860 #if defined(TARGET_PPC64)
1861 /* prtyd: PowerPC 2.05 specification */
1862 static void gen_prtyd(DisasContext *ctx)
1863 {
1864 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1865 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1866 TCGv t0 = tcg_temp_new();
1867 tcg_gen_shri_tl(t0, rs, 32);
1868 tcg_gen_xor_tl(ra, rs, t0);
1869 tcg_gen_shri_tl(t0, ra, 16);
1870 tcg_gen_xor_tl(ra, ra, t0);
1871 tcg_gen_shri_tl(t0, ra, 8);
1872 tcg_gen_xor_tl(ra, ra, t0);
1873 tcg_gen_andi_tl(ra, ra, 1);
1874 tcg_temp_free(t0);
1875 }
1876 #endif
1877
1878 #if defined(TARGET_PPC64)
1879 /* bpermd */
1880 static void gen_bpermd(DisasContext *ctx)
1881 {
1882 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1883 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1884 }
1885 #endif
1886
1887 #if defined(TARGET_PPC64)
1888 /* extsw & extsw. */
1889 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1890
1891 /* cntlzd */
1892 static void gen_cntlzd(DisasContext *ctx)
1893 {
1894 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1895 if (unlikely(Rc(ctx->opcode) != 0))
1896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1897 }
1898
1899 /* cnttzd */
1900 static void gen_cnttzd(DisasContext *ctx)
1901 {
1902 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1903 if (unlikely(Rc(ctx->opcode) != 0)) {
1904 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1905 }
1906 }
1907
1908 /* darn */
1909 static void gen_darn(DisasContext *ctx)
1910 {
1911 int l = L(ctx->opcode);
1912
1913 if (l == 0) {
1914 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1915 } else if (l <= 2) {
1916 /* Return 64-bit random for both CRN and RRN */
1917 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1918 } else {
1919 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1920 }
1921 }
1922 #endif
1923
1924 /*** Integer rotate ***/
1925
1926 /* rlwimi & rlwimi. */
1927 static void gen_rlwimi(DisasContext *ctx)
1928 {
1929 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1930 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1931 uint32_t sh = SH(ctx->opcode);
1932 uint32_t mb = MB(ctx->opcode);
1933 uint32_t me = ME(ctx->opcode);
1934
1935 if (sh == (31-me) && mb <= me) {
1936 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1937 } else {
1938 target_ulong mask;
1939 TCGv t1;
1940
1941 #if defined(TARGET_PPC64)
1942 mb += 32;
1943 me += 32;
1944 #endif
1945 mask = MASK(mb, me);
1946
1947 t1 = tcg_temp_new();
1948 if (mask <= 0xffffffffu) {
1949 TCGv_i32 t0 = tcg_temp_new_i32();
1950 tcg_gen_trunc_tl_i32(t0, t_rs);
1951 tcg_gen_rotli_i32(t0, t0, sh);
1952 tcg_gen_extu_i32_tl(t1, t0);
1953 tcg_temp_free_i32(t0);
1954 } else {
1955 #if defined(TARGET_PPC64)
1956 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1957 tcg_gen_rotli_i64(t1, t1, sh);
1958 #else
1959 g_assert_not_reached();
1960 #endif
1961 }
1962
1963 tcg_gen_andi_tl(t1, t1, mask);
1964 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1965 tcg_gen_or_tl(t_ra, t_ra, t1);
1966 tcg_temp_free(t1);
1967 }
1968 if (unlikely(Rc(ctx->opcode) != 0)) {
1969 gen_set_Rc0(ctx, t_ra);
1970 }
1971 }
1972
1973 /* rlwinm & rlwinm. */
1974 static void gen_rlwinm(DisasContext *ctx)
1975 {
1976 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1977 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1978 int sh = SH(ctx->opcode);
1979 int mb = MB(ctx->opcode);
1980 int me = ME(ctx->opcode);
1981 int len = me - mb + 1;
1982 int rsh = (32 - sh) & 31;
1983
1984 if (sh != 0 && len > 0 && me == (31 - sh)) {
1985 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1986 } else if (me == 31 && rsh + len <= 32) {
1987 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1988 } else {
1989 target_ulong mask;
1990 #if defined(TARGET_PPC64)
1991 mb += 32;
1992 me += 32;
1993 #endif
1994 mask = MASK(mb, me);
1995 if (sh == 0) {
1996 tcg_gen_andi_tl(t_ra, t_rs, mask);
1997 } else if (mask <= 0xffffffffu) {
1998 TCGv_i32 t0 = tcg_temp_new_i32();
1999 tcg_gen_trunc_tl_i32(t0, t_rs);
2000 tcg_gen_rotli_i32(t0, t0, sh);
2001 tcg_gen_andi_i32(t0, t0, mask);
2002 tcg_gen_extu_i32_tl(t_ra, t0);
2003 tcg_temp_free_i32(t0);
2004 } else {
2005 #if defined(TARGET_PPC64)
2006 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2007 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2008 tcg_gen_andi_i64(t_ra, t_ra, mask);
2009 #else
2010 g_assert_not_reached();
2011 #endif
2012 }
2013 }
2014 if (unlikely(Rc(ctx->opcode) != 0)) {
2015 gen_set_Rc0(ctx, t_ra);
2016 }
2017 }
2018
2019 /* rlwnm & rlwnm. */
2020 static void gen_rlwnm(DisasContext *ctx)
2021 {
2022 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2023 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2024 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2025 uint32_t mb = MB(ctx->opcode);
2026 uint32_t me = ME(ctx->opcode);
2027 target_ulong mask;
2028
2029 #if defined(TARGET_PPC64)
2030 mb += 32;
2031 me += 32;
2032 #endif
2033 mask = MASK(mb, me);
2034
2035 if (mask <= 0xffffffffu) {
2036 TCGv_i32 t0 = tcg_temp_new_i32();
2037 TCGv_i32 t1 = tcg_temp_new_i32();
2038 tcg_gen_trunc_tl_i32(t0, t_rb);
2039 tcg_gen_trunc_tl_i32(t1, t_rs);
2040 tcg_gen_andi_i32(t0, t0, 0x1f);
2041 tcg_gen_rotl_i32(t1, t1, t0);
2042 tcg_gen_extu_i32_tl(t_ra, t1);
2043 tcg_temp_free_i32(t0);
2044 tcg_temp_free_i32(t1);
2045 } else {
2046 #if defined(TARGET_PPC64)
2047 TCGv_i64 t0 = tcg_temp_new_i64();
2048 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2049 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2050 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2051 tcg_temp_free_i64(t0);
2052 #else
2053 g_assert_not_reached();
2054 #endif
2055 }
2056
2057 tcg_gen_andi_tl(t_ra, t_ra, mask);
2058
2059 if (unlikely(Rc(ctx->opcode) != 0)) {
2060 gen_set_Rc0(ctx, t_ra);
2061 }
2062 }
2063
2064 #if defined(TARGET_PPC64)
2065 #define GEN_PPC64_R2(name, opc1, opc2) \
2066 static void glue(gen_, name##0)(DisasContext *ctx) \
2067 { \
2068 gen_##name(ctx, 0); \
2069 } \
2070 \
2071 static void glue(gen_, name##1)(DisasContext *ctx) \
2072 { \
2073 gen_##name(ctx, 1); \
2074 }
2075 #define GEN_PPC64_R4(name, opc1, opc2) \
2076 static void glue(gen_, name##0)(DisasContext *ctx) \
2077 { \
2078 gen_##name(ctx, 0, 0); \
2079 } \
2080 \
2081 static void glue(gen_, name##1)(DisasContext *ctx) \
2082 { \
2083 gen_##name(ctx, 0, 1); \
2084 } \
2085 \
2086 static void glue(gen_, name##2)(DisasContext *ctx) \
2087 { \
2088 gen_##name(ctx, 1, 0); \
2089 } \
2090 \
2091 static void glue(gen_, name##3)(DisasContext *ctx) \
2092 { \
2093 gen_##name(ctx, 1, 1); \
2094 }
2095
2096 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2097 {
2098 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2099 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2100 int len = me - mb + 1;
2101 int rsh = (64 - sh) & 63;
2102
2103 if (sh != 0 && len > 0 && me == (63 - sh)) {
2104 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2105 } else if (me == 63 && rsh + len <= 64) {
2106 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2107 } else {
2108 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2109 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2110 }
2111 if (unlikely(Rc(ctx->opcode) != 0)) {
2112 gen_set_Rc0(ctx, t_ra);
2113 }
2114 }
2115
2116 /* rldicl - rldicl. */
2117 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2118 {
2119 uint32_t sh, mb;
2120
2121 sh = SH(ctx->opcode) | (shn << 5);
2122 mb = MB(ctx->opcode) | (mbn << 5);
2123 gen_rldinm(ctx, mb, 63, sh);
2124 }
2125 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2126
2127 /* rldicr - rldicr. */
2128 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2129 {
2130 uint32_t sh, me;
2131
2132 sh = SH(ctx->opcode) | (shn << 5);
2133 me = MB(ctx->opcode) | (men << 5);
2134 gen_rldinm(ctx, 0, me, sh);
2135 }
2136 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2137
2138 /* rldic - rldic. */
2139 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2140 {
2141 uint32_t sh, mb;
2142
2143 sh = SH(ctx->opcode) | (shn << 5);
2144 mb = MB(ctx->opcode) | (mbn << 5);
2145 gen_rldinm(ctx, mb, 63 - sh, sh);
2146 }
2147 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2148
2149 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2150 {
2151 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2152 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2153 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2154 TCGv t0;
2155
2156 t0 = tcg_temp_new();
2157 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2158 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2159 tcg_temp_free(t0);
2160
2161 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2162 if (unlikely(Rc(ctx->opcode) != 0)) {
2163 gen_set_Rc0(ctx, t_ra);
2164 }
2165 }
2166
2167 /* rldcl - rldcl. */
2168 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2169 {
2170 uint32_t mb;
2171
2172 mb = MB(ctx->opcode) | (mbn << 5);
2173 gen_rldnm(ctx, mb, 63);
2174 }
2175 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2176
2177 /* rldcr - rldcr. */
2178 static inline void gen_rldcr(DisasContext *ctx, int men)
2179 {
2180 uint32_t me;
2181
2182 me = MB(ctx->opcode) | (men << 5);
2183 gen_rldnm(ctx, 0, me);
2184 }
2185 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2186
2187 /* rldimi - rldimi. */
2188 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2189 {
2190 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2191 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2192 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2193 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2194 uint32_t me = 63 - sh;
2195
2196 if (mb <= me) {
2197 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2198 } else {
2199 target_ulong mask = MASK(mb, me);
2200 TCGv t1 = tcg_temp_new();
2201
2202 tcg_gen_rotli_tl(t1, t_rs, sh);
2203 tcg_gen_andi_tl(t1, t1, mask);
2204 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2205 tcg_gen_or_tl(t_ra, t_ra, t1);
2206 tcg_temp_free(t1);
2207 }
2208 if (unlikely(Rc(ctx->opcode) != 0)) {
2209 gen_set_Rc0(ctx, t_ra);
2210 }
2211 }
2212 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2213 #endif
2214
2215 /*** Integer shift ***/
2216
2217 /* slw & slw. */
2218 static void gen_slw(DisasContext *ctx)
2219 {
2220 TCGv t0, t1;
2221
2222 t0 = tcg_temp_new();
2223 /* AND rS with a mask that is 0 when rB >= 0x20 */
2224 #if defined(TARGET_PPC64)
2225 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2226 tcg_gen_sari_tl(t0, t0, 0x3f);
2227 #else
2228 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2229 tcg_gen_sari_tl(t0, t0, 0x1f);
2230 #endif
2231 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2232 t1 = tcg_temp_new();
2233 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2234 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2235 tcg_temp_free(t1);
2236 tcg_temp_free(t0);
2237 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2238 if (unlikely(Rc(ctx->opcode) != 0))
2239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2240 }
2241
2242 /* sraw & sraw. */
2243 static void gen_sraw(DisasContext *ctx)
2244 {
2245 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2246 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2247 if (unlikely(Rc(ctx->opcode) != 0))
2248 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2249 }
2250
2251 /* srawi & srawi. */
2252 static void gen_srawi(DisasContext *ctx)
2253 {
2254 int sh = SH(ctx->opcode);
2255 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2256 TCGv src = cpu_gpr[rS(ctx->opcode)];
2257 if (sh == 0) {
2258 tcg_gen_ext32s_tl(dst, src);
2259 tcg_gen_movi_tl(cpu_ca, 0);
2260 } else {
2261 TCGv t0;
2262 tcg_gen_ext32s_tl(dst, src);
2263 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2264 t0 = tcg_temp_new();
2265 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2266 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2267 tcg_temp_free(t0);
2268 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2269 tcg_gen_sari_tl(dst, dst, sh);
2270 }
2271 if (unlikely(Rc(ctx->opcode) != 0)) {
2272 gen_set_Rc0(ctx, dst);
2273 }
2274 }
2275
2276 /* srw & srw. */
2277 static void gen_srw(DisasContext *ctx)
2278 {
2279 TCGv t0, t1;
2280
2281 t0 = tcg_temp_new();
2282 /* AND rS with a mask that is 0 when rB >= 0x20 */
2283 #if defined(TARGET_PPC64)
2284 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2285 tcg_gen_sari_tl(t0, t0, 0x3f);
2286 #else
2287 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2288 tcg_gen_sari_tl(t0, t0, 0x1f);
2289 #endif
2290 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2291 tcg_gen_ext32u_tl(t0, t0);
2292 t1 = tcg_temp_new();
2293 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2294 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2295 tcg_temp_free(t1);
2296 tcg_temp_free(t0);
2297 if (unlikely(Rc(ctx->opcode) != 0))
2298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2299 }
2300
2301 #if defined(TARGET_PPC64)
2302 /* sld & sld. */
2303 static void gen_sld(DisasContext *ctx)
2304 {
2305 TCGv t0, t1;
2306
2307 t0 = tcg_temp_new();
2308 /* AND rS with a mask that is 0 when rB >= 0x40 */
2309 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2310 tcg_gen_sari_tl(t0, t0, 0x3f);
2311 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2312 t1 = tcg_temp_new();
2313 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2314 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2315 tcg_temp_free(t1);
2316 tcg_temp_free(t0);
2317 if (unlikely(Rc(ctx->opcode) != 0))
2318 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2319 }
2320
2321 /* srad & srad. */
2322 static void gen_srad(DisasContext *ctx)
2323 {
2324 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2325 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2326 if (unlikely(Rc(ctx->opcode) != 0))
2327 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2328 }
2329 /* sradi & sradi. */
2330 static inline void gen_sradi(DisasContext *ctx, int n)
2331 {
2332 int sh = SH(ctx->opcode) + (n << 5);
2333 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2334 TCGv src = cpu_gpr[rS(ctx->opcode)];
2335 if (sh == 0) {
2336 tcg_gen_mov_tl(dst, src);
2337 tcg_gen_movi_tl(cpu_ca, 0);
2338 } else {
2339 TCGv t0;
2340 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2341 t0 = tcg_temp_new();
2342 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2343 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2344 tcg_temp_free(t0);
2345 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2346 tcg_gen_sari_tl(dst, src, sh);
2347 }
2348 if (unlikely(Rc(ctx->opcode) != 0)) {
2349 gen_set_Rc0(ctx, dst);
2350 }
2351 }
2352
2353 static void gen_sradi0(DisasContext *ctx)
2354 {
2355 gen_sradi(ctx, 0);
2356 }
2357
2358 static void gen_sradi1(DisasContext *ctx)
2359 {
2360 gen_sradi(ctx, 1);
2361 }
2362
2363 /* extswsli & extswsli. */
2364 static inline void gen_extswsli(DisasContext *ctx, int n)
2365 {
2366 int sh = SH(ctx->opcode) + (n << 5);
2367 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2368 TCGv src = cpu_gpr[rS(ctx->opcode)];
2369
2370 tcg_gen_ext32s_tl(dst, src);
2371 tcg_gen_shli_tl(dst, dst, sh);
2372 if (unlikely(Rc(ctx->opcode) != 0)) {
2373 gen_set_Rc0(ctx, dst);
2374 }
2375 }
2376
2377 static void gen_extswsli0(DisasContext *ctx)
2378 {
2379 gen_extswsli(ctx, 0);
2380 }
2381
2382 static void gen_extswsli1(DisasContext *ctx)
2383 {
2384 gen_extswsli(ctx, 1);
2385 }
2386
2387 /* srd & srd. */
2388 static void gen_srd(DisasContext *ctx)
2389 {
2390 TCGv t0, t1;
2391
2392 t0 = tcg_temp_new();
2393 /* AND rS with a mask that is 0 when rB >= 0x40 */
2394 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2395 tcg_gen_sari_tl(t0, t0, 0x3f);
2396 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2397 t1 = tcg_temp_new();
2398 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2399 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2400 tcg_temp_free(t1);
2401 tcg_temp_free(t0);
2402 if (unlikely(Rc(ctx->opcode) != 0))
2403 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2404 }
2405 #endif
2406
2407 /*** Addressing modes ***/
2408 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2409 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2410 target_long maskl)
2411 {
2412 target_long simm = SIMM(ctx->opcode);
2413
2414 simm &= ~maskl;
2415 if (rA(ctx->opcode) == 0) {
2416 if (NARROW_MODE(ctx)) {
2417 simm = (uint32_t)simm;
2418 }
2419 tcg_gen_movi_tl(EA, simm);
2420 } else if (likely(simm != 0)) {
2421 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2422 if (NARROW_MODE(ctx)) {
2423 tcg_gen_ext32u_tl(EA, EA);
2424 }
2425 } else {
2426 if (NARROW_MODE(ctx)) {
2427 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2428 } else {
2429 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2430 }
2431 }
2432 }
2433
2434 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2435 {
2436 if (rA(ctx->opcode) == 0) {
2437 if (NARROW_MODE(ctx)) {
2438 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2439 } else {
2440 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2441 }
2442 } else {
2443 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2444 if (NARROW_MODE(ctx)) {
2445 tcg_gen_ext32u_tl(EA, EA);
2446 }
2447 }
2448 }
2449
2450 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2451 {
2452 if (rA(ctx->opcode) == 0) {
2453 tcg_gen_movi_tl(EA, 0);
2454 } else if (NARROW_MODE(ctx)) {
2455 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2456 } else {
2457 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2458 }
2459 }
2460
2461 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2462 target_long val)
2463 {
2464 tcg_gen_addi_tl(ret, arg1, val);
2465 if (NARROW_MODE(ctx)) {
2466 tcg_gen_ext32u_tl(ret, ret);
2467 }
2468 }
2469
2470 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2471 {
2472 TCGLabel *l1 = gen_new_label();
2473 TCGv t0 = tcg_temp_new();
2474 TCGv_i32 t1, t2;
2475 tcg_gen_andi_tl(t0, EA, mask);
2476 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2477 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2478 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2479 gen_update_nip(ctx, ctx->nip - 4);
2480 gen_helper_raise_exception_err(cpu_env, t1, t2);
2481 tcg_temp_free_i32(t1);
2482 tcg_temp_free_i32(t2);
2483 gen_set_label(l1);
2484 tcg_temp_free(t0);
2485 }
2486
2487 static inline void gen_align_no_le(DisasContext *ctx)
2488 {
2489 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2490 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2491 }
2492
2493 /*** Integer load ***/
2494 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2495 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2496
2497 #define GEN_QEMU_LOAD_TL(ldop, op) \
2498 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2499 TCGv val, \
2500 TCGv addr) \
2501 { \
2502 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2503 }
2504
2505 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2506 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2507 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2508 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2509 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2510
2511 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2512 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2513
2514 #define GEN_QEMU_LOAD_64(ldop, op) \
2515 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2516 TCGv_i64 val, \
2517 TCGv addr) \
2518 { \
2519 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2520 }
2521
2522 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2523 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2524 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2525 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2526 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2527
2528 #if defined(TARGET_PPC64)
2529 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2530 #endif
2531
2532 #define GEN_QEMU_STORE_TL(stop, op) \
2533 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2534 TCGv val, \
2535 TCGv addr) \
2536 { \
2537 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2538 }
2539
2540 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2541 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2542 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2543
2544 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2545 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2546
2547 #define GEN_QEMU_STORE_64(stop, op) \
2548 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2549 TCGv_i64 val, \
2550 TCGv addr) \
2551 { \
2552 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2553 }
2554
2555 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2556 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2557 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2558 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2559
2560 #if defined(TARGET_PPC64)
2561 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2562 #endif
2563
2564 #define GEN_LD(name, ldop, opc, type) \
2565 static void glue(gen_, name)(DisasContext *ctx) \
2566 { \
2567 TCGv EA; \
2568 gen_set_access_type(ctx, ACCESS_INT); \
2569 EA = tcg_temp_new(); \
2570 gen_addr_imm_index(ctx, EA, 0); \
2571 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2572 tcg_temp_free(EA); \
2573 }
2574
2575 #define GEN_LDU(name, ldop, opc, type) \
2576 static void glue(gen_, name##u)(DisasContext *ctx) \
2577 { \
2578 TCGv EA; \
2579 if (unlikely(rA(ctx->opcode) == 0 || \
2580 rA(ctx->opcode) == rD(ctx->opcode))) { \
2581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2582 return; \
2583 } \
2584 gen_set_access_type(ctx, ACCESS_INT); \
2585 EA = tcg_temp_new(); \
2586 if (type == PPC_64B) \
2587 gen_addr_imm_index(ctx, EA, 0x03); \
2588 else \
2589 gen_addr_imm_index(ctx, EA, 0); \
2590 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2591 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2592 tcg_temp_free(EA); \
2593 }
2594
2595 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2596 static void glue(gen_, name##ux)(DisasContext *ctx) \
2597 { \
2598 TCGv EA; \
2599 if (unlikely(rA(ctx->opcode) == 0 || \
2600 rA(ctx->opcode) == rD(ctx->opcode))) { \
2601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2602 return; \
2603 } \
2604 gen_set_access_type(ctx, ACCESS_INT); \
2605 EA = tcg_temp_new(); \
2606 gen_addr_reg_index(ctx, EA); \
2607 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2608 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2609 tcg_temp_free(EA); \
2610 }
2611
2612 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2613 static void glue(gen_, name##x)(DisasContext *ctx) \
2614 { \
2615 TCGv EA; \
2616 chk; \
2617 gen_set_access_type(ctx, ACCESS_INT); \
2618 EA = tcg_temp_new(); \
2619 gen_addr_reg_index(ctx, EA); \
2620 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2621 tcg_temp_free(EA); \
2622 }
2623
2624 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2625 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2626
2627 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2628 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2629
2630 #define GEN_LDS(name, ldop, op, type) \
2631 GEN_LD(name, ldop, op | 0x20, type); \
2632 GEN_LDU(name, ldop, op | 0x21, type); \
2633 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2634 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2635
2636 /* lbz lbzu lbzux lbzx */
2637 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2638 /* lha lhau lhaux lhax */
2639 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2640 /* lhz lhzu lhzux lhzx */
2641 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2642 /* lwz lwzu lwzux lwzx */
2643 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2644 #if defined(TARGET_PPC64)
2645 /* lwaux */
2646 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2647 /* lwax */
2648 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2649 /* ldux */
2650 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2651 /* ldx */
2652 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2653
2654 /* CI load/store variants */
2655 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2656 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2657 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2658 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2659
2660 static void gen_ld(DisasContext *ctx)
2661 {
2662 TCGv EA;
2663 if (Rc(ctx->opcode)) {
2664 if (unlikely(rA(ctx->opcode) == 0 ||
2665 rA(ctx->opcode) == rD(ctx->opcode))) {
2666 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2667 return;
2668 }
2669 }
2670 gen_set_access_type(ctx, ACCESS_INT);
2671 EA = tcg_temp_new();
2672 gen_addr_imm_index(ctx, EA, 0x03);
2673 if (ctx->opcode & 0x02) {
2674 /* lwa (lwau is undefined) */
2675 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2676 } else {
2677 /* ld - ldu */
2678 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2679 }
2680 if (Rc(ctx->opcode))
2681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2682 tcg_temp_free(EA);
2683 }
2684
2685 /* lq */
2686 static void gen_lq(DisasContext *ctx)
2687 {
2688 int ra, rd;
2689 TCGv EA;
2690
2691 /* lq is a legal user mode instruction starting in ISA 2.07 */
2692 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2693 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2694
2695 if (!legal_in_user_mode && ctx->pr) {
2696 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2697 return;
2698 }
2699
2700 if (!le_is_supported && ctx->le_mode) {
2701 gen_align_no_le(ctx);
2702 return;
2703 }
2704 ra = rA(ctx->opcode);
2705 rd = rD(ctx->opcode);
2706 if (unlikely((rd & 1) || rd == ra)) {
2707 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2708 return;
2709 }
2710
2711 gen_set_access_type(ctx, ACCESS_INT);
2712 EA = tcg_temp_new();
2713 gen_addr_imm_index(ctx, EA, 0x0F);
2714
2715 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2716 necessary 64-bit byteswap already. */
2717 if (unlikely(ctx->le_mode)) {
2718 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2719 gen_addr_add(ctx, EA, EA, 8);
2720 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2721 } else {
2722 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2723 gen_addr_add(ctx, EA, EA, 8);
2724 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2725 }
2726 tcg_temp_free(EA);
2727 }
2728 #endif
2729
2730 /*** Integer store ***/
2731 #define GEN_ST(name, stop, opc, type) \
2732 static void glue(gen_, name)(DisasContext *ctx) \
2733 { \
2734 TCGv EA; \
2735 gen_set_access_type(ctx, ACCESS_INT); \
2736 EA = tcg_temp_new(); \
2737 gen_addr_imm_index(ctx, EA, 0); \
2738 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2739 tcg_temp_free(EA); \
2740 }
2741
2742 #define GEN_STU(name, stop, opc, type) \
2743 static void glue(gen_, stop##u)(DisasContext *ctx) \
2744 { \
2745 TCGv EA; \
2746 if (unlikely(rA(ctx->opcode) == 0)) { \
2747 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2748 return; \
2749 } \
2750 gen_set_access_type(ctx, ACCESS_INT); \
2751 EA = tcg_temp_new(); \
2752 if (type == PPC_64B) \
2753 gen_addr_imm_index(ctx, EA, 0x03); \
2754 else \
2755 gen_addr_imm_index(ctx, EA, 0); \
2756 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2758 tcg_temp_free(EA); \
2759 }
2760
2761 #define GEN_STUX(name, stop, opc2, opc3, type) \
2762 static void glue(gen_, name##ux)(DisasContext *ctx) \
2763 { \
2764 TCGv EA; \
2765 if (unlikely(rA(ctx->opcode) == 0)) { \
2766 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2767 return; \
2768 } \
2769 gen_set_access_type(ctx, ACCESS_INT); \
2770 EA = tcg_temp_new(); \
2771 gen_addr_reg_index(ctx, EA); \
2772 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2773 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2774 tcg_temp_free(EA); \
2775 }
2776
2777 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2778 static void glue(gen_, name##x)(DisasContext *ctx) \
2779 { \
2780 TCGv EA; \
2781 chk; \
2782 gen_set_access_type(ctx, ACCESS_INT); \
2783 EA = tcg_temp_new(); \
2784 gen_addr_reg_index(ctx, EA); \
2785 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2786 tcg_temp_free(EA); \
2787 }
2788 #define GEN_STX(name, stop, opc2, opc3, type) \
2789 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2790
2791 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2792 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2793
2794 #define GEN_STS(name, stop, op, type) \
2795 GEN_ST(name, stop, op | 0x20, type); \
2796 GEN_STU(name, stop, op | 0x21, type); \
2797 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2798 GEN_STX(name, stop, 0x17, op | 0x00, type)
2799
2800 /* stb stbu stbux stbx */
2801 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2802 /* sth sthu sthux sthx */
2803 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2804 /* stw stwu stwux stwx */
2805 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2806 #if defined(TARGET_PPC64)
2807 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2808 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2809 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2810 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2811 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2812 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2813
2814 static void gen_std(DisasContext *ctx)
2815 {
2816 int rs;
2817 TCGv EA;
2818
2819 rs = rS(ctx->opcode);
2820 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2821 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2822 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2823
2824 if (!(ctx->insns_flags & PPC_64BX)) {
2825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2826 }
2827
2828 if (!legal_in_user_mode && ctx->pr) {
2829 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2830 return;
2831 }
2832
2833 if (!le_is_supported && ctx->le_mode) {
2834 gen_align_no_le(ctx);
2835 return;
2836 }
2837
2838 if (unlikely(rs & 1)) {
2839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2840 return;
2841 }
2842 gen_set_access_type(ctx, ACCESS_INT);
2843 EA = tcg_temp_new();
2844 gen_addr_imm_index(ctx, EA, 0x03);
2845
2846 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2847 necessary 64-bit byteswap already. */
2848 if (unlikely(ctx->le_mode)) {
2849 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2850 gen_addr_add(ctx, EA, EA, 8);
2851 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2852 } else {
2853 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2854 gen_addr_add(ctx, EA, EA, 8);
2855 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2856 }
2857 tcg_temp_free(EA);
2858 } else {
2859 /* std / stdu*/
2860 if (Rc(ctx->opcode)) {
2861 if (unlikely(rA(ctx->opcode) == 0)) {
2862 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2863 return;
2864 }
2865 }
2866 gen_set_access_type(ctx, ACCESS_INT);
2867 EA = tcg_temp_new();
2868 gen_addr_imm_index(ctx, EA, 0x03);
2869 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2870 if (Rc(ctx->opcode))
2871 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2872 tcg_temp_free(EA);
2873 }
2874 }
2875 #endif
2876 /*** Integer load and store with byte reverse ***/
2877
2878 /* lhbrx */
2879 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2880
2881 /* lwbrx */
2882 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2883
2884 #if defined(TARGET_PPC64)
2885 /* ldbrx */
2886 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2887 /* stdbrx */
2888 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2889 #endif /* TARGET_PPC64 */
2890
2891 /* sthbrx */
2892 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2893 /* stwbrx */
2894 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2895
2896 /*** Integer load and store multiple ***/
2897
2898 /* lmw */
2899 static void gen_lmw(DisasContext *ctx)
2900 {
2901 TCGv t0;
2902 TCGv_i32 t1;
2903
2904 if (ctx->le_mode) {
2905 gen_align_no_le(ctx);
2906 return;
2907 }
2908 gen_set_access_type(ctx, ACCESS_INT);
2909 t0 = tcg_temp_new();
2910 t1 = tcg_const_i32(rD(ctx->opcode));
2911 gen_addr_imm_index(ctx, t0, 0);
2912 gen_helper_lmw(cpu_env, t0, t1);
2913 tcg_temp_free(t0);
2914 tcg_temp_free_i32(t1);
2915 }
2916
2917 /* stmw */
2918 static void gen_stmw(DisasContext *ctx)
2919 {
2920 TCGv t0;
2921 TCGv_i32 t1;
2922
2923 if (ctx->le_mode) {
2924 gen_align_no_le(ctx);
2925 return;
2926 }
2927 gen_set_access_type(ctx, ACCESS_INT);
2928 t0 = tcg_temp_new();
2929 t1 = tcg_const_i32(rS(ctx->opcode));
2930 gen_addr_imm_index(ctx, t0, 0);
2931 gen_helper_stmw(cpu_env, t0, t1);
2932 tcg_temp_free(t0);
2933 tcg_temp_free_i32(t1);
2934 }
2935
2936 /*** Integer load and store strings ***/
2937
2938 /* lswi */
2939 /* PowerPC32 specification says we must generate an exception if
2940 * rA is in the range of registers to be loaded.
2941 * In an other hand, IBM says this is valid, but rA won't be loaded.
2942 * For now, I'll follow the spec...
2943 */
2944 static void gen_lswi(DisasContext *ctx)
2945 {
2946 TCGv t0;
2947 TCGv_i32 t1, t2;
2948 int nb = NB(ctx->opcode);
2949 int start = rD(ctx->opcode);
2950 int ra = rA(ctx->opcode);
2951 int nr;
2952
2953 if (ctx->le_mode) {
2954 gen_align_no_le(ctx);
2955 return;
2956 }
2957 if (nb == 0)
2958 nb = 32;
2959 nr = (nb + 3) / 4;
2960 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2962 return;
2963 }
2964 gen_set_access_type(ctx, ACCESS_INT);
2965 t0 = tcg_temp_new();
2966 gen_addr_register(ctx, t0);
2967 t1 = tcg_const_i32(nb);
2968 t2 = tcg_const_i32(start);
2969 gen_helper_lsw(cpu_env, t0, t1, t2);
2970 tcg_temp_free(t0);
2971 tcg_temp_free_i32(t1);
2972 tcg_temp_free_i32(t2);
2973 }
2974
2975 /* lswx */
2976 static void gen_lswx(DisasContext *ctx)
2977 {
2978 TCGv t0;
2979 TCGv_i32 t1, t2, t3;
2980
2981 if (ctx->le_mode) {
2982 gen_align_no_le(ctx);
2983 return;
2984 }
2985 gen_set_access_type(ctx, ACCESS_INT);
2986 t0 = tcg_temp_new();
2987 gen_addr_reg_index(ctx, t0);
2988 t1 = tcg_const_i32(rD(ctx->opcode));
2989 t2 = tcg_const_i32(rA(ctx->opcode));
2990 t3 = tcg_const_i32(rB(ctx->opcode));
2991 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2992 tcg_temp_free(t0);
2993 tcg_temp_free_i32(t1);
2994 tcg_temp_free_i32(t2);
2995 tcg_temp_free_i32(t3);
2996 }
2997
2998 /* stswi */
2999 static void gen_stswi(DisasContext *ctx)
3000 {
3001 TCGv t0;
3002 TCGv_i32 t1, t2;
3003 int nb = NB(ctx->opcode);
3004
3005 if (ctx->le_mode) {
3006 gen_align_no_le(ctx);
3007 return;
3008 }
3009 gen_set_access_type(ctx, ACCESS_INT);
3010 t0 = tcg_temp_new();
3011 gen_addr_register(ctx, t0);
3012 if (nb == 0)
3013 nb = 32;
3014 t1 = tcg_const_i32(nb);
3015 t2 = tcg_const_i32(rS(ctx->opcode));
3016 gen_helper_stsw(cpu_env, t0, t1, t2);
3017 tcg_temp_free(t0);
3018 tcg_temp_free_i32(t1);
3019 tcg_temp_free_i32(t2);
3020 }
3021
3022 /* stswx */
3023 static void gen_stswx(DisasContext *ctx)
3024 {
3025 TCGv t0;
3026 TCGv_i32 t1, t2;
3027
3028 if (ctx->le_mode) {
3029 gen_align_no_le(ctx);
3030 return;
3031 }
3032 gen_set_access_type(ctx, ACCESS_INT);
3033 t0 = tcg_temp_new();
3034 gen_addr_reg_index(ctx, t0);
3035 t1 = tcg_temp_new_i32();
3036 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3037 tcg_gen_andi_i32(t1, t1, 0x7F);
3038 t2 = tcg_const_i32(rS(ctx->opcode));
3039 gen_helper_stsw(cpu_env, t0, t1, t2);
3040 tcg_temp_free(t0);
3041 tcg_temp_free_i32(t1);
3042 tcg_temp_free_i32(t2);
3043 }
3044
3045 /*** Memory synchronisation ***/
3046 /* eieio */
3047 static void gen_eieio(DisasContext *ctx)
3048 {
3049 }
3050
3051 #if !defined(CONFIG_USER_ONLY)
3052 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3053 {
3054 TCGv_i32 t;
3055 TCGLabel *l;
3056
3057 if (!ctx->lazy_tlb_flush) {
3058 return;
3059 }
3060 l = gen_new_label();
3061 t = tcg_temp_new_i32();
3062 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3063 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3064 if (global) {
3065 gen_helper_check_tlb_flush_global(cpu_env);
3066 } else {
3067 gen_helper_check_tlb_flush_local(cpu_env);
3068 }
3069 gen_set_label(l);
3070 tcg_temp_free_i32(t);
3071 }
3072 #else
3073 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3074 #endif
3075
3076 /* isync */
3077 static void gen_isync(DisasContext *ctx)
3078 {
3079 /*
3080 * We need to check for a pending TLB flush. This can only happen in
3081 * kernel mode however so check MSR_PR
3082 */
3083 if (!ctx->pr) {
3084 gen_check_tlb_flush(ctx, false);
3085 }
3086 gen_stop_exception(ctx);
3087 }
3088
3089 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3090
3091 #define LARX(name, memop) \
3092 static void gen_##name(DisasContext *ctx) \
3093 { \
3094 TCGv t0; \
3095 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3096 int len = MEMOP_GET_SIZE(memop); \
3097 gen_set_access_type(ctx, ACCESS_RES); \
3098 t0 = tcg_temp_local_new(); \
3099 gen_addr_reg_index(ctx, t0); \
3100 if ((len) > 1) { \
3101 gen_check_align(ctx, t0, (len)-1); \
3102 } \
3103 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3104 tcg_gen_mov_tl(cpu_reserve, t0); \
3105 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3106 tcg_temp_free(t0); \
3107 }
3108
3109 /* lwarx */
3110 LARX(lbarx, DEF_MEMOP(MO_UB))
3111 LARX(lharx, DEF_MEMOP(MO_UW))
3112 LARX(lwarx, DEF_MEMOP(MO_UL))
3113
3114 #if defined(CONFIG_USER_ONLY)
3115 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3116 int reg, int memop)
3117 {
3118 TCGv t0 = tcg_temp_new();
3119
3120 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3121 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3122 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3123 tcg_temp_free(t0);
3124 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3125 }
3126 #else
3127 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3128 int reg, int memop)
3129 {
3130 TCGLabel *l1;
3131
3132 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3133 l1 = gen_new_label();
3134 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3135 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3136 tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
3137 gen_set_label(l1);
3138 tcg_gen_movi_tl(cpu_reserve, -1);
3139 }
3140 #endif
3141
3142 #define STCX(name, memop) \
3143 static void gen_##name(DisasContext *ctx) \
3144 { \
3145 TCGv t0; \
3146 int len = MEMOP_GET_SIZE(memop); \
3147 gen_set_access_type(ctx, ACCESS_RES); \
3148 t0 = tcg_temp_local_new(); \
3149 gen_addr_reg_index(ctx, t0); \
3150 if (len > 1) { \
3151 gen_check_align(ctx, t0, (len) - 1); \
3152 } \
3153 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3154 tcg_temp_free(t0); \
3155 }
3156
3157 STCX(stbcx_, DEF_MEMOP(MO_UB))
3158 STCX(sthcx_, DEF_MEMOP(MO_UW))
3159 STCX(stwcx_, DEF_MEMOP(MO_UL))
3160
3161 #if defined(TARGET_PPC64)
3162 /* ldarx */
3163 LARX(ldarx, DEF_MEMOP(MO_Q))
3164 /* stdcx. */
3165 STCX(stdcx_, DEF_MEMOP(MO_Q))
3166
3167 /* lqarx */
3168 static void gen_lqarx(DisasContext *ctx)
3169 {
3170 TCGv EA;
3171 int rd = rD(ctx->opcode);
3172 TCGv gpr1, gpr2;
3173
3174 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3175 (rd == rB(ctx->opcode)))) {
3176 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3177 return;
3178 }
3179
3180 gen_set_access_type(ctx, ACCESS_RES);
3181 EA = tcg_temp_local_new();
3182 gen_addr_reg_index(ctx, EA);
3183 gen_check_align(ctx, EA, 15);
3184 if (unlikely(ctx->le_mode)) {
3185 gpr1 = cpu_gpr[rd+1];
3186 gpr2 = cpu_gpr[rd];
3187 } else {
3188 gpr1 = cpu_gpr[rd];
3189 gpr2 = cpu_gpr[rd+1];
3190 }
3191 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3192 tcg_gen_mov_tl(cpu_reserve, EA);
3193 gen_addr_add(ctx, EA, EA, 8);
3194 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3195
3196 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3197 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3198 tcg_temp_free(EA);
3199 }
3200
3201 /* stqcx. */
3202 static void gen_stqcx_(DisasContext *ctx)
3203 {
3204 TCGv EA;
3205 int reg = rS(ctx->opcode);
3206 int len = 16;
3207 #if !defined(CONFIG_USER_ONLY)
3208 TCGLabel *l1;
3209 TCGv gpr1, gpr2;
3210 #endif
3211
3212 if (unlikely((rD(ctx->opcode) & 1))) {
3213 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3214 return;
3215 }
3216 gen_set_access_type(ctx, ACCESS_RES);
3217 EA = tcg_temp_local_new();
3218 gen_addr_reg_index(ctx, EA);
3219 if (len > 1) {
3220 gen_check_align(ctx, EA, (len) - 1);
3221 }
3222
3223 #if defined(CONFIG_USER_ONLY)
3224 gen_conditional_store(ctx, EA, reg, 16);
3225 #else
3226 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3227 l1 = gen_new_label();
3228 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3229 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3230
3231 if (unlikely(ctx->le_mode)) {
3232 gpr1 = cpu_gpr[reg + 1];
3233 gpr2 = cpu_gpr[reg];
3234 } else {
3235 gpr1 = cpu_gpr[reg];
3236 gpr2 = cpu_gpr[reg + 1];
3237 }
3238 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3239 gen_addr_add(ctx, EA, EA, 8);
3240 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3241
3242 gen_set_label(l1);
3243 tcg_gen_movi_tl(cpu_reserve, -1);
3244 #endif
3245 tcg_temp_free(EA);
3246 }
3247
3248 #endif /* defined(TARGET_PPC64) */
3249
3250 /* sync */
3251 static void gen_sync(DisasContext *ctx)
3252 {
3253 uint32_t l = (ctx->opcode >> 21) & 3;
3254
3255 /*
3256 * We may need to check for a pending TLB flush.
3257 *
3258 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3259 *
3260 * Additionally, this can only happen in kernel mode however so
3261 * check MSR_PR as well.
3262 */
3263 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3264 gen_check_tlb_flush(ctx, true);
3265 }
3266 }
3267
3268 /* wait */
3269 static void gen_wait(DisasContext *ctx)
3270 {
3271 TCGv_i32 t0 = tcg_const_i32(1);
3272 tcg_gen_st_i32(t0, cpu_env,
3273 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3274 tcg_temp_free_i32(t0);
3275 /* Stop translation, as the CPU is supposed to sleep from now */
3276 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3277 }
3278
3279 #if defined(TARGET_PPC64)
3280 static void gen_doze(DisasContext *ctx)
3281 {
3282 #if defined(CONFIG_USER_ONLY)
3283 GEN_PRIV;
3284 #else
3285 TCGv_i32 t;
3286
3287 CHK_HV;
3288 t = tcg_const_i32(PPC_PM_DOZE);
3289 gen_helper_pminsn(cpu_env, t);
3290 tcg_temp_free_i32(t);
3291 gen_stop_exception(ctx);
3292 #endif /* defined(CONFIG_USER_ONLY) */
3293 }
3294
3295 static void gen_nap(DisasContext *ctx)
3296 {
3297 #if defined(CONFIG_USER_ONLY)
3298 GEN_PRIV;
3299 #else
3300 TCGv_i32 t;
3301
3302 CHK_HV;
3303 t = tcg_const_i32(PPC_PM_NAP);
3304 gen_helper_pminsn(cpu_env, t);
3305 tcg_temp_free_i32(t);
3306 gen_stop_exception(ctx);
3307 #endif /* defined(CONFIG_USER_ONLY) */
3308 }
3309
3310 static void gen_sleep(DisasContext *ctx)
3311 {
3312 #if defined(CONFIG_USER_ONLY)
3313 GEN_PRIV;
3314 #else
3315 TCGv_i32 t;
3316
3317 CHK_HV;
3318 t = tcg_const_i32(PPC_PM_SLEEP);
3319 gen_helper_pminsn(cpu_env, t);
3320 tcg_temp_free_i32(t);
3321 gen_stop_exception(ctx);
3322 #endif /* defined(CONFIG_USER_ONLY) */
3323 }
3324
3325 static void gen_rvwinkle(DisasContext *ctx)
3326 {
3327 #if defined(CONFIG_USER_ONLY)
3328 GEN_PRIV;
3329 #else
3330 TCGv_i32 t;
3331
3332 CHK_HV;
3333 t = tcg_const_i32(PPC_PM_RVWINKLE);
3334 gen_helper_pminsn(cpu_env, t);
3335 tcg_temp_free_i32(t);
3336 gen_stop_exception(ctx);
3337 #endif /* defined(CONFIG_USER_ONLY) */
3338 }
3339 #endif /* #if defined(TARGET_PPC64) */
3340
3341 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3342 {
3343 #if defined(TARGET_PPC64)
3344 if (ctx->has_cfar)
3345 tcg_gen_movi_tl(cpu_cfar, nip);
3346 #endif
3347 }
3348
3349 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3350 {
3351 if (unlikely(ctx->singlestep_enabled)) {
3352 return false;
3353 }
3354
3355 #ifndef CONFIG_USER_ONLY
3356 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3357 #else
3358 return true;
3359 #endif
3360 }
3361
3362 /*** Branch ***/
3363 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3364 {
3365 if (NARROW_MODE(ctx)) {
3366 dest = (uint32_t) dest;
3367 }
3368 if (use_goto_tb(ctx, dest)) {
3369 tcg_gen_goto_tb(n);
3370 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3371 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3372 } else {
3373 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3374 if (unlikely(ctx->singlestep_enabled)) {
3375 if ((ctx->singlestep_enabled &
3376 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3377 (ctx->exception == POWERPC_EXCP_BRANCH ||
3378 ctx->exception == POWERPC_EXCP_TRACE)) {
3379 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3380 }
3381 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3382 gen_debug_exception(ctx);
3383 }
3384 }
3385 tcg_gen_exit_tb(0);
3386 }
3387 }
3388
3389 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3390 {
3391 if (NARROW_MODE(ctx)) {
3392 nip = (uint32_t)nip;
3393 }
3394 tcg_gen_movi_tl(cpu_lr, nip);
3395 }
3396
3397 /* b ba bl bla */
3398 static void gen_b(DisasContext *ctx)
3399 {
3400 target_ulong li, target;
3401
3402 ctx->exception = POWERPC_EXCP_BRANCH;
3403 /* sign extend LI */
3404 li = LI(ctx->opcode);
3405 li = (li ^ 0x02000000) - 0x02000000;
3406 if (likely(AA(ctx->opcode) == 0)) {
3407 target = ctx->nip + li - 4;
3408 } else {
3409 target = li;
3410 }
3411 if (LK(ctx->opcode)) {
3412 gen_setlr(ctx, ctx->nip);
3413 }
3414 gen_update_cfar(ctx, ctx->nip - 4);
3415 gen_goto_tb(ctx, 0, target);
3416 }
3417
3418 #define BCOND_IM 0
3419 #define BCOND_LR 1
3420 #define BCOND_CTR 2
3421 #define BCOND_TAR 3
3422
3423 static inline void gen_bcond(DisasContext *ctx, int type)
3424 {
3425 uint32_t bo = BO(ctx->opcode);
3426 TCGLabel *l1;
3427 TCGv target;
3428
3429 ctx->exception = POWERPC_EXCP_BRANCH;
3430 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3431 target = tcg_temp_local_new();
3432 if (type == BCOND_CTR)
3433 tcg_gen_mov_tl(target, cpu_ctr);
3434 else if (type == BCOND_TAR)
3435 gen_load_spr(target, SPR_TAR);
3436 else
3437 tcg_gen_mov_tl(target, cpu_lr);
3438 } else {
3439 TCGV_UNUSED(target);
3440 }
3441 if (LK(ctx->opcode))
3442 gen_setlr(ctx, ctx->nip);
3443 l1 = gen_new_label();
3444 if ((bo & 0x4) == 0) {
3445 /* Decrement and test CTR */
3446 TCGv temp = tcg_temp_new();
3447 if (unlikely(type == BCOND_CTR)) {
3448 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3449 return;
3450 }
3451 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3452 if (NARROW_MODE(ctx)) {
3453 tcg_gen_ext32u_tl(temp, cpu_ctr);
3454 } else {
3455 tcg_gen_mov_tl(temp, cpu_ctr);
3456 }
3457 if (bo & 0x2) {
3458 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3459 } else {
3460 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3461 }
3462 tcg_temp_free(temp);
3463 }
3464 if ((bo & 0x10) == 0) {
3465 /* Test CR */
3466 uint32_t bi = BI(ctx->opcode);
3467 uint32_t mask = 0x08 >> (bi & 0x03);
3468 TCGv_i32 temp = tcg_temp_new_i32();
3469
3470 if (bo & 0x8) {
3471 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3472 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3473 } else {
3474 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3475 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3476 }
3477 tcg_temp_free_i32(temp);
3478 }
3479 gen_update_cfar(ctx, ctx->nip - 4);
3480 if (type == BCOND_IM) {
3481 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3482 if (likely(AA(ctx->opcode) == 0)) {
3483 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3484 } else {
3485 gen_goto_tb(ctx, 0, li);
3486 }
3487 if ((bo & 0x14) != 0x14) {
3488 gen_set_label(l1);
3489 gen_goto_tb(ctx, 1, ctx->nip);
3490 }
3491 } else {
3492 if (NARROW_MODE(ctx)) {
3493 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3494 } else {
3495 tcg_gen_andi_tl(cpu_nip, target, ~3);
3496 }
3497 tcg_gen_exit_tb(0);
3498 if ((bo & 0x14) != 0x14) {
3499 gen_set_label(l1);
3500 gen_update_nip(ctx, ctx->nip);
3501 tcg_gen_exit_tb(0);
3502 }
3503 }
3504 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3505 tcg_temp_free(target);
3506 }
3507 }
3508
3509 static void gen_bc(DisasContext *ctx)
3510 {
3511 gen_bcond(ctx, BCOND_IM);
3512 }
3513
3514 static void gen_bcctr(DisasContext *ctx)
3515 {
3516 gen_bcond(ctx, BCOND_CTR);
3517 }
3518
3519 static void gen_bclr(DisasContext *ctx)
3520 {
3521 gen_bcond(ctx, BCOND_LR);
3522 }
3523
3524 static void gen_bctar(DisasContext *ctx)
3525 {
3526 gen_bcond(ctx, BCOND_TAR);
3527 }
3528
3529 /*** Condition register logical ***/
3530 #define GEN_CRLOGIC(name, tcg_op, opc) \
3531 static void glue(gen_, name)(DisasContext *ctx) \
3532 { \
3533 uint8_t bitmask; \
3534 int sh; \
3535 TCGv_i32 t0, t1; \
3536 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3537 t0 = tcg_temp_new_i32(); \
3538 if (sh > 0) \
3539 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3540 else if (sh < 0) \
3541 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3542 else \
3543 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3544 t1 = tcg_temp_new_i32(); \
3545 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3546 if (sh > 0) \
3547 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3548 else if (sh < 0) \
3549 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3550 else \
3551 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3552 tcg_op(t0, t0, t1); \
3553 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3554 tcg_gen_andi_i32(t0, t0, bitmask); \
3555 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3556 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3557 tcg_temp_free_i32(t0); \
3558 tcg_temp_free_i32(t1); \
3559 }
3560
3561 /* crand */
3562 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3563 /* crandc */
3564 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3565 /* creqv */
3566 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3567 /* crnand */
3568 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3569 /* crnor */
3570 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3571 /* cror */
3572 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3573 /* crorc */
3574 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3575 /* crxor */
3576 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3577
3578 /* mcrf */
3579 static void gen_mcrf(DisasContext *ctx)
3580 {
3581 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3582 }
3583
3584 /*** System linkage ***/
3585
3586 /* rfi (supervisor only) */
3587 static void gen_rfi(DisasContext *ctx)
3588 {
3589 #if defined(CONFIG_USER_ONLY)
3590 GEN_PRIV;
3591 #else
3592 /* This instruction doesn't exist anymore on 64-bit server
3593 * processors compliant with arch 2.x
3594 */
3595 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3596 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3597 return;
3598 }
3599 /* Restore CPU state */
3600 CHK_SV;
3601 gen_update_cfar(ctx, ctx->nip - 4);
3602 gen_helper_rfi(cpu_env);
3603 gen_sync_exception(ctx);
3604 #endif
3605 }
3606
3607 #if defined(TARGET_PPC64)
3608 static void gen_rfid(DisasContext *ctx)
3609 {
3610 #if defined(CONFIG_USER_ONLY)
3611 GEN_PRIV;
3612 #else
3613 /* Restore CPU state */
3614 CHK_SV;
3615 gen_update_cfar(ctx, ctx->nip - 4);
3616 gen_helper_rfid(cpu_env);
3617 gen_sync_exception(ctx);
3618 #endif
3619 }
3620
3621 static void gen_hrfid(DisasContext *ctx)
3622 {
3623 #if defined(CONFIG_USER_ONLY)
3624 GEN_PRIV;
3625 #else
3626 /* Restore CPU state */
3627 CHK_HV;
3628 gen_helper_hrfid(cpu_env);
3629 gen_sync_exception(ctx);
3630 #endif
3631 }
3632 #endif
3633
3634 /* sc */
3635 #if defined(CONFIG_USER_ONLY)
3636 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3637 #else
3638 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3639 #endif
3640 static void gen_sc(DisasContext *ctx)
3641 {
3642 uint32_t lev;
3643
3644 lev = (ctx->opcode >> 5) & 0x7F;
3645 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3646 }
3647
3648 /*** Trap ***/
3649
3650 /* Check for unconditional traps (always or never) */
3651 static bool check_unconditional_trap(DisasContext *ctx)
3652 {
3653 /* Trap never */
3654 if (TO(ctx->opcode) == 0) {
3655 return true;
3656 }
3657 /* Trap always */
3658 if (TO(ctx->opcode) == 31) {
3659 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3660 return true;
3661 }
3662 return false;
3663 }
3664
3665 /* tw */
3666 static void gen_tw(DisasContext *ctx)
3667 {
3668 TCGv_i32 t0;
3669
3670 if (check_unconditional_trap(ctx)) {
3671 return;
3672 }
3673 t0 = tcg_const_i32(TO(ctx->opcode));
3674 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3675 t0);
3676 tcg_temp_free_i32(t0);
3677 }
3678
3679 /* twi */
3680 static void gen_twi(DisasContext *ctx)
3681 {
3682 TCGv t0;
3683 TCGv_i32 t1;
3684
3685 if (check_unconditional_trap(ctx)) {
3686 return;
3687 }
3688 t0 = tcg_const_tl(SIMM(ctx->opcode));
3689 t1 = tcg_const_i32(TO(ctx->opcode));
3690 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3691 tcg_temp_free(t0);
3692 tcg_temp_free_i32(t1);
3693 }
3694
3695 #if defined(TARGET_PPC64)
3696 /* td */
3697 static void gen_td(DisasContext *ctx)
3698 {
3699 TCGv_i32 t0;
3700
3701 if (check_unconditional_trap(ctx)) {
3702 return;
3703 }
3704 t0 = tcg_const_i32(TO(ctx->opcode));
3705 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3706 t0);
3707 tcg_temp_free_i32(t0);
3708 }
3709
3710 /* tdi */
3711 static void gen_tdi(DisasContext *ctx)
3712 {
3713 TCGv t0;
3714 TCGv_i32 t1;
3715
3716 if (check_unconditional_trap(ctx)) {
3717 return;
3718 }
3719 t0 = tcg_const_tl(SIMM(ctx->opcode));
3720 t1 = tcg_const_i32(TO(ctx->opcode));
3721 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3722 tcg_temp_free(t0);
3723 tcg_temp_free_i32(t1);
3724 }
3725 #endif
3726
3727 /*** Processor control ***/
3728
3729 static void gen_read_xer(TCGv dst)
3730 {
3731 TCGv t0 = tcg_temp_new();
3732 TCGv t1 = tcg_temp_new();
3733 TCGv t2 = tcg_temp_new();
3734 tcg_gen_mov_tl(dst, cpu_xer);
3735 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3736 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3737 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3738 tcg_gen_or_tl(t0, t0, t1);
3739 tcg_gen_or_tl(dst, dst, t2);
3740 tcg_gen_or_tl(dst, dst, t0);
3741 tcg_temp_free(t0);
3742 tcg_temp_free(t1);
3743 tcg_temp_free(t2);
3744 }
3745
3746 static void gen_write_xer(TCGv src)
3747 {
3748 tcg_gen_andi_tl(cpu_xer, src,
3749 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3750 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3751 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3752 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3753 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3754 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3755 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3756 }
3757
3758 /* mcrxr */
3759 static void gen_mcrxr(DisasContext *ctx)
3760 {
3761 TCGv_i32 t0 = tcg_temp_new_i32();
3762 TCGv_i32 t1 = tcg_temp_new_i32();
3763 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3764
3765 tcg_gen_trunc_tl_i32(t0, cpu_so);
3766 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3767 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3768 tcg_gen_shli_i32(t0, t0, 3);
3769 tcg_gen_shli_i32(t1, t1, 2);
3770 tcg_gen_shli_i32(dst, dst, 1);
3771 tcg_gen_or_i32(dst, dst, t0);
3772 tcg_gen_or_i32(dst, dst, t1);
3773 tcg_temp_free_i32(t0);
3774 tcg_temp_free_i32(t1);
3775
3776 tcg_gen_movi_tl(cpu_so, 0);
3777 tcg_gen_movi_tl(cpu_ov, 0);
3778 tcg_gen_movi_tl(cpu_ca, 0);
3779 }
3780
3781 /* mfcr mfocrf */
3782 static void gen_mfcr(DisasContext *ctx)
3783 {
3784 uint32_t crm, crn;
3785
3786 if (likely(ctx->opcode & 0x00100000)) {
3787 crm = CRM(ctx->opcode);
3788 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3789 crn = ctz32 (crm);
3790 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3791 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3792 cpu_gpr[rD(ctx->opcode)], crn * 4);
3793 }
3794 } else {
3795 TCGv_i32 t0 = tcg_temp_new_i32();
3796 tcg_gen_mov_i32(t0, cpu_crf[0]);
3797 tcg_gen_shli_i32(t0, t0, 4);
3798 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3799 tcg_gen_shli_i32(t0, t0, 4);
3800 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3801 tcg_gen_shli_i32(t0, t0, 4);
3802 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3803 tcg_gen_shli_i32(t0, t0, 4);
3804 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3805 tcg_gen_shli_i32(t0, t0, 4);
3806 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3807 tcg_gen_shli_i32(t0, t0, 4);
3808 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3809 tcg_gen_shli_i32(t0, t0, 4);
3810 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3811 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3812 tcg_temp_free_i32(t0);
3813 }
3814 }
3815
3816 /* mfmsr */
3817 static void gen_mfmsr(DisasContext *ctx)
3818 {
3819 CHK_SV;
3820 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3821 }
3822
3823 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3824 {
3825 #if 0
3826 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3827 printf("ERROR: try to access SPR %d !\n", sprn);
3828 #endif
3829 }
3830 #define SPR_NOACCESS (&spr_noaccess)
3831
3832 /* mfspr */
3833 static inline void gen_op_mfspr(DisasContext *ctx)
3834 {
3835 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3836 uint32_t sprn = SPR(ctx->opcode);
3837
3838 #if defined(CONFIG_USER_ONLY)
3839 read_cb = ctx->spr_cb[sprn].uea_read;
3840 #else
3841 if (ctx->pr) {
3842 read_cb = ctx->spr_cb[sprn].uea_read;
3843 } else if (ctx->hv) {
3844 read_cb = ctx->spr_cb[sprn].hea_read;
3845 } else {
3846 read_cb = ctx->spr_cb[sprn].oea_read;
3847 }
3848 #endif
3849 if (likely(read_cb != NULL)) {
3850 if (likely(read_cb != SPR_NOACCESS)) {
3851 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3852 } else {
3853 /* Privilege exception */
3854 /* This is a hack to avoid warnings when running Linux:
3855 * this OS breaks the PowerPC virtualisation model,
3856 * allowing userland application to read the PVR
3857 */
3858 if (sprn != SPR_PVR) {
3859 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3860 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3861 if (qemu_log_separate()) {
3862 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3863 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3864 }
3865 }
3866 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3867 }
3868 } else {
3869 /* ISA 2.07 defines these as no-ops */
3870 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3871 (sprn >= 808 && sprn <= 811)) {
3872 /* This is a nop */
3873 return;
3874 }
3875 /* Not defined */
3876 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3877 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3878 if (qemu_log_separate()) {
3879 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3880 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3881 }
3882
3883 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3884 * it can generate a priv, a hv emu or a no-op
3885 */
3886 if (sprn & 0x10) {
3887 if (ctx->pr) {
3888 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3889 }
3890 } else {
3891 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3892 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3893 }
3894 }
3895 }
3896 }
3897
3898 static void gen_mfspr(DisasContext *ctx)
3899 {
3900 gen_op_mfspr(ctx);
3901 }
3902
3903 /* mftb */
3904 static void gen_mftb(DisasContext *ctx)
3905 {
3906 gen_op_mfspr(ctx);
3907 }
3908
3909 /* mtcrf mtocrf*/
3910 static void gen_mtcrf(DisasContext *ctx)
3911 {
3912 uint32_t crm, crn;
3913
3914 crm = CRM(ctx->opcode);
3915 if (likely((ctx->opcode & 0x00100000))) {
3916 if (crm && ((crm & (crm - 1)) == 0)) {
3917 TCGv_i32 temp = tcg_temp_new_i32();
3918 crn = ctz32 (crm);
3919 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3920 tcg_gen_shri_i32(temp, temp, crn * 4);
3921 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3922 tcg_temp_free_i32(temp);
3923 }
3924 } else {
3925 TCGv_i32 temp = tcg_temp_new_i32();
3926 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3927 for (crn = 0 ; crn < 8 ; crn++) {
3928 if (crm & (1 << crn)) {
3929 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3930 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3931 }
3932 }
3933 tcg_temp_free_i32(temp);
3934 }
3935 }
3936
3937 /* mtmsr */
3938 #if defined(TARGET_PPC64)
3939 static void gen_mtmsrd(DisasContext *ctx)
3940 {
3941 CHK_SV;
3942
3943 #if !defined(CONFIG_USER_ONLY)
3944 if (ctx->opcode & 0x00010000) {
3945 /* Special form that does not need any synchronisation */
3946 TCGv t0 = tcg_temp_new();
3947 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3948 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3949 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3950 tcg_temp_free(t0);
3951 } else {
3952 /* XXX: we need to update nip before the store
3953 * if we enter power saving mode, we will exit the loop
3954 * directly from ppc_store_msr
3955 */
3956 gen_update_nip(ctx, ctx->nip);
3957 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3958 /* Must stop the translation as machine state (may have) changed */
3959 /* Note that mtmsr is not always defined as context-synchronizing */
3960 gen_stop_exception(ctx);
3961 }
3962 #endif /* !defined(CONFIG_USER_ONLY) */
3963 }
3964 #endif /* defined(TARGET_PPC64) */
3965
3966 static void gen_mtmsr(DisasContext *ctx)
3967 {
3968 CHK_SV;
3969
3970 #if !defined(CONFIG_USER_ONLY)
3971 if (ctx->opcode & 0x00010000) {
3972 /* Special form that does not need any synchronisation */
3973 TCGv t0 = tcg_temp_new();
3974 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3975 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3976 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3977 tcg_temp_free(t0);
3978 } else {
3979 TCGv msr = tcg_temp_new();
3980
3981 /* XXX: we need to update nip before the store
3982 * if we enter power saving mode, we will exit the loop
3983 * directly from ppc_store_msr
3984 */
3985 gen_update_nip(ctx, ctx->nip);
3986 #if defined(TARGET_PPC64)
3987 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3988 #else
3989 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3990 #endif
3991 gen_helper_store_msr(cpu_env, msr);
3992 tcg_temp_free(msr);
3993 /* Must stop the translation as machine state (may have) changed */
3994 /* Note that mtmsr is not always defined as context-synchronizing */
3995 gen_stop_exception(ctx);
3996 }
3997 #endif
3998 }
3999
4000 /* mtspr */
4001 static void gen_mtspr(DisasContext *ctx)
4002 {
4003 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4004 uint32_t sprn = SPR(ctx->opcode);
4005
4006 #if defined(CONFIG_USER_ONLY)
4007 write_cb = ctx->spr_cb[sprn].uea_write;
4008 #else
4009 if (ctx->pr) {
4010 write_cb = ctx->spr_cb[sprn].uea_write;
4011 } else if (ctx->hv) {
4012 write_cb = ctx->spr_cb[sprn].hea_write;
4013 } else {
4014 write_cb = ctx->spr_cb[sprn].oea_write;
4015 }
4016 #endif
4017 if (likely(write_cb != NULL)) {
4018 if (likely(write_cb != SPR_NOACCESS)) {
4019 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4020 } else {
4021 /* Privilege exception */
4022 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4023 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4024 if (qemu_log_separate()) {
4025 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4026 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4027 }
4028 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4029 }
4030 } else {
4031 /* ISA 2.07 defines these as no-ops */
4032 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4033 (sprn >= 808 && sprn <= 811)) {
4034 /* This is a nop */
4035 return;
4036 }
4037
4038 /* Not defined */
4039 if (qemu_log_separate()) {
4040 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4041 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4042 }
4043 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4044 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4045
4046
4047 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4048 * it can generate a priv, a hv emu or a no-op
4049 */
4050 if (sprn & 0x10) {
4051 if (ctx->pr) {
4052 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4053 }
4054 } else {
4055 if (ctx->pr || sprn == 0) {
4056 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4057 }
4058 }
4059 }
4060 }
4061
4062 #if defined(TARGET_PPC64)
4063 /* setb */
4064 static void gen_setb(DisasContext *ctx)
4065 {
4066 TCGv_i32 t0 = tcg_temp_new_i32();
4067 TCGv_i32 t8 = tcg_temp_new_i32();
4068 TCGv_i32 tm1 = tcg_temp_new_i32();
4069 int crf = crfS(ctx->opcode);
4070
4071 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4072 tcg_gen_movi_i32(t8, 8);
4073 tcg_gen_movi_i32(tm1, -1);
4074 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4075 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4076
4077 tcg_temp_free_i32(t0);
4078 tcg_temp_free_i32(t8);
4079 tcg_temp_free_i32(tm1);
4080 }
4081 #endif
4082
4083 /*** Cache management ***/
4084
4085 /* dcbf */
4086 static void gen_dcbf(DisasContext *ctx)
4087 {
4088 /* XXX: specification says this is treated as a load by the MMU */
4089 TCGv t0;
4090 gen_set_access_type(ctx, ACCESS_CACHE);
4091 t0 = tcg_temp_new();
4092 gen_addr_reg_index(ctx, t0);
4093 gen_qemu_ld8u(ctx, t0, t0);
4094 tcg_temp_free(t0);
4095 }
4096
4097 /* dcbi (Supervisor only) */
4098 static void gen_dcbi(DisasContext *ctx)
4099 {
4100 #if defined(CONFIG_USER_ONLY)
4101 GEN_PRIV;
4102 #else
4103 TCGv EA, val;
4104
4105 CHK_SV;
4106 EA = tcg_temp_new();
4107 gen_set_access_type(ctx, ACCESS_CACHE);
4108 gen_addr_reg_index(ctx, EA);
4109 val = tcg_temp_new();
4110 /* XXX: specification says this should be treated as a store by the MMU */
4111 gen_qemu_ld8u(ctx, val, EA);
4112 gen_qemu_st8(ctx, val, EA);
4113 tcg_temp_free(val);
4114 tcg_temp_free(EA);
4115 #endif /* defined(CONFIG_USER_ONLY) */
4116 }
4117
4118 /* dcdst */
4119 static void gen_dcbst(DisasContext *ctx)
4120 {
4121 /* XXX: specification say this is treated as a load by the MMU */
4122 TCGv t0;
4123 gen_set_access_type(ctx, ACCESS_CACHE);
4124 t0 = tcg_temp_new();
4125 gen_addr_reg_index(ctx, t0);
4126 gen_qemu_ld8u(ctx, t0, t0);
4127 tcg_temp_free(t0);
4128 }
4129
4130 /* dcbt */
4131 static void gen_dcbt(DisasContext *ctx)
4132 {
4133 /* interpreted as no-op */
4134 /* XXX: specification say this is treated as a load by the MMU
4135 * but does not generate any exception
4136 */
4137 }
4138
4139 /* dcbtst */
4140 static void gen_dcbtst(DisasContext *ctx)
4141 {
4142 /* interpreted as no-op */
4143 /* XXX: specification say this is treated as a load by the MMU
4144 * but does not generate any exception
4145 */
4146 }
4147
4148 /* dcbtls */
4149 static void gen_dcbtls(DisasContext *ctx)
4150 {
4151 /* Always fails locking the cache */
4152 TCGv t0 = tcg_temp_new();
4153 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4154 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4155 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4156 tcg_temp_free(t0);
4157 }
4158
4159 /* dcbz */
4160 static void gen_dcbz(DisasContext *ctx)
4161 {
4162 TCGv tcgv_addr;
4163 TCGv_i32 tcgv_op;
4164
4165 gen_set_access_type(ctx, ACCESS_CACHE);
4166 tcgv_addr = tcg_temp_new();
4167 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4168 gen_addr_reg_index(ctx, tcgv_addr);
4169 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4170 tcg_temp_free(tcgv_addr);
4171 tcg_temp_free_i32(tcgv_op);
4172 }
4173
4174 /* dst / dstt */
4175 static void gen_dst(DisasContext *ctx)
4176 {
4177 if (rA(ctx->opcode) == 0) {
4178 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4179 } else {
4180 /* interpreted as no-op */
4181 }
4182 }
4183
4184 /* dstst /dststt */
4185 static void gen_dstst(DisasContext *ctx)
4186 {
4187 if (rA(ctx->opcode) == 0) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4189 } else {
4190 /* interpreted as no-op */
4191 }
4192
4193 }
4194
4195 /* dss / dssall */
4196 static void gen_dss(DisasContext *ctx)
4197 {
4198 /* interpreted as no-op */
4199 }
4200
4201 /* icbi */
4202 static void gen_icbi(DisasContext *ctx)
4203 {
4204 TCGv t0;
4205 gen_set_access_type(ctx, ACCESS_CACHE);
4206 t0 = tcg_temp_new();
4207 gen_addr_reg_index(ctx, t0);
4208 gen_helper_icbi(cpu_env, t0);
4209 tcg_temp_free(t0);
4210 }
4211
4212 /* Optional: */
4213 /* dcba */
4214 static void gen_dcba(DisasContext *ctx)
4215 {
4216 /* interpreted as no-op */
4217 /* XXX: specification say this is treated as a store by the MMU
4218 * but does not generate any exception
4219 */
4220 }
4221
4222 /*** Segment register manipulation ***/
4223 /* Supervisor only: */
4224
4225 /* mfsr */
4226 static void gen_mfsr(DisasContext *ctx)
4227 {
4228 #if defined(CONFIG_USER_ONLY)
4229 GEN_PRIV;
4230 #else
4231 TCGv t0;
4232
4233 CHK_SV;
4234 t0 = tcg_const_tl(SR(ctx->opcode));
4235 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4236 tcg_temp_free(t0);
4237 #endif /* defined(CONFIG_USER_ONLY) */
4238 }
4239
4240 /* mfsrin */
4241 static void gen_mfsrin(DisasContext *ctx)
4242 {
4243 #if defined(CONFIG_USER_ONLY)
4244 GEN_PRIV;
4245 #else
4246 TCGv t0;
4247
4248 CHK_SV;
4249 t0 = tcg_temp_new();
4250 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4251 tcg_gen_andi_tl(t0, t0, 0xF);
4252 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4253 tcg_temp_free(t0);
4254 #endif /* defined(CONFIG_USER_ONLY) */
4255 }
4256
4257 /* mtsr */
4258 static void gen_mtsr(DisasContext *ctx)
4259 {
4260 #if defined(CONFIG_USER_ONLY)
4261 GEN_PRIV;
4262 #else
4263 TCGv t0;
4264
4265 CHK_SV;
4266 t0 = tcg_const_tl(SR(ctx->opcode));
4267 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4268 tcg_temp_free(t0);
4269 #endif /* defined(CONFIG_USER_ONLY) */
4270 }
4271
4272 /* mtsrin */
4273 static void gen_mtsrin(DisasContext *ctx)
4274 {
4275 #if defined(CONFIG_USER_ONLY)
4276 GEN_PRIV;
4277 #else
4278 TCGv t0;
4279 CHK_SV;
4280
4281 t0 = tcg_temp_new();
4282 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4283 tcg_gen_andi_tl(t0, t0, 0xF);
4284 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4285 tcg_temp_free(t0);
4286 #endif /* defined(CONFIG_USER_ONLY) */
4287 }
4288
4289 #if defined(TARGET_PPC64)
4290 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4291
4292 /* mfsr */
4293 static void gen_mfsr_64b(DisasContext *ctx)
4294 {
4295 #if defined(CONFIG_USER_ONLY)
4296 GEN_PRIV;
4297 #else
4298 TCGv t0;
4299
4300 CHK_SV;
4301 t0 = tcg_const_tl(SR(ctx->opcode));
4302 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4303 tcg_temp_free(t0);
4304 #endif /* defined(CONFIG_USER_ONLY) */
4305 }
4306
4307 /* mfsrin */
4308 static void gen_mfsrin_64b(DisasContext *ctx)
4309 {
4310 #if defined(CONFIG_USER_ONLY)
4311 GEN_PRIV;
4312 #else
4313 TCGv t0;
4314
4315 CHK_SV;
4316 t0 = tcg_temp_new();
4317 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4318 tcg_gen_andi_tl(t0, t0, 0xF);
4319 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4320 tcg_temp_free(t0);
4321 #endif /* defined(CONFIG_USER_ONLY) */
4322 }
4323
4324 /* mtsr */
4325 static void gen_mtsr_64b(DisasContext *ctx)
4326 {
4327 #if defined(CONFIG_USER_ONLY)
4328 GEN_PRIV;
4329 #else
4330 TCGv t0;
4331
4332 CHK_SV;
4333 t0 = tcg_const_tl(SR(ctx->opcode));
4334 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4335 tcg_temp_free(t0);
4336 #endif /* defined(CONFIG_USER_ONLY) */
4337 }
4338
4339 /* mtsrin */
4340 static void gen_mtsrin_64b(DisasContext *ctx)
4341 {
4342 #if defined(CONFIG_USER_ONLY)
4343 GEN_PRIV;
4344 #else
4345 TCGv t0;
4346
4347 CHK_SV;
4348 t0 = tcg_temp_new();
4349 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4350 tcg_gen_andi_tl(t0, t0, 0xF);
4351 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4352 tcg_temp_free(t0);
4353 #endif /* defined(CONFIG_USER_ONLY) */
4354 }
4355
4356 /* slbmte */
4357 static void gen_slbmte(DisasContext *ctx)
4358 {
4359 #if defined(CONFIG_USER_ONLY)
4360 GEN_PRIV;
4361 #else
4362 CHK_SV;
4363
4364 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4365 cpu_gpr[rS(ctx->opcode)]);
4366 #endif /* defined(CONFIG_USER_ONLY) */
4367 }
4368
4369 static void gen_slbmfee(DisasContext *ctx)
4370 {
4371 #if defined(CONFIG_USER_ONLY)
4372 GEN_PRIV;
4373 #else
4374 CHK_SV;
4375
4376 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4377 cpu_gpr[rB(ctx->opcode)]);
4378 #endif /* defined(CONFIG_USER_ONLY) */
4379 }
4380
4381 static void gen_slbmfev(DisasContext *ctx)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 GEN_PRIV;
4385 #else
4386 CHK_SV;
4387
4388 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4389 cpu_gpr[rB(ctx->opcode)]);
4390 #endif /* defined(CONFIG_USER_ONLY) */
4391 }
4392
4393 static void gen_slbfee_(DisasContext *ctx)
4394 {
4395 #if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4397 #else
4398 TCGLabel *l1, *l2;
4399
4400 if (unlikely(ctx->pr)) {
4401 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4402 return;
4403 }
4404 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4405 cpu_gpr[rB(ctx->opcode)]);
4406 l1 = gen_new_label();
4407 l2 = gen_new_label();
4408 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4409 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4410 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4411 tcg_gen_br(l2);
4412 gen_set_label(l1);
4413 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4414 gen_set_label(l2);
4415 #endif
4416 }
4417 #endif /* defined(TARGET_PPC64) */
4418
4419 /*** Lookaside buffer management ***/
4420 /* Optional & supervisor only: */
4421
4422 /* tlbia */
4423 static void gen_tlbia(DisasContext *ctx)
4424 {
4425 #if defined(CONFIG_USER_ONLY)
4426 GEN_PRIV;
4427 #else
4428 CHK_HV;
4429
4430 gen_helper_tlbia(cpu_env);
4431 #endif /* defined(CONFIG_USER_ONLY) */
4432 }
4433
4434 /* tlbiel */
4435 static void gen_tlbiel(DisasContext *ctx)
4436 {
4437 #if defined(CONFIG_USER_ONLY)
4438 GEN_PRIV;
4439 #else
4440 CHK_SV;
4441
4442 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4443 #endif /* defined(CONFIG_USER_ONLY) */
4444 }
4445
4446 /* tlbie */
4447 static void gen_tlbie(DisasContext *ctx)
4448 {
4449 #if defined(CONFIG_USER_ONLY)
4450 GEN_PRIV;
4451 #else
4452 TCGv_i32 t1;
4453 CHK_HV;
4454
4455 if (NARROW_MODE(ctx)) {
4456 TCGv t0 = tcg_temp_new();
4457 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4458 gen_helper_tlbie(cpu_env, t0);
4459 tcg_temp_free(t0);
4460 } else {
4461 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4462 }
4463 t1 = tcg_temp_new_i32();
4464 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4465 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4466 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4467 tcg_temp_free_i32(t1);
4468 #endif /* defined(CONFIG_USER_ONLY) */
4469 }
4470
4471 /* tlbsync */
4472 static void gen_tlbsync(DisasContext *ctx)
4473 {
4474 #if defined(CONFIG_USER_ONLY)
4475 GEN_PRIV;
4476 #else
4477 CHK_HV;
4478
4479 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4480 if (ctx->insns_flags & PPC_BOOKE) {
4481 gen_check_tlb_flush(ctx, true);
4482 }
4483 #endif /* defined(CONFIG_USER_ONLY) */
4484 }
4485
4486 #if defined(TARGET_PPC64)
4487 /* slbia */
4488 static void gen_slbia(DisasContext *ctx)
4489 {
4490 #if defined(CONFIG_USER_ONLY)
4491 GEN_PRIV;
4492 #else
4493 CHK_SV;
4494
4495 gen_helper_slbia(cpu_env);
4496 #endif /* defined(CONFIG_USER_ONLY) */
4497 }
4498
4499 /* slbie */
4500 static void gen_slbie(DisasContext *ctx)
4501 {
4502 #if defined(CONFIG_USER_ONLY)
4503 GEN_PRIV;
4504 #else
4505 CHK_SV;
4506
4507 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4508 #endif /* defined(CONFIG_USER_ONLY) */
4509 }
4510 #endif /* defined(TARGET_PPC64) */
4511
4512 /*** External control ***/
4513 /* Optional: */
4514
4515 /* eciwx */
4516 static void gen_eciwx(DisasContext *ctx)
4517 {
4518 TCGv t0;
4519 /* Should check EAR[E] ! */
4520 gen_set_access_type(ctx, ACCESS_EXT);
4521 t0 = tcg_temp_new();
4522 gen_addr_reg_index(ctx, t0);
4523 gen_check_align(ctx, t0, 0x03);
4524 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4525 tcg_temp_free(t0);
4526 }
4527
4528 /* ecowx */
4529 static void gen_ecowx(DisasContext *ctx)
4530 {
4531 TCGv t0;
4532 /* Should check EAR[E] ! */
4533 gen_set_access_type(ctx, ACCESS_EXT);
4534 t0 = tcg_temp_new();
4535 gen_addr_reg_index(ctx, t0);
4536 gen_check_align(ctx, t0, 0x03);
4537 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4538 tcg_temp_free(t0);
4539 }
4540
4541 /* PowerPC 601 specific instructions */
4542
4543 /* abs - abs. */
4544 static void gen_abs(DisasContext *ctx)
4545 {
4546 TCGLabel *l1 = gen_new_label();
4547 TCGLabel *l2 = gen_new_label();
4548 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4549 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4550 tcg_gen_br(l2);
4551 gen_set_label(l1);
4552 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4553 gen_set_label(l2);
4554 if (unlikely(Rc(ctx->opcode) != 0))
4555 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4556 }
4557
4558 /* abso - abso. */
4559 static void gen_abso(DisasContext *ctx)
4560 {
4561 TCGLabel *l1 = gen_new_label();
4562 TCGLabel *l2 = gen_new_label();
4563 TCGLabel *l3 = gen_new_label();
4564 /* Start with XER OV disabled, the most likely case */
4565 tcg_gen_movi_tl(cpu_ov, 0);
4566 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4567 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4568 tcg_gen_movi_tl(cpu_ov, 1);
4569 tcg_gen_movi_tl(cpu_so, 1);
4570 tcg_gen_br(l2);
4571 gen_set_label(l1);
4572 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4573 tcg_gen_br(l3);
4574 gen_set_label(l2);
4575 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4576 gen_set_label(l3);
4577 if (unlikely(Rc(ctx->opcode) != 0))
4578 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4579 }
4580
4581 /* clcs */
4582 static void gen_clcs(DisasContext *ctx)
4583 {
4584 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4585 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4586 tcg_temp_free_i32(t0);
4587 /* Rc=1 sets CR0 to an undefined state */
4588 }
4589
4590 /* div - div. */
4591 static void gen_div(DisasContext *ctx)
4592 {
4593 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4594 cpu_gpr[rB(ctx->opcode)]);
4595 if (unlikely(Rc(ctx->opcode) != 0))
4596 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4597 }
4598
4599 /* divo - divo. */
4600 static void gen_divo(DisasContext *ctx)
4601 {
4602 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4603 cpu_gpr[rB(ctx->opcode)]);
4604 if (unlikely(Rc(ctx->opcode) != 0))
4605 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4606 }
4607
4608 /* divs - divs. */
4609 static void gen_divs(DisasContext *ctx)
4610 {
4611 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4612 cpu_gpr[rB(ctx->opcode)]);
4613 if (unlikely(Rc(ctx->opcode) != 0))
4614 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4615 }
4616
4617 /* divso - divso. */
4618 static void gen_divso(DisasContext *ctx)
4619 {
4620 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4621 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4622 if (unlikely(Rc(ctx->opcode) != 0))
4623 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4624 }
4625
4626 /* doz - doz. */
4627 static void gen_doz(DisasContext *ctx)
4628 {
4629 TCGLabel *l1 = gen_new_label();
4630 TCGLabel *l2 = gen_new_label();
4631 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4632 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4633 tcg_gen_br(l2);
4634 gen_set_label(l1);
4635 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4636 gen_set_label(l2);
4637 if (unlikely(Rc(ctx->opcode) != 0))
4638 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4639 }
4640
4641 /* dozo - dozo. */
4642 static void gen_dozo(DisasContext *ctx)
4643 {
4644 TCGLabel *l1 = gen_new_label();
4645 TCGLabel *l2 = gen_new_label();
4646 TCGv t0 = tcg_temp_new();
4647 TCGv t1 = tcg_temp_new();
4648 TCGv t2 = tcg_temp_new();
4649 /* Start with XER OV disabled, the most likely case */
4650 tcg_gen_movi_tl(cpu_ov, 0);
4651 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4652 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4653 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4654 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4655 tcg_gen_andc_tl(t1, t1, t2);
4656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4657 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4658 tcg_gen_movi_tl(cpu_ov, 1);
4659 tcg_gen_movi_tl(cpu_so, 1);
4660 tcg_gen_br(l2);
4661 gen_set_label(l1);
4662 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4663 gen_set_label(l2);
4664 tcg_temp_free(t0);
4665 tcg_temp_free(t1);
4666 tcg_temp_free(t2);
4667 if (unlikely(Rc(ctx->opcode) != 0))
4668 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4669 }
4670
4671 /* dozi */
4672 static void gen_dozi(DisasContext *ctx)
4673 {
4674 target_long simm = SIMM(ctx->opcode);
4675 TCGLabel *l1 = gen_new_label();
4676 TCGLabel *l2 = gen_new_label();
4677 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4678 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4679 tcg_gen_br(l2);
4680 gen_set_label(l1);
4681 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4682 gen_set_label(l2);
4683 if (unlikely(Rc(ctx->opcode) != 0))
4684 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4685 }
4686
4687 /* lscbx - lscbx. */
4688 static void gen_lscbx(DisasContext *ctx)
4689 {
4690 TCGv t0 = tcg_temp_new();
4691 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4692 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4693 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4694
4695 gen_addr_reg_index(ctx, t0);
4696 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4697 tcg_temp_free_i32(t1);
4698 tcg_temp_free_i32(t2);
4699 tcg_temp_free_i32(t3);
4700 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4701 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4702 if (unlikely(Rc(ctx->opcode) != 0))
4703 gen_set_Rc0(ctx, t0);
4704 tcg_temp_free(t0);
4705 }
4706
4707 /* maskg - maskg. */
4708 static void gen_maskg(DisasContext *ctx)
4709 {
4710 TCGLabel *l1 = gen_new_label();
4711 TCGv t0 = tcg_temp_new();
4712 TCGv t1 = tcg_temp_new();
4713 TCGv t2 = tcg_temp_new();
4714 TCGv t3 = tcg_temp_new();
4715 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4716 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4717 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4718 tcg_gen_addi_tl(t2, t0, 1);
4719 tcg_gen_shr_tl(t2, t3, t2);
4720 tcg_gen_shr_tl(t3, t3, t1);
4721 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4722 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4723 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4724 gen_set_label(l1);
4725 tcg_temp_free(t0);
4726 tcg_temp_free(t1);
4727 tcg_temp_free(t2);
4728 tcg_temp_free(t3);
4729 if (unlikely(Rc(ctx->opcode) != 0))
4730 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4731 }
4732
4733 /* maskir - maskir. */
4734 static void gen_maskir(DisasContext *ctx)
4735 {
4736 TCGv t0 = tcg_temp_new();
4737 TCGv t1 = tcg_temp_new();
4738 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4739 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4740 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4741 tcg_temp_free(t0);
4742 tcg_temp_free(t1);
4743 if (unlikely(Rc(ctx->opcode) != 0))
4744 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4745 }
4746
4747 /* mul - mul. */
4748 static void gen_mul(DisasContext *ctx)
4749 {
4750 TCGv_i64 t0 = tcg_temp_new_i64();
4751 TCGv_i64 t1 = tcg_temp_new_i64();
4752 TCGv t2 = tcg_temp_new();
4753 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4754 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4755 tcg_gen_mul_i64(t0, t0, t1);
4756 tcg_gen_trunc_i64_tl(t2, t0);
4757 gen_store_spr(SPR_MQ, t2);
4758 tcg_gen_shri_i64(t1, t0, 32);
4759 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4760 tcg_temp_free_i64(t0);
4761 tcg_temp_free_i64(t1);
4762 tcg_temp_free(t2);
4763 if (unlikely(Rc(ctx->opcode) != 0))
4764 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4765 }
4766
4767 /* mulo - mulo. */
4768 static void gen_mulo(DisasContext *ctx)
4769 {
4770 TCGLabel *l1 = gen_new_label();
4771 TCGv_i64 t0 = tcg_temp_new_i64();
4772 TCGv_i64 t1 = tcg_temp_new_i64();
4773 TCGv t2 = tcg_temp_new();
4774 /* Start with XER OV disabled, the most likely case */
4775 tcg_gen_movi_tl(cpu_ov, 0);
4776 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4777 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4778 tcg_gen_mul_i64(t0, t0, t1);
4779 tcg_gen_trunc_i64_tl(t2, t0);
4780 gen_store_spr(SPR_MQ, t2);
4781 tcg_gen_shri_i64(t1, t0, 32);
4782 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4783 tcg_gen_ext32s_i64(t1, t0);
4784 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4785 tcg_gen_movi_tl(cpu_ov, 1);
4786 tcg_gen_movi_tl(cpu_so, 1);
4787 gen_set_label(l1);
4788 tcg_temp_free_i64(t0);
4789 tcg_temp_free_i64(t1);
4790 tcg_temp_free(t2);
4791 if (unlikely(Rc(ctx->opcode) != 0))
4792 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4793 }
4794
4795 /* nabs - nabs. */
4796 static void gen_nabs(DisasContext *ctx)
4797 {
4798 TCGLabel *l1 = gen_new_label();
4799 TCGLabel *l2 = gen_new_label();
4800 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4801 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4802 tcg_gen_br(l2);
4803 gen_set_label(l1);
4804 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4805 gen_set_label(l2);
4806 if (unlikely(Rc(ctx->opcode) != 0))
4807 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4808 }
4809
4810 /* nabso - nabso. */
4811 static void gen_nabso(DisasContext *ctx)
4812 {
4813 TCGLabel *l1 = gen_new_label();
4814 TCGLabel *l2 = gen_new_label();
4815 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4816 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4817 tcg_gen_br(l2);
4818 gen_set_label(l1);
4819 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4820 gen_set_label(l2);
4821 /* nabs never overflows */
4822 tcg_gen_movi_tl(cpu_ov, 0);
4823 if (unlikely(Rc(ctx->opcode) != 0))
4824 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4825 }
4826
4827 /* rlmi - rlmi. */
4828 static void gen_rlmi(DisasContext *ctx)
4829 {
4830 uint32_t mb = MB(ctx->opcode);
4831 uint32_t me = ME(ctx->opcode);
4832 TCGv t0 = tcg_temp_new();
4833 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4834 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4835 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4836 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4837 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4838 tcg_temp_free(t0);
4839 if (unlikely(Rc(ctx->opcode) != 0))
4840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4841 }
4842
4843 /* rrib - rrib. */
4844 static void gen_rrib(DisasContext *ctx)
4845 {
4846 TCGv t0 = tcg_temp_new();
4847 TCGv t1 = tcg_temp_new();
4848 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4849 tcg_gen_movi_tl(t1, 0x80000000);
4850 tcg_gen_shr_tl(t1, t1, t0);
4851 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4852 tcg_gen_and_tl(t0, t0, t1);
4853 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4854 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4855 tcg_temp_free(t0);
4856 tcg_temp_free(t1);
4857 if (unlikely(Rc(ctx->opcode) != 0))
4858 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4859 }
4860
4861 /* sle - sle. */
4862 static void gen_sle(DisasContext *ctx)
4863 {
4864 TCGv t0 = tcg_temp_new();
4865 TCGv t1 = tcg_temp_new();
4866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4867 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4868 tcg_gen_subfi_tl(t1, 32, t1);
4869 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4870 tcg_gen_or_tl(t1, t0, t1);
4871 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4872 gen_store_spr(SPR_MQ, t1);
4873 tcg_temp_free(t0);
4874 tcg_temp_free(t1);
4875 if (unlikely(Rc(ctx->opcode) != 0))
4876 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4877 }
4878
4879 /* sleq - sleq. */
4880 static void gen_sleq(DisasContext *ctx)
4881 {
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 TCGv t2 = tcg_temp_new();
4885 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4886 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4887 tcg_gen_shl_tl(t2, t2, t0);
4888 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4889 gen_load_spr(t1, SPR_MQ);
4890 gen_store_spr(SPR_MQ, t0);
4891 tcg_gen_and_tl(t0, t0, t2);
4892 tcg_gen_andc_tl(t1, t1, t2);
4893 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4894 tcg_temp_free(t0);
4895 tcg_temp_free(t1);
4896 tcg_temp_free(t2);
4897 if (unlikely(Rc(ctx->opcode) != 0))
4898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4899 }
4900
4901 /* sliq - sliq. */
4902 static void gen_sliq(DisasContext *ctx)
4903 {
4904 int sh = SH(ctx->opcode);
4905 TCGv t0 = tcg_temp_new();
4906 TCGv t1 = tcg_temp_new();
4907 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4908 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4909 tcg_gen_or_tl(t1, t0, t1);
4910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4911 gen_store_spr(SPR_MQ, t1);
4912 tcg_temp_free(t0);
4913 tcg_temp_free(t1);
4914 if (unlikely(Rc(ctx->opcode) != 0))
4915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4916 }
4917
4918 /* slliq - slliq. */
4919 static void gen_slliq(DisasContext *ctx)
4920 {
4921 int sh = SH(ctx->opcode);
4922 TCGv t0 = tcg_temp_new();
4923 TCGv t1 = tcg_temp_new();
4924 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4925 gen_load_spr(t1, SPR_MQ);
4926 gen_store_spr(SPR_MQ, t0);
4927 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4928 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4929 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4930 tcg_temp_free(t0);
4931 tcg_temp_free(t1);
4932 if (unlikely(Rc(ctx->opcode) != 0))
4933 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4934 }
4935
4936 /* sllq - sllq. */
4937 static void gen_sllq(DisasContext *ctx)
4938 {
4939 TCGLabel *l1 = gen_new_label();
4940 TCGLabel *l2 = gen_new_label();
4941 TCGv t0 = tcg_temp_local_new();
4942 TCGv t1 = tcg_temp_local_new();
4943 TCGv t2 = tcg_temp_local_new();
4944 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4945 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4946 tcg_gen_shl_tl(t1, t1, t2);
4947 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4948 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4949 gen_load_spr(t0, SPR_MQ);
4950 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4951 tcg_gen_br(l2);
4952 gen_set_label(l1);
4953 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4954 gen_load_spr(t2, SPR_MQ);
4955 tcg_gen_andc_tl(t1, t2, t1);
4956 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4957 gen_set_label(l2);
4958 tcg_temp_free(t0);
4959 tcg_temp_free(t1);
4960 tcg_temp_free(t2);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4963 }
4964
4965 /* slq - slq. */
4966 static void gen_slq(DisasContext *ctx)
4967 {
4968 TCGLabel *l1 = gen_new_label();
4969 TCGv t0 = tcg_temp_new();
4970 TCGv t1 = tcg_temp_new();
4971 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4972 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4973 tcg_gen_subfi_tl(t1, 32, t1);
4974 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4975 tcg_gen_or_tl(t1, t0, t1);
4976 gen_store_spr(SPR_MQ, t1);
4977 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4978 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4979 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4980 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4981 gen_set_label(l1);
4982 tcg_temp_free(t0);
4983 tcg_temp_free(t1);
4984 if (unlikely(Rc(ctx->opcode) != 0))
4985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4986 }
4987
4988 /* sraiq - sraiq. */
4989 static void gen_sraiq(DisasContext *ctx)
4990 {
4991 int sh = SH(ctx->opcode);
4992 TCGLabel *l1 = gen_new_label();
4993 TCGv t0 = tcg_temp_new();
4994 TCGv t1 = tcg_temp_new();
4995 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4996 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4997 tcg_gen_or_tl(t0, t0, t1);
4998 gen_store_spr(SPR_MQ, t0);
4999 tcg_gen_movi_tl(cpu_ca, 0);
5000 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5001 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5002 tcg_gen_movi_tl(cpu_ca, 1);
5003 gen_set_label(l1);
5004 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5005 tcg_temp_free(t0);
5006 tcg_temp_free(t1);
5007 if (unlikely(Rc(ctx->opcode) != 0))
5008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5009 }
5010
5011 /* sraq - sraq. */
5012 static void gen_sraq(DisasContext *ctx)
5013 {
5014 TCGLabel *l1 = gen_new_label();
5015 TCGLabel *l2 = gen_new_label();
5016 TCGv t0 = tcg_temp_new();
5017 TCGv t1 = tcg_temp_local_new();
5018 TCGv t2 = tcg_temp_local_new();
5019 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5020 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5021 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5022 tcg_gen_subfi_tl(t2, 32, t2);
5023 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5024 tcg_gen_or_tl(t0, t0, t2);
5025 gen_store_spr(SPR_MQ, t0);
5026 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5027 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5028 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5029 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5030 gen_set_label(l1);
5031 tcg_temp_free(t0);
5032 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5033 tcg_gen_movi_tl(cpu_ca, 0);
5034 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5035 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5036 tcg_gen_movi_tl(cpu_ca, 1);
5037 gen_set_label(l2);
5038 tcg_temp_free(t1);
5039 tcg_temp_free(t2);
5040 if (unlikely(Rc(ctx->opcode) != 0))
5041 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5042 }
5043
5044 /* sre - sre. */
5045 static void gen_sre(DisasContext *ctx)
5046 {
5047 TCGv t0 = tcg_temp_new();
5048 TCGv t1 = tcg_temp_new();
5049 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5050 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5051 tcg_gen_subfi_tl(t1, 32, t1);
5052 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5053 tcg_gen_or_tl(t1, t0, t1);
5054 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5055 gen_store_spr(SPR_MQ, t1);
5056 tcg_temp_free(t0);
5057 tcg_temp_free(t1);
5058 if (unlikely(Rc(ctx->opcode) != 0))
5059 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5060 }
5061
5062 /* srea - srea. */
5063 static void gen_srea(DisasContext *ctx)
5064 {
5065 TCGv t0 = tcg_temp_new();
5066 TCGv t1 = tcg_temp_new();
5067 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5068 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5069 gen_store_spr(SPR_MQ, t0);
5070 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5071 tcg_temp_free(t0);
5072 tcg_temp_free(t1);
5073 if (unlikely(Rc(ctx->opcode) != 0))
5074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5075 }
5076
5077 /* sreq */
5078 static void gen_sreq(DisasContext *ctx)
5079 {
5080 TCGv t0 = tcg_temp_new();
5081 TCGv t1 = tcg_temp_new();
5082 TCGv t2 = tcg_temp_new();
5083 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5084 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5085 tcg_gen_shr_tl(t1, t1, t0);
5086 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5087 gen_load_spr(t2, SPR_MQ);
5088 gen_store_spr(SPR_MQ, t0);
5089 tcg_gen_and_tl(t0, t0, t1);
5090 tcg_gen_andc_tl(t2, t2, t1);
5091 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5092 tcg_temp_free(t0);
5093 tcg_temp_free(t1);
5094 tcg_temp_free(t2);
5095 if (unlikely(Rc(ctx->opcode) != 0))
5096 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5097 }
5098
5099 /* sriq */
5100 static void gen_sriq(DisasContext *ctx)
5101 {
5102 int sh = SH(ctx->opcode);
5103 TCGv t0 = tcg_temp_new();
5104 TCGv t1 = tcg_temp_new();
5105 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5106 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5107 tcg_gen_or_tl(t1, t0, t1);
5108 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5109 gen_store_spr(SPR_MQ, t1);
5110 tcg_temp_free(t0);
5111 tcg_temp_free(t1);
5112 if (unlikely(Rc(ctx->opcode) != 0))
5113 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5114 }
5115
5116 /* srliq */
5117 static void gen_srliq(DisasContext *ctx)
5118 {
5119 int sh = SH(ctx->opcode);
5120 TCGv t0 = tcg_temp_new();
5121 TCGv t1 = tcg_temp_new();
5122 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5123 gen_load_spr(t1, SPR_MQ);
5124 gen_store_spr(SPR_MQ, t0);
5125 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5126 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5127 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5128 tcg_temp_free(t0);
5129 tcg_temp_free(t1);
5130 if (unlikely(Rc(ctx->opcode) != 0))
5131 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5132 }
5133
5134 /* srlq */
5135 static void gen_srlq(DisasContext *ctx)
5136 {
5137 TCGLabel *l1 = gen_new_label();
5138 TCGLabel *l2 = gen_new_label();
5139 TCGv t0 = tcg_temp_local_new();
5140 TCGv t1 = tcg_temp_local_new();
5141 TCGv t2 = tcg_temp_local_new();
5142 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5143 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5144 tcg_gen_shr_tl(t2, t1, t2);
5145 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5146 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5147 gen_load_spr(t0, SPR_MQ);
5148 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5149 tcg_gen_br(l2);
5150 gen_set_label(l1);
5151 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5152 tcg_gen_and_tl(t0, t0, t2);
5153 gen_load_spr(t1, SPR_MQ);
5154 tcg_gen_andc_tl(t1, t1, t2);
5155 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5156 gen_set_label(l2);
5157 tcg_temp_free(t0);
5158 tcg_temp_free(t1);
5159 tcg_temp_free(t2);
5160 if (unlikely(Rc(ctx->opcode) != 0))
5161 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5162 }
5163
5164 /* srq */
5165 static void gen_srq(DisasContext *ctx)
5166 {
5167 TCGLabel *l1 = gen_new_label();
5168 TCGv t0 = tcg_temp_new();
5169 TCGv t1 = tcg_temp_new();
5170 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5171 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5172 tcg_gen_subfi_tl(t1, 32, t1);
5173 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5174 tcg_gen_or_tl(t1, t0, t1);
5175 gen_store_spr(SPR_MQ, t1);
5176 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5177 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5178 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5179 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5180 gen_set_label(l1);
5181 tcg_temp_free(t0);
5182 tcg_temp_free(t1);
5183 if (unlikely(Rc(ctx->opcode) != 0))
5184 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5185 }
5186
5187 /* PowerPC 602 specific instructions */
5188
5189 /* dsa */
5190 static void gen_dsa(DisasContext *ctx)
5191 {
5192 /* XXX: TODO */
5193 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5194 }
5195
5196 /* esa */
5197 static void gen_esa(DisasContext *ctx)
5198 {
5199 /* XXX: TODO */
5200 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5201 }
5202
5203 /* mfrom */
5204 static void gen_mfrom(DisasContext *ctx)
5205 {
5206 #if defined(CONFIG_USER_ONLY)
5207 GEN_PRIV;
5208 #else
5209 CHK_SV;
5210 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5211 #endif /* defined(CONFIG_USER_ONLY) */
5212 }
5213
5214 /* 602 - 603 - G2 TLB management */
5215
5216 /* tlbld */
5217 static void gen_tlbld_6xx(DisasContext *ctx)
5218 {
5219 #if defined(CONFIG_USER_ONLY)
5220 GEN_PRIV;
5221 #else
5222 CHK_SV;
5223 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5224 #endif /* defined(CONFIG_USER_ONLY) */
5225 }
5226
5227 /* tlbli */
5228 static void gen_tlbli_6xx(DisasContext *ctx)
5229 {
5230 #if defined(CONFIG_USER_ONLY)
5231 GEN_PRIV;
5232 #else
5233 CHK_SV;
5234 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5235 #endif /* defined(CONFIG_USER_ONLY) */
5236 }
5237
5238 /* 74xx TLB management */
5239
5240 /* tlbld */
5241 static void gen_tlbld_74xx(DisasContext *ctx)
5242 {
5243 #if defined(CONFIG_USER_ONLY)
5244 GEN_PRIV;
5245 #else
5246 CHK_SV;
5247 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5248 #endif /* defined(CONFIG_USER_ONLY) */
5249 }
5250
5251 /* tlbli */
5252 static void gen_tlbli_74xx(DisasContext *ctx)
5253 {
5254 #if defined(CONFIG_USER_ONLY)
5255 GEN_PRIV;
5256 #else
5257 CHK_SV;
5258 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5259 #endif /* defined(CONFIG_USER_ONLY) */
5260 }
5261
5262 /* POWER instructions not in PowerPC 601 */
5263
5264 /* clf */
5265 static void gen_clf(DisasContext *ctx)
5266 {
5267 /* Cache line flush: implemented as no-op */
5268 }
5269
5270 /* cli */
5271 static void gen_cli(DisasContext *ctx)
5272 {
5273 #if defined(CONFIG_USER_ONLY)
5274 GEN_PRIV;
5275 #else
5276 /* Cache line invalidate: privileged and treated as no-op */
5277 CHK_SV;
5278 #endif /* defined(CONFIG_USER_ONLY) */
5279 }
5280
5281 /* dclst */
5282 static void gen_dclst(DisasContext *ctx)
5283 {
5284 /* Data cache line store: treated as no-op */
5285 }
5286
5287 static void gen_mfsri(DisasContext *ctx)
5288 {
5289 #if defined(CONFIG_USER_ONLY)
5290 GEN_PRIV;
5291 #else
5292 int ra = rA(ctx->opcode);
5293 int rd = rD(ctx->opcode);
5294 TCGv t0;
5295
5296 CHK_SV;
5297 t0 = tcg_temp_new();
5298 gen_addr_reg_index(ctx, t0);
5299 tcg_gen_shri_tl(t0, t0, 28);
5300 tcg_gen_andi_tl(t0, t0, 0xF);
5301 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5302 tcg_temp_free(t0);
5303 if (ra != 0 && ra != rd)
5304 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5305 #endif /* defined(CONFIG_USER_ONLY) */
5306 }
5307
5308 static void gen_rac(DisasContext *ctx)
5309 {
5310 #if defined(CONFIG_USER_ONLY)
5311 GEN_PRIV;
5312 #else
5313 TCGv t0;
5314
5315 CHK_SV;
5316 t0 = tcg_temp_new();
5317 gen_addr_reg_index(ctx, t0);
5318 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5319 tcg_temp_free(t0);
5320 #endif /* defined(CONFIG_USER_ONLY) */
5321 }
5322
5323 static void gen_rfsvc(DisasContext *ctx)
5324 {
5325 #if defined(CONFIG_USER_ONLY)
5326 GEN_PRIV;
5327 #else
5328 CHK_SV;
5329
5330 gen_helper_rfsvc(cpu_env);
5331 gen_sync_exception(ctx);
5332 #endif /* defined(CONFIG_USER_ONLY) */
5333 }
5334
5335 /* svc is not implemented for now */
5336
5337 /* BookE specific instructions */
5338
5339 /* XXX: not implemented on 440 ? */
5340 static void gen_mfapidi(DisasContext *ctx)
5341 {
5342 /* XXX: TODO */
5343 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5344 }
5345
5346 /* XXX: not implemented on 440 ? */
5347 static void gen_tlbiva(DisasContext *ctx)
5348 {
5349 #if defined(CONFIG_USER_ONLY)
5350 GEN_PRIV;
5351 #else
5352 TCGv t0;
5353
5354 CHK_SV;
5355 t0 = tcg_temp_new();
5356 gen_addr_reg_index(ctx, t0);
5357 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5358 tcg_temp_free(t0);
5359 #endif /* defined(CONFIG_USER_ONLY) */
5360 }
5361
5362 /* All 405 MAC instructions are translated here */
5363 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5364 int ra, int rb, int rt, int Rc)
5365 {
5366 TCGv t0, t1;
5367
5368 t0 = tcg_temp_local_new();
5369 t1 = tcg_temp_local_new();
5370
5371 switch (opc3 & 0x0D) {
5372 case 0x05:
5373 /* macchw - macchw. - macchwo - macchwo. */
5374 /* macchws - macchws. - macchwso - macchwso. */
5375 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5376 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5377 /* mulchw - mulchw. */
5378 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5379 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5380 tcg_gen_ext16s_tl(t1, t1);
5381 break;
5382 case 0x04:
5383 /* macchwu - macchwu. - macchwuo - macchwuo. */
5384 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5385 /* mulchwu - mulchwu. */
5386 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5387 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5388 tcg_gen_ext16u_tl(t1, t1);
5389 break;
5390 case 0x01:
5391 /* machhw - machhw. - machhwo - machhwo. */
5392 /* machhws - machhws. - machhwso - machhwso. */
5393 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5394 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5395 /* mulhhw - mulhhw. */
5396 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5397 tcg_gen_ext16s_tl(t0, t0);
5398 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5399 tcg_gen_ext16s_tl(t1, t1);
5400 break;
5401 case 0x00:
5402 /* machhwu - machhwu. - machhwuo - machhwuo. */
5403 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5404 /* mulhhwu - mulhhwu. */
5405 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5406 tcg_gen_ext16u_tl(t0, t0);
5407 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5408 tcg_gen_ext16u_tl(t1, t1);
5409 break;
5410 case 0x0D:
5411 /* maclhw - maclhw. - maclhwo - maclhwo. */
5412 /* maclhws - maclhws. - maclhwso - maclhwso. */
5413 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5414 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5415 /* mullhw - mullhw. */
5416 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5417 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5418 break;
5419 case 0x0C:
5420 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5421 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5422 /* mullhwu - mullhwu. */
5423 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5424 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5425 break;
5426 }
5427 if (opc2 & 0x04) {
5428 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5429 tcg_gen_mul_tl(t1, t0, t1);
5430 if (opc2 & 0x02) {
5431 /* nmultiply-and-accumulate (0x0E) */
5432 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5433 } else {
5434 /* multiply-and-accumulate (0x0C) */
5435 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5436 }
5437
5438 if (opc3 & 0x12) {
5439 /* Check overflow and/or saturate */
5440 TCGLabel *l1 = gen_new_label();
5441
5442 if (opc3 & 0x10) {
5443 /* Start with XER OV disabled, the most likely case */
5444 tcg_gen_movi_tl(cpu_ov, 0);
5445 }
5446 if (opc3 & 0x01) {
5447 /* Signed */
5448 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5449 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5450 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5451 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5452 if (opc3 & 0x02) {
5453 /* Saturate */
5454 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5455 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5456 }
5457 } else {
5458 /* Unsigned */
5459 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5460 if (opc3 & 0x02) {
5461 /* Saturate */
5462 tcg_gen_movi_tl(t0, UINT32_MAX);
5463 }
5464 }
5465 if (opc3 & 0x10) {
5466 /* Check overflow */
5467 tcg_gen_movi_tl(cpu_ov, 1);
5468 tcg_gen_movi_tl(cpu_so, 1);
5469 }
5470 gen_set_label(l1);
5471 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5472 }
5473 } else {
5474 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5475 }
5476 tcg_temp_free(t0);
5477 tcg_temp_free(t1);
5478 if (unlikely(Rc) != 0) {
5479 /* Update Rc0 */
5480 gen_set_Rc0(ctx, cpu_gpr[rt]);
5481 }
5482 }
5483
5484 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5485 static void glue(gen_, name)(DisasContext *ctx) \
5486 { \
5487 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5488 rD(ctx->opcode), Rc(ctx->opcode)); \
5489 }
5490
5491 /* macchw - macchw. */
5492 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5493 /* macchwo - macchwo. */
5494 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5495 /* macchws - macchws. */
5496 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5497 /* macchwso - macchwso. */
5498 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5499 /* macchwsu - macchwsu. */
5500 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5501 /* macchwsuo - macchwsuo. */
5502 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5503 /* macchwu - macchwu. */
5504 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5505 /* macchwuo - macchwuo. */
5506 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5507 /* machhw - machhw. */
5508 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5509 /* machhwo - machhwo. */
5510 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5511 /* machhws - machhws. */
5512 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5513 /* machhwso - machhwso. */
5514 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5515 /* machhwsu - machhwsu. */
5516 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5517 /* machhwsuo - machhwsuo. */
5518 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5519 /* machhwu - machhwu. */
5520 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5521 /* machhwuo - machhwuo. */
5522 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5523 /* maclhw - maclhw. */
5524 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5525 /* maclhwo - maclhwo. */
5526 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5527 /* maclhws - maclhws. */
5528 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5529 /* maclhwso - maclhwso. */
5530 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5531 /* maclhwu - maclhwu. */
5532 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5533 /* maclhwuo - maclhwuo. */
5534 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5535 /* maclhwsu - maclhwsu. */
5536 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5537 /* maclhwsuo - maclhwsuo. */
5538 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5539 /* nmacchw - nmacchw. */
5540 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5541 /* nmacchwo - nmacchwo. */
5542 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5543 /* nmacchws - nmacchws. */
5544 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5545 /* nmacchwso - nmacchwso. */
5546 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5547 /* nmachhw - nmachhw. */
5548 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5549 /* nmachhwo - nmachhwo. */
5550 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5551 /* nmachhws - nmachhws. */
5552 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5553 /* nmachhwso - nmachhwso. */
5554 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5555 /* nmaclhw - nmaclhw. */
5556 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5557 /* nmaclhwo - nmaclhwo. */
5558 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5559 /* nmaclhws - nmaclhws. */
5560 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5561 /* nmaclhwso - nmaclhwso. */
5562 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5563
5564 /* mulchw - mulchw. */
5565 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5566 /* mulchwu - mulchwu. */
5567 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5568 /* mulhhw - mulhhw. */
5569 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5570 /* mulhhwu - mulhhwu. */
5571 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5572 /* mullhw - mullhw. */
5573 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5574 /* mullhwu - mullhwu. */
5575 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5576
5577 /* mfdcr */
5578 static void gen_mfdcr(DisasContext *ctx)
5579 {
5580 #if defined(CONFIG_USER_ONLY)
5581 GEN_PRIV;
5582 #else
5583 TCGv dcrn;
5584
5585 CHK_SV;
5586 dcrn = tcg_const_tl(SPR(ctx->opcode));
5587 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5588 tcg_temp_free(dcrn);
5589 #endif /* defined(CONFIG_USER_ONLY) */
5590 }
5591
5592 /* mtdcr */
5593 static void gen_mtdcr(DisasContext *ctx)
5594 {
5595 #if defined(CONFIG_USER_ONLY)
5596 GEN_PRIV;
5597 #else
5598 TCGv dcrn;
5599
5600 CHK_SV;
5601 dcrn = tcg_const_tl(SPR(ctx->opcode));
5602 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5603 tcg_temp_free(dcrn);
5604 #endif /* defined(CONFIG_USER_ONLY) */
5605 }
5606
5607 /* mfdcrx */
5608 /* XXX: not implemented on 440 ? */
5609 static void gen_mfdcrx(DisasContext *ctx)
5610 {
5611 #if defined(CONFIG_USER_ONLY)
5612 GEN_PRIV;
5613 #else
5614 CHK_SV;
5615 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5616 cpu_gpr[rA(ctx->opcode)]);
5617 /* Note: Rc update flag set leads to undefined state of Rc0 */
5618 #endif /* defined(CONFIG_USER_ONLY) */
5619 }
5620
5621 /* mtdcrx */
5622 /* XXX: not implemented on 440 ? */
5623 static void gen_mtdcrx(DisasContext *ctx)
5624 {
5625 #if defined(CONFIG_USER_ONLY)
5626 GEN_PRIV;
5627 #else
5628 CHK_SV;
5629 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5630 cpu_gpr[rS(ctx->opcode)]);
5631 /* Note: Rc update flag set leads to undefined state of Rc0 */
5632 #endif /* defined(CONFIG_USER_ONLY) */
5633 }
5634
5635 /* mfdcrux (PPC 460) : user-mode access to DCR */
5636 static void gen_mfdcrux(DisasContext *ctx)
5637 {
5638 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5639 cpu_gpr[rA(ctx->opcode)]);
5640 /* Note: Rc update flag set leads to undefined state of Rc0 */
5641 }
5642
5643 /* mtdcrux (PPC 460) : user-mode access to DCR */
5644 static void gen_mtdcrux(DisasContext *ctx)
5645 {
5646 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5647 cpu_gpr[rS(ctx->opcode)]);
5648 /* Note: Rc update flag set leads to undefined state of Rc0 */
5649 }
5650
5651 /* dccci */
5652 static void gen_dccci(DisasContext *ctx)
5653 {
5654 CHK_SV;
5655 /* interpreted as no-op */
5656 }
5657
5658 /* dcread */
5659 static void gen_dcread(DisasContext *ctx)
5660 {
5661 #if defined(CONFIG_USER_ONLY)
5662 GEN_PRIV;
5663 #else
5664 TCGv EA, val;
5665
5666 CHK_SV;
5667 gen_set_access_type(ctx, ACCESS_CACHE);
5668 EA = tcg_temp_new();
5669 gen_addr_reg_index(ctx, EA);
5670 val = tcg_temp_new();
5671 gen_qemu_ld32u(ctx, val, EA);
5672 tcg_temp_free(val);
5673 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5674 tcg_temp_free(EA);
5675 #endif /* defined(CONFIG_USER_ONLY) */
5676 }
5677
5678 /* icbt */
5679 static void gen_icbt_40x(DisasContext *ctx)
5680 {
5681 /* interpreted as no-op */
5682 /* XXX: specification say this is treated as a load by the MMU
5683 * but does not generate any exception
5684 */
5685 }
5686
5687 /* iccci */
5688 static void gen_iccci(DisasContext *ctx)
5689 {
5690 CHK_SV;
5691 /* interpreted as no-op */
5692 }
5693
5694 /* icread */
5695 static void gen_icread(DisasContext *ctx)
5696 {
5697 CHK_SV;
5698 /* interpreted as no-op */
5699 }
5700
5701 /* rfci (supervisor only) */
5702 static void gen_rfci_40x(DisasContext *ctx)
5703 {
5704 #if defined(CONFIG_USER_ONLY)
5705 GEN_PRIV;
5706 #else
5707 CHK_SV;
5708 /* Restore CPU state */
5709 gen_helper_40x_rfci(cpu_env);
5710 gen_sync_exception(ctx);
5711 #endif /* defined(CONFIG_USER_ONLY) */
5712 }
5713
5714 static void gen_rfci(DisasContext *ctx)
5715 {
5716 #if defined(CONFIG_USER_ONLY)
5717 GEN_PRIV;
5718 #else
5719 CHK_SV;
5720 /* Restore CPU state */
5721 gen_helper_rfci(cpu_env);
5722 gen_sync_exception(ctx);
5723 #endif /* defined(CONFIG_USER_ONLY) */
5724 }
5725
5726 /* BookE specific */
5727
5728 /* XXX: not implemented on 440 ? */
5729 static void gen_rfdi(DisasContext *ctx)
5730 {
5731 #if defined(CONFIG_USER_ONLY)
5732 GEN_PRIV;
5733 #else
5734 CHK_SV;
5735 /* Restore CPU state */
5736 gen_helper_rfdi(cpu_env);
5737 gen_sync_exception(ctx);
5738 #endif /* defined(CONFIG_USER_ONLY) */
5739 }
5740
5741 /* XXX: not implemented on 440 ? */
5742 static void gen_rfmci(DisasContext *ctx)
5743 {
5744 #if defined(CONFIG_USER_ONLY)
5745 GEN_PRIV;
5746 #else
5747 CHK_SV;
5748 /* Restore CPU state */
5749 gen_helper_rfmci(cpu_env);
5750 gen_sync_exception(ctx);
5751 #endif /* defined(CONFIG_USER_ONLY) */
5752 }
5753
5754 /* TLB management - PowerPC 405 implementation */
5755
5756 /* tlbre */
5757 static void gen_tlbre_40x(DisasContext *ctx)
5758 {
5759 #if defined(CONFIG_USER_ONLY)
5760 GEN_PRIV;
5761 #else
5762 CHK_SV;
5763 switch (rB(ctx->opcode)) {
5764 case 0:
5765 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5766 cpu_gpr[rA(ctx->opcode)]);
5767 break;
5768 case 1:
5769 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5770 cpu_gpr[rA(ctx->opcode)]);
5771 break;
5772 default:
5773 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5774 break;
5775 }
5776 #endif /* defined(CONFIG_USER_ONLY) */
5777 }
5778
5779 /* tlbsx - tlbsx. */
5780 static void gen_tlbsx_40x(DisasContext *ctx)
5781 {
5782 #if defined(CONFIG_USER_ONLY)
5783 GEN_PRIV;
5784 #else
5785 TCGv t0;
5786
5787 CHK_SV;
5788 t0 = tcg_temp_new();
5789 gen_addr_reg_index(ctx, t0);
5790 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5791 tcg_temp_free(t0);
5792 if (Rc(ctx->opcode)) {
5793 TCGLabel *l1 = gen_new_label();
5794 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5795 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5796 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5797 gen_set_label(l1);
5798 }
5799 #endif /* defined(CONFIG_USER_ONLY) */
5800 }
5801
5802 /* tlbwe */
5803 static void gen_tlbwe_40x(DisasContext *ctx)
5804 {
5805 #if defined(CONFIG_USER_ONLY)
5806 GEN_PRIV;
5807 #else
5808 CHK_SV;
5809
5810 switch (rB(ctx->opcode)) {
5811 case 0:
5812 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5813 cpu_gpr[rS(ctx->opcode)]);
5814 break;
5815 case 1:
5816 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5817 cpu_gpr[rS(ctx->opcode)]);
5818 break;
5819 default:
5820 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5821 break;
5822 }
5823 #endif /* defined(CONFIG_USER_ONLY) */
5824 }
5825
5826 /* TLB management - PowerPC 440 implementation */
5827
5828 /* tlbre */
5829 static void gen_tlbre_440(DisasContext *ctx)
5830 {
5831 #if defined(CONFIG_USER_ONLY)
5832 GEN_PRIV;
5833 #else
5834 CHK_SV;
5835
5836 switch (rB(ctx->opcode)) {
5837 case 0:
5838 case 1:
5839 case 2:
5840 {
5841 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5842 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5843 t0, cpu_gpr[rA(ctx->opcode)]);
5844 tcg_temp_free_i32(t0);
5845 }
5846 break;
5847 default:
5848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5849 break;
5850 }
5851 #endif /* defined(CONFIG_USER_ONLY) */
5852 }
5853
5854 /* tlbsx - tlbsx. */
5855 static void gen_tlbsx_440(DisasContext *ctx)
5856 {
5857 #if defined(CONFIG_USER_ONLY)
5858 GEN_PRIV;
5859 #else
5860 TCGv t0;
5861
5862 CHK_SV;
5863 t0 = tcg_temp_new();
5864 gen_addr_reg_index(ctx, t0);
5865 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5866 tcg_temp_free(t0);
5867 if (Rc(ctx->opcode)) {
5868 TCGLabel *l1 = gen_new_label();
5869 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5870 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5871 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5872 gen_set_label(l1);
5873 }
5874 #endif /* defined(CONFIG_USER_ONLY) */
5875 }
5876
5877 /* tlbwe */
5878 static void gen_tlbwe_440(DisasContext *ctx)
5879 {
5880 #if defined(CONFIG_USER_ONLY)
5881 GEN_PRIV;
5882 #else
5883 CHK_SV;
5884 switch (rB(ctx->opcode)) {
5885 case 0:
5886 case 1:
5887 case 2:
5888 {
5889 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5890 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5891 cpu_gpr[rS(ctx->opcode)]);
5892 tcg_temp_free_i32(t0);
5893 }
5894 break;
5895 default:
5896 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5897 break;
5898 }
5899 #endif /* defined(CONFIG_USER_ONLY) */
5900 }
5901
5902 /* TLB management - PowerPC BookE 2.06 implementation */
5903
5904 /* tlbre */
5905 static void gen_tlbre_booke206(DisasContext *ctx)
5906 {
5907 #if defined(CONFIG_USER_ONLY)
5908 GEN_PRIV;
5909 #else
5910 CHK_SV;
5911 gen_helper_booke206_tlbre(cpu_env);
5912 #endif /* defined(CONFIG_USER_ONLY) */
5913 }
5914
5915 /* tlbsx - tlbsx. */
5916 static void gen_tlbsx_booke206(DisasContext *ctx)
5917 {
5918 #if defined(CONFIG_USER_ONLY)
5919 GEN_PRIV;
5920 #else
5921 TCGv t0;
5922
5923 CHK_SV;
5924 if (rA(ctx->opcode)) {
5925 t0 = tcg_temp_new();
5926 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5927 } else {
5928 t0 = tcg_const_tl(0);
5929 }
5930
5931 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5932 gen_helper_booke206_tlbsx(cpu_env, t0);
5933 tcg_temp_free(t0);
5934 #endif /* defined(CONFIG_USER_ONLY) */
5935 }
5936
5937 /* tlbwe */
5938 static void gen_tlbwe_booke206(DisasContext *ctx)
5939 {
5940 #if defined(CONFIG_USER_ONLY)
5941 GEN_PRIV;
5942 #else
5943 CHK_SV;
5944 gen_helper_booke206_tlbwe(cpu_env);
5945 #endif /* defined(CONFIG_USER_ONLY) */
5946 }
5947
5948 static void gen_tlbivax_booke206(DisasContext *ctx)
5949 {
5950 #if defined(CONFIG_USER_ONLY)
5951 GEN_PRIV;
5952 #else
5953 TCGv t0;
5954
5955 CHK_SV;
5956 t0 = tcg_temp_new();
5957 gen_addr_reg_index(ctx, t0);
5958 gen_helper_booke206_tlbivax(cpu_env, t0);
5959 tcg_temp_free(t0);
5960 #endif /* defined(CONFIG_USER_ONLY) */
5961 }
5962
5963 static void gen_tlbilx_booke206(DisasContext *ctx)
5964 {
5965 #if defined(CONFIG_USER_ONLY)
5966 GEN_PRIV;
5967 #else
5968 TCGv t0;
5969
5970 CHK_SV;
5971 t0 = tcg_temp_new();
5972 gen_addr_reg_index(ctx, t0);
5973
5974 switch((ctx->opcode >> 21) & 0x3) {
5975 case 0:
5976 gen_helper_booke206_tlbilx0(cpu_env, t0);
5977 break;
5978 case 1:
5979 gen_helper_booke206_tlbilx1(cpu_env, t0);
5980 break;
5981 case 3:
5982 gen_helper_booke206_tlbilx3(cpu_env, t0);
5983 break;
5984 default:
5985 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5986 break;
5987 }
5988
5989 tcg_temp_free(t0);
5990 #endif /* defined(CONFIG_USER_ONLY) */
5991 }
5992
5993
5994 /* wrtee */
5995 static void gen_wrtee(DisasContext *ctx)
5996 {
5997 #if defined(CONFIG_USER_ONLY)
5998 GEN_PRIV;
5999 #else
6000 TCGv t0;
6001
6002 CHK_SV;
6003 t0 = tcg_temp_new();
6004 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6005 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6006 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6007 tcg_temp_free(t0);
6008 /* Stop translation to have a chance to raise an exception
6009 * if we just set msr_ee to 1
6010 */
6011 gen_stop_exception(ctx);
6012 #endif /* defined(CONFIG_USER_ONLY) */
6013 }
6014
6015 /* wrteei */
6016 static void gen_wrteei(DisasContext *ctx)
6017 {
6018 #if defined(CONFIG_USER_ONLY)
6019 GEN_PRIV;
6020 #else
6021 CHK_SV;
6022 if (ctx->opcode & 0x00008000) {
6023 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6024 /* Stop translation to have a chance to raise an exception */
6025 gen_stop_exception(ctx);
6026 } else {
6027 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6028 }
6029 #endif /* defined(CONFIG_USER_ONLY) */
6030 }
6031
6032 /* PowerPC 440 specific instructions */
6033
6034 /* dlmzb */
6035 static void gen_dlmzb(DisasContext *ctx)
6036 {
6037 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6038 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6039 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6040 tcg_temp_free_i32(t0);
6041 }
6042
6043 /* mbar replaces eieio on 440 */
6044 static void gen_mbar(DisasContext *ctx)
6045 {
6046 /* interpreted as no-op */
6047 }
6048
6049 /* msync replaces sync on 440 */
6050 static void gen_msync_4xx(DisasContext *ctx)
6051 {
6052 /* interpreted as no-op */
6053 }
6054
6055 /* icbt */
6056 static void gen_icbt_440(DisasContext *ctx)
6057 {
6058 /* interpreted as no-op */
6059 /* XXX: specification say this is treated as a load by the MMU
6060 * but does not generate any exception
6061 */
6062 }
6063
6064 /* Embedded.Processor Control */
6065
6066 static void gen_msgclr(DisasContext *ctx)
6067 {
6068 #if defined(CONFIG_USER_ONLY)
6069 GEN_PRIV;
6070 #else
6071 CHK_SV;
6072 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6073 #endif /* defined(CONFIG_USER_ONLY) */
6074 }
6075
6076 static void gen_msgsnd(DisasContext *ctx)
6077 {
6078 #if defined(CONFIG_USER_ONLY)
6079 GEN_PRIV;
6080 #else
6081 CHK_SV;
6082 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6083 #endif /* defined(CONFIG_USER_ONLY) */
6084 }
6085
6086
6087 #if defined(TARGET_PPC64)
6088 static void gen_maddld(DisasContext *ctx)
6089 {
6090 TCGv_i64 t1 = tcg_temp_new_i64();
6091
6092 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6093 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6094 tcg_temp_free_i64(t1);
6095 }
6096
6097 /* maddhd maddhdu */
6098 static void gen_maddhd_maddhdu(DisasContext *ctx)
6099 {
6100 TCGv_i64 lo = tcg_temp_new_i64();
6101 TCGv_i64 hi = tcg_temp_new_i64();
6102 TCGv_i64 t1 = tcg_temp_new_i64();
6103
6104 if (Rc(ctx->opcode)) {
6105 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6106 cpu_gpr[rB(ctx->opcode)]);
6107 tcg_gen_movi_i64(t1, 0);
6108 } else {
6109 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6110 cpu_gpr[rB(ctx->opcode)]);
6111 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6112 }
6113 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6114 cpu_gpr[rC(ctx->opcode)], t1);
6115 tcg_temp_free_i64(lo);
6116 tcg_temp_free_i64(hi);
6117 tcg_temp_free_i64(t1);
6118 }
6119 #endif /* defined(TARGET_PPC64) */
6120
6121 static void gen_tbegin(DisasContext *ctx)
6122 {
6123 if (unlikely(!ctx->tm_enabled)) {
6124 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6125 return;
6126 }
6127 gen_helper_tbegin(cpu_env);
6128 }
6129
6130 #define GEN_TM_NOOP(name) \
6131 static inline void gen_##name(DisasContext *ctx) \
6132 { \
6133 if (unlikely(!ctx->tm_enabled)) { \
6134 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6135 return; \
6136 } \
6137 /* Because tbegin always fails in QEMU, these user \
6138 * space instructions all have a simple implementation: \
6139 * \
6140 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6141 * = 0b0 || 0b00 || 0b0 \
6142 */ \
6143 tcg_gen_movi_i32(cpu_crf[0], 0); \
6144 }
6145
6146 GEN_TM_NOOP(tend);
6147 GEN_TM_NOOP(tabort);
6148 GEN_TM_NOOP(tabortwc);
6149 GEN_TM_NOOP(tabortwci);
6150 GEN_TM_NOOP(tabortdc);
6151 GEN_TM_NOOP(tabortdci);
6152 GEN_TM_NOOP(tsr);
6153
6154 static void gen_tcheck(DisasContext *ctx)
6155 {
6156 if (unlikely(!ctx->tm_enabled)) {
6157 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6158 return;
6159 }
6160 /* Because tbegin always fails, the tcheck implementation
6161 * is simple:
6162 *
6163 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6164 * = 0b1 || 0b00 || 0b0
6165 */
6166 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6167 }
6168
6169 #if defined(CONFIG_USER_ONLY)
6170 #define GEN_TM_PRIV_NOOP(name) \
6171 static inline void gen_##name(DisasContext *ctx) \
6172 { \
6173 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6174 }
6175
6176 #else
6177
6178 #define GEN_TM_PRIV_NOOP(name) \
6179 static inline void gen_##name(DisasContext *ctx) \
6180 { \
6181 CHK_SV; \
6182 if (unlikely(!ctx->tm_enabled)) { \
6183 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6184 return; \
6185 } \
6186 /* Because tbegin always fails, the implementation is \
6187 * simple: \
6188 * \
6189 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6190 * = 0b0 || 0b00 | 0b0 \
6191 */ \
6192 tcg_gen_movi_i32(cpu_crf[0], 0); \
6193 }
6194
6195 #endif
6196
6197 GEN_TM_PRIV_NOOP(treclaim);
6198 GEN_TM_PRIV_NOOP(trechkpt);
6199
6200 #include "translate/fp-impl.inc.c"
6201
6202 #include "translate/vmx-impl.inc.c"
6203
6204 #include "translate/vsx-impl.inc.c"
6205
6206 #include "translate/dfp-impl.inc.c"
6207
6208 #include "translate/spe-impl.inc.c"
6209
6210 static opcode_t opcodes[] = {
6211 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6212 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6213 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6214 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6215 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6216 #if defined(TARGET_PPC64)
6217 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6218 #endif
6219 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6220 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6221 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6222 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6223 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6224 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6225 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6226 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6227 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6228 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6229 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6230 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6231 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6232 #if defined(TARGET_PPC64)
6233 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6234 #endif
6235 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6236 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6237 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6238 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6239 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6240 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6241 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6242 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6243 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6244 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6245 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6246 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6247 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6248 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6249 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6250 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6251 #if defined(TARGET_PPC64)
6252 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6253 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6254 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6255 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6256 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6257 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6258 #endif
6259 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6260 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6261 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6262 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6263 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6264 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6265 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6266 #if defined(TARGET_PPC64)
6267 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6268 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6269 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6270 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6271 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6272 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6273 PPC_NONE, PPC2_ISA300),
6274 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6275 PPC_NONE, PPC2_ISA300),
6276 #endif
6277 #if defined(TARGET_PPC64)
6278 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6279 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6280 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6281 #endif
6282 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6283 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6284 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6285 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6286 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6287 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6288 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6289 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6290 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6291 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6292 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6293 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6294 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6295 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6296 #if defined(TARGET_PPC64)
6297 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6298 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6299 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6300 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6301 #endif
6302 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6303 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6304 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6305 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6306 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6307 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6308 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6309 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6310 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6311 #if defined(TARGET_PPC64)
6312 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6313 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6314 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6315 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6316 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6317 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6318 #endif
6319 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6320 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6321 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6322 #if defined(TARGET_PPC64)
6323 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6324 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6325 #endif
6326 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6327 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6328 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6329 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6330 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6331 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6332 #if defined(TARGET_PPC64)
6333 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6334 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6335 #endif
6336 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6337 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6338 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6339 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6340 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6341 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6342 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6343 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6344 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6345 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6346 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6347 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6348 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6349 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6350 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6351 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6352 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6353 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6354 #if defined(TARGET_PPC64)
6355 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6356 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6357 PPC_SEGMENT_64B),
6358 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6359 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6360 PPC_SEGMENT_64B),
6361 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6362 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6363 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6364 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6365 #endif
6366 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6367 /* XXX Those instructions will need to be handled differently for
6368 * different ISA versions */
6369 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6370 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6371 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6372 #if defined(TARGET_PPC64)
6373 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6374 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6375 #endif
6376 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6377 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6378 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6379 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6380 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6381 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6382 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6383 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6384 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6385 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6386 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6387 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6388 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6389 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6390 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6391 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6392 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6393 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6394 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6395 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6396 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6397 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6398 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6399 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6400 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6401 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6402 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6403 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6404 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6405 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6406 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6407 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6408 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6409 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6410 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6411 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6412 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6413 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6414 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6415 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6416 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6417 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6418 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6419 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6420 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6421 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6422 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6423 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6424 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6425 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6426 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6427 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6428 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6429 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6430 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6431 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6432 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6433 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6434 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6435 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6436 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6437 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6438 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6439 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6440 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6441 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6442 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6443 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6444 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6445 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6446 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6447 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6448 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6449 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6450 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6451 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6452 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6453 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6454 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6455 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6456 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6457 PPC_NONE, PPC2_BOOKE206),
6458 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6459 PPC_NONE, PPC2_BOOKE206),
6460 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6461 PPC_NONE, PPC2_BOOKE206),
6462 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6463 PPC_NONE, PPC2_BOOKE206),
6464 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6465 PPC_NONE, PPC2_BOOKE206),
6466 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6467 PPC_NONE, PPC2_PRCNTL),
6468 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6469 PPC_NONE, PPC2_PRCNTL),
6470 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6471 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6472 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6473 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6474 PPC_BOOKE, PPC2_BOOKE206),
6475 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6476 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6477 PPC_BOOKE, PPC2_BOOKE206),
6478 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6479 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6480 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6481 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6482 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6483 #if defined(TARGET_PPC64)
6484 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6485 PPC2_ISA300),
6486 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6487 #endif
6488
6489 #undef GEN_INT_ARITH_ADD
6490 #undef GEN_INT_ARITH_ADD_CONST
6491 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6492 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6493 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6494 add_ca, compute_ca, compute_ov) \
6495 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6496 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6497 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6498 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6499 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6500 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6501 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6502 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6503 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6504 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6505 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6506
6507 #undef GEN_INT_ARITH_DIVW
6508 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6509 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6510 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6511 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6512 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6513 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6514 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6515 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6516 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6517 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6518 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6519 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6520
6521 #if defined(TARGET_PPC64)
6522 #undef GEN_INT_ARITH_DIVD
6523 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6524 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6525 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6526 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6527 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6528 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6529
6530 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6531 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6532 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6533 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6534 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6535 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6536
6537 #undef GEN_INT_ARITH_MUL_HELPER
6538 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6539 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6540 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6541 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6542 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6543 #endif
6544
6545 #undef GEN_INT_ARITH_SUBF
6546 #undef GEN_INT_ARITH_SUBF_CONST
6547 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6548 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6549 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6550 add_ca, compute_ca, compute_ov) \
6551 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6552 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6553 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6554 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6555 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6556 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6557 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6558 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6559 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6560 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6561 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6562
6563 #undef GEN_LOGICAL1
6564 #undef GEN_LOGICAL2
6565 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6566 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6567 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6568 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6569 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6570 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6571 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6572 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6573 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6574 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6575 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6576 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6577 #if defined(TARGET_PPC64)
6578 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6579 #endif
6580
6581 #if defined(TARGET_PPC64)
6582 #undef GEN_PPC64_R2
6583 #undef GEN_PPC64_R4
6584 #define GEN_PPC64_R2(name, opc1, opc2) \
6585 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6586 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6587 PPC_64B)
6588 #define GEN_PPC64_R4(name, opc1, opc2) \
6589 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6590 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6591 PPC_64B), \
6592 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6593 PPC_64B), \
6594 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6595 PPC_64B)
6596 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6597 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6598 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6599 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6600 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6601 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6602 #endif
6603
6604 #undef GEN_LD
6605 #undef GEN_LDU
6606 #undef GEN_LDUX
6607 #undef GEN_LDX_E
6608 #undef GEN_LDS
6609 #define GEN_LD(name, ldop, opc, type) \
6610 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6611 #define GEN_LDU(name, ldop, opc, type) \
6612 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6613 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6614 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6615 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6616 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6617 #define GEN_LDS(name, ldop, op, type) \
6618 GEN_LD(name, ldop, op | 0x20, type) \
6619 GEN_LDU(name, ldop, op | 0x21, type) \
6620 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6621 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6622
6623 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6624 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6625 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6626 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6627 #if defined(TARGET_PPC64)
6628 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6629 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6630 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6631 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6632 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6633
6634 /* HV/P7 and later only */
6635 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6636 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6637 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6638 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6639 #endif
6640 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6641 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6642
6643 #undef GEN_ST
6644 #undef GEN_STU
6645 #undef GEN_STUX
6646 #undef GEN_STX_E
6647 #undef GEN_STS
6648 #define GEN_ST(name, stop, opc, type) \
6649 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6650 #define GEN_STU(name, stop, opc, type) \
6651 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6652 #define GEN_STUX(name, stop, opc2, opc3, type) \
6653 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6654 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6655 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6656 #define GEN_STS(name, stop, op, type) \
6657 GEN_ST(name, stop, op | 0x20, type) \
6658 GEN_STU(name, stop, op | 0x21, type) \
6659 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6660 GEN_STX(name, stop, 0x17, op | 0x00, type)
6661
6662 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6663 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6664 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6665 #if defined(TARGET_PPC64)
6666 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6667 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6668 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6669 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6670 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6671 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6672 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6673 #endif
6674 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6675 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6676
6677 #undef GEN_CRLOGIC
6678 #define GEN_CRLOGIC(name, tcg_op, opc) \
6679 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6680 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6681 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6682 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6683 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6684 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6685 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6686 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6687 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6688
6689 #undef GEN_MAC_HANDLER
6690 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6691 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6692 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6693 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6694 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6695 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6696 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6697 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6698 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6699 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6700 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6701 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6702 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6703 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6704 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6705 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6706 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6707 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6708 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6709 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6710 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6711 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6712 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6713 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6714 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6715 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6716 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6717 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6718 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6719 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6720 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6721 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6722 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6723 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6724 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6725 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6726 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6727 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6728 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6729 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6730 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6731 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6732 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6733 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6734
6735 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6736 PPC_NONE, PPC2_TM),
6737 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6738 PPC_NONE, PPC2_TM),
6739 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6740 PPC_NONE, PPC2_TM),
6741 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6742 PPC_NONE, PPC2_TM),
6743 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6744 PPC_NONE, PPC2_TM),
6745 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6746 PPC_NONE, PPC2_TM),
6747 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6748 PPC_NONE, PPC2_TM),
6749 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6750 PPC_NONE, PPC2_TM),
6751 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6752 PPC_NONE, PPC2_TM),
6753 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6754 PPC_NONE, PPC2_TM),
6755 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6756 PPC_NONE, PPC2_TM),
6757
6758 #include "translate/fp-ops.inc.c"
6759
6760 #include "translate/vmx-ops.inc.c"
6761
6762 #include "translate/vsx-ops.inc.c"
6763
6764 #include "translate/dfp-ops.inc.c"
6765
6766 #include "translate/spe-ops.inc.c"
6767 };
6768
6769 #include "helper_regs.h"
6770 #include "translate_init.c"
6771
6772 /*****************************************************************************/
6773 /* Misc PowerPC helpers */
6774 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6775 int flags)
6776 {
6777 #define RGPL 4
6778 #define RFPL 4
6779
6780 PowerPCCPU *cpu = POWERPC_CPU(cs);
6781 CPUPPCState *env = &cpu->env;
6782 int i;
6783
6784 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6785 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6786 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6787 cs->cpu_index);
6788 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6789 TARGET_FMT_lx " iidx %d didx %d\n",
6790 env->msr, env->spr[SPR_HID0],
6791 env->hflags, env->immu_idx, env->dmmu_idx);
6792 #if !defined(NO_TIMER_DUMP)
6793 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6794 #if !defined(CONFIG_USER_ONLY)
6795 " DECR %08" PRIu32
6796 #endif
6797 "\n",
6798 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6799 #if !defined(CONFIG_USER_ONLY)
6800 , cpu_ppc_load_decr(env)
6801 #endif
6802 );
6803 #endif
6804 for (i = 0; i < 32; i++) {
6805 if ((i & (RGPL - 1)) == 0)
6806 cpu_fprintf(f, "GPR%02d", i);
6807 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6808 if ((i & (RGPL - 1)) == (RGPL - 1))
6809 cpu_fprintf(f, "\n");
6810 }
6811 cpu_fprintf(f, "CR ");
6812 for (i = 0; i < 8; i++)
6813 cpu_fprintf(f, "%01x", env->crf[i]);
6814 cpu_fprintf(f, " [");
6815 for (i = 0; i < 8; i++) {
6816 char a = '-';
6817 if (env->crf[i] & 0x08)
6818 a = 'L';
6819 else if (env->crf[i] & 0x04)
6820 a = 'G';
6821 else if (env->crf[i] & 0x02)
6822 a = 'E';
6823 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6824 }
6825 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6826 env->reserve_addr);
6827 for (i = 0; i < 32; i++) {
6828 if ((i & (RFPL - 1)) == 0)
6829 cpu_fprintf(f, "FPR%02d", i);
6830 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6831 if ((i & (RFPL - 1)) == (RFPL - 1))
6832 cpu_fprintf(f, "\n");
6833 }
6834 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6835 #if !defined(CONFIG_USER_ONLY)
6836 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6837 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6838 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6839 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6840
6841 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6842 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6843 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6844 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6845
6846 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6847 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6848 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6849 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6850
6851 #if defined(TARGET_PPC64)
6852 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6853 env->excp_model == POWERPC_EXCP_POWER8) {
6854 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6855 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6856 }
6857 #endif
6858 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6859 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6860 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6861 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6862 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6863
6864 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6865 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6866 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6867 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6868
6869 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6870 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6871 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6872 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6873
6874 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6875 " EPR " TARGET_FMT_lx "\n",
6876 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6877 env->spr[SPR_BOOKE_EPR]);
6878
6879 /* FSL-specific */
6880 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6881 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6882 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6883 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6884
6885 /*
6886 * IVORs are left out as they are large and do not change often --
6887 * they can be read with "p $ivor0", "p $ivor1", etc.
6888 */
6889 }
6890
6891 #if defined(TARGET_PPC64)
6892 if (env->flags & POWERPC_FLAG_CFAR) {
6893 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6894 }
6895 #endif
6896
6897 switch (env->mmu_model) {
6898 case POWERPC_MMU_32B:
6899 case POWERPC_MMU_601:
6900 case POWERPC_MMU_SOFT_6xx:
6901 case POWERPC_MMU_SOFT_74xx:
6902 #if defined(TARGET_PPC64)
6903 case POWERPC_MMU_64B:
6904 case POWERPC_MMU_2_03:
6905 case POWERPC_MMU_2_06:
6906 case POWERPC_MMU_2_06a:
6907 case POWERPC_MMU_2_07:
6908 case POWERPC_MMU_2_07a:
6909 #endif
6910 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6911 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6912 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6913 break;
6914 case POWERPC_MMU_BOOKE206:
6915 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6916 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6917 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6918 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6919
6920 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6921 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6922 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6923 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6924
6925 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6926 " TLB1CFG " TARGET_FMT_lx "\n",
6927 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6928 env->spr[SPR_BOOKE_TLB1CFG]);
6929 break;
6930 default:
6931 break;
6932 }
6933 #endif
6934
6935 #undef RGPL
6936 #undef RFPL
6937 }
6938
6939 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6940 fprintf_function cpu_fprintf, int flags)
6941 {
6942 #if defined(DO_PPC_STATISTICS)
6943 PowerPCCPU *cpu = POWERPC_CPU(cs);
6944 opc_handler_t **t1, **t2, **t3, *handler;
6945 int op1, op2, op3;
6946
6947 t1 = cpu->env.opcodes;
6948 for (op1 = 0; op1 < 64; op1++) {
6949 handler = t1[op1];
6950 if (is_indirect_opcode(handler)) {
6951 t2 = ind_table(handler);
6952 for (op2 = 0; op2 < 32; op2++) {
6953 handler = t2[op2];
6954 if (is_indirect_opcode(handler)) {
6955 t3 = ind_table(handler);
6956 for (op3 = 0; op3 < 32; op3++) {
6957 handler = t3[op3];
6958 if (handler->count == 0)
6959 continue;
6960 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6961 "%016" PRIx64 " %" PRId64 "\n",
6962 op1, op2, op3, op1, (op3 << 5) | op2,
6963 handler->oname,
6964 handler->count, handler->count);
6965 }
6966 } else {
6967 if (handler->count == 0)
6968 continue;
6969 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6970 "%016" PRIx64 " %" PRId64 "\n",
6971 op1, op2, op1, op2, handler->oname,
6972 handler->count, handler->count);
6973 }
6974 }
6975 } else {
6976 if (handler->count == 0)
6977 continue;
6978 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6979 " %" PRId64 "\n",
6980 op1, op1, handler->oname,
6981 handler->count, handler->count);
6982 }
6983 }
6984 #endif
6985 }
6986
6987 /*****************************************************************************/
6988 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6989 {
6990 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6991 CPUState *cs = CPU(cpu);
6992 DisasContext ctx, *ctxp = &ctx;
6993 opc_handler_t **table, *handler;
6994 target_ulong pc_start;
6995 int num_insns;
6996 int max_insns;
6997
6998 pc_start = tb->pc;
6999 ctx.nip = pc_start;
7000 ctx.tb = tb;
7001 ctx.exception = POWERPC_EXCP_NONE;
7002 ctx.spr_cb = env->spr_cb;
7003 ctx.pr = msr_pr;
7004 ctx.mem_idx = env->dmmu_idx;
7005 ctx.dr = msr_dr;
7006 #if !defined(CONFIG_USER_ONLY)
7007 ctx.hv = msr_hv || !env->has_hv_mode;
7008 #endif
7009 ctx.insns_flags = env->insns_flags;
7010 ctx.insns_flags2 = env->insns_flags2;
7011 ctx.access_type = -1;
7012 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7013 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7014 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7015 #if defined(TARGET_PPC64)
7016 ctx.sf_mode = msr_is_64bit(env, env->msr);
7017 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7018 #endif
7019 if (env->mmu_model == POWERPC_MMU_32B ||
7020 env->mmu_model == POWERPC_MMU_601 ||
7021 (env->mmu_model & POWERPC_MMU_64B))
7022 ctx.lazy_tlb_flush = true;
7023
7024 ctx.fpu_enabled = !!msr_fp;
7025 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7026 ctx.spe_enabled = !!msr_spe;
7027 else
7028 ctx.spe_enabled = false;
7029 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7030 ctx.altivec_enabled = !!msr_vr;
7031 else
7032 ctx.altivec_enabled = false;
7033 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7034 ctx.vsx_enabled = !!msr_vsx;
7035 } else {
7036 ctx.vsx_enabled = false;
7037 }
7038 #if defined(TARGET_PPC64)
7039 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7040 ctx.tm_enabled = !!msr_tm;
7041 } else {
7042 ctx.tm_enabled = false;
7043 }
7044 #endif
7045 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7046 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7047 else
7048 ctx.singlestep_enabled = 0;
7049 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7050 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7051 if (unlikely(cs->singlestep_enabled)) {
7052 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7053 }
7054 #if defined (DO_SINGLE_STEP) && 0
7055 /* Single step trace mode */
7056 msr_se = 1;
7057 #endif
7058 num_insns = 0;
7059 max_insns = tb->cflags & CF_COUNT_MASK;
7060 if (max_insns == 0) {
7061 max_insns = CF_COUNT_MASK;
7062 }
7063 if (max_insns > TCG_MAX_INSNS) {
7064 max_insns = TCG_MAX_INSNS;
7065 }
7066
7067 gen_tb_start(tb);
7068 tcg_clear_temp_count();
7069 /* Set env in case of segfault during code fetch */
7070 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7071 tcg_gen_insn_start(ctx.nip);
7072 num_insns++;
7073
7074 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7075 gen_debug_exception(ctxp);
7076 /* The address covered by the breakpoint must be included in
7077 [tb->pc, tb->pc + tb->size) in order to for it to be
7078 properly cleared -- thus we increment the PC here so that
7079 the logic setting tb->size below does the right thing. */
7080 ctx.nip += 4;
7081 break;
7082 }
7083
7084 LOG_DISAS("----------------\n");
7085 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7086 ctx.nip, ctx.mem_idx, (int)msr_ir);
7087 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7088 gen_io_start();
7089 if (unlikely(need_byteswap(&ctx))) {
7090 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7091 } else {
7092 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7093 }
7094 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7095 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7096 opc3(ctx.opcode), opc4(ctx.opcode),
7097 ctx.le_mode ? "little" : "big");
7098 ctx.nip += 4;
7099 table = env->opcodes;
7100 handler = table[opc1(ctx.opcode)];
7101 if (is_indirect_opcode(handler)) {
7102 table = ind_table(handler);
7103 handler = table[opc2(ctx.opcode)];
7104 if (is_indirect_opcode(handler)) {
7105 table = ind_table(handler);
7106 handler = table[opc3(ctx.opcode)];
7107 if (is_indirect_opcode(handler)) {
7108 table = ind_table(handler);
7109 handler = table[opc4(ctx.opcode)];
7110 }
7111 }
7112 }
7113 /* Is opcode *REALLY* valid ? */
7114 if (unlikely(handler->handler == &gen_invalid)) {
7115 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7116 "%02x - %02x - %02x - %02x (%08x) "
7117 TARGET_FMT_lx " %d\n",
7118 opc1(ctx.opcode), opc2(ctx.opcode),
7119 opc3(ctx.opcode), opc4(ctx.opcode),
7120 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7121 } else {
7122 uint32_t inval;
7123
7124 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7125 inval = handler->inval2;
7126 } else {
7127 inval = handler->inval1;
7128 }
7129
7130 if (unlikely((ctx.opcode & inval) != 0)) {
7131 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7132 "%02x - %02x - %02x - %02x (%08x) "
7133 TARGET_FMT_lx "\n", ctx.opcode & inval,
7134 opc1(ctx.opcode), opc2(ctx.opcode),
7135 opc3(ctx.opcode), opc4(ctx.opcode),
7136 ctx.opcode, ctx.nip - 4);
7137 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7138 break;
7139 }
7140 }
7141 (*(handler->handler))(&ctx);
7142 #if defined(DO_PPC_STATISTICS)
7143 handler->count++;
7144 #endif
7145 /* Check trace mode exceptions */
7146 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7147 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7148 ctx.exception != POWERPC_SYSCALL &&
7149 ctx.exception != POWERPC_EXCP_TRAP &&
7150 ctx.exception != POWERPC_EXCP_BRANCH)) {
7151 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7152 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7153 (cs->singlestep_enabled) ||
7154 singlestep ||
7155 num_insns >= max_insns)) {
7156 /* if we reach a page boundary or are single stepping, stop
7157 * generation
7158 */
7159 break;
7160 }
7161 if (tcg_check_temp_count()) {
7162 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7163 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7164 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7165 exit(1);
7166 }
7167 }
7168 if (tb->cflags & CF_LAST_IO)
7169 gen_io_end();
7170 if (ctx.exception == POWERPC_EXCP_NONE) {
7171 gen_goto_tb(&ctx, 0, ctx.nip);
7172 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7173 if (unlikely(cs->singlestep_enabled)) {
7174 gen_debug_exception(ctxp);
7175 }
7176 /* Generate the return instruction */
7177 tcg_gen_exit_tb(0);
7178 }
7179 gen_tb_end(tb, num_insns);
7180
7181 tb->size = ctx.nip - pc_start;
7182 tb->icount = num_insns;
7183
7184 #if defined(DEBUG_DISAS)
7185 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7186 && qemu_log_in_addr_range(pc_start)) {
7187 int flags;
7188 flags = env->bfd_mach;
7189 flags |= ctx.le_mode << 16;
7190 qemu_log_lock();
7191 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7192 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7193 qemu_log("\n");
7194 qemu_log_unlock();
7195 }
7196 #endif
7197 }
7198
7199 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7200 target_ulong *data)
7201 {
7202 env->nip = data[0];
7203 }
AR7 emulation for QEMU