| blob | f0dd71dd087d50b2596e0bbd8fa81674cc02e0d2 |
1 #
2 # HPPA instruction decode definitions.
3 #
4 # Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
5 #
6 # This library is free software; you can redistribute it and/or
7 # modify it under the terms of the GNU Lesser General Public
8 # License as published by the Free Software Foundation; either
9 # version 2 of the License, or (at your option) any later version.
10 #
11 # This library is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 # Lesser General Public License for more details.
15 #
16 # You should have received a copy of the GNU Lesser General Public
17 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
20 ####
21 # Field definitions
22 ####
24 %assemble_sr3 13:1 14:2
25 %assemble_sr3x 13:1 14:2 !function=expand_sr3x
27 %assemble_11a 0:s1 4:10 !function=expand_shl3
28 %assemble_12 0:s1 2:1 3:10 !function=expand_shl2
29 %assemble_12a 0:s1 3:11 !function=expand_shl2
30 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
31 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
33 %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
35 %lowsign_11 0:s1 1:10
36 %lowsign_14 0:s1 1:13
38 %sm_imm 16:10 !function=expand_sm_imm
40 %rm64 1:1 16:5
41 %rt64 6:1 0:5
42 %ra64 7:1 21:5
43 %rb64 12:1 16:5
44 %rc64 8:1 13:3 9:2
45 %rc32 13:3 9:2
47 %im5_0 0:s1 1:4
48 %im5_16 16:s1 17:4
49 %ma_to_m 5:1 13:1 !function=ma_to_m
50 %ma2_to_m 2:2 !function=ma_to_m
51 %pos_to_m 0:1 !function=pos_to_m
52 %neg_to_m 0:1 !function=neg_to_m
53 %a_to_m 2:1 !function=neg_to_m
55 ####
56 # Argument set definitions
57 ####
59 # All insns that need to form a virtual address should use this set.
60 &ldst t b x disp sp m scale size
62 &rr_cf t r cf
63 &rrr_cf t r1 r2 cf
64 &rrr_cf_sh t r1 r2 cf sh
65 &rri_cf t r i cf
67 &rrb_c_f disp n c f r1 r2
68 &rib_c_f disp n c f r i
70 ####
71 # Format definitions
72 ####
74 @rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf
75 @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
76 @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
77 @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
78 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
80 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
81 &rrb_c_f disp=%assemble_12
82 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \
83 &rib_c_f disp=%assemble_12 i=%im5_16
85 ####
86 # System
87 ####
89 break 000000 ----- ----- --- 00000000 -----
91 mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3
92 mtctl 000000 t:5 r:5 --- 11000010 00000
93 mtsarcm 000000 01011 r:5 --- 11000110 00000
94 mtsm 000000 00000 r:5 000 11000011 00000
96 mfia 000000 ----- 00000 --- 10100101 t:5
97 mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
98 mfctl 000000 r:5 00000- e:1 -01000101 t:5
100 sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
102 ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
104 rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
105 ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
107 rfi 000000 ----- ----- --- 01100000 00000
108 rfi_r 000000 ----- ----- --- 01100101 00000
110 # These are artificial instructions used by QEMU firmware.
111 # They are allocated from the unassigned instruction space.
112 halt 1111 1111 1111 1101 1110 1010 1101 0000
113 reset 1111 1111 1111 1101 1110 1010 1101 0001
115 ####
116 # Memory Management
117 ####
119 @addrx ...... b:5 x:5 .. ........ m:1 ..... \
120 &ldst disp=0 scale=0 t=0 sp=0 size=0
122 nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
123 nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
124 nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
125 nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
126 nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
127 nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
128 nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
130 probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
132 ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
133 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
134 sp=%assemble_sr3x data=0
136 # pcxl and pcxl2 Fast TLB Insert instructions
137 ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
139 pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
140 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
141 sp=%assemble_sr3x data=0
143 lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
144 &ldst disp=0 scale=0 size=0
146 lci 000001 ----- ----- -- 01001100 0 t:5
148 ####
149 # Arith/Log
150 ####
152 andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf
153 and 000010 ..... ..... .... 001000 0 ..... @rrr_cf
154 or 000010 ..... ..... .... 001001 0 ..... @rrr_cf
155 xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf
156 uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
157 ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
158 cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
159 uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf
160 uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf
161 dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf
162 dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf
164 add 000010 ..... ..... .... 0110.. 0 ..... @rrr_cf_sh
165 add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
166 add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh
167 add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0
168 add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0
170 sub 000010 ..... ..... .... 010000 0 ..... @rrr_cf
171 sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
172 sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
173 sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
174 sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf
175 sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf
177 ldil 001000 t:5 ..................... i=%assemble_21
178 addil 001010 r:5 ..................... i=%assemble_21
179 ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
181 addi 101101 ..... ..... .... 0 ........... @rri_cf
182 addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
183 addi_tc 101100 ..... ..... .... 0 ........... @rri_cf
184 addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
186 subi 100101 ..... ..... .... 0 ........... @rri_cf
187 subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
189 cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf
191 ####
192 # Index Mem
193 ####
195 @ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
196 @ldim5 ...... b:5 ..... sp:2 ......... t:5 \
197 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
198 @stim5 ...... b:5 t:5 sp:2 ......... ..... \
199 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
201 ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
202 ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
203 st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
204 ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
205 ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
206 lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
207 lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
208 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
209 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
211 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
212 &ldst t=%rt64 disp=0 size=2
213 @fldstwi ...... b:5 ..... sp:2 . ....... . ..... \
214 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2
216 fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx
217 fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi
218 fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx
219 fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi
221 @fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \
222 &ldst disp=0 size=3
223 @fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \
224 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3
226 fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx
227 fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi
228 fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx
229 fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
231 ####
232 # Offset Mem
233 ####
235 @ldstim14 ...... b:5 t:5 sp:2 .............. \
236 &ldst disp=%lowsign_14 x=0 scale=0 m=0
237 @ldstim14m ...... b:5 t:5 sp:2 .............. \
238 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
239 @ldstim12m ...... b:5 t:5 sp:2 .............. \
240 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
242 # LDB, LDH, LDW, LDWM
243 ld 010000 ..... ..... .. .............. @ldstim14 size=0
244 ld 010001 ..... ..... .. .............. @ldstim14 size=1
245 ld 010010 ..... ..... .. .............. @ldstim14 size=2
246 ld 010011 ..... ..... .. .............. @ldstim14m size=2
247 ld 010111 ..... ..... .. ...........10. @ldstim12m size=2
249 # STB, STH, STW, STWM
250 st 011000 ..... ..... .. .............. @ldstim14 size=0
251 st 011001 ..... ..... .. .............. @ldstim14 size=1
252 st 011010 ..... ..... .. .............. @ldstim14 size=2
253 st 011011 ..... ..... .. .............. @ldstim14m size=2
254 st 011111 ..... ..... .. ...........10. @ldstim12m size=2
256 fldw 010110 b:5 ..... sp:2 .............. \
257 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
258 fldw 010111 b:5 ..... sp:2 ...........0.. \
259 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
261 fstw 011110 b:5 ..... sp:2 .............. \
262 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
263 fstw 011111 b:5 ..... sp:2 ...........0.. \
264 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
266 fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \
267 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
269 fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \
270 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
272 ####
273 # Floating-point Multiply Add
274 ####
276 &mpyadd rm1 rm2 ta ra tm
277 @mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
279 fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
280 fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
281 fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
282 fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
284 ####
285 # Conditional Branches
286 ####
288 bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
289 bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
291 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
292 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
294 cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=0
295 cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=1
296 cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=0
297 cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=1
299 addb 101000 ..... ..... ... ........... . . @rrb_cf f=0
300 addb 101010 ..... ..... ... ........... . . @rrb_cf f=1
301 addbi 101001 ..... ..... ... ........... . . @rib_cf f=0
302 addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
304 ####
305 # Shift, Extract, Deposit
306 ####
308 shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
309 shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
311 extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5
312 extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5
314 depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5
315 depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5
316 depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16
317 depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16
319 ####
320 # Branch External
321 ####
323 &BE b l n disp sp
324 @be ...... b:5 ..... ... ........... n:1 . \
325 &BE disp=%assemble_17 sp=%assemble_sr3
327 be 111000 ..... ..... ... ........... . . @be l=0
328 be 111001 ..... ..... ... ........... . . @be l=31
330 ####
331 # Branch
332 ####
334 &BL l n disp
335 @bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17
337 # B,L and B,L,PUSH
338 bl 111010 ..... ..... 000 ........... . . @bl
339 bl 111010 ..... ..... 100 ........... . . @bl
340 # B,L (long displacement)
341 bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \
342 disp=%assemble_22
343 b_gate 111010 ..... ..... 001 ........... . . @bl
344 blr 111010 l:5 x:5 010 00000000000 n:1 0
345 bv 111010 b:5 x:5 110 00000000000 n:1 0
346 bve 111010 b:5 00000 110 10000000000 n:1 - l=0
347 bve 111010 b:5 00000 111 10000000000 n:1 - l=2
349 ####
350 # FP Fused Multiple-Add
351 ####
353 fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \
354 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64
355 fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
357 ####
358 # FP operations
359 ####
361 &fclass01 r t
362 &fclass2 r1 r2 c y
363 &fclass3 r1 r2 t
365 @f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01
366 @f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01
367 @f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2
368 @f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3
370 @f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \
371 &fclass01 r=%ra64 t=%rt64
372 @f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01
374 @f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \
375 &fclass01 r=%ra64 t=%rt64
376 @f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64
377 @f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64
378 @f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01
380 @f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \
381 &fclass2 r1=%ra64 r2=%rb64
382 @f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2
384 @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \
385 &fclass3 r1=%ra64 r2=%rb64 t=%rt64
386 @f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5
388 # Floating point class 0
390 # FID. With r = t = 0, which via fcpy puts 0 into fr0.
391 # This is machine/revision = 0, which is reserved for simulator.
392 fcpy_f 001100 00000 00000 00000 000000 00000 \
393 &fclass01 r=0 t=0
395 fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0
396 fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0
397 fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0
398 frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0
399 fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0
400 fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0
402 fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0
403 fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0
404 fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0
405 frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0
406 fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0
407 fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0
409 fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0
410 fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0
411 fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0
412 frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0
413 fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0
414 fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0
416 fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0
417 fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0
418 fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0
419 frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0
420 fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0
421 fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0
423 # Floating point class 1
425 # float/float
426 fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1
427 fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1
429 fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1
430 fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1
432 # int/float
433 fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1
434 fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1
435 fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1
436 fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1
438 fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1
439 fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1
440 fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1
441 fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1
443 # float/int
444 fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1
445 fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1
446 fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1
447 fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1
449 fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1
450 fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1
451 fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1
452 fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1
454 # float/int truncate
455 fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1
456 fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1
457 fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1
458 fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1
460 fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1
461 fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1
462 fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1
463 fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1
465 # uint/float
466 fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1
467 fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1
468 fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1
469 fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1
471 fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1
472 fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1
473 fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1
474 fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1
476 # float/int
477 fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1
478 fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1
479 fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1
480 fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1
482 fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1
483 fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1
484 fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1
485 fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1
487 # float/int truncate
488 fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1
489 fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1
490 fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1
491 fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1
493 fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1
494 fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1
495 fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1
496 fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1
498 # Floating point class 2
500 ftest 001100 00000 00000 y:3 00 10000 1 c:5
502 fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2
503 fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2
505 fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2
506 fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2
508 # Floating point class 3
510 fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3
511 fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3
512 fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3
513 fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3
515 fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3
516 fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3
517 fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3
518 fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3
520 fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3
521 fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3
522 fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3
523 fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3
525 fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3
526 fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3
527 fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3
528 fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
530 xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64
532 # diag
533 diag 000101 ----- ----- ---- ---- ---- ----