hw/net/e1000e.c

   1 /*
   2 * QEMU INTEL 82574 GbE NIC emulation
   3 *
   4 * Software developer's manuals:
   5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
   6 *
   7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   8 * Developed by Daynix Computing LTD (http://www.daynix.com)
   9 *
  10 * Authors:
  11 * Dmitry Fleytman <dmitry@daynix.com>
  12 * Leonid Bloch <leonid@daynix.com>
  13 * Yan Vugenfirer <yan@daynix.com>
  14 *
  15 * Based on work done by:
  16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  17 * Copyright (c) 2008 Qumranet
  18 * Based on work done by:
  19 * Copyright (c) 2007 Dan Aloni
  20 * Copyright (c) 2004 Antony T Curtis
  21 *
  22 * This library is free software; you can redistribute it and/or
  23 * modify it under the terms of the GNU Lesser General Public
  24 * License as published by the Free Software Foundation; either
  25 * version 2 of the License, or (at your option) any later version.
  26 *
  27 * This library is distributed in the hope that it will be useful,
  28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  30 * Lesser General Public License for more details.
  31 *
  32 * You should have received a copy of the GNU Lesser General Public
  33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  34 */
  35
  36 #include "qemu/osdep.h"
  37 #include "qemu/units.h"
  38 #include "net/net.h"
  39 #include "net/tap.h"
  40 #include "qemu/range.h"
  41 #include "sysemu/sysemu.h"
  42 #include "hw/pci/msi.h"
  43 #include "hw/pci/msix.h"
  44
  45 #include "e1000_regs.h"
  46
  47 #include "e1000x_common.h"
  48 #include "e1000e_core.h"
  49
  50 #include "trace.h"
  51 #include "qapi/error.h"
  52
  53 #define TYPE_E1000E "e1000e"
  54 #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
  55
  56 typedef struct E1000EState {
  57     PCIDevice parent_obj;
  58     NICState *nic;
  59     NICConf conf;
  60
  61     MemoryRegion mmio;
  62     MemoryRegion flash;
  63     MemoryRegion io;
  64     MemoryRegion msix;
  65
  66     uint32_t ioaddr;
  67
  68     uint16_t subsys_ven;
  69     uint16_t subsys;
  70
  71     uint16_t subsys_ven_used;
  72     uint16_t subsys_used;
  73
  74     bool disable_vnet;
  75
  76     E1000ECore core;
  77
  78 } E1000EState;
  79
  80 #define E1000E_MMIO_IDX     0
  81 #define E1000E_FLASH_IDX    1
  82 #define E1000E_IO_IDX       2
  83 #define E1000E_MSIX_IDX     3
  84
  85 #define E1000E_MMIO_SIZE    (128 * KiB)
  86 #define E1000E_FLASH_SIZE   (128 * KiB)
  87 #define E1000E_IO_SIZE      (32)
  88 #define E1000E_MSIX_SIZE    (16 * KiB)
  89
  90 #define E1000E_MSIX_TABLE   (0x0000)
  91 #define E1000E_MSIX_PBA     (0x2000)
  92
  93 static uint64_t
  94 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
  95 {
  96     E1000EState *s = opaque;
  97     return e1000e_core_read(&s->core, addr, size);
  98 }
  99
 100 static void
 101 e1000e_mmio_write(void *opaque, hwaddr addr,
 102                    uint64_t val, unsigned size)
 103 {
 104     E1000EState *s = opaque;
 105     e1000e_core_write(&s->core, addr, val, size);
 106 }
 107
 108 static bool
 109 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
 110 {
 111     if (s->ioaddr < 0x1FFFF) {
 112         *idx = s->ioaddr;
 113         return true;
 114     }
 115
 116     if (s->ioaddr < 0x7FFFF) {
 117         trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
 118         return false;
 119     }
 120
 121     if (s->ioaddr < 0xFFFFF) {
 122         trace_e1000e_wrn_io_addr_flash(s->ioaddr);
 123         return false;
 124     }
 125
 126     trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
 127     return false;
 128 }
 129
 130 static uint64_t
 131 e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
 132 {
 133     E1000EState *s = opaque;
 134     uint32_t idx = 0;
 135     uint64_t val;
 136
 137     switch (addr) {
 138     case E1000_IOADDR:
 139         trace_e1000e_io_read_addr(s->ioaddr);
 140         return s->ioaddr;
 141     case E1000_IODATA:
 142         if (e1000e_io_get_reg_index(s, &idx)) {
 143             val = e1000e_core_read(&s->core, idx, sizeof(val));
 144             trace_e1000e_io_read_data(idx, val);
 145             return val;
 146         }
 147         return 0;
 148     default:
 149         trace_e1000e_wrn_io_read_unknown(addr);
 150         return 0;
 151     }
 152 }
 153
 154 static void
 155 e1000e_io_write(void *opaque, hwaddr addr,
 156                 uint64_t val, unsigned size)
 157 {
 158     E1000EState *s = opaque;
 159     uint32_t idx = 0;
 160
 161     switch (addr) {
 162     case E1000_IOADDR:
 163         trace_e1000e_io_write_addr(val);
 164         s->ioaddr = (uint32_t) val;
 165         return;
 166     case E1000_IODATA:
 167         if (e1000e_io_get_reg_index(s, &idx)) {
 168             trace_e1000e_io_write_data(idx, val);
 169             e1000e_core_write(&s->core, idx, val, sizeof(val));
 170         }
 171         return;
 172     default:
 173         trace_e1000e_wrn_io_write_unknown(addr);
 174         return;
 175     }
 176 }
 177
 178 static const MemoryRegionOps mmio_ops = {
 179     .read = e1000e_mmio_read,
 180     .write = e1000e_mmio_write,
 181     .endianness = DEVICE_LITTLE_ENDIAN,
 182     .impl = {
 183         .min_access_size = 4,
 184         .max_access_size = 4,
 185     },
 186 };
 187
 188 static const MemoryRegionOps io_ops = {
 189     .read = e1000e_io_read,
 190     .write = e1000e_io_write,
 191     .endianness = DEVICE_LITTLE_ENDIAN,
 192     .impl = {
 193         .min_access_size = 4,
 194         .max_access_size = 4,
 195     },
 196 };
 197
 198 static int
 199 e1000e_nc_can_receive(NetClientState *nc)
 200 {
 201     E1000EState *s = qemu_get_nic_opaque(nc);
 202     return e1000e_can_receive(&s->core);
 203 }
 204
 205 static ssize_t
 206 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
 207 {
 208     E1000EState *s = qemu_get_nic_opaque(nc);
 209     return e1000e_receive_iov(&s->core, iov, iovcnt);
 210 }
 211
 212 static ssize_t
 213 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 214 {
 215     E1000EState *s = qemu_get_nic_opaque(nc);
 216     return e1000e_receive(&s->core, buf, size);
 217 }
 218
 219 static void
 220 e1000e_set_link_status(NetClientState *nc)
 221 {
 222     E1000EState *s = qemu_get_nic_opaque(nc);
 223     e1000e_core_set_link_status(&s->core);
 224 }
 225
 226 static NetClientInfo net_e1000e_info = {
 227     .type = NET_CLIENT_DRIVER_NIC,
 228     .size = sizeof(NICState),
 229     .can_receive = e1000e_nc_can_receive,
 230     .receive = e1000e_nc_receive,
 231     .receive_iov = e1000e_nc_receive_iov,
 232     .link_status_changed = e1000e_set_link_status,
 233 };
 234
 235 /*
 236 * EEPROM (NVM) contents documented in Table 36, section 6.1
 237 * and generally 6.1.2 Software accessed words.
 238 */
 239 static const uint16_t e1000e_eeprom_template[64] = {
 240   /*        Address        |    Compat.    | ImVer |   Compat.     */
 241     0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
 242   /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
 243     0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
 244   /*    NVM words 1,2,3    |-------------------------------|PCI-EID*/
 245     0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
 246   /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
 247     0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
 248   /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
 249     0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
 250   /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP  */
 251     0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
 252   /*                            SW Section                         */
 253     0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
 254   /*                      SW Section                       |CHKSUM */
 255     0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
 256 };
 257
 258 static void e1000e_core_realize(E1000EState *s)
 259 {
 260     s->core.owner = &s->parent_obj;
 261     s->core.owner_nic = s->nic;
 262 }
 263
 264 static void
 265 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
 266 {
 267     int i;
 268     for (i = 0; i < num_vectors; i++) {
 269         msix_vector_unuse(PCI_DEVICE(s), i);
 270     }
 271 }
 272
 273 static bool
 274 e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
 275 {
 276     int i;
 277     for (i = 0; i < num_vectors; i++) {
 278         int res = msix_vector_use(PCI_DEVICE(s), i);
 279         if (res < 0) {
 280             trace_e1000e_msix_use_vector_fail(i, res);
 281             e1000e_unuse_msix_vectors(s, i);
 282             return false;
 283         }
 284     }
 285     return true;
 286 }
 287
 288 static void
 289 e1000e_init_msix(E1000EState *s)
 290 {
 291     PCIDevice *d = PCI_DEVICE(s);
 292     int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
 293                         &s->msix,
 294                         E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
 295                         &s->msix,
 296                         E1000E_MSIX_IDX, E1000E_MSIX_PBA,
 297                         0xA0, NULL);
 298
 299     if (res < 0) {
 300         trace_e1000e_msix_init_fail(res);
 301     } else {
 302         if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
 303             msix_uninit(d, &s->msix, &s->msix);
 304         }
 305     }
 306 }
 307
 308 static void
 309 e1000e_cleanup_msix(E1000EState *s)
 310 {
 311     if (msix_present(PCI_DEVICE(s))) {
 312         e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
 313         msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
 314     }
 315 }
 316
 317 static void
 318 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
 319 {
 320     DeviceState *dev = DEVICE(pci_dev);
 321     NetClientState *nc;
 322     int i;
 323
 324     s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
 325         object_get_typename(OBJECT(s)), dev->id, s);
 326
 327     s->core.max_queue_num = s->conf.peers.queues - 1;
 328
 329     trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
 330     memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
 331
 332     qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
 333
 334     /* Setup virtio headers */
 335     if (s->disable_vnet) {
 336         s->core.has_vnet = false;
 337         trace_e1000e_cfg_support_virtio(false);
 338         return;
 339     } else {
 340         s->core.has_vnet = true;
 341     }
 342
 343     for (i = 0; i < s->conf.peers.queues; i++) {
 344         nc = qemu_get_subqueue(s->nic, i);
 345         if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
 346             s->core.has_vnet = false;
 347             trace_e1000e_cfg_support_virtio(false);
 348             return;
 349         }
 350     }
 351
 352     trace_e1000e_cfg_support_virtio(true);
 353
 354     for (i = 0; i < s->conf.peers.queues; i++) {
 355         nc = qemu_get_subqueue(s->nic, i);
 356         qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
 357         qemu_using_vnet_hdr(nc->peer, true);
 358     }
 359 }
 360
 361 static inline uint64_t
 362 e1000e_gen_dsn(uint8_t *mac)
 363 {
 364     return (uint64_t)(mac[5])        |
 365            (uint64_t)(mac[4])  << 8  |
 366            (uint64_t)(mac[3])  << 16 |
 367            (uint64_t)(0x00FF)  << 24 |
 368            (uint64_t)(0x00FF)  << 32 |
 369            (uint64_t)(mac[2])  << 40 |
 370            (uint64_t)(mac[1])  << 48 |
 371            (uint64_t)(mac[0])  << 56;
 372 }
 373
 374 static int
 375 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
 376 {
 377     Error *local_err = NULL;
 378     int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
 379                                  PCI_PM_SIZEOF, &local_err);
 380
 381     if (local_err) {
 382         error_report_err(local_err);
 383         return ret;
 384     }
 385
 386     pci_set_word(pdev->config + offset + PCI_PM_PMC,
 387                  PCI_PM_CAP_VER_1_1 |
 388                  pmc);
 389
 390     pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
 391                  PCI_PM_CTRL_STATE_MASK |
 392                  PCI_PM_CTRL_PME_ENABLE |
 393                  PCI_PM_CTRL_DATA_SEL_MASK);
 394
 395     pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
 396                  PCI_PM_CTRL_PME_STATUS);
 397
 398     return ret;
 399 }
 400
 401 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
 402                                 uint32_t val, int len)
 403 {
 404     E1000EState *s = E1000E(pci_dev);
 405
 406     pci_default_write_config(pci_dev, address, val, len);
 407
 408     if (range_covers_byte(address, len, PCI_COMMAND) &&
 409         (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
 410         e1000e_start_recv(&s->core);
 411     }
 412 }
 413
 414 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
 415 {
 416     static const uint16_t e1000e_pmrb_offset = 0x0C8;
 417     static const uint16_t e1000e_pcie_offset = 0x0E0;
 418     static const uint16_t e1000e_aer_offset =  0x100;
 419     static const uint16_t e1000e_dsn_offset =  0x140;
 420     E1000EState *s = E1000E(pci_dev);
 421     uint8_t *macaddr;
 422     int ret;
 423
 424     trace_e1000e_cb_pci_realize();
 425
 426     pci_dev->config_write = e1000e_write_config;
 427
 428     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
 429     pci_dev->config[PCI_INTERRUPT_PIN] = 1;
 430
 431     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
 432     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
 433
 434     s->subsys_ven_used = s->subsys_ven;
 435     s->subsys_used = s->subsys;
 436
 437     /* Define IO/MMIO regions */
 438     memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
 439                           "e1000e-mmio", E1000E_MMIO_SIZE);
 440     pci_register_bar(pci_dev, E1000E_MMIO_IDX,
 441                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 442
 443     /*
 444      * We provide a dummy implementation for the flash BAR
 445      * for drivers that may theoretically probe for its presence.
 446      */
 447     memory_region_init(&s->flash, OBJECT(s),
 448                        "e1000e-flash", E1000E_FLASH_SIZE);
 449     pci_register_bar(pci_dev, E1000E_FLASH_IDX,
 450                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
 451
 452     memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
 453                           "e1000e-io", E1000E_IO_SIZE);
 454     pci_register_bar(pci_dev, E1000E_IO_IDX,
 455                      PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 456
 457     memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
 458                        E1000E_MSIX_SIZE);
 459     pci_register_bar(pci_dev, E1000E_MSIX_IDX,
 460                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
 461
 462     /* Create networking backend */
 463     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 464     macaddr = s->conf.macaddr.a;
 465
 466     e1000e_init_msix(s);
 467
 468     if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
 469         hw_error("Failed to initialize PCIe capability");
 470     }
 471
 472     ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
 473     if (ret) {
 474         trace_e1000e_msi_init_fail(ret);
 475     }
 476
 477     if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
 478                                   PCI_PM_CAP_DSI) < 0) {
 479         hw_error("Failed to initialize PM capability");
 480     }
 481
 482     if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
 483                       PCI_ERR_SIZEOF, NULL) < 0) {
 484         hw_error("Failed to initialize AER capability");
 485     }
 486
 487     pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
 488                           e1000e_gen_dsn(macaddr));
 489
 490     e1000e_init_net_peer(s, pci_dev, macaddr);
 491
 492     /* Initialize core */
 493     e1000e_core_realize(s);
 494
 495     e1000e_core_pci_realize(&s->core,
 496                             e1000e_eeprom_template,
 497                             sizeof(e1000e_eeprom_template),
 498                             macaddr);
 499 }
 500
 501 static void e1000e_pci_uninit(PCIDevice *pci_dev)
 502 {
 503     E1000EState *s = E1000E(pci_dev);
 504
 505     trace_e1000e_cb_pci_uninit();
 506
 507     e1000e_core_pci_uninit(&s->core);
 508
 509     pcie_aer_exit(pci_dev);
 510     pcie_cap_exit(pci_dev);
 511
 512     qemu_del_nic(s->nic);
 513
 514     e1000e_cleanup_msix(s);
 515     msi_uninit(pci_dev);
 516 }
 517
 518 static void e1000e_qdev_reset(DeviceState *dev)
 519 {
 520     E1000EState *s = E1000E(dev);
 521
 522     trace_e1000e_cb_qdev_reset();
 523
 524     e1000e_core_reset(&s->core);
 525 }
 526
 527 static int e1000e_pre_save(void *opaque)
 528 {
 529     E1000EState *s = opaque;
 530
 531     trace_e1000e_cb_pre_save();
 532
 533     e1000e_core_pre_save(&s->core);
 534
 535     return 0;
 536 }
 537
 538 static int e1000e_post_load(void *opaque, int version_id)
 539 {
 540     E1000EState *s = opaque;
 541
 542     trace_e1000e_cb_post_load();
 543
 544     if ((s->subsys != s->subsys_used) ||
 545         (s->subsys_ven != s->subsys_ven_used)) {
 546         fprintf(stderr,
 547             "ERROR: Cannot migrate while device properties "
 548             "(subsys/subsys_ven) differ");
 549         return -1;
 550     }
 551
 552     return e1000e_core_post_load(&s->core);
 553 }
 554
 555 static const VMStateDescription e1000e_vmstate_tx = {
 556     .name = "e1000e-tx",
 557     .version_id = 1,
 558     .minimum_version_id = 1,
 559     .fields = (VMStateField[]) {
 560         VMSTATE_UINT8(sum_needed, struct e1000e_tx),
 561         VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
 562         VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
 563         VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
 564         VMSTATE_UINT8(props.tucss, struct e1000e_tx),
 565         VMSTATE_UINT8(props.tucso, struct e1000e_tx),
 566         VMSTATE_UINT16(props.tucse, struct e1000e_tx),
 567         VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
 568         VMSTATE_UINT16(props.mss, struct e1000e_tx),
 569         VMSTATE_UINT32(props.paylen, struct e1000e_tx),
 570         VMSTATE_INT8(props.ip, struct e1000e_tx),
 571         VMSTATE_INT8(props.tcp, struct e1000e_tx),
 572         VMSTATE_BOOL(props.tse, struct e1000e_tx),
 573         VMSTATE_BOOL(cptse, struct e1000e_tx),
 574         VMSTATE_BOOL(skip_cp, struct e1000e_tx),
 575         VMSTATE_END_OF_LIST()
 576     }
 577 };
 578
 579 static const VMStateDescription e1000e_vmstate_intr_timer = {
 580     .name = "e1000e-intr-timer",
 581     .version_id = 1,
 582     .minimum_version_id = 1,
 583     .fields = (VMStateField[]) {
 584         VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
 585         VMSTATE_BOOL(running, E1000IntrDelayTimer),
 586         VMSTATE_END_OF_LIST()
 587     }
 588 };
 589
 590 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s)                     \
 591     VMSTATE_STRUCT(_f, _s, 0,                                       \
 592                    e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 593
 594 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)         \
 595     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
 596                          e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 597
 598 static const VMStateDescription e1000e_vmstate = {
 599     .name = "e1000e",
 600     .version_id = 1,
 601     .minimum_version_id = 1,
 602     .pre_save = e1000e_pre_save,
 603     .post_load = e1000e_post_load,
 604     .fields = (VMStateField[]) {
 605         VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
 606         VMSTATE_MSIX(parent_obj, E1000EState),
 607
 608         VMSTATE_UINT32(ioaddr, E1000EState),
 609         VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
 610         VMSTATE_UINT8(core.rx_desc_len, E1000EState),
 611         VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
 612                              E1000_PSRCTL_BUFFS_PER_DESC),
 613         VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
 614         VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
 615         VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
 616                                E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
 617         VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
 618         VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
 619
 620         VMSTATE_UINT32(core.delayed_causes, E1000EState),
 621
 622         VMSTATE_UINT16(subsys, E1000EState),
 623         VMSTATE_UINT16(subsys_ven, E1000EState),
 624
 625         VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
 626         VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
 627         VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
 628         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
 629         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
 630
 631         VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
 632         VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
 633
 634         VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
 635                                               E1000E_MSIX_VEC_NUM),
 636         VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
 637                            E1000E_MSIX_VEC_NUM),
 638
 639         VMSTATE_UINT32(core.itr_guest_value, E1000EState),
 640         VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
 641                              E1000E_MSIX_VEC_NUM),
 642
 643         VMSTATE_UINT16(core.vet, E1000EState),
 644
 645         VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
 646                              e1000e_vmstate_tx, struct e1000e_tx),
 647         VMSTATE_END_OF_LIST()
 648     }
 649 };
 650
 651 static PropertyInfo e1000e_prop_disable_vnet,
 652                     e1000e_prop_subsys_ven,
 653                     e1000e_prop_subsys;
 654
 655 static Property e1000e_properties[] = {
 656     DEFINE_NIC_PROPERTIES(E1000EState, conf),
 657     DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
 658                         e1000e_prop_disable_vnet, bool),
 659     DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
 660                         PCI_VENDOR_ID_INTEL,
 661                         e1000e_prop_subsys_ven, uint16_t),
 662     DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
 663                         e1000e_prop_subsys, uint16_t),
 664     DEFINE_PROP_END_OF_LIST(),
 665 };
 666
 667 static void e1000e_class_init(ObjectClass *class, void *data)
 668 {
 669     DeviceClass *dc = DEVICE_CLASS(class);
 670     PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
 671
 672     c->realize = e1000e_pci_realize;
 673     c->exit = e1000e_pci_uninit;
 674     c->vendor_id = PCI_VENDOR_ID_INTEL;
 675     c->device_id = E1000_DEV_ID_82574L;
 676     c->revision = 0;
 677     c->romfile = "efi-e1000e.rom";
 678     c->class_id = PCI_CLASS_NETWORK_ETHERNET;
 679
 680     dc->desc = "Intel 82574L GbE Controller";
 681     dc->reset = e1000e_qdev_reset;
 682     dc->vmsd = &e1000e_vmstate;
 683     dc->props = e1000e_properties;
 684
 685     e1000e_prop_disable_vnet = qdev_prop_uint8;
 686     e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
 687                                            "perform SW offloads emulation "
 688                                            "instead";
 689
 690     e1000e_prop_subsys_ven = qdev_prop_uint16;
 691     e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
 692
 693     e1000e_prop_subsys = qdev_prop_uint16;
 694     e1000e_prop_subsys.description = "PCI device Subsystem ID";
 695
 696     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 697 }
 698
 699 static void e1000e_instance_init(Object *obj)
 700 {
 701     E1000EState *s = E1000E(obj);
 702     device_add_bootindex_property(obj, &s->conf.bootindex,
 703                                   "bootindex", "/ethernet-phy@0",
 704                                   DEVICE(obj), NULL);
 705 }
 706
 707 static const TypeInfo e1000e_info = {
 708     .name = TYPE_E1000E,
 709     .parent = TYPE_PCI_DEVICE,
 710     .instance_size = sizeof(E1000EState),
 711     .class_init = e1000e_class_init,
 712     .instance_init = e1000e_instance_init,
 713     .interfaces = (InterfaceInfo[]) {
 714         { INTERFACE_PCIE_DEVICE },
 715         { }
 716     },
 717 };
 718
 719 static void e1000e_register_types(void)
 720 {
 721     type_register_static(&e1000e_info);
 722 }
 723
 724 type_init(e1000e_register_types)