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PPC: E500: Add FSL I2C controller and integrate RTC with it
[qemu/ar7.git] / hw / display / qxl.c
blobc8ce5781e037fa607966b9027fa3776f87a337db
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include <zlib.h>
24
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "qemu/timer.h"
28 #include "qemu/queue.h"
29 #include "qemu/atomic.h"
30 #include "sysemu/sysemu.h"
31 #include "migration/blocker.h"
32 #include "trace.h"
33
34 #include "qxl.h"
35
36 /*
37 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
38 * such can be changed by the guest, so to avoid a guest trigerrable
39 * abort we just qxl_set_guest_bug and set the return to NULL. Still
40 * it may happen as a result of emulator bug as well.
41 */
42 #undef SPICE_RING_PROD_ITEM
43 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
44 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
45 if (prod >= ARRAY_SIZE((r)->items)) { \
46 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
47 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
48 ret = NULL; \
49 } else { \
50 ret = &(r)->items[prod].el; \
51 } \
52 }
53
54 #undef SPICE_RING_CONS_ITEM
55 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
56 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
57 if (cons >= ARRAY_SIZE((r)->items)) { \
58 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
59 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
60 ret = NULL; \
61 } else { \
62 ret = &(r)->items[cons].el; \
63 } \
64 }
65
66 #undef ALIGN
67 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
68
69 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
70
71 #define QXL_MODE(_x, _y, _b, _o) \
72 { .x_res = _x, \
73 .y_res = _y, \
74 .bits = _b, \
75 .stride = (_x) * (_b) / 8, \
76 .x_mili = PIXEL_SIZE * (_x), \
77 .y_mili = PIXEL_SIZE * (_y), \
78 .orientation = _o, \
79 }
80
81 #define QXL_MODE_16_32(x_res, y_res, orientation) \
82 QXL_MODE(x_res, y_res, 16, orientation), \
83 QXL_MODE(x_res, y_res, 32, orientation)
84
85 #define QXL_MODE_EX(x_res, y_res) \
86 QXL_MODE_16_32(x_res, y_res, 0), \
87 QXL_MODE_16_32(x_res, y_res, 1)
88
89 static QXLMode qxl_modes[] = {
90 QXL_MODE_EX(640, 480),
91 QXL_MODE_EX(800, 480),
92 QXL_MODE_EX(800, 600),
93 QXL_MODE_EX(832, 624),
94 QXL_MODE_EX(960, 640),
95 QXL_MODE_EX(1024, 600),
96 QXL_MODE_EX(1024, 768),
97 QXL_MODE_EX(1152, 864),
98 QXL_MODE_EX(1152, 870),
99 QXL_MODE_EX(1280, 720),
100 QXL_MODE_EX(1280, 760),
101 QXL_MODE_EX(1280, 768),
102 QXL_MODE_EX(1280, 800),
103 QXL_MODE_EX(1280, 960),
104 QXL_MODE_EX(1280, 1024),
105 QXL_MODE_EX(1360, 768),
106 QXL_MODE_EX(1366, 768),
107 QXL_MODE_EX(1400, 1050),
108 QXL_MODE_EX(1440, 900),
109 QXL_MODE_EX(1600, 900),
110 QXL_MODE_EX(1600, 1200),
111 QXL_MODE_EX(1680, 1050),
112 QXL_MODE_EX(1920, 1080),
113 /* these modes need more than 8 MB video memory */
114 QXL_MODE_EX(1920, 1200),
115 QXL_MODE_EX(1920, 1440),
116 QXL_MODE_EX(2000, 2000),
117 QXL_MODE_EX(2048, 1536),
118 QXL_MODE_EX(2048, 2048),
119 QXL_MODE_EX(2560, 1440),
120 QXL_MODE_EX(2560, 1600),
121 /* these modes need more than 16 MB video memory */
122 QXL_MODE_EX(2560, 2048),
123 QXL_MODE_EX(2800, 2100),
124 QXL_MODE_EX(3200, 2400),
125 /* these modes need more than 32 MB video memory */
126 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
127 QXL_MODE_EX(4096, 2160), /* 4k */
128 /* these modes need more than 64 MB video memory */
129 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
130 /* these modes need more than 128 MB video memory */
131 QXL_MODE_EX(8192, 4320), /* 8k */
132 };
133
134 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
135 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
136 static void qxl_reset_memslots(PCIQXLDevice *d);
137 static void qxl_reset_surfaces(PCIQXLDevice *d);
138 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
139
140 static void qxl_hw_update(void *opaque);
141
142 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
143 {
144 trace_qxl_set_guest_bug(qxl->id);
145 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
146 qxl->guest_bug = 1;
147 if (qxl->guestdebug) {
148 va_list ap;
149 va_start(ap, msg);
150 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
151 vfprintf(stderr, msg, ap);
152 fprintf(stderr, "\n");
153 va_end(ap);
154 }
155 }
156
157 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
158 {
159 qxl->guest_bug = 0;
160 }
161
162 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
163 struct QXLRect *area, struct QXLRect *dirty_rects,
164 uint32_t num_dirty_rects,
165 uint32_t clear_dirty_region,
166 qxl_async_io async, struct QXLCookie *cookie)
167 {
168 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
169 area->top, area->bottom);
170 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
171 clear_dirty_region);
172 if (async == QXL_SYNC) {
173 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
174 dirty_rects, num_dirty_rects, clear_dirty_region);
175 } else {
176 assert(cookie != NULL);
177 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
178 clear_dirty_region, (uintptr_t)cookie);
179 }
180 }
181
182 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
183 uint32_t id)
184 {
185 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
186 qemu_mutex_lock(&qxl->track_lock);
187 qxl->guest_surfaces.cmds[id] = 0;
188 qxl->guest_surfaces.count--;
189 qemu_mutex_unlock(&qxl->track_lock);
190 }
191
192 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
193 qxl_async_io async)
194 {
195 QXLCookie *cookie;
196
197 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
198 if (async) {
199 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_DESTROY_SURFACE_ASYNC);
201 cookie->u.surface_id = id;
202 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
203 } else {
204 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
205 qxl_spice_destroy_surface_wait_complete(qxl, id);
206 }
207 }
208
209 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
210 {
211 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
212 qxl->num_free_res);
213 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
214 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
215 QXL_IO_FLUSH_SURFACES_ASYNC));
216 }
217
218 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
219 uint32_t count)
220 {
221 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
222 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
223 }
224
225 void qxl_spice_oom(PCIQXLDevice *qxl)
226 {
227 trace_qxl_spice_oom(qxl->id);
228 spice_qxl_oom(&qxl->ssd.qxl);
229 }
230
231 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
232 {
233 trace_qxl_spice_reset_memslots(qxl->id);
234 spice_qxl_reset_memslots(&qxl->ssd.qxl);
235 }
236
237 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
238 {
239 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
240 qemu_mutex_lock(&qxl->track_lock);
241 memset(qxl->guest_surfaces.cmds, 0,
242 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
243 qxl->guest_surfaces.count = 0;
244 qemu_mutex_unlock(&qxl->track_lock);
245 }
246
247 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
248 {
249 trace_qxl_spice_destroy_surfaces(qxl->id, async);
250 if (async) {
251 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
252 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
253 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
254 } else {
255 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
256 qxl_spice_destroy_surfaces_complete(qxl);
257 }
258 }
259
260 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
261 {
262 QXLMonitorsConfig *cfg;
263
264 trace_qxl_spice_monitors_config(qxl->id);
265 if (replay) {
266 /*
267 * don't use QXL_COOKIE_TYPE_IO:
268 * - we are not running yet (post_load), we will assert
269 * in send_events
270 * - this is not a guest io, but a reply, so async_io isn't set.
271 */
272 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
273 qxl->guest_monitors_config,
274 MEMSLOT_GROUP_GUEST,
275 (uintptr_t)qxl_cookie_new(
276 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
277 0));
278 } else {
279 /* >= release 0.12.6, < release 0.14.2 */
280 #if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
281 if (qxl->max_outputs) {
282 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
283 }
284 #endif
285 qxl->guest_monitors_config = qxl->ram->monitors_config;
286 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
287 qxl->ram->monitors_config,
288 MEMSLOT_GROUP_GUEST,
289 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
290 QXL_IO_MONITORS_CONFIG_ASYNC));
291 }
292
293 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
294 if (cfg != NULL && cfg->count == 1) {
295 qxl->guest_primary.resized = 1;
296 qxl->guest_head0_width = cfg->heads[0].width;
297 qxl->guest_head0_height = cfg->heads[0].height;
298 } else {
299 qxl->guest_head0_width = 0;
300 qxl->guest_head0_height = 0;
301 }
302 }
303
304 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
305 {
306 trace_qxl_spice_reset_image_cache(qxl->id);
307 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
308 }
309
310 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
311 {
312 trace_qxl_spice_reset_cursor(qxl->id);
313 spice_qxl_reset_cursor(&qxl->ssd.qxl);
314 qemu_mutex_lock(&qxl->track_lock);
315 qxl->guest_cursor = 0;
316 qemu_mutex_unlock(&qxl->track_lock);
317 if (qxl->ssd.cursor) {
318 cursor_put(qxl->ssd.cursor);
319 }
320 qxl->ssd.cursor = cursor_builtin_hidden();
321 }
322
323 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
324 {
325 /*
326 * zlib xors the seed with 0xffffffff, and xors the result
327 * again with 0xffffffff; Both are not done with linux's crc32,
328 * which we want to be compatible with, so undo that.
329 */
330 return crc32(0xffffffff, p, len) ^ 0xffffffff;
331 }
332
333 static ram_addr_t qxl_rom_size(void)
334 {
335 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
336 #define QXL_ROM_SZ 8192
337
338 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
339 return QXL_ROM_SZ;
340 }
341
342 static void init_qxl_rom(PCIQXLDevice *d)
343 {
344 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
345 QXLModes *modes = (QXLModes *)(rom + 1);
346 uint32_t ram_header_size;
347 uint32_t surface0_area_size;
348 uint32_t num_pages;
349 uint32_t fb;
350 int i, n;
351
352 memset(rom, 0, d->rom_size);
353
354 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
355 rom->id = cpu_to_le32(d->id);
356 rom->log_level = cpu_to_le32(d->guestdebug);
357 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
358
359 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
360 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
361 rom->slots_start = 1;
362 rom->slots_end = NUM_MEMSLOTS - 1;
363 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
364
365 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
366 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
367 if (fb > d->vgamem_size) {
368 continue;
369 }
370 modes->modes[n].id = cpu_to_le32(i);
371 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
372 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
373 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
374 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
375 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
376 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
377 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
378 n++;
379 }
380 modes->n_modes = cpu_to_le32(n);
381
382 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
383 surface0_area_size = ALIGN(d->vgamem_size, 4096);
384 num_pages = d->vga.vram_size;
385 num_pages -= ram_header_size;
386 num_pages -= surface0_area_size;
387 num_pages = num_pages / QXL_PAGE_SIZE;
388
389 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
390
391 rom->draw_area_offset = cpu_to_le32(0);
392 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
393 rom->pages_offset = cpu_to_le32(surface0_area_size);
394 rom->num_pages = cpu_to_le32(num_pages);
395 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
396
397 if (d->xres && d->yres) {
398 /* needs linux kernel 4.12+ to work */
399 rom->client_monitors_config.count = 1;
400 rom->client_monitors_config.heads[0].left = 0;
401 rom->client_monitors_config.heads[0].top = 0;
402 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
403 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
404 rom->client_monitors_config_crc = qxl_crc32(
405 (const uint8_t *)&rom->client_monitors_config,
406 sizeof(rom->client_monitors_config));
407 }
408
409 d->shadow_rom = *rom;
410 d->rom = rom;
411 d->modes = modes;
412 }
413
414 static void init_qxl_ram(PCIQXLDevice *d)
415 {
416 uint8_t *buf;
417 uint64_t *item;
418
419 buf = d->vga.vram_ptr;
420 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
421 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
422 d->ram->int_pending = cpu_to_le32(0);
423 d->ram->int_mask = cpu_to_le32(0);
424 d->ram->update_surface = 0;
425 d->ram->monitors_config = 0;
426 SPICE_RING_INIT(&d->ram->cmd_ring);
427 SPICE_RING_INIT(&d->ram->cursor_ring);
428 SPICE_RING_INIT(&d->ram->release_ring);
429 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
430 assert(item);
431 *item = 0;
432 qxl_ring_set_dirty(d);
433 }
434
435 /* can be called from spice server thread context */
436 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
437 {
438 memory_region_set_dirty(mr, addr, end - addr);
439 }
440
441 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
442 {
443 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
444 }
445
446 /* called from spice server thread context only */
447 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
448 {
449 void *base = qxl->vga.vram_ptr;
450 intptr_t offset;
451
452 offset = ptr - base;
453 assert(offset < qxl->vga.vram_size);
454 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
455 }
456
457 /* can be called from spice server thread context */
458 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
459 {
460 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
461 ram_addr_t end = qxl->vga.vram_size;
462 qxl_set_dirty(&qxl->vga.vram, addr, end);
463 }
464
465 /*
466 * keep track of some command state, for savevm/loadvm.
467 * called from spice server thread context only
468 */
469 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
470 {
471 switch (le32_to_cpu(ext->cmd.type)) {
472 case QXL_CMD_SURFACE:
473 {
474 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
475
476 if (!cmd) {
477 return 1;
478 }
479 uint32_t id = le32_to_cpu(cmd->surface_id);
480
481 if (id >= qxl->ssd.num_surfaces) {
482 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
483 qxl->ssd.num_surfaces);
484 return 1;
485 }
486 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
487 (cmd->u.surface_create.stride & 0x03) != 0) {
488 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
489 cmd->u.surface_create.stride);
490 return 1;
491 }
492 qemu_mutex_lock(&qxl->track_lock);
493 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
494 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
495 qxl->guest_surfaces.count++;
496 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
497 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
498 }
499 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
500 qxl->guest_surfaces.cmds[id] = 0;
501 qxl->guest_surfaces.count--;
502 }
503 qemu_mutex_unlock(&qxl->track_lock);
504 break;
505 }
506 case QXL_CMD_CURSOR:
507 {
508 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
509
510 if (!cmd) {
511 return 1;
512 }
513 if (cmd->type == QXL_CURSOR_SET) {
514 qemu_mutex_lock(&qxl->track_lock);
515 qxl->guest_cursor = ext->cmd.data;
516 qemu_mutex_unlock(&qxl->track_lock);
517 }
518 if (cmd->type == QXL_CURSOR_HIDE) {
519 qemu_mutex_lock(&qxl->track_lock);
520 qxl->guest_cursor = 0;
521 qemu_mutex_unlock(&qxl->track_lock);
522 }
523 break;
524 }
525 }
526 return 0;
527 }
528
529 /* spice display interface callbacks */
530
531 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
532 {
533 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
534
535 trace_qxl_interface_attach_worker(qxl->id);
536 }
537
538 static void interface_set_compression_level(QXLInstance *sin, int level)
539 {
540 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
541
542 trace_qxl_interface_set_compression_level(qxl->id, level);
543 qxl->shadow_rom.compression_level = cpu_to_le32(level);
544 qxl->rom->compression_level = cpu_to_le32(level);
545 qxl_rom_set_dirty(qxl);
546 }
547
548 #if SPICE_NEEDS_SET_MM_TIME
549 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
550 {
551 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
552
553 if (!qemu_spice_display_is_running(&qxl->ssd)) {
554 return;
555 }
556
557 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
558 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
559 qxl->rom->mm_clock = cpu_to_le32(mm_time);
560 qxl_rom_set_dirty(qxl);
561 }
562 #endif
563
564 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
565 {
566 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
567
568 trace_qxl_interface_get_init_info(qxl->id);
569 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
570 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
571 info->num_memslots = NUM_MEMSLOTS;
572 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
573 info->internal_groupslot_id = 0;
574 info->qxl_ram_size =
575 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
576 info->n_surfaces = qxl->ssd.num_surfaces;
577 }
578
579 static const char *qxl_mode_to_string(int mode)
580 {
581 switch (mode) {
582 case QXL_MODE_COMPAT:
583 return "compat";
584 case QXL_MODE_NATIVE:
585 return "native";
586 case QXL_MODE_UNDEFINED:
587 return "undefined";
588 case QXL_MODE_VGA:
589 return "vga";
590 }
591 return "INVALID";
592 }
593
594 static const char *io_port_to_string(uint32_t io_port)
595 {
596 if (io_port >= QXL_IO_RANGE_SIZE) {
597 return "out of range";
598 }
599 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
600 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
601 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
602 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
603 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
604 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
605 [QXL_IO_RESET] = "QXL_IO_RESET",
606 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
607 [QXL_IO_LOG] = "QXL_IO_LOG",
608 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
609 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
610 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
611 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
612 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
613 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
614 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
615 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
616 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
617 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
618 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
619 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
620 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
621 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
622 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
623 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
624 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
625 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
626 };
627 return io_port_to_string[io_port];
628 }
629
630 /* called from spice server thread context only */
631 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
632 {
633 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
634 SimpleSpiceUpdate *update;
635 QXLCommandRing *ring;
636 QXLCommand *cmd;
637 int notify, ret;
638
639 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
640
641 switch (qxl->mode) {
642 case QXL_MODE_VGA:
643 ret = false;
644 qemu_mutex_lock(&qxl->ssd.lock);
645 update = QTAILQ_FIRST(&qxl->ssd.updates);
646 if (update != NULL) {
647 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
648 *ext = update->ext;
649 ret = true;
650 }
651 qemu_mutex_unlock(&qxl->ssd.lock);
652 if (ret) {
653 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
654 qxl_log_command(qxl, "vga", ext);
655 }
656 return ret;
657 case QXL_MODE_COMPAT:
658 case QXL_MODE_NATIVE:
659 case QXL_MODE_UNDEFINED:
660 ring = &qxl->ram->cmd_ring;
661 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
662 return false;
663 }
664 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
665 if (!cmd) {
666 return false;
667 }
668 ext->cmd = *cmd;
669 ext->group_id = MEMSLOT_GROUP_GUEST;
670 ext->flags = qxl->cmdflags;
671 SPICE_RING_POP(ring, notify);
672 qxl_ring_set_dirty(qxl);
673 if (notify) {
674 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
675 }
676 qxl->guest_primary.commands++;
677 qxl_track_command(qxl, ext);
678 qxl_log_command(qxl, "cmd", ext);
679 {
680 /*
681 * Windows 8 drivers place qxl commands in the vram
682 * (instead of the ram) bar. We can't live migrate such a
683 * guest, so add a migration blocker in case we detect
684 * this, to avoid triggering the assert in pre_save().
685 *
686 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
687 */
688 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
689 if (msg != NULL && (
690 msg < (void *)qxl->vga.vram_ptr ||
691 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
692 if (!qxl->migration_blocker) {
693 Error *local_err = NULL;
694 error_setg(&qxl->migration_blocker,
695 "qxl: guest bug: command not in ram bar");
696 migrate_add_blocker(qxl->migration_blocker, &local_err);
697 if (local_err) {
698 error_report_err(local_err);
699 }
700 }
701 }
702 }
703 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
704 return true;
705 default:
706 return false;
707 }
708 }
709
710 /* called from spice server thread context only */
711 static int interface_req_cmd_notification(QXLInstance *sin)
712 {
713 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
714 int wait = 1;
715
716 trace_qxl_ring_command_req_notification(qxl->id);
717 switch (qxl->mode) {
718 case QXL_MODE_COMPAT:
719 case QXL_MODE_NATIVE:
720 case QXL_MODE_UNDEFINED:
721 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
722 qxl_ring_set_dirty(qxl);
723 break;
724 default:
725 /* nothing */
726 break;
727 }
728 return wait;
729 }
730
731 /* called from spice server thread context only */
732 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
733 {
734 QXLReleaseRing *ring = &d->ram->release_ring;
735 uint64_t *item;
736 int notify;
737
738 #define QXL_FREE_BUNCH_SIZE 32
739
740 if (ring->prod - ring->cons + 1 == ring->num_items) {
741 /* ring full -- can't push */
742 return;
743 }
744 if (!flush && d->oom_running) {
745 /* collect everything from oom handler before pushing */
746 return;
747 }
748 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
749 /* collect a bit more before pushing */
750 return;
751 }
752
753 SPICE_RING_PUSH(ring, notify);
754 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
755 d->guest_surfaces.count, d->num_free_res,
756 d->last_release, notify ? "yes" : "no");
757 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
758 ring->num_items, ring->prod, ring->cons);
759 if (notify) {
760 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
761 }
762 SPICE_RING_PROD_ITEM(d, ring, item);
763 if (!item) {
764 return;
765 }
766 *item = 0;
767 d->num_free_res = 0;
768 d->last_release = NULL;
769 qxl_ring_set_dirty(d);
770 }
771
772 /* called from spice server thread context only */
773 static void interface_release_resource(QXLInstance *sin,
774 QXLReleaseInfoExt ext)
775 {
776 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
777 QXLReleaseRing *ring;
778 uint64_t *item, id;
779
780 if (ext.group_id == MEMSLOT_GROUP_HOST) {
781 /* host group -> vga mode update request */
782 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
783 SimpleSpiceUpdate *update;
784 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
785 update = container_of(cmdext, SimpleSpiceUpdate, ext);
786 qemu_spice_destroy_update(&qxl->ssd, update);
787 return;
788 }
789
790 /*
791 * ext->info points into guest-visible memory
792 * pci bar 0, $command.release_info
793 */
794 ring = &qxl->ram->release_ring;
795 SPICE_RING_PROD_ITEM(qxl, ring, item);
796 if (!item) {
797 return;
798 }
799 if (*item == 0) {
800 /* stick head into the ring */
801 id = ext.info->id;
802 ext.info->next = 0;
803 qxl_ram_set_dirty(qxl, &ext.info->next);
804 *item = id;
805 qxl_ring_set_dirty(qxl);
806 } else {
807 /* append item to the list */
808 qxl->last_release->next = ext.info->id;
809 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
810 ext.info->next = 0;
811 qxl_ram_set_dirty(qxl, &ext.info->next);
812 }
813 qxl->last_release = ext.info;
814 qxl->num_free_res++;
815 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
816 qxl_push_free_res(qxl, 0);
817 }
818
819 /* called from spice server thread context only */
820 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
821 {
822 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
823 QXLCursorRing *ring;
824 QXLCommand *cmd;
825 int notify;
826
827 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
828
829 switch (qxl->mode) {
830 case QXL_MODE_COMPAT:
831 case QXL_MODE_NATIVE:
832 case QXL_MODE_UNDEFINED:
833 ring = &qxl->ram->cursor_ring;
834 if (SPICE_RING_IS_EMPTY(ring)) {
835 return false;
836 }
837 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
838 if (!cmd) {
839 return false;
840 }
841 ext->cmd = *cmd;
842 ext->group_id = MEMSLOT_GROUP_GUEST;
843 ext->flags = qxl->cmdflags;
844 SPICE_RING_POP(ring, notify);
845 qxl_ring_set_dirty(qxl);
846 if (notify) {
847 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
848 }
849 qxl->guest_primary.commands++;
850 qxl_track_command(qxl, ext);
851 qxl_log_command(qxl, "csr", ext);
852 if (qxl->have_vga) {
853 qxl_render_cursor(qxl, ext);
854 }
855 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
856 return true;
857 default:
858 return false;
859 }
860 }
861
862 /* called from spice server thread context only */
863 static int interface_req_cursor_notification(QXLInstance *sin)
864 {
865 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
866 int wait = 1;
867
868 trace_qxl_ring_cursor_req_notification(qxl->id);
869 switch (qxl->mode) {
870 case QXL_MODE_COMPAT:
871 case QXL_MODE_NATIVE:
872 case QXL_MODE_UNDEFINED:
873 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
874 qxl_ring_set_dirty(qxl);
875 break;
876 default:
877 /* nothing */
878 break;
879 }
880 return wait;
881 }
882
883 /* called from spice server thread context */
884 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
885 {
886 /*
887 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
888 * use by xf86-video-qxl and is defined out in the qxl windows driver.
889 * Probably was at some earlier version that is prior to git start (2009),
890 * and is still guest trigerrable.
891 */
892 fprintf(stderr, "%s: deprecated\n", __func__);
893 }
894
895 /* called from spice server thread context only */
896 static int interface_flush_resources(QXLInstance *sin)
897 {
898 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
899 int ret;
900
901 ret = qxl->num_free_res;
902 if (ret) {
903 qxl_push_free_res(qxl, 1);
904 }
905 return ret;
906 }
907
908 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
909
910 /* called from spice server thread context only */
911 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
912 {
913 uint32_t current_async;
914
915 qemu_mutex_lock(&qxl->async_lock);
916 current_async = qxl->current_async;
917 qxl->current_async = QXL_UNDEFINED_IO;
918 qemu_mutex_unlock(&qxl->async_lock);
919
920 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
921 if (!cookie) {
922 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
923 return;
924 }
925 if (cookie && current_async != cookie->io) {
926 fprintf(stderr,
927 "qxl: %s: error: current_async = %d != %"
928 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
929 }
930 switch (current_async) {
931 case QXL_IO_MEMSLOT_ADD_ASYNC:
932 case QXL_IO_DESTROY_PRIMARY_ASYNC:
933 case QXL_IO_UPDATE_AREA_ASYNC:
934 case QXL_IO_FLUSH_SURFACES_ASYNC:
935 case QXL_IO_MONITORS_CONFIG_ASYNC:
936 break;
937 case QXL_IO_CREATE_PRIMARY_ASYNC:
938 qxl_create_guest_primary_complete(qxl);
939 break;
940 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
941 qxl_spice_destroy_surfaces_complete(qxl);
942 break;
943 case QXL_IO_DESTROY_SURFACE_ASYNC:
944 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
945 break;
946 default:
947 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
948 current_async);
949 }
950 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
951 }
952
953 /* called from spice server thread context only */
954 static void interface_update_area_complete(QXLInstance *sin,
955 uint32_t surface_id,
956 QXLRect *dirty, uint32_t num_updated_rects)
957 {
958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
959 int i;
960 int qxl_i;
961
962 qemu_mutex_lock(&qxl->ssd.lock);
963 if (surface_id != 0 || !num_updated_rects ||
964 !qxl->render_update_cookie_num) {
965 qemu_mutex_unlock(&qxl->ssd.lock);
966 return;
967 }
968 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
969 dirty->right, dirty->top, dirty->bottom);
970 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
971 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
972 /*
973 * overflow - treat this as a full update. Not expected to be common.
974 */
975 trace_qxl_interface_update_area_complete_overflow(qxl->id,
976 QXL_NUM_DIRTY_RECTS);
977 qxl->guest_primary.resized = 1;
978 }
979 if (qxl->guest_primary.resized) {
980 /*
981 * Don't bother copying or scheduling the bh since we will flip
982 * the whole area anyway on completion of the update_area async call
983 */
984 qemu_mutex_unlock(&qxl->ssd.lock);
985 return;
986 }
987 qxl_i = qxl->num_dirty_rects;
988 for (i = 0; i < num_updated_rects; i++) {
989 qxl->dirty[qxl_i++] = dirty[i];
990 }
991 qxl->num_dirty_rects += num_updated_rects;
992 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
993 qxl->num_dirty_rects);
994 qemu_bh_schedule(qxl->update_area_bh);
995 qemu_mutex_unlock(&qxl->ssd.lock);
996 }
997
998 /* called from spice server thread context only */
999 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
1000 {
1001 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1002 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
1003
1004 switch (cookie->type) {
1005 case QXL_COOKIE_TYPE_IO:
1006 interface_async_complete_io(qxl, cookie);
1007 g_free(cookie);
1008 break;
1009 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1010 qxl_render_update_area_done(qxl, cookie);
1011 break;
1012 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1013 break;
1014 default:
1015 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1016 __func__, cookie->type);
1017 g_free(cookie);
1018 }
1019 }
1020
1021 /* called from spice server thread context only */
1022 static void interface_set_client_capabilities(QXLInstance *sin,
1023 uint8_t client_present,
1024 uint8_t caps[58])
1025 {
1026 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1027
1028 if (qxl->revision < 4) {
1029 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1030 qxl->revision);
1031 return;
1032 }
1033
1034 if (runstate_check(RUN_STATE_INMIGRATE) ||
1035 runstate_check(RUN_STATE_POSTMIGRATE)) {
1036 return;
1037 }
1038
1039 qxl->shadow_rom.client_present = client_present;
1040 memcpy(qxl->shadow_rom.client_capabilities, caps,
1041 sizeof(qxl->shadow_rom.client_capabilities));
1042 qxl->rom->client_present = client_present;
1043 memcpy(qxl->rom->client_capabilities, caps,
1044 sizeof(qxl->rom->client_capabilities));
1045 qxl_rom_set_dirty(qxl);
1046
1047 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1048 }
1049
1050 static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1051 VDAgentMonitorsConfig *monitors_config,
1052 unsigned int max_outputs)
1053 {
1054 int i;
1055 unsigned int monitors_count;
1056
1057 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1058
1059 if (rom->client_monitors_config.count != monitors_count) {
1060 return true;
1061 }
1062
1063 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1064 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1065 QXLURect *rect = &rom->client_monitors_config.heads[i];
1066 /* monitor->depth ignored */
1067 if ((rect->left != monitor->x) ||
1068 (rect->top != monitor->y) ||
1069 (rect->right != monitor->x + monitor->width) ||
1070 (rect->bottom != monitor->y + monitor->height)) {
1071 return true;
1072 }
1073 }
1074
1075 return false;
1076 }
1077
1078 /* called from main context only */
1079 static int interface_client_monitors_config(QXLInstance *sin,
1080 VDAgentMonitorsConfig *monitors_config)
1081 {
1082 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1083 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1084 int i;
1085 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1086 bool config_changed = false;
1087
1088 if (qxl->revision < 4) {
1089 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1090 qxl->revision);
1091 return 0;
1092 }
1093 /*
1094 * Older windows drivers set int_mask to 0 when their ISR is called,
1095 * then later set it to ~0. So it doesn't relate to the actual interrupts
1096 * handled. However, they are old, so clearly they don't support this
1097 * interrupt
1098 */
1099 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1100 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1101 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1102 qxl->ram->int_mask,
1103 monitors_config);
1104 return 0;
1105 }
1106 if (!monitors_config) {
1107 return 1;
1108 }
1109
1110 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1111 /* limit number of outputs based on setting limit */
1112 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1113 max_outputs = qxl->max_outputs;
1114 }
1115 #endif
1116
1117 config_changed = qxl_rom_monitors_config_changed(rom,
1118 monitors_config,
1119 max_outputs);
1120
1121 memset(&rom->client_monitors_config, 0,
1122 sizeof(rom->client_monitors_config));
1123 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1124 /* monitors_config->flags ignored */
1125 if (rom->client_monitors_config.count >= max_outputs) {
1126 trace_qxl_client_monitors_config_capped(qxl->id,
1127 monitors_config->num_of_monitors,
1128 max_outputs);
1129 rom->client_monitors_config.count = max_outputs;
1130 }
1131 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1132 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1133 QXLURect *rect = &rom->client_monitors_config.heads[i];
1134 /* monitor->depth ignored */
1135 rect->left = monitor->x;
1136 rect->top = monitor->y;
1137 rect->right = monitor->x + monitor->width;
1138 rect->bottom = monitor->y + monitor->height;
1139 }
1140 rom->client_monitors_config_crc = qxl_crc32(
1141 (const uint8_t *)&rom->client_monitors_config,
1142 sizeof(rom->client_monitors_config));
1143 trace_qxl_client_monitors_config_crc(qxl->id,
1144 sizeof(rom->client_monitors_config),
1145 rom->client_monitors_config_crc);
1146
1147 trace_qxl_interrupt_client_monitors_config(qxl->id,
1148 rom->client_monitors_config.count,
1149 rom->client_monitors_config.heads);
1150 if (config_changed) {
1151 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1152 }
1153 return 1;
1154 }
1155
1156 static const QXLInterface qxl_interface = {
1157 .base.type = SPICE_INTERFACE_QXL,
1158 .base.description = "qxl gpu",
1159 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1160 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1161
1162 .attache_worker = interface_attach_worker,
1163 .set_compression_level = interface_set_compression_level,
1164 #if SPICE_NEEDS_SET_MM_TIME
1165 .set_mm_time = interface_set_mm_time,
1166 #endif
1167 .get_init_info = interface_get_init_info,
1168
1169 /* the callbacks below are called from spice server thread context */
1170 .get_command = interface_get_command,
1171 .req_cmd_notification = interface_req_cmd_notification,
1172 .release_resource = interface_release_resource,
1173 .get_cursor_command = interface_get_cursor_command,
1174 .req_cursor_notification = interface_req_cursor_notification,
1175 .notify_update = interface_notify_update,
1176 .flush_resources = interface_flush_resources,
1177 .async_complete = interface_async_complete,
1178 .update_area_complete = interface_update_area_complete,
1179 .set_client_capabilities = interface_set_client_capabilities,
1180 .client_monitors_config = interface_client_monitors_config,
1181 };
1182
1183 static const GraphicHwOps qxl_ops = {
1184 .gfx_update = qxl_hw_update,
1185 };
1186
1187 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1188 {
1189 if (d->mode == QXL_MODE_VGA) {
1190 return;
1191 }
1192 trace_qxl_enter_vga_mode(d->id);
1193 spice_qxl_driver_unload(&d->ssd.qxl);
1194 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1195 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1196 qemu_spice_create_host_primary(&d->ssd);
1197 d->mode = QXL_MODE_VGA;
1198 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1199 vga_dirty_log_start(&d->vga);
1200 graphic_hw_update(d->vga.con);
1201 }
1202
1203 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1204 {
1205 if (d->mode != QXL_MODE_VGA) {
1206 return;
1207 }
1208 trace_qxl_exit_vga_mode(d->id);
1209 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1210 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1211 vga_dirty_log_stop(&d->vga);
1212 qxl_destroy_primary(d, QXL_SYNC);
1213 }
1214
1215 static void qxl_update_irq(PCIQXLDevice *d)
1216 {
1217 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1218 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1219 int level = !!(pending & mask);
1220 pci_set_irq(&d->pci, level);
1221 qxl_ring_set_dirty(d);
1222 }
1223
1224 static void qxl_check_state(PCIQXLDevice *d)
1225 {
1226 QXLRam *ram = d->ram;
1227 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1228
1229 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1230 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1231 }
1232
1233 static void qxl_reset_state(PCIQXLDevice *d)
1234 {
1235 QXLRom *rom = d->rom;
1236
1237 qxl_check_state(d);
1238 d->shadow_rom.update_id = cpu_to_le32(0);
1239 *rom = d->shadow_rom;
1240 qxl_rom_set_dirty(d);
1241 init_qxl_ram(d);
1242 d->num_free_res = 0;
1243 d->last_release = NULL;
1244 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1245 qxl_update_irq(d);
1246 }
1247
1248 static void qxl_soft_reset(PCIQXLDevice *d)
1249 {
1250 trace_qxl_soft_reset(d->id);
1251 qxl_check_state(d);
1252 qxl_clear_guest_bug(d);
1253 qemu_mutex_lock(&d->async_lock);
1254 d->current_async = QXL_UNDEFINED_IO;
1255 qemu_mutex_unlock(&d->async_lock);
1256
1257 if (d->have_vga) {
1258 qxl_enter_vga_mode(d);
1259 } else {
1260 d->mode = QXL_MODE_UNDEFINED;
1261 }
1262 }
1263
1264 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1265 {
1266 bool startstop = qemu_spice_display_is_running(&d->ssd);
1267
1268 trace_qxl_hard_reset(d->id, loadvm);
1269
1270 if (startstop) {
1271 qemu_spice_display_stop();
1272 }
1273
1274 qxl_spice_reset_cursor(d);
1275 qxl_spice_reset_image_cache(d);
1276 qxl_reset_surfaces(d);
1277 qxl_reset_memslots(d);
1278
1279 /* pre loadvm reset must not touch QXLRam. This lives in
1280 * device memory, is migrated together with RAM and thus
1281 * already loaded at this point */
1282 if (!loadvm) {
1283 qxl_reset_state(d);
1284 }
1285 qemu_spice_create_host_memslot(&d->ssd);
1286 qxl_soft_reset(d);
1287
1288 if (d->migration_blocker) {
1289 migrate_del_blocker(d->migration_blocker);
1290 error_free(d->migration_blocker);
1291 d->migration_blocker = NULL;
1292 }
1293
1294 if (startstop) {
1295 qemu_spice_display_start();
1296 }
1297 }
1298
1299 static void qxl_reset_handler(DeviceState *dev)
1300 {
1301 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1302
1303 qxl_hard_reset(d, 0);
1304 }
1305
1306 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1307 {
1308 VGACommonState *vga = opaque;
1309 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1310
1311 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1312 if (qxl->mode != QXL_MODE_VGA) {
1313 qxl_destroy_primary(qxl, QXL_SYNC);
1314 qxl_soft_reset(qxl);
1315 }
1316 vga_ioport_write(opaque, addr, val);
1317 }
1318
1319 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1320 { 0x04, 2, 1, .read = vga_ioport_read,
1321 .write = qxl_vga_ioport_write }, /* 3b4 */
1322 { 0x0a, 1, 1, .read = vga_ioport_read,
1323 .write = qxl_vga_ioport_write }, /* 3ba */
1324 { 0x10, 16, 1, .read = vga_ioport_read,
1325 .write = qxl_vga_ioport_write }, /* 3c0 */
1326 { 0x24, 2, 1, .read = vga_ioport_read,
1327 .write = qxl_vga_ioport_write }, /* 3d4 */
1328 { 0x2a, 1, 1, .read = vga_ioport_read,
1329 .write = qxl_vga_ioport_write }, /* 3da */
1330 PORTIO_END_OF_LIST(),
1331 };
1332
1333 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1334 qxl_async_io async)
1335 {
1336 static const int regions[] = {
1337 QXL_RAM_RANGE_INDEX,
1338 QXL_VRAM_RANGE_INDEX,
1339 QXL_VRAM64_RANGE_INDEX,
1340 };
1341 uint64_t guest_start;
1342 uint64_t guest_end;
1343 int pci_region;
1344 pcibus_t pci_start;
1345 pcibus_t pci_end;
1346 MemoryRegion *mr;
1347 intptr_t virt_start;
1348 QXLDevMemSlot memslot;
1349 int i;
1350
1351 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1352 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1353
1354 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1355
1356 if (slot_id >= NUM_MEMSLOTS) {
1357 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1358 slot_id, NUM_MEMSLOTS);
1359 return 1;
1360 }
1361 if (guest_start > guest_end) {
1362 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1363 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1364 return 1;
1365 }
1366
1367 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1368 pci_region = regions[i];
1369 pci_start = d->pci.io_regions[pci_region].addr;
1370 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1371 /* mapped? */
1372 if (pci_start == -1) {
1373 continue;
1374 }
1375 /* start address in range ? */
1376 if (guest_start < pci_start || guest_start > pci_end) {
1377 continue;
1378 }
1379 /* end address in range ? */
1380 if (guest_end > pci_end) {
1381 continue;
1382 }
1383 /* passed */
1384 break;
1385 }
1386 if (i == ARRAY_SIZE(regions)) {
1387 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1388 return 1;
1389 }
1390
1391 switch (pci_region) {
1392 case QXL_RAM_RANGE_INDEX:
1393 mr = &d->vga.vram;
1394 break;
1395 case QXL_VRAM_RANGE_INDEX:
1396 case 4 /* vram 64bit */:
1397 mr = &d->vram_bar;
1398 break;
1399 default:
1400 /* should not happen */
1401 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1402 return 1;
1403 }
1404
1405 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1406 memslot.slot_id = slot_id;
1407 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1408 memslot.virt_start = virt_start + (guest_start - pci_start);
1409 memslot.virt_end = virt_start + (guest_end - pci_start);
1410 memslot.addr_delta = memslot.virt_start - delta;
1411 memslot.generation = d->rom->slot_generation = 0;
1412 qxl_rom_set_dirty(d);
1413
1414 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1415 d->guest_slots[slot_id].mr = mr;
1416 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1417 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1418 d->guest_slots[slot_id].delta = delta;
1419 d->guest_slots[slot_id].active = 1;
1420 return 0;
1421 }
1422
1423 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1424 {
1425 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1426 d->guest_slots[slot_id].active = 0;
1427 }
1428
1429 static void qxl_reset_memslots(PCIQXLDevice *d)
1430 {
1431 qxl_spice_reset_memslots(d);
1432 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1433 }
1434
1435 static void qxl_reset_surfaces(PCIQXLDevice *d)
1436 {
1437 trace_qxl_reset_surfaces(d->id);
1438 d->mode = QXL_MODE_UNDEFINED;
1439 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1440 }
1441
1442 /* can be also called from spice server thread context */
1443 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1444 uint32_t *s, uint64_t *o)
1445 {
1446 uint64_t phys = le64_to_cpu(pqxl);
1447 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1448 uint64_t offset = phys & 0xffffffffffff;
1449
1450 if (slot >= NUM_MEMSLOTS) {
1451 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1452 NUM_MEMSLOTS);
1453 return false;
1454 }
1455 if (!qxl->guest_slots[slot].active) {
1456 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1457 return false;
1458 }
1459 if (offset < qxl->guest_slots[slot].delta) {
1460 qxl_set_guest_bug(qxl,
1461 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1462 slot, offset, qxl->guest_slots[slot].delta);
1463 return false;
1464 }
1465 offset -= qxl->guest_slots[slot].delta;
1466 if (offset > qxl->guest_slots[slot].size) {
1467 qxl_set_guest_bug(qxl,
1468 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1469 slot, offset, qxl->guest_slots[slot].size);
1470 return false;
1471 }
1472
1473 *s = slot;
1474 *o = offset;
1475 return true;
1476 }
1477
1478 /* can be also called from spice server thread context */
1479 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1480 {
1481 uint64_t offset;
1482 uint32_t slot;
1483 void *ptr;
1484
1485 switch (group_id) {
1486 case MEMSLOT_GROUP_HOST:
1487 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1488 return (void *)(intptr_t)offset;
1489 case MEMSLOT_GROUP_GUEST:
1490 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
1491 return NULL;
1492 }
1493 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1494 ptr += qxl->guest_slots[slot].offset;
1495 ptr += offset;
1496 return ptr;
1497 }
1498 return NULL;
1499 }
1500
1501 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1502 {
1503 /* for local rendering */
1504 qxl_render_resize(qxl);
1505 }
1506
1507 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1508 qxl_async_io async)
1509 {
1510 QXLDevSurfaceCreate surface;
1511 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1512 uint32_t requested_height = le32_to_cpu(sc->height);
1513 int requested_stride = le32_to_cpu(sc->stride);
1514
1515 if (requested_stride == INT32_MIN ||
1516 abs(requested_stride) * (uint64_t)requested_height
1517 > qxl->vgamem_size) {
1518 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1519 " stride %d x height %" PRIu32 " > %" PRIu32,
1520 __func__, requested_stride, requested_height,
1521 qxl->vgamem_size);
1522 return;
1523 }
1524
1525 if (qxl->mode == QXL_MODE_NATIVE) {
1526 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1527 __func__);
1528 }
1529 qxl_exit_vga_mode(qxl);
1530
1531 surface.format = le32_to_cpu(sc->format);
1532 surface.height = le32_to_cpu(sc->height);
1533 surface.mem = le64_to_cpu(sc->mem);
1534 surface.position = le32_to_cpu(sc->position);
1535 surface.stride = le32_to_cpu(sc->stride);
1536 surface.width = le32_to_cpu(sc->width);
1537 surface.type = le32_to_cpu(sc->type);
1538 surface.flags = le32_to_cpu(sc->flags);
1539 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1540 sc->format, sc->position);
1541 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1542 sc->flags);
1543
1544 if ((surface.stride & 0x3) != 0) {
1545 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1546 surface.stride);
1547 return;
1548 }
1549
1550 surface.mouse_mode = true;
1551 surface.group_id = MEMSLOT_GROUP_GUEST;
1552 if (loadvm) {
1553 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1554 }
1555
1556 qxl->mode = QXL_MODE_NATIVE;
1557 qxl->cmdflags = 0;
1558 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1559
1560 if (async == QXL_SYNC) {
1561 qxl_create_guest_primary_complete(qxl);
1562 }
1563 }
1564
1565 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1566 * done (in QXL_SYNC case), 0 otherwise. */
1567 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1568 {
1569 if (d->mode == QXL_MODE_UNDEFINED) {
1570 return 0;
1571 }
1572 trace_qxl_destroy_primary(d->id);
1573 d->mode = QXL_MODE_UNDEFINED;
1574 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1575 qxl_spice_reset_cursor(d);
1576 return 1;
1577 }
1578
1579 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1580 {
1581 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1582 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1583 QXLMode *mode = d->modes->modes + modenr;
1584 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1585 QXLMemSlot slot = {
1586 .mem_start = start,
1587 .mem_end = end
1588 };
1589
1590 if (modenr >= d->modes->n_modes) {
1591 qxl_set_guest_bug(d, "mode number out of range");
1592 return;
1593 }
1594
1595 QXLSurfaceCreate surface = {
1596 .width = mode->x_res,
1597 .height = mode->y_res,
1598 .stride = -mode->x_res * 4,
1599 .format = SPICE_SURFACE_FMT_32_xRGB,
1600 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1601 .mouse_mode = true,
1602 .mem = devmem + d->shadow_rom.draw_area_offset,
1603 };
1604
1605 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1606 devmem);
1607 if (!loadvm) {
1608 qxl_hard_reset(d, 0);
1609 }
1610
1611 d->guest_slots[0].slot = slot;
1612 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1613
1614 d->guest_primary.surface = surface;
1615 qxl_create_guest_primary(d, 0, QXL_SYNC);
1616
1617 d->mode = QXL_MODE_COMPAT;
1618 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1619 if (mode->bits == 16) {
1620 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1621 }
1622 d->shadow_rom.mode = cpu_to_le32(modenr);
1623 d->rom->mode = cpu_to_le32(modenr);
1624 qxl_rom_set_dirty(d);
1625 }
1626
1627 static void ioport_write(void *opaque, hwaddr addr,
1628 uint64_t val, unsigned size)
1629 {
1630 PCIQXLDevice *d = opaque;
1631 uint32_t io_port = addr;
1632 qxl_async_io async = QXL_SYNC;
1633 uint32_t orig_io_port = io_port;
1634
1635 if (d->guest_bug && io_port != QXL_IO_RESET) {
1636 return;
1637 }
1638
1639 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1640 io_port > QXL_IO_FLUSH_RELEASE) {
1641 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1642 io_port, d->revision);
1643 return;
1644 }
1645
1646 switch (io_port) {
1647 case QXL_IO_RESET:
1648 case QXL_IO_SET_MODE:
1649 case QXL_IO_MEMSLOT_ADD:
1650 case QXL_IO_MEMSLOT_DEL:
1651 case QXL_IO_CREATE_PRIMARY:
1652 case QXL_IO_UPDATE_IRQ:
1653 case QXL_IO_LOG:
1654 case QXL_IO_MEMSLOT_ADD_ASYNC:
1655 case QXL_IO_CREATE_PRIMARY_ASYNC:
1656 break;
1657 default:
1658 if (d->mode != QXL_MODE_VGA) {
1659 break;
1660 }
1661 trace_qxl_io_unexpected_vga_mode(d->id,
1662 addr, val, io_port_to_string(io_port));
1663 /* be nice to buggy guest drivers */
1664 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1665 io_port < QXL_IO_RANGE_SIZE) {
1666 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1667 }
1668 return;
1669 }
1670
1671 /* we change the io_port to avoid ifdeffery in the main switch */
1672 orig_io_port = io_port;
1673 switch (io_port) {
1674 case QXL_IO_UPDATE_AREA_ASYNC:
1675 io_port = QXL_IO_UPDATE_AREA;
1676 goto async_common;
1677 case QXL_IO_MEMSLOT_ADD_ASYNC:
1678 io_port = QXL_IO_MEMSLOT_ADD;
1679 goto async_common;
1680 case QXL_IO_CREATE_PRIMARY_ASYNC:
1681 io_port = QXL_IO_CREATE_PRIMARY;
1682 goto async_common;
1683 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1684 io_port = QXL_IO_DESTROY_PRIMARY;
1685 goto async_common;
1686 case QXL_IO_DESTROY_SURFACE_ASYNC:
1687 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1688 goto async_common;
1689 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1690 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1691 goto async_common;
1692 case QXL_IO_FLUSH_SURFACES_ASYNC:
1693 case QXL_IO_MONITORS_CONFIG_ASYNC:
1694 async_common:
1695 async = QXL_ASYNC;
1696 qemu_mutex_lock(&d->async_lock);
1697 if (d->current_async != QXL_UNDEFINED_IO) {
1698 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1699 io_port, d->current_async);
1700 qemu_mutex_unlock(&d->async_lock);
1701 return;
1702 }
1703 d->current_async = orig_io_port;
1704 qemu_mutex_unlock(&d->async_lock);
1705 break;
1706 default:
1707 break;
1708 }
1709 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1710 addr, io_port_to_string(addr),
1711 val, size, async);
1712
1713 switch (io_port) {
1714 case QXL_IO_UPDATE_AREA:
1715 {
1716 QXLCookie *cookie = NULL;
1717 QXLRect update = d->ram->update_area;
1718
1719 if (d->ram->update_surface > d->ssd.num_surfaces) {
1720 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1721 d->ram->update_surface);
1722 break;
1723 }
1724 if (update.left >= update.right || update.top >= update.bottom ||
1725 update.left < 0 || update.top < 0) {
1726 qxl_set_guest_bug(d,
1727 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1728 update.left, update.top, update.right, update.bottom);
1729 if (update.left == update.right || update.top == update.bottom) {
1730 /* old drivers may provide empty area, keep going */
1731 qxl_clear_guest_bug(d);
1732 goto cancel_async;
1733 }
1734 break;
1735 }
1736 if (async == QXL_ASYNC) {
1737 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1738 QXL_IO_UPDATE_AREA_ASYNC);
1739 cookie->u.area = update;
1740 }
1741 qxl_spice_update_area(d, d->ram->update_surface,
1742 cookie ? &cookie->u.area : &update,
1743 NULL, 0, 0, async, cookie);
1744 break;
1745 }
1746 case QXL_IO_NOTIFY_CMD:
1747 qemu_spice_wakeup(&d->ssd);
1748 break;
1749 case QXL_IO_NOTIFY_CURSOR:
1750 qemu_spice_wakeup(&d->ssd);
1751 break;
1752 case QXL_IO_UPDATE_IRQ:
1753 qxl_update_irq(d);
1754 break;
1755 case QXL_IO_NOTIFY_OOM:
1756 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1757 break;
1758 }
1759 d->oom_running = 1;
1760 qxl_spice_oom(d);
1761 d->oom_running = 0;
1762 break;
1763 case QXL_IO_SET_MODE:
1764 qxl_set_mode(d, val, 0);
1765 break;
1766 case QXL_IO_LOG:
1767 if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) {
1768 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1769 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1770 sizeof(d->ram->log_buf));
1771 trace_qxl_io_log(d->id, log_buf);
1772 if (d->guestdebug) {
1773 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1774 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1775 }
1776 g_free(log_buf);
1777 }
1778 break;
1779 case QXL_IO_RESET:
1780 qxl_hard_reset(d, 0);
1781 break;
1782 case QXL_IO_MEMSLOT_ADD:
1783 if (val >= NUM_MEMSLOTS) {
1784 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1785 break;
1786 }
1787 if (d->guest_slots[val].active) {
1788 qxl_set_guest_bug(d,
1789 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1790 break;
1791 }
1792 d->guest_slots[val].slot = d->ram->mem_slot;
1793 qxl_add_memslot(d, val, 0, async);
1794 break;
1795 case QXL_IO_MEMSLOT_DEL:
1796 if (val >= NUM_MEMSLOTS) {
1797 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1798 break;
1799 }
1800 qxl_del_memslot(d, val);
1801 break;
1802 case QXL_IO_CREATE_PRIMARY:
1803 if (val != 0) {
1804 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1805 async);
1806 goto cancel_async;
1807 }
1808 d->guest_primary.surface = d->ram->create_surface;
1809 qxl_create_guest_primary(d, 0, async);
1810 break;
1811 case QXL_IO_DESTROY_PRIMARY:
1812 if (val != 0) {
1813 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1814 async);
1815 goto cancel_async;
1816 }
1817 if (!qxl_destroy_primary(d, async)) {
1818 trace_qxl_io_destroy_primary_ignored(d->id,
1819 qxl_mode_to_string(d->mode));
1820 goto cancel_async;
1821 }
1822 break;
1823 case QXL_IO_DESTROY_SURFACE_WAIT:
1824 if (val >= d->ssd.num_surfaces) {
1825 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1826 "%" PRIu64 " >= NUM_SURFACES", async, val);
1827 goto cancel_async;
1828 }
1829 qxl_spice_destroy_surface_wait(d, val, async);
1830 break;
1831 case QXL_IO_FLUSH_RELEASE: {
1832 QXLReleaseRing *ring = &d->ram->release_ring;
1833 if (ring->prod - ring->cons + 1 == ring->num_items) {
1834 fprintf(stderr,
1835 "ERROR: no flush, full release ring [p%d,%dc]\n",
1836 ring->prod, ring->cons);
1837 }
1838 qxl_push_free_res(d, 1 /* flush */);
1839 break;
1840 }
1841 case QXL_IO_FLUSH_SURFACES_ASYNC:
1842 qxl_spice_flush_surfaces_async(d);
1843 break;
1844 case QXL_IO_DESTROY_ALL_SURFACES:
1845 d->mode = QXL_MODE_UNDEFINED;
1846 qxl_spice_destroy_surfaces(d, async);
1847 break;
1848 case QXL_IO_MONITORS_CONFIG_ASYNC:
1849 qxl_spice_monitors_config_async(d, 0);
1850 break;
1851 default:
1852 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1853 }
1854 return;
1855 cancel_async:
1856 if (async) {
1857 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1858 qemu_mutex_lock(&d->async_lock);
1859 d->current_async = QXL_UNDEFINED_IO;
1860 qemu_mutex_unlock(&d->async_lock);
1861 }
1862 }
1863
1864 static uint64_t ioport_read(void *opaque, hwaddr addr,
1865 unsigned size)
1866 {
1867 PCIQXLDevice *qxl = opaque;
1868
1869 trace_qxl_io_read_unexpected(qxl->id);
1870 return 0xff;
1871 }
1872
1873 static const MemoryRegionOps qxl_io_ops = {
1874 .read = ioport_read,
1875 .write = ioport_write,
1876 .valid = {
1877 .min_access_size = 1,
1878 .max_access_size = 1,
1879 },
1880 };
1881
1882 static void qxl_update_irq_bh(void *opaque)
1883 {
1884 PCIQXLDevice *d = opaque;
1885 qxl_update_irq(d);
1886 }
1887
1888 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1889 {
1890 uint32_t old_pending;
1891 uint32_t le_events = cpu_to_le32(events);
1892
1893 trace_qxl_send_events(d->id, events);
1894 if (!qemu_spice_display_is_running(&d->ssd)) {
1895 /* spice-server tracks guest running state and should not do this */
1896 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1897 __func__);
1898 trace_qxl_send_events_vm_stopped(d->id, events);
1899 return;
1900 }
1901 /*
1902 * Older versions of Spice forgot to define the QXLRam struct
1903 * with the '__aligned__(4)' attribute. clang 7 and newer will
1904 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
1905 * might be a misaligned atomic access, and will generate an
1906 * out-of-line call for it, which results in a link error since
1907 * we don't currently link against libatomic.
1908 *
1909 * In fact we set up d->ram in init_qxl_ram() so it always starts
1910 * at a 4K boundary, so we know that &d->ram->int_pending is
1911 * naturally aligned for a uint32_t. Newer Spice versions
1912 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1913 * will fix the bug directly. To deal with older versions,
1914 * we tell the compiler to assume the address really is aligned.
1915 * Any compiler which cares about the misalignment will have
1916 * __builtin_assume_aligned.
1917 */
1918 #ifdef HAS_ASSUME_ALIGNED
1919 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1920 #else
1921 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1922 #endif
1923
1924 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1925 le_events);
1926 if ((old_pending & le_events) == le_events) {
1927 return;
1928 }
1929 qemu_bh_schedule(d->update_irq);
1930 }
1931
1932 /* graphics console */
1933
1934 static void qxl_hw_update(void *opaque)
1935 {
1936 PCIQXLDevice *qxl = opaque;
1937
1938 qxl_render_update(qxl);
1939 }
1940
1941 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1942 uint32_t height, int32_t stride)
1943 {
1944 uint64_t offset, size;
1945 uint32_t slot;
1946 bool rc;
1947
1948 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1949 assert(rc == true);
1950 size = (uint64_t)height * abs(stride);
1951 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1952 qxl_set_dirty(qxl->guest_slots[slot].mr,
1953 qxl->guest_slots[slot].offset + offset,
1954 qxl->guest_slots[slot].offset + offset + size);
1955 }
1956
1957 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1958 {
1959 int i;
1960
1961 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1962 return;
1963 }
1964
1965 /* dirty the primary surface */
1966 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1967 qxl->guest_primary.surface.height,
1968 qxl->guest_primary.surface.stride);
1969
1970 /* dirty the off-screen surfaces */
1971 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1972 QXLSurfaceCmd *cmd;
1973
1974 if (qxl->guest_surfaces.cmds[i] == 0) {
1975 continue;
1976 }
1977
1978 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1979 MEMSLOT_GROUP_GUEST);
1980 assert(cmd);
1981 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1982 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1983 cmd->u.surface_create.height,
1984 cmd->u.surface_create.stride);
1985 }
1986 }
1987
1988 static void qxl_vm_change_state_handler(void *opaque, int running,
1989 RunState state)
1990 {
1991 PCIQXLDevice *qxl = opaque;
1992
1993 if (running) {
1994 /*
1995 * if qxl_send_events was called from spice server context before
1996 * migration ended, qxl_update_irq for these events might not have been
1997 * called
1998 */
1999 qxl_update_irq(qxl);
2000 } else {
2001 /* make sure surfaces are saved before migration */
2002 qxl_dirty_surfaces(qxl);
2003 }
2004 }
2005
2006 /* display change listener */
2007
2008 static void display_update(DisplayChangeListener *dcl,
2009 int x, int y, int w, int h)
2010 {
2011 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2012
2013 if (qxl->mode == QXL_MODE_VGA) {
2014 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2015 }
2016 }
2017
2018 static void display_switch(DisplayChangeListener *dcl,
2019 struct DisplaySurface *surface)
2020 {
2021 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2022
2023 qxl->ssd.ds = surface;
2024 if (qxl->mode == QXL_MODE_VGA) {
2025 qemu_spice_display_switch(&qxl->ssd, surface);
2026 }
2027 }
2028
2029 static void display_refresh(DisplayChangeListener *dcl)
2030 {
2031 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2032
2033 if (qxl->mode == QXL_MODE_VGA) {
2034 qemu_spice_display_refresh(&qxl->ssd);
2035 }
2036 }
2037
2038 static DisplayChangeListenerOps display_listener_ops = {
2039 .dpy_name = "spice/qxl",
2040 .dpy_gfx_update = display_update,
2041 .dpy_gfx_switch = display_switch,
2042 .dpy_refresh = display_refresh,
2043 };
2044
2045 static void qxl_init_ramsize(PCIQXLDevice *qxl)
2046 {
2047 /* vga mode framebuffer / primary surface (bar 0, first part) */
2048 if (qxl->vgamem_size_mb < 8) {
2049 qxl->vgamem_size_mb = 8;
2050 }
2051 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2052 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2053 */
2054 if (qxl->vgamem_size_mb > 256) {
2055 qxl->vgamem_size_mb = 256;
2056 }
2057 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2058
2059 /* vga ram (bar 0, total) */
2060 if (qxl->ram_size_mb != -1) {
2061 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2062 }
2063 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2064 qxl->vga.vram_size = qxl->vgamem_size * 2;
2065 }
2066
2067 /* vram32 (surfaces, 32bit, bar 1) */
2068 if (qxl->vram32_size_mb != -1) {
2069 qxl->vram32_size = qxl->vram32_size_mb * MiB;
2070 }
2071 if (qxl->vram32_size < 4096) {
2072 qxl->vram32_size = 4096;
2073 }
2074
2075 /* vram (surfaces, 64bit, bar 4+5) */
2076 if (qxl->vram_size_mb != -1) {
2077 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2078 }
2079 if (qxl->vram_size < qxl->vram32_size) {
2080 qxl->vram_size = qxl->vram32_size;
2081 }
2082
2083 if (qxl->revision == 1) {
2084 qxl->vram32_size = 4096;
2085 qxl->vram_size = 4096;
2086 }
2087 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2088 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2089 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2090 qxl->vram_size = pow2ceil(qxl->vram_size);
2091 }
2092
2093 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2094 {
2095 uint8_t* config = qxl->pci.config;
2096 uint32_t pci_device_rev;
2097 uint32_t io_size;
2098
2099 qemu_spice_display_init_common(&qxl->ssd);
2100 qxl->mode = QXL_MODE_UNDEFINED;
2101 qxl->num_memslots = NUM_MEMSLOTS;
2102 qemu_mutex_init(&qxl->track_lock);
2103 qemu_mutex_init(&qxl->async_lock);
2104 qxl->current_async = QXL_UNDEFINED_IO;
2105 qxl->guest_bug = 0;
2106
2107 switch (qxl->revision) {
2108 case 1: /* spice 0.4 -- qxl-1 */
2109 pci_device_rev = QXL_REVISION_STABLE_V04;
2110 io_size = 8;
2111 break;
2112 case 2: /* spice 0.6 -- qxl-2 */
2113 pci_device_rev = QXL_REVISION_STABLE_V06;
2114 io_size = 16;
2115 break;
2116 case 3: /* qxl-3 */
2117 pci_device_rev = QXL_REVISION_STABLE_V10;
2118 io_size = 32; /* PCI region size must be pow2 */
2119 break;
2120 case 4: /* qxl-4 */
2121 pci_device_rev = QXL_REVISION_STABLE_V12;
2122 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2123 break;
2124 default:
2125 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2126 qxl->revision, QXL_DEFAULT_REVISION);
2127 return;
2128 }
2129
2130 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2131 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2132
2133 qxl->rom_size = qxl_rom_size();
2134 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2135 qxl->rom_size, &error_fatal);
2136 init_qxl_rom(qxl);
2137 init_qxl_ram(qxl);
2138
2139 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2140 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2141 qxl->vram_size, &error_fatal);
2142 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2143 &qxl->vram_bar, 0, qxl->vram32_size);
2144
2145 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2146 "qxl-ioports", io_size);
2147 if (qxl->have_vga) {
2148 vga_dirty_log_start(&qxl->vga);
2149 }
2150 memory_region_set_flush_coalesced(&qxl->io_bar);
2151
2152
2153 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2154 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2155
2156 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2157 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2158
2159 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2160 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2161
2162 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2163 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2164
2165 if (qxl->vram32_size < qxl->vram_size) {
2166 /*
2167 * Make the 64bit vram bar show up only in case it is
2168 * configured to be larger than the 32bit vram bar.
2169 */
2170 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2171 PCI_BASE_ADDRESS_SPACE_MEMORY |
2172 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2173 PCI_BASE_ADDRESS_MEM_PREFETCH,
2174 &qxl->vram_bar);
2175 }
2176
2177 /* print pci bar details */
2178 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2179 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2180 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2181 qxl->vram32_size / MiB);
2182 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2183 qxl->vram_size / MiB,
2184 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2185
2186 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2187 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2188 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2189 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2190 return;
2191 }
2192
2193 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2194 char device_address[256] = "";
2195 if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) {
2196 spice_qxl_set_device_info(&qxl->ssd.qxl,
2197 device_address,
2198 0,
2199 qxl->max_outputs);
2200 }
2201 #endif
2202
2203 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2204
2205 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2206 qxl_reset_state(qxl);
2207
2208 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2209 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2210 }
2211
2212 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2213 {
2214 PCIQXLDevice *qxl = PCI_QXL(dev);
2215 VGACommonState *vga = &qxl->vga;
2216 Error *local_err = NULL;
2217
2218 qxl_init_ramsize(qxl);
2219 vga->vbe_size = qxl->vgamem_size;
2220 vga->vram_size_mb = qxl->vga.vram_size / MiB;
2221 vga_common_init(vga, OBJECT(dev));
2222 vga_init(vga, OBJECT(dev),
2223 pci_address_space(dev), pci_address_space_io(dev), false);
2224 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2225 vga, "vga");
2226 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2227 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2228 qxl->have_vga = true;
2229
2230 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2231 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2232 if (qxl->id != 0) {
2233 error_setg(errp, "primary qxl-vga device must be console 0 "
2234 "(first display device on the command line)");
2235 return;
2236 }
2237
2238 qxl_realize_common(qxl, &local_err);
2239 if (local_err) {
2240 error_propagate(errp, local_err);
2241 return;
2242 }
2243
2244 qxl->ssd.dcl.ops = &display_listener_ops;
2245 qxl->ssd.dcl.con = vga->con;
2246 register_displaychangelistener(&qxl->ssd.dcl);
2247 }
2248
2249 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2250 {
2251 PCIQXLDevice *qxl = PCI_QXL(dev);
2252
2253 qxl_init_ramsize(qxl);
2254 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2255 qxl->vga.vram_size, &error_fatal);
2256 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2257 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2258 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2259
2260 qxl_realize_common(qxl, errp);
2261 }
2262
2263 static int qxl_pre_save(void *opaque)
2264 {
2265 PCIQXLDevice* d = opaque;
2266 uint8_t *ram_start = d->vga.vram_ptr;
2267
2268 trace_qxl_pre_save(d->id);
2269 if (d->last_release == NULL) {
2270 d->last_release_offset = 0;
2271 } else {
2272 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2273 }
2274 assert(d->last_release_offset < d->vga.vram_size);
2275
2276 return 0;
2277 }
2278
2279 static int qxl_pre_load(void *opaque)
2280 {
2281 PCIQXLDevice* d = opaque;
2282
2283 trace_qxl_pre_load(d->id);
2284 qxl_hard_reset(d, 1);
2285 qxl_exit_vga_mode(d);
2286 return 0;
2287 }
2288
2289 static void qxl_create_memslots(PCIQXLDevice *d)
2290 {
2291 int i;
2292
2293 for (i = 0; i < NUM_MEMSLOTS; i++) {
2294 if (!d->guest_slots[i].active) {
2295 continue;
2296 }
2297 qxl_add_memslot(d, i, 0, QXL_SYNC);
2298 }
2299 }
2300
2301 static int qxl_post_load(void *opaque, int version)
2302 {
2303 PCIQXLDevice* d = opaque;
2304 uint8_t *ram_start = d->vga.vram_ptr;
2305 QXLCommandExt *cmds;
2306 int in, out, newmode;
2307
2308 assert(d->last_release_offset < d->vga.vram_size);
2309 if (d->last_release_offset == 0) {
2310 d->last_release = NULL;
2311 } else {
2312 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2313 }
2314
2315 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2316
2317 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2318 newmode = d->mode;
2319 d->mode = QXL_MODE_UNDEFINED;
2320
2321 switch (newmode) {
2322 case QXL_MODE_UNDEFINED:
2323 qxl_create_memslots(d);
2324 break;
2325 case QXL_MODE_VGA:
2326 qxl_create_memslots(d);
2327 qxl_enter_vga_mode(d);
2328 break;
2329 case QXL_MODE_NATIVE:
2330 qxl_create_memslots(d);
2331 qxl_create_guest_primary(d, 1, QXL_SYNC);
2332
2333 /* replay surface-create and cursor-set commands */
2334 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2335 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2336 if (d->guest_surfaces.cmds[in] == 0) {
2337 continue;
2338 }
2339 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2340 cmds[out].cmd.type = QXL_CMD_SURFACE;
2341 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2342 out++;
2343 }
2344 if (d->guest_cursor) {
2345 cmds[out].cmd.data = d->guest_cursor;
2346 cmds[out].cmd.type = QXL_CMD_CURSOR;
2347 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2348 out++;
2349 }
2350 qxl_spice_loadvm_commands(d, cmds, out);
2351 g_free(cmds);
2352 if (d->guest_monitors_config) {
2353 qxl_spice_monitors_config_async(d, 1);
2354 }
2355 break;
2356 case QXL_MODE_COMPAT:
2357 /* note: no need to call qxl_create_memslots, qxl_set_mode
2358 * creates the mem slot. */
2359 qxl_set_mode(d, d->shadow_rom.mode, 1);
2360 break;
2361 }
2362 return 0;
2363 }
2364
2365 #define QXL_SAVE_VERSION 21
2366
2367 static bool qxl_monitors_config_needed(void *opaque)
2368 {
2369 PCIQXLDevice *qxl = opaque;
2370
2371 return qxl->guest_monitors_config != 0;
2372 }
2373
2374
2375 static VMStateDescription qxl_memslot = {
2376 .name = "qxl-memslot",
2377 .version_id = QXL_SAVE_VERSION,
2378 .minimum_version_id = QXL_SAVE_VERSION,
2379 .fields = (VMStateField[]) {
2380 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2381 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2382 VMSTATE_UINT32(active, struct guest_slots),
2383 VMSTATE_END_OF_LIST()
2384 }
2385 };
2386
2387 static VMStateDescription qxl_surface = {
2388 .name = "qxl-surface",
2389 .version_id = QXL_SAVE_VERSION,
2390 .minimum_version_id = QXL_SAVE_VERSION,
2391 .fields = (VMStateField[]) {
2392 VMSTATE_UINT32(width, QXLSurfaceCreate),
2393 VMSTATE_UINT32(height, QXLSurfaceCreate),
2394 VMSTATE_INT32(stride, QXLSurfaceCreate),
2395 VMSTATE_UINT32(format, QXLSurfaceCreate),
2396 VMSTATE_UINT32(position, QXLSurfaceCreate),
2397 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2398 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2399 VMSTATE_UINT32(type, QXLSurfaceCreate),
2400 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2401 VMSTATE_END_OF_LIST()
2402 }
2403 };
2404
2405 static VMStateDescription qxl_vmstate_monitors_config = {
2406 .name = "qxl/monitors-config",
2407 .version_id = 1,
2408 .minimum_version_id = 1,
2409 .needed = qxl_monitors_config_needed,
2410 .fields = (VMStateField[]) {
2411 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2412 VMSTATE_END_OF_LIST()
2413 },
2414 };
2415
2416 static VMStateDescription qxl_vmstate = {
2417 .name = "qxl",
2418 .version_id = QXL_SAVE_VERSION,
2419 .minimum_version_id = QXL_SAVE_VERSION,
2420 .pre_save = qxl_pre_save,
2421 .pre_load = qxl_pre_load,
2422 .post_load = qxl_post_load,
2423 .fields = (VMStateField[]) {
2424 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2425 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2426 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2427 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2428 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2429 VMSTATE_UINT32(mode, PCIQXLDevice),
2430 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2431 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2432 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2433 qxl_memslot, struct guest_slots),
2434 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2435 qxl_surface, QXLSurfaceCreate),
2436 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2437 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2438 ssd.num_surfaces, 0,
2439 vmstate_info_uint64, uint64_t),
2440 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2441 VMSTATE_END_OF_LIST()
2442 },
2443 .subsections = (const VMStateDescription*[]) {
2444 &qxl_vmstate_monitors_config,
2445 NULL
2446 }
2447 };
2448
2449 static Property qxl_properties[] = {
2450 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2451 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2452 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2453 QXL_DEFAULT_REVISION),
2454 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2455 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2456 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2457 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2458 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2459 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2460 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2461 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2462 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2463 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2464 #endif
2465 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2466 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2467 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2468 DEFINE_PROP_END_OF_LIST(),
2469 };
2470
2471 static void qxl_pci_class_init(ObjectClass *klass, void *data)
2472 {
2473 DeviceClass *dc = DEVICE_CLASS(klass);
2474 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2475
2476 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2477 k->device_id = QXL_DEVICE_ID_STABLE;
2478 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2479 dc->reset = qxl_reset_handler;
2480 dc->vmsd = &qxl_vmstate;
2481 dc->props = qxl_properties;
2482 }
2483
2484 static const TypeInfo qxl_pci_type_info = {
2485 .name = TYPE_PCI_QXL,
2486 .parent = TYPE_PCI_DEVICE,
2487 .instance_size = sizeof(PCIQXLDevice),
2488 .abstract = true,
2489 .class_init = qxl_pci_class_init,
2490 .interfaces = (InterfaceInfo[]) {
2491 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2492 { },
2493 },
2494 };
2495
2496 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2497 {
2498 DeviceClass *dc = DEVICE_CLASS(klass);
2499 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2500
2501 k->realize = qxl_realize_primary;
2502 k->romfile = "vgabios-qxl.bin";
2503 k->class_id = PCI_CLASS_DISPLAY_VGA;
2504 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2505 dc->hotpluggable = false;
2506 }
2507
2508 static const TypeInfo qxl_primary_info = {
2509 .name = "qxl-vga",
2510 .parent = TYPE_PCI_QXL,
2511 .class_init = qxl_primary_class_init,
2512 };
2513
2514 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2515 {
2516 DeviceClass *dc = DEVICE_CLASS(klass);
2517 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2518
2519 k->realize = qxl_realize_secondary;
2520 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2521 dc->desc = "Spice QXL GPU (secondary)";
2522 }
2523
2524 static const TypeInfo qxl_secondary_info = {
2525 .name = "qxl",
2526 .parent = TYPE_PCI_QXL,
2527 .class_init = qxl_secondary_class_init,
2528 };
2529
2530 static void qxl_register_types(void)
2531 {
2532 type_register_static(&qxl_pci_type_info);
2533 type_register_static(&qxl_primary_info);
2534 type_register_static(&qxl_secondary_info);
2535 }
2536
2537 type_init(qxl_register_types)
AR7 emulation for QEMU