target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/sh4/sh_intc.h"
  25 #endif
  26
  27 #if defined(CONFIG_USER_ONLY)
  28
  29 void superh_cpu_do_interrupt(CPUState *cs)
  30 {
  31     cs->exception_index = -1;
  32 }
  33
  34 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  35                                 int mmu_idx)
  36 {
  37     SuperHCPU *cpu = SUPERH_CPU(cs);
  38     CPUSH4State *env = &cpu->env;
  39
  40     env->tea = address;
  41     cs->exception_index = -1;
  42     switch (rw) {
  43     case 0:
  44         cs->exception_index = 0x0a0;
  45         break;
  46     case 1:
  47         cs->exception_index = 0x0c0;
  48         break;
  49     case 2:
  50         cs->exception_index = 0x0a0;
  51         break;
  52     }
  53     return 1;
  54 }
  55
  56 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  57 {
  58     /* For user mode, only U0 area is cachable. */
  59     return !(addr & 0x80000000);
  60 }
  61
  62 #else /* !CONFIG_USER_ONLY */
  63
  64 #define MMU_OK                   0
  65 #define MMU_ITLB_MISS            (-1)
  66 #define MMU_ITLB_MULTIPLE        (-2)
  67 #define MMU_ITLB_VIOLATION       (-3)
  68 #define MMU_DTLB_MISS_READ       (-4)
  69 #define MMU_DTLB_MISS_WRITE      (-5)
  70 #define MMU_DTLB_INITIAL_WRITE   (-6)
  71 #define MMU_DTLB_VIOLATION_READ  (-7)
  72 #define MMU_DTLB_VIOLATION_WRITE (-8)
  73 #define MMU_DTLB_MULTIPLE        (-9)
  74 #define MMU_DTLB_MISS            (-10)
  75 #define MMU_IADDR_ERROR          (-11)
  76 #define MMU_DADDR_ERROR_READ     (-12)
  77 #define MMU_DADDR_ERROR_WRITE    (-13)
  78
  79 void superh_cpu_do_interrupt(CPUState *cs)
  80 {
  81     SuperHCPU *cpu = SUPERH_CPU(cs);
  82     CPUSH4State *env = &cpu->env;
  83     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
  84     int do_exp, irq_vector = cs->exception_index;
  85
  86     /* prioritize exceptions over interrupts */
  87
  88     do_exp = cs->exception_index != -1;
  89     do_irq = do_irq && (cs->exception_index == -1);
  90
  91     if (env->sr & SR_BL) {
  92         if (do_exp && cs->exception_index != 0x1e0) {
  93             cs->exception_index = 0x000; /* masked exception -> reset */
  94         }
  95         if (do_irq && !env->in_sleep) {
  96             return; /* masked */
  97         }
  98     }
  99     env->in_sleep = 0;
 100
 101     if (do_irq) {
 102         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 103                                                 (env->sr >> 4) & 0xf);
 104         if (irq_vector == -1) {
 105             return; /* masked */
 106         }
 107     }
 108
 109     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 110         const char *expname;
 111         switch (cs->exception_index) {
 112         case 0x0e0:
 113             expname = "addr_error";
 114             break;
 115         case 0x040:
 116             expname = "tlb_miss";
 117             break;
 118         case 0x0a0:
 119             expname = "tlb_violation";
 120             break;
 121         case 0x180:
 122             expname = "illegal_instruction";
 123             break;
 124         case 0x1a0:
 125             expname = "slot_illegal_instruction";
 126             break;
 127         case 0x800:
 128             expname = "fpu_disable";
 129             break;
 130         case 0x820:
 131             expname = "slot_fpu";
 132             break;
 133         case 0x100:
 134             expname = "data_write";
 135             break;
 136         case 0x060:
 137             expname = "dtlb_miss_write";
 138             break;
 139         case 0x0c0:
 140             expname = "dtlb_violation_write";
 141             break;
 142         case 0x120:
 143             expname = "fpu_exception";
 144             break;
 145         case 0x080:
 146             expname = "initial_page_write";
 147             break;
 148         case 0x160:
 149             expname = "trapa";
 150             break;
 151         default:
 152             expname = do_irq ? "interrupt" : "???";
 153             break;
 154         }
 155         qemu_log("exception 0x%03x [%s] raised\n",
 156                   irq_vector, expname);
 157         log_cpu_state(cs, 0);
 158     }
 159
 160     env->ssr = env->sr;
 161     env->spc = env->pc;
 162     env->sgr = env->gregs[15];
 163     env->sr |= SR_BL | SR_MD | SR_RB;
 164
 165     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 166         /* Branch instruction should be executed again before delay slot. */
 167         env->spc -= 2;
 168         /* Clear flags for exception/interrupt routine. */
 169         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 170     }
 171     if (env->flags & DELAY_SLOT_CLEARME)
 172         env->flags = 0;
 173
 174     if (do_exp) {
 175         env->expevt = cs->exception_index;
 176         switch (cs->exception_index) {
 177         case 0x000:
 178         case 0x020:
 179         case 0x140:
 180             env->sr &= ~SR_FD;
 181             env->sr |= 0xf << 4; /* IMASK */
 182             env->pc = 0xa0000000;
 183             break;
 184         case 0x040:
 185         case 0x060:
 186             env->pc = env->vbr + 0x400;
 187             break;
 188         case 0x160:
 189             env->spc += 2; /* special case for TRAPA */
 190             /* fall through */
 191         default:
 192             env->pc = env->vbr + 0x100;
 193             break;
 194         }
 195         return;
 196     }
 197
 198     if (do_irq) {
 199         env->intevt = irq_vector;
 200         env->pc = env->vbr + 0x600;
 201         return;
 202     }
 203 }
 204
 205 static void update_itlb_use(CPUSH4State * env, int itlbnb)
 206 {
 207     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 208
 209     switch (itlbnb) {
 210     case 0:
 211         and_mask = 0x1f;
 212         break;
 213     case 1:
 214         and_mask = 0xe7;
 215         or_mask = 0x80;
 216         break;
 217     case 2:
 218         and_mask = 0xfb;
 219         or_mask = 0x50;
 220         break;
 221     case 3:
 222         or_mask = 0x2c;
 223         break;
 224     }
 225
 226     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 227     env->mmucr |= (or_mask << 24);
 228 }
 229
 230 static int itlb_replacement(CPUSH4State * env)
 231 {
 232     SuperHCPU *cpu = sh_env_get_cpu(env);
 233
 234     if ((env->mmucr & 0xe0000000) == 0xe0000000) {
 235         return 0;
 236     }
 237     if ((env->mmucr & 0x98000000) == 0x18000000) {
 238         return 1;
 239     }
 240     if ((env->mmucr & 0x54000000) == 0x04000000) {
 241         return 2;
 242     }
 243     if ((env->mmucr & 0x2c000000) == 0x00000000) {
 244         return 3;
 245     }
 246     cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
 247 }
 248
 249 /* Find the corresponding entry in the right TLB
 250    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 251 */
 252 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
 253                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 254 {
 255     int match = MMU_DTLB_MISS;
 256     uint32_t start, end;
 257     uint8_t asid;
 258     int i;
 259
 260     asid = env->pteh & 0xff;
 261
 262     for (i = 0; i < nbtlb; i++) {
 263         if (!entries[i].v)
 264             continue;           /* Invalid entry */
 265         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 266             continue;           /* Bad ASID */
 267         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 268         end = start + entries[i].size - 1;
 269         if (address >= start && address <= end) {       /* Match */
 270             if (match != MMU_DTLB_MISS)
 271                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 272             match = i;
 273         }
 274     }
 275     return match;
 276 }
 277
 278 static void increment_urc(CPUSH4State * env)
 279 {
 280     uint8_t urb, urc;
 281
 282     /* Increment URC */
 283     urb = ((env->mmucr) >> 18) & 0x3f;
 284     urc = ((env->mmucr) >> 10) & 0x3f;
 285     urc++;
 286     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 287         urc = 0;
 288     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 289 }
 290
 291 /* Copy and utlb entry into itlb
 292    Return entry
 293 */
 294 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 295 {
 296     int itlb;
 297
 298     tlb_t * ientry;
 299     itlb = itlb_replacement(env);
 300     ientry = &env->itlb[itlb];
 301     if (ientry->v) {
 302         tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
 303     }
 304     *ientry = env->utlb[utlb];
 305     update_itlb_use(env, itlb);
 306     return itlb;
 307 }
 308
 309 /* Find itlb entry
 310    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 311 */
 312 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 313                            int use_asid)
 314 {
 315     int e;
 316
 317     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 318     if (e == MMU_DTLB_MULTIPLE) {
 319         e = MMU_ITLB_MULTIPLE;
 320     } else if (e == MMU_DTLB_MISS) {
 321         e = MMU_ITLB_MISS;
 322     } else if (e >= 0) {
 323         update_itlb_use(env, e);
 324     }
 325     return e;
 326 }
 327
 328 /* Find utlb entry
 329    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 330 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
 331 {
 332     /* per utlb access */
 333     increment_urc(env);
 334
 335     /* Return entry */
 336     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 337 }
 338
 339 /* Match address against MMU
 340    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 341    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 342    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 343    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 344    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 345 */
 346 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
 347                            int *prot, target_ulong address,
 348                            int rw, int access_type)
 349 {
 350     int use_asid, n;
 351     tlb_t *matching = NULL;
 352
 353     use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 354
 355     if (rw == 2) {
 356         n = find_itlb_entry(env, address, use_asid);
 357         if (n >= 0) {
 358             matching = &env->itlb[n];
 359             if (!(env->sr & SR_MD) && !(matching->pr & 2))
 360                 n = MMU_ITLB_VIOLATION;
 361             else
 362                 *prot = PAGE_EXEC;
 363         } else {
 364             n = find_utlb_entry(env, address, use_asid);
 365             if (n >= 0) {
 366                 n = copy_utlb_entry_itlb(env, n);
 367                 matching = &env->itlb[n];
 368                 if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 369                       n = MMU_ITLB_VIOLATION;
 370                 } else {
 371                     *prot = PAGE_READ | PAGE_EXEC;
 372                     if ((matching->pr & 1) && matching->d) {
 373                         *prot |= PAGE_WRITE;
 374                     }
 375                 }
 376             } else if (n == MMU_DTLB_MULTIPLE) {
 377                 n = MMU_ITLB_MULTIPLE;
 378             } else if (n == MMU_DTLB_MISS) {
 379                 n = MMU_ITLB_MISS;
 380             }
 381         }
 382     } else {
 383         n = find_utlb_entry(env, address, use_asid);
 384         if (n >= 0) {
 385             matching = &env->utlb[n];
 386             if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 387                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 388                     MMU_DTLB_VIOLATION_READ;
 389             } else if ((rw == 1) && !(matching->pr & 1)) {
 390                 n = MMU_DTLB_VIOLATION_WRITE;
 391             } else if ((rw == 1) && !matching->d) {
 392                 n = MMU_DTLB_INITIAL_WRITE;
 393             } else {
 394                 *prot = PAGE_READ;
 395                 if ((matching->pr & 1) && matching->d) {
 396                     *prot |= PAGE_WRITE;
 397                 }
 398             }
 399         } else if (n == MMU_DTLB_MISS) {
 400             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 401                 MMU_DTLB_MISS_READ;
 402         }
 403     }
 404     if (n >= 0) {
 405         n = MMU_OK;
 406         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 407             (address & (matching->size - 1));
 408     }
 409     return n;
 410 }
 411
 412 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 413                                 int *prot, target_ulong address,
 414                                 int rw, int access_type)
 415 {
 416     /* P1, P2 and P4 areas do not use translation */
 417     if ((address >= 0x80000000 && address < 0xc0000000) ||
 418         address >= 0xe0000000) {
 419         if (!(env->sr & SR_MD)
 420             && (address < 0xe0000000 || address >= 0xe4000000)) {
 421             /* Unauthorized access in user mode (only store queues are available) */
 422             fprintf(stderr, "Unauthorized access\n");
 423             if (rw == 0)
 424                 return MMU_DADDR_ERROR_READ;
 425             else if (rw == 1)
 426                 return MMU_DADDR_ERROR_WRITE;
 427             else
 428                 return MMU_IADDR_ERROR;
 429         }
 430         if (address >= 0x80000000 && address < 0xc0000000) {
 431             /* Mask upper 3 bits for P1 and P2 areas */
 432             *physical = address & 0x1fffffff;
 433         } else {
 434             *physical = address;
 435         }
 436         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 437         return MMU_OK;
 438     }
 439
 440     /* If MMU is disabled, return the corresponding physical page */
 441     if (!(env->mmucr & MMUCR_AT)) {
 442         *physical = address & 0x1FFFFFFF;
 443         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 444         return MMU_OK;
 445     }
 446
 447     /* We need to resort to the MMU */
 448     return get_mmu_address(env, physical, prot, address, rw, access_type);
 449 }
 450
 451 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 452                                 int mmu_idx)
 453 {
 454     SuperHCPU *cpu = SUPERH_CPU(cs);
 455     CPUSH4State *env = &cpu->env;
 456     target_ulong physical;
 457     int prot, ret, access_type;
 458
 459     access_type = ACCESS_INT;
 460     ret =
 461         get_physical_address(env, &physical, &prot, address, rw,
 462                              access_type);
 463
 464     if (ret != MMU_OK) {
 465         env->tea = address;
 466         if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
 467             env->pteh = (env->pteh & PTEH_ASID_MASK) |
 468                     (address & PTEH_VPN_MASK);
 469         }
 470         switch (ret) {
 471         case MMU_ITLB_MISS:
 472         case MMU_DTLB_MISS_READ:
 473             cs->exception_index = 0x040;
 474             break;
 475         case MMU_DTLB_MULTIPLE:
 476         case MMU_ITLB_MULTIPLE:
 477             cs->exception_index = 0x140;
 478             break;
 479         case MMU_ITLB_VIOLATION:
 480             cs->exception_index = 0x0a0;
 481             break;
 482         case MMU_DTLB_MISS_WRITE:
 483             cs->exception_index = 0x060;
 484             break;
 485         case MMU_DTLB_INITIAL_WRITE:
 486             cs->exception_index = 0x080;
 487             break;
 488         case MMU_DTLB_VIOLATION_READ:
 489             cs->exception_index = 0x0a0;
 490             break;
 491         case MMU_DTLB_VIOLATION_WRITE:
 492             cs->exception_index = 0x0c0;
 493             break;
 494         case MMU_IADDR_ERROR:
 495         case MMU_DADDR_ERROR_READ:
 496             cs->exception_index = 0x0e0;
 497             break;
 498         case MMU_DADDR_ERROR_WRITE:
 499             cs->exception_index = 0x100;
 500             break;
 501         default:
 502             cpu_abort(cs, "Unhandled MMU fault");
 503         }
 504         return 1;
 505     }
 506
 507     address &= TARGET_PAGE_MASK;
 508     physical &= TARGET_PAGE_MASK;
 509
 510     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 511     return 0;
 512 }
 513
 514 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 515 {
 516     SuperHCPU *cpu = SUPERH_CPU(cs);
 517     target_ulong physical;
 518     int prot;
 519
 520     get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
 521     return physical;
 522 }
 523
 524 void cpu_load_tlb(CPUSH4State * env)
 525 {
 526     SuperHCPU *cpu = sh_env_get_cpu(env);
 527     int n = cpu_mmucr_urc(env->mmucr);
 528     tlb_t * entry = &env->utlb[n];
 529
 530     if (entry->v) {
 531         /* Overwriting valid entry in utlb. */
 532         target_ulong address = entry->vpn << 10;
 533         tlb_flush_page(CPU(cpu), address);
 534     }
 535
 536     /* Take values into cpu status from registers. */
 537     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 538     entry->vpn  = cpu_pteh_vpn(env->pteh);
 539     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 540     entry->ppn  = cpu_ptel_ppn(env->ptel);
 541     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 542     switch (entry->sz) {
 543     case 0: /* 00 */
 544         entry->size = 1024; /* 1K */
 545         break;
 546     case 1: /* 01 */
 547         entry->size = 1024 * 4; /* 4K */
 548         break;
 549     case 2: /* 10 */
 550         entry->size = 1024 * 64; /* 64K */
 551         break;
 552     case 3: /* 11 */
 553         entry->size = 1024 * 1024; /* 1M */
 554         break;
 555     default:
 556         cpu_abort(CPU(cpu), "Unhandled load_tlb");
 557         break;
 558     }
 559     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 560     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 561     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 562     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 563     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 564     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 565     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 566 }
 567
 568  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 569 {
 570     int i;
 571
 572     /* UTLB */
 573     for (i = 0; i < UTLB_SIZE; i++) {
 574         tlb_t * entry = &s->utlb[i];
 575         entry->v = 0;
 576     }
 577     /* ITLB */
 578     for (i = 0; i < ITLB_SIZE; i++) {
 579         tlb_t * entry = &s->itlb[i];
 580         entry->v = 0;
 581     }
 582
 583     tlb_flush(CPU(sh_env_get_cpu(s)), 1);
 584 }
 585
 586 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 587                                        hwaddr addr)
 588 {
 589     int index = (addr & 0x00000300) >> 8;
 590     tlb_t * entry = &s->itlb[index];
 591
 592     return (entry->vpn  << 10) |
 593            (entry->v    <<  8) |
 594            (entry->asid);
 595 }
 596
 597 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 598                                     uint32_t mem_value)
 599 {
 600     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 601     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 602     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 603
 604     int index = (addr & 0x00000300) >> 8;
 605     tlb_t * entry = &s->itlb[index];
 606     if (entry->v) {
 607         /* Overwriting valid entry in itlb. */
 608         target_ulong address = entry->vpn << 10;
 609         tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 610     }
 611     entry->asid = asid;
 612     entry->vpn = vpn;
 613     entry->v = v;
 614 }
 615
 616 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 617                                        hwaddr addr)
 618 {
 619     int array = (addr & 0x00800000) >> 23;
 620     int index = (addr & 0x00000300) >> 8;
 621     tlb_t * entry = &s->itlb[index];
 622
 623     if (array == 0) {
 624         /* ITLB Data Array 1 */
 625         return (entry->ppn << 10) |
 626                (entry->v   <<  8) |
 627                (entry->pr  <<  5) |
 628                ((entry->sz & 1) <<  6) |
 629                ((entry->sz & 2) <<  4) |
 630                (entry->c   <<  3) |
 631                (entry->sh  <<  1);
 632     } else {
 633         /* ITLB Data Array 2 */
 634         return (entry->tc << 1) |
 635                (entry->sa);
 636     }
 637 }
 638
 639 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 640                                     uint32_t mem_value)
 641 {
 642     int array = (addr & 0x00800000) >> 23;
 643     int index = (addr & 0x00000300) >> 8;
 644     tlb_t * entry = &s->itlb[index];
 645
 646     if (array == 0) {
 647         /* ITLB Data Array 1 */
 648         if (entry->v) {
 649             /* Overwriting valid entry in utlb. */
 650             target_ulong address = entry->vpn << 10;
 651             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 652         }
 653         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 654         entry->v   = (mem_value & 0x00000100) >> 8;
 655         entry->sz  = (mem_value & 0x00000080) >> 6 |
 656                      (mem_value & 0x00000010) >> 4;
 657         entry->pr  = (mem_value & 0x00000040) >> 5;
 658         entry->c   = (mem_value & 0x00000008) >> 3;
 659         entry->sh  = (mem_value & 0x00000002) >> 1;
 660     } else {
 661         /* ITLB Data Array 2 */
 662         entry->tc  = (mem_value & 0x00000008) >> 3;
 663         entry->sa  = (mem_value & 0x00000007);
 664     }
 665 }
 666
 667 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 668                                        hwaddr addr)
 669 {
 670     int index = (addr & 0x00003f00) >> 8;
 671     tlb_t * entry = &s->utlb[index];
 672
 673     increment_urc(s); /* per utlb access */
 674
 675     return (entry->vpn  << 10) |
 676            (entry->v    <<  8) |
 677            (entry->asid);
 678 }
 679
 680 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 681                                     uint32_t mem_value)
 682 {
 683     int associate = addr & 0x0000080;
 684     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 685     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 686     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 687     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 688     int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
 689
 690     if (associate) {
 691         int i;
 692         tlb_t * utlb_match_entry = NULL;
 693         int needs_tlb_flush = 0;
 694
 695         /* search UTLB */
 696         for (i = 0; i < UTLB_SIZE; i++) {
 697             tlb_t * entry = &s->utlb[i];
 698             if (!entry->v)
 699                 continue;
 700
 701             if (entry->vpn == vpn
 702                 && (!use_asid || entry->asid == asid || entry->sh)) {
 703                 if (utlb_match_entry) {
 704                     CPUState *cs = CPU(sh_env_get_cpu(s));
 705
 706                     /* Multiple TLB Exception */
 707                     cs->exception_index = 0x140;
 708                     s->tea = addr;
 709                     break;
 710                 }
 711                 if (entry->v && !v)
 712                     needs_tlb_flush = 1;
 713                 entry->v = v;
 714                 entry->d = d;
 715                 utlb_match_entry = entry;
 716             }
 717             increment_urc(s); /* per utlb access */
 718         }
 719
 720         /* search ITLB */
 721         for (i = 0; i < ITLB_SIZE; i++) {
 722             tlb_t * entry = &s->itlb[i];
 723             if (entry->vpn == vpn
 724                 && (!use_asid || entry->asid == asid || entry->sh)) {
 725                 if (entry->v && !v)
 726                     needs_tlb_flush = 1;
 727                 if (utlb_match_entry)
 728                     *entry = *utlb_match_entry;
 729                 else
 730                     entry->v = v;
 731                 break;
 732             }
 733         }
 734
 735         if (needs_tlb_flush) {
 736             tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
 737         }
 738
 739     } else {
 740         int index = (addr & 0x00003f00) >> 8;
 741         tlb_t * entry = &s->utlb[index];
 742         if (entry->v) {
 743             CPUState *cs = CPU(sh_env_get_cpu(s));
 744
 745             /* Overwriting valid entry in utlb. */
 746             target_ulong address = entry->vpn << 10;
 747             tlb_flush_page(cs, address);
 748         }
 749         entry->asid = asid;
 750         entry->vpn = vpn;
 751         entry->d = d;
 752         entry->v = v;
 753         increment_urc(s);
 754     }
 755 }
 756
 757 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 758                                        hwaddr addr)
 759 {
 760     int array = (addr & 0x00800000) >> 23;
 761     int index = (addr & 0x00003f00) >> 8;
 762     tlb_t * entry = &s->utlb[index];
 763
 764     increment_urc(s); /* per utlb access */
 765
 766     if (array == 0) {
 767         /* ITLB Data Array 1 */
 768         return (entry->ppn << 10) |
 769                (entry->v   <<  8) |
 770                (entry->pr  <<  5) |
 771                ((entry->sz & 1) <<  6) |
 772                ((entry->sz & 2) <<  4) |
 773                (entry->c   <<  3) |
 774                (entry->d   <<  2) |
 775                (entry->sh  <<  1) |
 776                (entry->wt);
 777     } else {
 778         /* ITLB Data Array 2 */
 779         return (entry->tc << 1) |
 780                (entry->sa);
 781     }
 782 }
 783
 784 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 785                                     uint32_t mem_value)
 786 {
 787     int array = (addr & 0x00800000) >> 23;
 788     int index = (addr & 0x00003f00) >> 8;
 789     tlb_t * entry = &s->utlb[index];
 790
 791     increment_urc(s); /* per utlb access */
 792
 793     if (array == 0) {
 794         /* UTLB Data Array 1 */
 795         if (entry->v) {
 796             /* Overwriting valid entry in utlb. */
 797             target_ulong address = entry->vpn << 10;
 798             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
 799         }
 800         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 801         entry->v   = (mem_value & 0x00000100) >> 8;
 802         entry->sz  = (mem_value & 0x00000080) >> 6 |
 803                      (mem_value & 0x00000010) >> 4;
 804         entry->pr  = (mem_value & 0x00000060) >> 5;
 805         entry->c   = (mem_value & 0x00000008) >> 3;
 806         entry->d   = (mem_value & 0x00000004) >> 2;
 807         entry->sh  = (mem_value & 0x00000002) >> 1;
 808         entry->wt  = (mem_value & 0x00000001);
 809     } else {
 810         /* UTLB Data Array 2 */
 811         entry->tc = (mem_value & 0x00000008) >> 3;
 812         entry->sa = (mem_value & 0x00000007);
 813     }
 814 }
 815
 816 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 817 {
 818     int n;
 819     int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 820
 821     /* check area */
 822     if (env->sr & SR_MD) {
 823         /* For previledged mode, P2 and P4 area is not cachable. */
 824         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 825             return 0;
 826     } else {
 827         /* For user mode, only U0 area is cachable. */
 828         if (0x80000000 <= addr)
 829             return 0;
 830     }
 831
 832     /*
 833      * TODO : Evaluate CCR and check if the cache is on or off.
 834      *        Now CCR is not in CPUSH4State, but in SH7750State.
 835      *        When you move the ccr into CPUSH4State, the code will be
 836      *        as follows.
 837      */
 838 #if 0
 839     /* check if operand cache is enabled or not. */
 840     if (!(env->ccr & 1))
 841         return 0;
 842 #endif
 843
 844     /* if MMU is off, no check for TLB. */
 845     if (env->mmucr & MMUCR_AT)
 846         return 1;
 847
 848     /* check TLB */
 849     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 850     if (n >= 0)
 851         return env->itlb[n].c;
 852
 853     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 854     if (n >= 0)
 855         return env->utlb[n].c;
 856
 857     return 0;
 858 }
 859
 860 #endif
 861
 862 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 863 {
 864     if (interrupt_request & CPU_INTERRUPT_HARD) {
 865         superh_cpu_do_interrupt(cs);
 866         return true;
 867     }
 868     return false;
 869 }