target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     return cs->interrupt_request &
  44         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  45          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  46          | CPU_INTERRUPT_EXITTB);
  47 }
  48
  49 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  50 {
  51     /* Reset a single ARMCPRegInfo register */
  52     ARMCPRegInfo *ri = value;
  53     ARMCPU *cpu = opaque;
  54
  55     if (ri->type & ARM_CP_SPECIAL) {
  56         return;
  57     }
  58
  59     if (ri->resetfn) {
  60         ri->resetfn(&cpu->env, ri);
  61         return;
  62     }
  63
  64     /* A zero offset is never possible as it would be regs[0]
  65      * so we use it to indicate that reset is being handled elsewhere.
  66      * This is basically only used for fields in non-core coprocessors
  67      * (like the pxa2xx ones).
  68      */
  69     if (!ri->fieldoffset) {
  70         return;
  71     }
  72
  73     if (cpreg_field_is_64bit(ri)) {
  74         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  75     } else {
  76         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  77     }
  78 }
  79
  80 /* CPUClass::reset() */
  81 static void arm_cpu_reset(CPUState *s)
  82 {
  83     ARMCPU *cpu = ARM_CPU(s);
  84     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  85     CPUARMState *env = &cpu->env;
  86
  87     acc->parent_reset(s);
  88
  89     memset(env, 0, offsetof(CPUARMState, features));
  90     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  91     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  92     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  93     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  94     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  95
  96     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  97         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  98     }
  99
 100     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 101         /* 64 bit CPUs always start in 64 bit mode */
 102         env->aarch64 = 1;
 103 #if defined(CONFIG_USER_ONLY)
 104         env->pstate = PSTATE_MODE_EL0t;
 105         /* Userspace expects access to CTL_EL0 and the cache ops */
 106         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 107         /* and to the FP/Neon instructions */
 108         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 109 #else
 110         env->pstate = PSTATE_MODE_EL1h;
 111         env->pc = cpu->rvbar;
 112 #endif
 113     } else {
 114 #if defined(CONFIG_USER_ONLY)
 115         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 116         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 117 #endif
 118     }
 119
 120 #if defined(CONFIG_USER_ONLY)
 121     env->uncached_cpsr = ARM_CPU_MODE_USR;
 122     /* For user mode we must enable access to coprocessors */
 123     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 124     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 125         env->cp15.c15_cpar = 3;
 126     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 127         env->cp15.c15_cpar = 1;
 128     }
 129 #else
 130     /* SVC mode with interrupts disabled.  */
 131     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 132     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 133     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 134      * clear at reset. Initial SP and PC are loaded from ROM.
 135      */
 136     if (IS_M(env)) {
 137         uint32_t initial_msp; /* Loaded from 0x0 */
 138         uint32_t initial_pc; /* Loaded from 0x4 */
 139         uint8_t *rom;
 140
 141         env->daif &= ~PSTATE_I;
 142         rom = rom_ptr(0);
 143         if (rom) {
 144             /* Address zero is covered by ROM which hasn't yet been
 145              * copied into physical memory.
 146              */
 147             initial_msp = ldl_p(rom);
 148             initial_pc = ldl_p(rom + 4);
 149         } else {
 150             /* Address zero not covered by a ROM blob, or the ROM blob
 151              * is in non-modifiable memory and this is a second reset after
 152              * it got copied into memory. In the latter case, rom_ptr
 153              * will return a NULL pointer and we should use ldl_phys instead.
 154              */
 155             initial_msp = ldl_phys(s->as, 0);
 156             initial_pc = ldl_phys(s->as, 4);
 157         }
 158
 159         env->regs[13] = initial_msp & 0xFFFFFFFC;
 160         env->regs[15] = initial_pc & ~1;
 161         env->thumb = initial_pc & 1;
 162     }
 163
 164     if (env->cp15.c1_sys & SCTLR_V) {
 165         env->regs[15] = 0xFFFF0000;
 166     }
 167
 168     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 169 #endif
 170     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 171     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 172     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 173     set_float_detect_tininess(float_tininess_before_rounding,
 174                               &env->vfp.fp_status);
 175     set_float_detect_tininess(float_tininess_before_rounding,
 176                               &env->vfp.standard_fp_status);
 177     tlb_flush(s, 1);
 178
 179 #ifndef CONFIG_USER_ONLY
 180     if (kvm_enabled()) {
 181         kvm_arm_reset_vcpu(cpu);
 182     }
 183 #endif
 184
 185     hw_breakpoint_update_all(cpu);
 186     hw_watchpoint_update_all(cpu);
 187 }
 188
 189 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 190 {
 191     CPUClass *cc = CPU_GET_CLASS(cs);
 192     bool ret = false;
 193
 194     if (interrupt_request & CPU_INTERRUPT_FIQ
 195         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 196         cs->exception_index = EXCP_FIQ;
 197         cc->do_interrupt(cs);
 198         ret = true;
 199     }
 200     /* ARMv7-M interrupt return works by loading a magic value
 201        into the PC.  On real hardware the load causes the
 202        return to occur.  The qemu implementation performs the
 203        jump normally, then does the exception return when the
 204        CPU tries to execute code at the magic address.
 205        This will cause the magic PC value to be pushed to
 206        the stack if an interrupt occurred at the wrong time.
 207        We avoid this by disabling interrupts when
 208        pc contains a magic address.  */
 209     if (interrupt_request & CPU_INTERRUPT_HARD
 210         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 211         cs->exception_index = EXCP_IRQ;
 212         cc->do_interrupt(cs);
 213         ret = true;
 214     }
 215     if (interrupt_request & CPU_INTERRUPT_VIRQ
 216         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 217         cs->exception_index = EXCP_VIRQ;
 218         cc->do_interrupt(cs);
 219         ret = true;
 220     }
 221     if (interrupt_request & CPU_INTERRUPT_VFIQ
 222         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 223         cs->exception_index = EXCP_VFIQ;
 224         cc->do_interrupt(cs);
 225         ret = true;
 226     }
 227
 228     return ret;
 229 }
 230
 231 #ifndef CONFIG_USER_ONLY
 232 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 233 {
 234     ARMCPU *cpu = opaque;
 235     CPUARMState *env = &cpu->env;
 236     CPUState *cs = CPU(cpu);
 237     static const int mask[] = {
 238         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 239         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 240         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 241         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 242     };
 243
 244     switch (irq) {
 245     case ARM_CPU_VIRQ:
 246     case ARM_CPU_VFIQ:
 247         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 248             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 249                      __func__, irq);
 250         }
 251         /* fall through */
 252     case ARM_CPU_IRQ:
 253     case ARM_CPU_FIQ:
 254         if (level) {
 255             cpu_interrupt(cs, mask[irq]);
 256         } else {
 257             cpu_reset_interrupt(cs, mask[irq]);
 258         }
 259         break;
 260     default:
 261         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 262     }
 263 }
 264
 265 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 266 {
 267 #ifdef CONFIG_KVM
 268     ARMCPU *cpu = opaque;
 269     CPUState *cs = CPU(cpu);
 270     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 271
 272     switch (irq) {
 273     case ARM_CPU_IRQ:
 274         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 275         break;
 276     case ARM_CPU_FIQ:
 277         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 278         break;
 279     default:
 280         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 281     }
 282     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 283     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 284 #endif
 285 }
 286 #endif
 287
 288 static inline void set_feature(CPUARMState *env, int feature)
 289 {
 290     env->features |= 1ULL << feature;
 291 }
 292
 293 static void arm_cpu_initfn(Object *obj)
 294 {
 295     CPUState *cs = CPU(obj);
 296     ARMCPU *cpu = ARM_CPU(obj);
 297     static bool inited;
 298
 299     cs->env_ptr = &cpu->env;
 300     cpu_exec_init(&cpu->env);
 301     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 302                                          g_free, g_free);
 303
 304 #ifndef CONFIG_USER_ONLY
 305     /* Our inbound IRQ and FIQ lines */
 306     if (kvm_enabled()) {
 307         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 308          * the same interface as non-KVM CPUs.
 309          */
 310         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 311     } else {
 312         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 313     }
 314
 315     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 316                                                 arm_gt_ptimer_cb, cpu);
 317     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 318                                                 arm_gt_vtimer_cb, cpu);
 319     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 320                        ARRAY_SIZE(cpu->gt_timer_outputs));
 321 #endif
 322
 323     /* DTB consumers generally don't in fact care what the 'compatible'
 324      * string is, so always provide some string and trust that a hypothetical
 325      * picky DTB consumer will also provide a helpful error message.
 326      */
 327     cpu->dtb_compatible = "qemu,unknown";
 328     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 329     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 330
 331     if (tcg_enabled() && !inited) {
 332         inited = true;
 333         arm_translate_init();
 334     }
 335 }
 336
 337 static Property arm_cpu_reset_cbar_property =
 338             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 339
 340 static Property arm_cpu_reset_hivecs_property =
 341             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 342
 343 static Property arm_cpu_rvbar_property =
 344             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 345
 346 static void arm_cpu_post_init(Object *obj)
 347 {
 348     ARMCPU *cpu = ARM_CPU(obj);
 349
 350     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 351         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 352         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 353                                  &error_abort);
 354     }
 355
 356     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 357         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 358                                  &error_abort);
 359     }
 360
 361     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 362         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 363                                  &error_abort);
 364     }
 365 }
 366
 367 static void arm_cpu_finalizefn(Object *obj)
 368 {
 369     ARMCPU *cpu = ARM_CPU(obj);
 370     g_hash_table_destroy(cpu->cp_regs);
 371 }
 372
 373 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 374 {
 375     CPUState *cs = CPU(dev);
 376     ARMCPU *cpu = ARM_CPU(dev);
 377     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 378     CPUARMState *env = &cpu->env;
 379
 380     /* Some features automatically imply others: */
 381     if (arm_feature(env, ARM_FEATURE_V8)) {
 382         set_feature(env, ARM_FEATURE_V7);
 383         set_feature(env, ARM_FEATURE_ARM_DIV);
 384         set_feature(env, ARM_FEATURE_LPAE);
 385     }
 386     if (arm_feature(env, ARM_FEATURE_V7)) {
 387         set_feature(env, ARM_FEATURE_VAPA);
 388         set_feature(env, ARM_FEATURE_THUMB2);
 389         set_feature(env, ARM_FEATURE_MPIDR);
 390         if (!arm_feature(env, ARM_FEATURE_M)) {
 391             set_feature(env, ARM_FEATURE_V6K);
 392         } else {
 393             set_feature(env, ARM_FEATURE_V6);
 394         }
 395     }
 396     if (arm_feature(env, ARM_FEATURE_V6K)) {
 397         set_feature(env, ARM_FEATURE_V6);
 398         set_feature(env, ARM_FEATURE_MVFR);
 399     }
 400     if (arm_feature(env, ARM_FEATURE_V6)) {
 401         set_feature(env, ARM_FEATURE_V5);
 402         if (!arm_feature(env, ARM_FEATURE_M)) {
 403             set_feature(env, ARM_FEATURE_AUXCR);
 404         }
 405     }
 406     if (arm_feature(env, ARM_FEATURE_V5)) {
 407         set_feature(env, ARM_FEATURE_V4T);
 408     }
 409     if (arm_feature(env, ARM_FEATURE_M)) {
 410         set_feature(env, ARM_FEATURE_THUMB_DIV);
 411     }
 412     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 413         set_feature(env, ARM_FEATURE_THUMB_DIV);
 414     }
 415     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 416         set_feature(env, ARM_FEATURE_VFP3);
 417         set_feature(env, ARM_FEATURE_VFP_FP16);
 418     }
 419     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 420         set_feature(env, ARM_FEATURE_VFP);
 421     }
 422     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 423         set_feature(env, ARM_FEATURE_V7MP);
 424         set_feature(env, ARM_FEATURE_PXN);
 425     }
 426     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 427         set_feature(env, ARM_FEATURE_CBAR);
 428     }
 429
 430     if (cpu->reset_hivecs) {
 431             cpu->reset_sctlr |= (1 << 13);
 432     }
 433
 434     register_cp_regs_for_features(cpu);
 435     arm_cpu_register_gdb_regs_for_features(cpu);
 436
 437     init_cpreg_list(cpu);
 438
 439     qemu_init_vcpu(cs);
 440     cpu_reset(cs);
 441
 442     acc->parent_realize(dev, errp);
 443 }
 444
 445 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 446 {
 447     ObjectClass *oc;
 448     char *typename;
 449
 450     if (!cpu_model) {
 451         return NULL;
 452     }
 453
 454     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 455     oc = object_class_by_name(typename);
 456     g_free(typename);
 457     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 458         object_class_is_abstract(oc)) {
 459         return NULL;
 460     }
 461     return oc;
 462 }
 463
 464 /* CPU models. These are not needed for the AArch64 linux-user build. */
 465 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 466
 467 static void arm920t_initfn(Object *obj)
 468 {
 469     ARMCPU *cpu = ARM_CPU(obj);
 470     /* TODO: check features. */
 471     set_feature(&cpu->env, ARM_FEATURE_V4T);
 472     cpu->midr = 0x41129200;
 473     cpu->ctr = 0x0d172172;
 474     cpu->reset_sctlr = 0x00000078;
 475 }
 476
 477 static void arm926_initfn(Object *obj)
 478 {
 479     ARMCPU *cpu = ARM_CPU(obj);
 480
 481     cpu->dtb_compatible = "arm,arm926";
 482     set_feature(&cpu->env, ARM_FEATURE_V5);
 483     set_feature(&cpu->env, ARM_FEATURE_VFP);
 484     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 485     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 486     cpu->midr = 0x41069265;
 487     cpu->reset_fpsid = 0x41011090;
 488     cpu->ctr = 0x1dd20d2;
 489     cpu->reset_sctlr = 0x00090078;
 490 }
 491
 492 static void arm946_initfn(Object *obj)
 493 {
 494     ARMCPU *cpu = ARM_CPU(obj);
 495
 496     cpu->dtb_compatible = "arm,arm946";
 497     set_feature(&cpu->env, ARM_FEATURE_V5);
 498     set_feature(&cpu->env, ARM_FEATURE_MPU);
 499     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 500     cpu->midr = 0x41059461;
 501     cpu->ctr = 0x0f004006;
 502     cpu->reset_sctlr = 0x00000078;
 503 }
 504
 505 static void arm1026_initfn(Object *obj)
 506 {
 507     ARMCPU *cpu = ARM_CPU(obj);
 508
 509     cpu->dtb_compatible = "arm,arm1026";
 510     set_feature(&cpu->env, ARM_FEATURE_V5);
 511     set_feature(&cpu->env, ARM_FEATURE_VFP);
 512     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 513     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 514     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 515     cpu->midr = 0x4106a262;
 516     cpu->reset_fpsid = 0x410110a0;
 517     cpu->ctr = 0x1dd20d2;
 518     cpu->reset_sctlr = 0x00090078;
 519     cpu->reset_auxcr = 1;
 520     {
 521         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 522         ARMCPRegInfo ifar = {
 523             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 524             .access = PL1_RW,
 525             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 526             .resetvalue = 0
 527         };
 528         define_one_arm_cp_reg(cpu, &ifar);
 529     }
 530 }
 531
 532 static void arm1136_r2_initfn(Object *obj)
 533 {
 534     ARMCPU *cpu = ARM_CPU(obj);
 535     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 536      * older core than plain "arm1136". In particular this does not
 537      * have the v6K features.
 538      * These ID register values are correct for 1136 but may be wrong
 539      * for 1136_r2 (in particular r0p2 does not actually implement most
 540      * of the ID registers).
 541      */
 542
 543     cpu->dtb_compatible = "arm,arm1136";
 544     set_feature(&cpu->env, ARM_FEATURE_V6);
 545     set_feature(&cpu->env, ARM_FEATURE_VFP);
 546     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 547     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 548     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 549     cpu->midr = 0x4107b362;
 550     cpu->reset_fpsid = 0x410120b4;
 551     cpu->mvfr0 = 0x11111111;
 552     cpu->mvfr1 = 0x00000000;
 553     cpu->ctr = 0x1dd20d2;
 554     cpu->reset_sctlr = 0x00050078;
 555     cpu->id_pfr0 = 0x111;
 556     cpu->id_pfr1 = 0x1;
 557     cpu->id_dfr0 = 0x2;
 558     cpu->id_afr0 = 0x3;
 559     cpu->id_mmfr0 = 0x01130003;
 560     cpu->id_mmfr1 = 0x10030302;
 561     cpu->id_mmfr2 = 0x01222110;
 562     cpu->id_isar0 = 0x00140011;
 563     cpu->id_isar1 = 0x12002111;
 564     cpu->id_isar2 = 0x11231111;
 565     cpu->id_isar3 = 0x01102131;
 566     cpu->id_isar4 = 0x141;
 567     cpu->reset_auxcr = 7;
 568 }
 569
 570 static void arm1136_initfn(Object *obj)
 571 {
 572     ARMCPU *cpu = ARM_CPU(obj);
 573
 574     cpu->dtb_compatible = "arm,arm1136";
 575     set_feature(&cpu->env, ARM_FEATURE_V6K);
 576     set_feature(&cpu->env, ARM_FEATURE_V6);
 577     set_feature(&cpu->env, ARM_FEATURE_VFP);
 578     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 579     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 580     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 581     cpu->midr = 0x4117b363;
 582     cpu->reset_fpsid = 0x410120b4;
 583     cpu->mvfr0 = 0x11111111;
 584     cpu->mvfr1 = 0x00000000;
 585     cpu->ctr = 0x1dd20d2;
 586     cpu->reset_sctlr = 0x00050078;
 587     cpu->id_pfr0 = 0x111;
 588     cpu->id_pfr1 = 0x1;
 589     cpu->id_dfr0 = 0x2;
 590     cpu->id_afr0 = 0x3;
 591     cpu->id_mmfr0 = 0x01130003;
 592     cpu->id_mmfr1 = 0x10030302;
 593     cpu->id_mmfr2 = 0x01222110;
 594     cpu->id_isar0 = 0x00140011;
 595     cpu->id_isar1 = 0x12002111;
 596     cpu->id_isar2 = 0x11231111;
 597     cpu->id_isar3 = 0x01102131;
 598     cpu->id_isar4 = 0x141;
 599     cpu->reset_auxcr = 7;
 600 }
 601
 602 static void arm1176_initfn(Object *obj)
 603 {
 604     ARMCPU *cpu = ARM_CPU(obj);
 605
 606     cpu->dtb_compatible = "arm,arm1176";
 607     set_feature(&cpu->env, ARM_FEATURE_V6K);
 608     set_feature(&cpu->env, ARM_FEATURE_VFP);
 609     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 610     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 611     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 612     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 613     set_feature(&cpu->env, ARM_FEATURE_V6_VECBASE);
 614     cpu->midr = 0x410fb767;
 615     cpu->reset_fpsid = 0x410120b5;
 616     cpu->mvfr0 = 0x11111111;
 617     cpu->mvfr1 = 0x00000000;
 618     cpu->ctr = 0x1dd20d2;
 619     cpu->reset_sctlr = 0x00050078;
 620     cpu->id_pfr0 = 0x111;
 621     cpu->id_pfr1 = 0x11;
 622     cpu->id_dfr0 = 0x33;
 623     cpu->id_afr0 = 0;
 624     cpu->id_mmfr0 = 0x01130003;
 625     cpu->id_mmfr1 = 0x10030302;
 626     cpu->id_mmfr2 = 0x01222100;
 627     cpu->id_isar0 = 0x0140011;
 628     cpu->id_isar1 = 0x12002111;
 629     cpu->id_isar2 = 0x11231121;
 630     cpu->id_isar3 = 0x01102131;
 631     cpu->id_isar4 = 0x01141;
 632     cpu->reset_auxcr = 7;
 633 }
 634
 635 static void arm11mpcore_initfn(Object *obj)
 636 {
 637     ARMCPU *cpu = ARM_CPU(obj);
 638
 639     cpu->dtb_compatible = "arm,arm11mpcore";
 640     set_feature(&cpu->env, ARM_FEATURE_V6K);
 641     set_feature(&cpu->env, ARM_FEATURE_VFP);
 642     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 643     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 644     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 645     cpu->midr = 0x410fb022;
 646     cpu->reset_fpsid = 0x410120b4;
 647     cpu->mvfr0 = 0x11111111;
 648     cpu->mvfr1 = 0x00000000;
 649     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 650     cpu->id_pfr0 = 0x111;
 651     cpu->id_pfr1 = 0x1;
 652     cpu->id_dfr0 = 0;
 653     cpu->id_afr0 = 0x2;
 654     cpu->id_mmfr0 = 0x01100103;
 655     cpu->id_mmfr1 = 0x10020302;
 656     cpu->id_mmfr2 = 0x01222000;
 657     cpu->id_isar0 = 0x00100011;
 658     cpu->id_isar1 = 0x12002111;
 659     cpu->id_isar2 = 0x11221011;
 660     cpu->id_isar3 = 0x01102131;
 661     cpu->id_isar4 = 0x141;
 662     cpu->reset_auxcr = 1;
 663 }
 664
 665 static void cortex_m3_initfn(Object *obj)
 666 {
 667     ARMCPU *cpu = ARM_CPU(obj);
 668     set_feature(&cpu->env, ARM_FEATURE_V7);
 669     set_feature(&cpu->env, ARM_FEATURE_M);
 670     cpu->midr = 0x410fc231;
 671 }
 672
 673 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 674 {
 675 #ifndef CONFIG_USER_ONLY
 676     CPUClass *cc = CPU_CLASS(oc);
 677
 678     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 679 #endif
 680 }
 681
 682 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 683     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 684       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 685     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 686       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 687     REGINFO_SENTINEL
 688 };
 689
 690 static void cortex_a8_initfn(Object *obj)
 691 {
 692     ARMCPU *cpu = ARM_CPU(obj);
 693
 694     cpu->dtb_compatible = "arm,cortex-a8";
 695     set_feature(&cpu->env, ARM_FEATURE_V7);
 696     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 697     set_feature(&cpu->env, ARM_FEATURE_NEON);
 698     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 699     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 700     cpu->midr = 0x410fc080;
 701     cpu->reset_fpsid = 0x410330c0;
 702     cpu->mvfr0 = 0x11110222;
 703     cpu->mvfr1 = 0x00011100;
 704     cpu->ctr = 0x82048004;
 705     cpu->reset_sctlr = 0x00c50078;
 706     cpu->id_pfr0 = 0x1031;
 707     cpu->id_pfr1 = 0x11;
 708     cpu->id_dfr0 = 0x400;
 709     cpu->id_afr0 = 0;
 710     cpu->id_mmfr0 = 0x31100003;
 711     cpu->id_mmfr1 = 0x20000000;
 712     cpu->id_mmfr2 = 0x01202000;
 713     cpu->id_mmfr3 = 0x11;
 714     cpu->id_isar0 = 0x00101111;
 715     cpu->id_isar1 = 0x12112111;
 716     cpu->id_isar2 = 0x21232031;
 717     cpu->id_isar3 = 0x11112131;
 718     cpu->id_isar4 = 0x00111142;
 719     cpu->dbgdidr = 0x15141000;
 720     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 721     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 722     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 723     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 724     cpu->reset_auxcr = 2;
 725     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 726 }
 727
 728 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 729     /* power_control should be set to maximum latency. Again,
 730      * default to 0 and set by private hook
 731      */
 732     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 733       .access = PL1_RW, .resetvalue = 0,
 734       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 735     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 736       .access = PL1_RW, .resetvalue = 0,
 737       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 738     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 739       .access = PL1_RW, .resetvalue = 0,
 740       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 741     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 742       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 743     /* TLB lockdown control */
 744     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 745       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 746     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 747       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 748     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 749       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 750     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 751       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 752     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 753       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 754     REGINFO_SENTINEL
 755 };
 756
 757 static void cortex_a9_initfn(Object *obj)
 758 {
 759     ARMCPU *cpu = ARM_CPU(obj);
 760
 761     cpu->dtb_compatible = "arm,cortex-a9";
 762     set_feature(&cpu->env, ARM_FEATURE_V7);
 763     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 764     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 765     set_feature(&cpu->env, ARM_FEATURE_NEON);
 766     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 767     /* Note that A9 supports the MP extensions even for
 768      * A9UP and single-core A9MP (which are both different
 769      * and valid configurations; we don't model A9UP).
 770      */
 771     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 772     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 773     cpu->midr = 0x410fc090;
 774     cpu->reset_fpsid = 0x41033090;
 775     cpu->mvfr0 = 0x11110222;
 776     cpu->mvfr1 = 0x01111111;
 777     cpu->ctr = 0x80038003;
 778     cpu->reset_sctlr = 0x00c50078;
 779     cpu->id_pfr0 = 0x1031;
 780     cpu->id_pfr1 = 0x11;
 781     cpu->id_dfr0 = 0x000;
 782     cpu->id_afr0 = 0;
 783     cpu->id_mmfr0 = 0x00100103;
 784     cpu->id_mmfr1 = 0x20000000;
 785     cpu->id_mmfr2 = 0x01230000;
 786     cpu->id_mmfr3 = 0x00002111;
 787     cpu->id_isar0 = 0x00101111;
 788     cpu->id_isar1 = 0x13112111;
 789     cpu->id_isar2 = 0x21232041;
 790     cpu->id_isar3 = 0x11112131;
 791     cpu->id_isar4 = 0x00111142;
 792     cpu->dbgdidr = 0x35141000;
 793     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 794     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 795     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 796     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 797 }
 798
 799 #ifndef CONFIG_USER_ONLY
 800 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 801 {
 802     /* Linux wants the number of processors from here.
 803      * Might as well set the interrupt-controller bit too.
 804      */
 805     return ((smp_cpus - 1) << 24) | (1 << 23);
 806 }
 807 #endif
 808
 809 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 810 #ifndef CONFIG_USER_ONLY
 811     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 812       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 813       .writefn = arm_cp_write_ignore, },
 814 #endif
 815     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 816       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 817     REGINFO_SENTINEL
 818 };
 819
 820 static void cortex_a15_initfn(Object *obj)
 821 {
 822     ARMCPU *cpu = ARM_CPU(obj);
 823
 824     cpu->dtb_compatible = "arm,cortex-a15";
 825     set_feature(&cpu->env, ARM_FEATURE_V7);
 826     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 827     set_feature(&cpu->env, ARM_FEATURE_NEON);
 828     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 829     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 830     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 831     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 832     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 833     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 834     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 835     cpu->midr = 0x412fc0f1;
 836     cpu->reset_fpsid = 0x410430f0;
 837     cpu->mvfr0 = 0x10110222;
 838     cpu->mvfr1 = 0x11111111;
 839     cpu->ctr = 0x8444c004;
 840     cpu->reset_sctlr = 0x00c50078;
 841     cpu->id_pfr0 = 0x00001131;
 842     cpu->id_pfr1 = 0x00011011;
 843     cpu->id_dfr0 = 0x02010555;
 844     cpu->id_afr0 = 0x00000000;
 845     cpu->id_mmfr0 = 0x10201105;
 846     cpu->id_mmfr1 = 0x20000000;
 847     cpu->id_mmfr2 = 0x01240000;
 848     cpu->id_mmfr3 = 0x02102211;
 849     cpu->id_isar0 = 0x02101110;
 850     cpu->id_isar1 = 0x13112111;
 851     cpu->id_isar2 = 0x21232041;
 852     cpu->id_isar3 = 0x11112131;
 853     cpu->id_isar4 = 0x10011142;
 854     cpu->dbgdidr = 0x3515f021;
 855     cpu->clidr = 0x0a200023;
 856     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 857     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 858     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 859     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 860 }
 861
 862 static void ti925t_initfn(Object *obj)
 863 {
 864     ARMCPU *cpu = ARM_CPU(obj);
 865     set_feature(&cpu->env, ARM_FEATURE_V4T);
 866     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 867     cpu->midr = ARM_CPUID_TI925T;
 868     cpu->ctr = 0x5109149;
 869     cpu->reset_sctlr = 0x00000070;
 870 }
 871
 872 static void sa1100_initfn(Object *obj)
 873 {
 874     ARMCPU *cpu = ARM_CPU(obj);
 875
 876     cpu->dtb_compatible = "intel,sa1100";
 877     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 878     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 879     cpu->midr = 0x4401A11B;
 880     cpu->reset_sctlr = 0x00000070;
 881 }
 882
 883 static void sa1110_initfn(Object *obj)
 884 {
 885     ARMCPU *cpu = ARM_CPU(obj);
 886     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 887     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 888     cpu->midr = 0x6901B119;
 889     cpu->reset_sctlr = 0x00000070;
 890 }
 891
 892 static void pxa250_initfn(Object *obj)
 893 {
 894     ARMCPU *cpu = ARM_CPU(obj);
 895
 896     cpu->dtb_compatible = "marvell,xscale";
 897     set_feature(&cpu->env, ARM_FEATURE_V5);
 898     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 899     cpu->midr = 0x69052100;
 900     cpu->ctr = 0xd172172;
 901     cpu->reset_sctlr = 0x00000078;
 902 }
 903
 904 static void pxa255_initfn(Object *obj)
 905 {
 906     ARMCPU *cpu = ARM_CPU(obj);
 907
 908     cpu->dtb_compatible = "marvell,xscale";
 909     set_feature(&cpu->env, ARM_FEATURE_V5);
 910     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 911     cpu->midr = 0x69052d00;
 912     cpu->ctr = 0xd172172;
 913     cpu->reset_sctlr = 0x00000078;
 914 }
 915
 916 static void pxa260_initfn(Object *obj)
 917 {
 918     ARMCPU *cpu = ARM_CPU(obj);
 919
 920     cpu->dtb_compatible = "marvell,xscale";
 921     set_feature(&cpu->env, ARM_FEATURE_V5);
 922     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 923     cpu->midr = 0x69052903;
 924     cpu->ctr = 0xd172172;
 925     cpu->reset_sctlr = 0x00000078;
 926 }
 927
 928 static void pxa261_initfn(Object *obj)
 929 {
 930     ARMCPU *cpu = ARM_CPU(obj);
 931
 932     cpu->dtb_compatible = "marvell,xscale";
 933     set_feature(&cpu->env, ARM_FEATURE_V5);
 934     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 935     cpu->midr = 0x69052d05;
 936     cpu->ctr = 0xd172172;
 937     cpu->reset_sctlr = 0x00000078;
 938 }
 939
 940 static void pxa262_initfn(Object *obj)
 941 {
 942     ARMCPU *cpu = ARM_CPU(obj);
 943
 944     cpu->dtb_compatible = "marvell,xscale";
 945     set_feature(&cpu->env, ARM_FEATURE_V5);
 946     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 947     cpu->midr = 0x69052d06;
 948     cpu->ctr = 0xd172172;
 949     cpu->reset_sctlr = 0x00000078;
 950 }
 951
 952 static void pxa270a0_initfn(Object *obj)
 953 {
 954     ARMCPU *cpu = ARM_CPU(obj);
 955
 956     cpu->dtb_compatible = "marvell,xscale";
 957     set_feature(&cpu->env, ARM_FEATURE_V5);
 958     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 959     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 960     cpu->midr = 0x69054110;
 961     cpu->ctr = 0xd172172;
 962     cpu->reset_sctlr = 0x00000078;
 963 }
 964
 965 static void pxa270a1_initfn(Object *obj)
 966 {
 967     ARMCPU *cpu = ARM_CPU(obj);
 968
 969     cpu->dtb_compatible = "marvell,xscale";
 970     set_feature(&cpu->env, ARM_FEATURE_V5);
 971     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 972     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 973     cpu->midr = 0x69054111;
 974     cpu->ctr = 0xd172172;
 975     cpu->reset_sctlr = 0x00000078;
 976 }
 977
 978 static void pxa270b0_initfn(Object *obj)
 979 {
 980     ARMCPU *cpu = ARM_CPU(obj);
 981
 982     cpu->dtb_compatible = "marvell,xscale";
 983     set_feature(&cpu->env, ARM_FEATURE_V5);
 984     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 985     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 986     cpu->midr = 0x69054112;
 987     cpu->ctr = 0xd172172;
 988     cpu->reset_sctlr = 0x00000078;
 989 }
 990
 991 static void pxa270b1_initfn(Object *obj)
 992 {
 993     ARMCPU *cpu = ARM_CPU(obj);
 994
 995     cpu->dtb_compatible = "marvell,xscale";
 996     set_feature(&cpu->env, ARM_FEATURE_V5);
 997     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 998     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 999     cpu->midr = 0x69054113;
1000     cpu->ctr = 0xd172172;
1001     cpu->reset_sctlr = 0x00000078;
1002 }
1003
1004 static void pxa270c0_initfn(Object *obj)
1005 {
1006     ARMCPU *cpu = ARM_CPU(obj);
1007
1008     cpu->dtb_compatible = "marvell,xscale";
1009     set_feature(&cpu->env, ARM_FEATURE_V5);
1010     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1011     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1012     cpu->midr = 0x69054114;
1013     cpu->ctr = 0xd172172;
1014     cpu->reset_sctlr = 0x00000078;
1015 }
1016
1017 static void pxa270c5_initfn(Object *obj)
1018 {
1019     ARMCPU *cpu = ARM_CPU(obj);
1020
1021     cpu->dtb_compatible = "marvell,xscale";
1022     set_feature(&cpu->env, ARM_FEATURE_V5);
1023     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1024     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1025     cpu->midr = 0x69054117;
1026     cpu->ctr = 0xd172172;
1027     cpu->reset_sctlr = 0x00000078;
1028 }
1029
1030 #ifdef CONFIG_USER_ONLY
1031 static void arm_any_initfn(Object *obj)
1032 {
1033     ARMCPU *cpu = ARM_CPU(obj);
1034     set_feature(&cpu->env, ARM_FEATURE_V8);
1035     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1036     set_feature(&cpu->env, ARM_FEATURE_NEON);
1037     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1038     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1039     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1040     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1041     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1042     set_feature(&cpu->env, ARM_FEATURE_CRC);
1043     cpu->midr = 0xffffffff;
1044 }
1045 #endif
1046
1047 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1048
1049 typedef struct ARMCPUInfo {
1050     const char *name;
1051     void (*initfn)(Object *obj);
1052     void (*class_init)(ObjectClass *oc, void *data);
1053 } ARMCPUInfo;
1054
1055 static const ARMCPUInfo arm_cpus[] = {
1056 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1057     { .name = "arm920t",     .initfn = arm920t_initfn },
1058     { .name = "arm926",      .initfn = arm926_initfn },
1059     { .name = "arm946",      .initfn = arm946_initfn },
1060     { .name = "arm1026",     .initfn = arm1026_initfn },
1061     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1062      * older core than plain "arm1136". In particular this does not
1063      * have the v6K features.
1064      */
1065     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1066     { .name = "arm1136",     .initfn = arm1136_initfn },
1067     { .name = "arm1176",     .initfn = arm1176_initfn },
1068     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1069     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1070                              .class_init = arm_v7m_class_init },
1071     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1072     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1073     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1074     { .name = "ti925t",      .initfn = ti925t_initfn },
1075     { .name = "sa1100",      .initfn = sa1100_initfn },
1076     { .name = "sa1110",      .initfn = sa1110_initfn },
1077     { .name = "pxa250",      .initfn = pxa250_initfn },
1078     { .name = "pxa255",      .initfn = pxa255_initfn },
1079     { .name = "pxa260",      .initfn = pxa260_initfn },
1080     { .name = "pxa261",      .initfn = pxa261_initfn },
1081     { .name = "pxa262",      .initfn = pxa262_initfn },
1082     /* "pxa270" is an alias for "pxa270-a0" */
1083     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1084     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1085     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1086     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1087     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1088     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1089     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1090 #ifdef CONFIG_USER_ONLY
1091     { .name = "any",         .initfn = arm_any_initfn },
1092 #endif
1093 #endif
1094     { .name = NULL }
1095 };
1096
1097 static Property arm_cpu_properties[] = {
1098     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1099     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1100     DEFINE_PROP_END_OF_LIST()
1101 };
1102
1103 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1104 {
1105     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1106     CPUClass *cc = CPU_CLASS(acc);
1107     DeviceClass *dc = DEVICE_CLASS(oc);
1108
1109     acc->parent_realize = dc->realize;
1110     dc->realize = arm_cpu_realizefn;
1111     dc->props = arm_cpu_properties;
1112
1113     acc->parent_reset = cc->reset;
1114     cc->reset = arm_cpu_reset;
1115
1116     cc->class_by_name = arm_cpu_class_by_name;
1117     cc->has_work = arm_cpu_has_work;
1118     cc->do_interrupt = arm_cpu_do_interrupt;
1119     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1120     cc->dump_state = arm_cpu_dump_state;
1121     cc->set_pc = arm_cpu_set_pc;
1122     cc->gdb_read_register = arm_cpu_gdb_read_register;
1123     cc->gdb_write_register = arm_cpu_gdb_write_register;
1124 #ifdef CONFIG_USER_ONLY
1125     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1126 #else
1127     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1128     cc->vmsd = &vmstate_arm_cpu;
1129 #endif
1130     cc->gdb_num_core_regs = 26;
1131     cc->gdb_core_xml_file = "arm-core.xml";
1132     cc->debug_excp_handler = arm_debug_excp_handler;
1133 }
1134
1135 static void cpu_register(const ARMCPUInfo *info)
1136 {
1137     TypeInfo type_info = {
1138         .parent = TYPE_ARM_CPU,
1139         .instance_size = sizeof(ARMCPU),
1140         .instance_init = info->initfn,
1141         .class_size = sizeof(ARMCPUClass),
1142         .class_init = info->class_init,
1143     };
1144
1145     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1146     type_register(&type_info);
1147     g_free((void *)type_info.name);
1148 }
1149
1150 static const TypeInfo arm_cpu_type_info = {
1151     .name = TYPE_ARM_CPU,
1152     .parent = TYPE_CPU,
1153     .instance_size = sizeof(ARMCPU),
1154     .instance_init = arm_cpu_initfn,
1155     .instance_post_init = arm_cpu_post_init,
1156     .instance_finalize = arm_cpu_finalizefn,
1157     .abstract = true,
1158     .class_size = sizeof(ARMCPUClass),
1159     .class_init = arm_cpu_class_init,
1160 };
1161
1162 static void arm_cpu_register_types(void)
1163 {
1164     const ARMCPUInfo *info = arm_cpus;
1165
1166     type_register_static(&arm_cpu_type_info);
1167
1168     while (info->name) {
1169         cpu_register(info);
1170         info++;
1171     }
1172 }
1173
1174 type_init(arm_cpu_register_types)