?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/arm/virt-acpi-build: use SMC if booting in EL2
[qemu/ar7.git] / hw / arm / virt-acpi-build.c
blob73aca9eac507c3e0e978dca9a8670fbbf47cb26d
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu-common.h"
32 #include "qemu/bitmap.h"
33 #include "trace.h"
34 #include "qom/cpu.h"
35 #include "target/arm/cpu.h"
36 #include "hw/acpi/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/hw.h"
42 #include "hw/acpi/aml-build.h"
43 #include "hw/pci/pcie_host.h"
44 #include "hw/pci/pci.h"
45 #include "hw/arm/virt.h"
46 #include "sysemu/numa.h"
47 #include "kvm_arm.h"
48
49 #define ARM_SPI_BASE 32
50 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
51
52 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
53 {
54 uint16_t i;
55
56 for (i = 0; i < smp_cpus; i++) {
57 Aml *dev = aml_device("C%.03X", i);
58 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
59 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
60 aml_append(scope, dev);
61 }
62 }
63
64 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
65 uint32_t uart_irq)
66 {
67 Aml *dev = aml_device("COM0");
68 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
69 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
70
71 Aml *crs = aml_resource_template();
72 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
73 uart_memmap->size, AML_READ_WRITE));
74 aml_append(crs,
75 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
76 AML_EXCLUSIVE, &uart_irq, 1));
77 aml_append(dev, aml_name_decl("_CRS", crs));
78
79 /* The _ADR entry is used to link this device to the UART described
80 * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
81 */
82 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
83
84 aml_append(scope, dev);
85 }
86
87 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
88 {
89 Aml *dev = aml_device("FWCF");
90 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
91 /* device present, functioning, decoding, not shown in UI */
92 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
93
94 Aml *crs = aml_resource_template();
95 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
96 fw_cfg_memmap->size, AML_READ_WRITE));
97 aml_append(dev, aml_name_decl("_CRS", crs));
98 aml_append(scope, dev);
99 }
100
101 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
102 {
103 Aml *dev, *crs;
104 hwaddr base = flash_memmap->base;
105 hwaddr size = flash_memmap->size / 2;
106
107 dev = aml_device("FLS0");
108 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
109 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
110
111 crs = aml_resource_template();
112 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
113 aml_append(dev, aml_name_decl("_CRS", crs));
114 aml_append(scope, dev);
115
116 dev = aml_device("FLS1");
117 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
118 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
119 crs = aml_resource_template();
120 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
121 aml_append(dev, aml_name_decl("_CRS", crs));
122 aml_append(scope, dev);
123 }
124
125 static void acpi_dsdt_add_virtio(Aml *scope,
126 const MemMapEntry *virtio_mmio_memmap,
127 uint32_t mmio_irq, int num)
128 {
129 hwaddr base = virtio_mmio_memmap->base;
130 hwaddr size = virtio_mmio_memmap->size;
131 int i;
132
133 for (i = 0; i < num; i++) {
134 uint32_t irq = mmio_irq + i;
135 Aml *dev = aml_device("VR%02u", i);
136 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
137 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
138
139 Aml *crs = aml_resource_template();
140 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
141 aml_append(crs,
142 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
143 AML_EXCLUSIVE, &irq, 1));
144 aml_append(dev, aml_name_decl("_CRS", crs));
145 aml_append(scope, dev);
146 base += size;
147 }
148 }
149
150 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
151 uint32_t irq, bool use_highmem)
152 {
153 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
154 int i, bus_no;
155 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
156 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
157 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
158 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
159 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
160 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
161 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
162
163 Aml *dev = aml_device("%s", "PCI0");
164 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
165 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
166 aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
167 aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
168 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
169 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
170 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
171 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
172
173 /* Declare the PCI Routing Table. */
174 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
175 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
176 for (i = 0; i < PCI_NUM_PINS; i++) {
177 int gsi = (i + bus_no) % PCI_NUM_PINS;
178 Aml *pkg = aml_package(4);
179 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
180 aml_append(pkg, aml_int(i));
181 aml_append(pkg, aml_name("GSI%d", gsi));
182 aml_append(pkg, aml_int(0));
183 aml_append(rt_pkg, pkg);
184 }
185 }
186 aml_append(dev, aml_name_decl("_PRT", rt_pkg));
187
188 /* Create GSI link device */
189 for (i = 0; i < PCI_NUM_PINS; i++) {
190 uint32_t irqs = irq + i;
191 Aml *dev_gsi = aml_device("GSI%d", i);
192 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
193 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
194 crs = aml_resource_template();
195 aml_append(crs,
196 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
197 AML_EXCLUSIVE, &irqs, 1));
198 aml_append(dev_gsi, aml_name_decl("_PRS", crs));
199 crs = aml_resource_template();
200 aml_append(crs,
201 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
202 AML_EXCLUSIVE, &irqs, 1));
203 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
204 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
205 aml_append(dev_gsi, method);
206 aml_append(dev, dev_gsi);
207 }
208
209 method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
210 aml_append(method, aml_return(aml_int(base_ecam)));
211 aml_append(dev, method);
212
213 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
214 Aml *rbuf = aml_resource_template();
215 aml_append(rbuf,
216 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
217 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
218 nr_pcie_buses));
219 aml_append(rbuf,
220 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
221 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
222 base_mmio + size_mmio - 1, 0x0000, size_mmio));
223 aml_append(rbuf,
224 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
225 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
226 size_pio));
227
228 if (use_highmem) {
229 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
230 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
231
232 aml_append(rbuf,
233 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
234 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
235 base_mmio_high,
236 base_mmio_high + size_mmio_high - 1, 0x0000,
237 size_mmio_high));
238 }
239
240 aml_append(method, aml_name_decl("RBUF", rbuf));
241 aml_append(method, aml_return(rbuf));
242 aml_append(dev, method);
243
244 /* Declare an _OSC (OS Control Handoff) method */
245 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
246 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
247 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
248 aml_append(method,
249 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
250
251 /* PCI Firmware Specification 3.0
252 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
253 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
254 * identified by the Universal Unique IDentifier (UUID)
255 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
256 */
257 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
258 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
259 aml_append(ifctx,
260 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
261 aml_append(ifctx,
262 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
263 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
264 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
265 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
266 aml_name("CTRL")));
267
268 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
269 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
270 aml_name("CDW1")));
271 aml_append(ifctx, ifctx1);
272
273 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
274 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
275 aml_name("CDW1")));
276 aml_append(ifctx, ifctx1);
277
278 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
279 aml_append(ifctx, aml_return(aml_arg(3)));
280 aml_append(method, ifctx);
281
282 elsectx = aml_else();
283 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
284 aml_name("CDW1")));
285 aml_append(elsectx, aml_return(aml_arg(3)));
286 aml_append(method, elsectx);
287 aml_append(dev, method);
288
289 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
290
291 /* PCI Firmware Specification 3.0
292 * 4.6.1. _DSM for PCI Express Slot Information
293 * The UUID in _DSM in this context is
294 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
295 */
296 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
297 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
298 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
299 uint8_t byte_list[1] = {1};
300 buf = aml_buffer(1, byte_list);
301 aml_append(ifctx1, aml_return(buf));
302 aml_append(ifctx, ifctx1);
303 aml_append(method, ifctx);
304
305 byte_list[0] = 0;
306 buf = aml_buffer(1, byte_list);
307 aml_append(method, aml_return(buf));
308 aml_append(dev, method);
309
310 Aml *dev_rp0 = aml_device("%s", "RP0");
311 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
312 aml_append(dev, dev_rp0);
313
314 Aml *dev_res0 = aml_device("%s", "RES0");
315 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
316 crs = aml_resource_template();
317 aml_append(crs, aml_memory32_fixed(base_ecam, size_ecam, AML_READ_WRITE));
318 aml_append(dev_res0, aml_name_decl("_CRS", crs));
319 aml_append(dev, dev_res0);
320 aml_append(scope, dev);
321 }
322
323 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
324 uint32_t gpio_irq)
325 {
326 Aml *dev = aml_device("GPO0");
327 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
328 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
329 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
330
331 Aml *crs = aml_resource_template();
332 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
333 AML_READ_WRITE));
334 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
335 AML_EXCLUSIVE, &gpio_irq, 1));
336 aml_append(dev, aml_name_decl("_CRS", crs));
337
338 Aml *aei = aml_resource_template();
339 /* Pin 3 for power button */
340 const uint32_t pin_list[1] = {3};
341 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
342 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
343 "GPO0", NULL, 0));
344 aml_append(dev, aml_name_decl("_AEI", aei));
345
346 /* _E03 is handle for power button */
347 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
348 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
349 aml_int(0x80)));
350 aml_append(dev, method);
351 aml_append(scope, dev);
352 }
353
354 static void acpi_dsdt_add_power_button(Aml *scope)
355 {
356 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
357 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
358 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
359 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
360 aml_append(scope, dev);
361 }
362
363 /* RSDP */
364 static GArray *
365 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
366 {
367 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
368 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
369 unsigned rsdt_pa_offset =
370 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
371
372 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
373 true /* fseg memory */);
374
375 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
376 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
377 rsdp->length = cpu_to_le32(sizeof(*rsdp));
378 rsdp->revision = 0x02;
379
380 /* Address to be filled by Guest linker */
381 bios_linker_loader_add_pointer(linker,
382 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
383 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
384
385 /* Checksum to be filled by Guest linker */
386 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
387 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
388 (char *)&rsdp->checksum - rsdp_table->data);
389
390 return rsdp_table;
391 }
392
393 static void
394 build_iort(GArray *table_data, BIOSLinker *linker)
395 {
396 int iort_start = table_data->len;
397 AcpiIortIdMapping *idmap;
398 AcpiIortItsGroup *its;
399 AcpiIortTable *iort;
400 size_t node_size, iort_length;
401 AcpiIortRC *rc;
402
403 iort = acpi_data_push(table_data, sizeof(*iort));
404
405 iort_length = sizeof(*iort);
406 iort->node_count = cpu_to_le32(2); /* RC and ITS nodes */
407 iort->node_offset = cpu_to_le32(sizeof(*iort));
408
409 /* ITS group node */
410 node_size = sizeof(*its) + sizeof(uint32_t);
411 iort_length += node_size;
412 its = acpi_data_push(table_data, node_size);
413
414 its->type = ACPI_IORT_NODE_ITS_GROUP;
415 its->length = cpu_to_le16(node_size);
416 its->its_count = cpu_to_le32(1);
417 its->identifiers[0] = 0; /* MADT translation_id */
418
419 /* Root Complex Node */
420 node_size = sizeof(*rc) + sizeof(*idmap);
421 iort_length += node_size;
422 rc = acpi_data_push(table_data, node_size);
423
424 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
425 rc->length = cpu_to_le16(node_size);
426 rc->mapping_count = cpu_to_le32(1);
427 rc->mapping_offset = cpu_to_le32(sizeof(*rc));
428
429 /* fully coherent device */
430 rc->memory_properties.cache_coherency = cpu_to_le32(1);
431 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
432 rc->pci_segment_number = 0; /* MCFG pci_segment */
433
434 /* Identity RID mapping covering the whole input RID range */
435 idmap = &rc->id_mapping_array[0];
436 idmap->input_base = 0;
437 idmap->id_count = cpu_to_le32(0xFFFF);
438 idmap->output_base = 0;
439 /* output IORT node is the ITS group node (the first node) */
440 idmap->output_reference = cpu_to_le32(iort->node_offset);
441
442 iort->length = cpu_to_le32(iort_length);
443
444 build_header(linker, table_data, (void *)(table_data->data + iort_start),
445 "IORT", table_data->len - iort_start, 0, NULL, NULL);
446 }
447
448 static void
449 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
450 {
451 AcpiSerialPortConsoleRedirection *spcr;
452 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
453 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
454
455 spcr = acpi_data_push(table_data, sizeof(*spcr));
456
457 spcr->interface_type = 0x3; /* ARM PL011 UART */
458
459 spcr->base_address.space_id = AML_SYSTEM_MEMORY;
460 spcr->base_address.bit_width = 8;
461 spcr->base_address.bit_offset = 0;
462 spcr->base_address.access_width = 1;
463 spcr->base_address.address = cpu_to_le64(uart_memmap->base);
464
465 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
466 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
467
468 spcr->baud = 3; /* Baud Rate: 3 = 9600 */
469 spcr->parity = 0; /* No Parity */
470 spcr->stopbits = 1; /* 1 Stop bit */
471 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
472 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
473
474 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
475 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
476
477 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2,
478 NULL, NULL);
479 }
480
481 static void
482 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
483 {
484 AcpiSystemResourceAffinityTable *srat;
485 AcpiSratProcessorGiccAffinity *core;
486 AcpiSratMemoryAffinity *numamem;
487 int i, j, srat_start;
488 uint64_t mem_base;
489 uint32_t *cpu_node = g_malloc0(vms->smp_cpus * sizeof(uint32_t));
490
491 for (i = 0; i < vms->smp_cpus; i++) {
492 j = numa_get_node_for_cpu(i);
493 if (j < nb_numa_nodes) {
494 cpu_node[i] = j;
495 }
496 }
497
498 srat_start = table_data->len;
499 srat = acpi_data_push(table_data, sizeof(*srat));
500 srat->reserved1 = cpu_to_le32(1);
501
502 for (i = 0; i < vms->smp_cpus; ++i) {
503 core = acpi_data_push(table_data, sizeof(*core));
504 core->type = ACPI_SRAT_PROCESSOR_GICC;
505 core->length = sizeof(*core);
506 core->proximity = cpu_to_le32(cpu_node[i]);
507 core->acpi_processor_uid = cpu_to_le32(i);
508 core->flags = cpu_to_le32(1);
509 }
510 g_free(cpu_node);
511
512 mem_base = vms->memmap[VIRT_MEM].base;
513 for (i = 0; i < nb_numa_nodes; ++i) {
514 numamem = acpi_data_push(table_data, sizeof(*numamem));
515 build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
516 MEM_AFFINITY_ENABLED);
517 mem_base += numa_info[i].node_mem;
518 }
519
520 build_header(linker, table_data, (void *)srat, "SRAT",
521 table_data->len - srat_start, 3, NULL, NULL);
522 }
523
524 static void
525 build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
526 {
527 AcpiTableMcfg *mcfg;
528 const MemMapEntry *memmap = vms->memmap;
529 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
530
531 mcfg = acpi_data_push(table_data, len);
532 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
533
534 /* Only a single allocation so no need to play with segments */
535 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
536 mcfg->allocation[0].start_bus_number = 0;
537 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
538 / PCIE_MMCFG_SIZE_MIN) - 1;
539
540 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
541 }
542
543 /* GTDT */
544 static void
545 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
546 {
547 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
548 int gtdt_start = table_data->len;
549 AcpiGenericTimerTable *gtdt;
550 uint32_t irqflags;
551
552 if (vmc->claim_edge_triggered_timers) {
553 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
554 } else {
555 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
556 }
557
558 gtdt = acpi_data_push(table_data, sizeof *gtdt);
559 /* The interrupt values are the same with the device tree when adding 16 */
560 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
561 gtdt->secure_el1_flags = cpu_to_le32(irqflags);
562
563 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
564 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
565 ACPI_GTDT_CAP_ALWAYS_ON);
566
567 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
568 gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
569
570 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
571 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
572
573 build_header(linker, table_data,
574 (void *)(table_data->data + gtdt_start), "GTDT",
575 table_data->len - gtdt_start, 2, NULL, NULL);
576 }
577
578 /* MADT */
579 static void
580 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
581 {
582 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
583 int madt_start = table_data->len;
584 const MemMapEntry *memmap = vms->memmap;
585 const int *irqmap = vms->irqmap;
586 AcpiMultipleApicTable *madt;
587 AcpiMadtGenericDistributor *gicd;
588 AcpiMadtGenericMsiFrame *gic_msi;
589 int i;
590
591 madt = acpi_data_push(table_data, sizeof *madt);
592
593 gicd = acpi_data_push(table_data, sizeof *gicd);
594 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
595 gicd->length = sizeof(*gicd);
596 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
597 gicd->version = vms->gic_version;
598
599 for (i = 0; i < vms->smp_cpus; i++) {
600 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
601 sizeof(*gicc));
602 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
603
604 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
605 gicc->length = sizeof(*gicc);
606 if (vms->gic_version == 2) {
607 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
608 }
609 gicc->cpu_interface_number = cpu_to_le32(i);
610 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
611 gicc->uid = cpu_to_le32(i);
612 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
613
614 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
615 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
616 }
617 }
618
619 if (vms->gic_version == 3) {
620 AcpiMadtGenericTranslator *gic_its;
621 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
622 sizeof *gicr);
623
624 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
625 gicr->length = sizeof(*gicr);
626 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
627 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
628
629 if (its_class_name() && !vmc->no_its) {
630 gic_its = acpi_data_push(table_data, sizeof *gic_its);
631 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
632 gic_its->length = sizeof(*gic_its);
633 gic_its->translation_id = 0;
634 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
635 }
636 } else {
637 gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
638 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
639 gic_msi->length = sizeof(*gic_msi);
640 gic_msi->gic_msi_frame_id = 0;
641 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
642 gic_msi->flags = cpu_to_le32(1);
643 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
644 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
645 }
646
647 build_header(linker, table_data,
648 (void *)(table_data->data + madt_start), "APIC",
649 table_data->len - madt_start, 3, NULL, NULL);
650 }
651
652 /* FADT */
653 static void build_fadt(GArray *table_data, BIOSLinker *linker,
654 VirtMachineState *vms, unsigned dsdt_tbl_offset)
655 {
656 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
657 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
658 uint16_t bootflags;
659
660 switch (vms->psci_conduit) {
661 case QEMU_PSCI_CONDUIT_DISABLED:
662 bootflags = 0;
663 break;
664 case QEMU_PSCI_CONDUIT_HVC:
665 bootflags = ACPI_FADT_ARM_PSCI_COMPLIANT | ACPI_FADT_ARM_PSCI_USE_HVC;
666 break;
667 case QEMU_PSCI_CONDUIT_SMC:
668 bootflags = ACPI_FADT_ARM_PSCI_COMPLIANT;
669 break;
670 default:
671 g_assert_not_reached();
672 }
673
674 /* Hardware Reduced = 1 and use PSCI 0.2+ */
675 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
676 fadt->arm_boot_flags = cpu_to_le16(bootflags);
677
678 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
679 fadt->minor_revision = 0x1;
680
681 /* DSDT address to be filled by Guest linker */
682 bios_linker_loader_add_pointer(linker,
683 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
684 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
685
686 build_header(linker, table_data,
687 (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL);
688 }
689
690 /* DSDT */
691 static void
692 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
693 {
694 Aml *scope, *dsdt;
695 const MemMapEntry *memmap = vms->memmap;
696 const int *irqmap = vms->irqmap;
697
698 dsdt = init_aml_allocator();
699 /* Reserve space for header */
700 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
701
702 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
703 * While UEFI can use libfdt to disable the RTC device node in the DTB that
704 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
705 * the RTC ACPI device at all when using UEFI.
706 */
707 scope = aml_scope("\\_SB");
708 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
709 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
710 (irqmap[VIRT_UART] + ARM_SPI_BASE));
711 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
712 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
713 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
714 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
715 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
716 vms->highmem);
717 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
718 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
719 acpi_dsdt_add_power_button(scope);
720
721 aml_append(dsdt, scope);
722
723 /* copy AML table into ACPI tables blob and patch header there */
724 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
725 build_header(linker, table_data,
726 (void *)(table_data->data + table_data->len - dsdt->buf->len),
727 "DSDT", dsdt->buf->len, 2, NULL, NULL);
728 free_aml_allocator();
729 }
730
731 typedef
732 struct AcpiBuildState {
733 /* Copy of table in RAM (for patching). */
734 MemoryRegion *table_mr;
735 MemoryRegion *rsdp_mr;
736 MemoryRegion *linker_mr;
737 /* Is table patched? */
738 bool patched;
739 } AcpiBuildState;
740
741 static
742 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
743 {
744 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
745 GArray *table_offsets;
746 unsigned dsdt, rsdt;
747 GArray *tables_blob = tables->table_data;
748
749 table_offsets = g_array_new(false, true /* clear */,
750 sizeof(uint32_t));
751
752 bios_linker_loader_alloc(tables->linker,
753 ACPI_BUILD_TABLE_FILE, tables_blob,
754 64, false /* high memory */);
755
756 /* DSDT is pointed to by FADT */
757 dsdt = tables_blob->len;
758 build_dsdt(tables_blob, tables->linker, vms);
759
760 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
761 acpi_add_table(table_offsets, tables_blob);
762 build_fadt(tables_blob, tables->linker, vms, dsdt);
763
764 acpi_add_table(table_offsets, tables_blob);
765 build_madt(tables_blob, tables->linker, vms);
766
767 acpi_add_table(table_offsets, tables_blob);
768 build_gtdt(tables_blob, tables->linker, vms);
769
770 acpi_add_table(table_offsets, tables_blob);
771 build_mcfg(tables_blob, tables->linker, vms);
772
773 acpi_add_table(table_offsets, tables_blob);
774 build_spcr(tables_blob, tables->linker, vms);
775
776 if (nb_numa_nodes > 0) {
777 acpi_add_table(table_offsets, tables_blob);
778 build_srat(tables_blob, tables->linker, vms);
779 }
780
781 if (its_class_name() && !vmc->no_its) {
782 acpi_add_table(table_offsets, tables_blob);
783 build_iort(tables_blob, tables->linker);
784 }
785
786 /* RSDT is pointed to by RSDP */
787 rsdt = tables_blob->len;
788 build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
789
790 /* RSDP is in FSEG memory, so allocate it separately */
791 build_rsdp(tables->rsdp, tables->linker, rsdt);
792
793 /* Cleanup memory that's no longer used. */
794 g_array_free(table_offsets, true);
795 }
796
797 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
798 {
799 uint32_t size = acpi_data_len(data);
800
801 /* Make sure RAM size is correct - in case it got changed
802 * e.g. by migration */
803 memory_region_ram_resize(mr, size, &error_abort);
804
805 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
806 memory_region_set_dirty(mr, 0, size);
807 }
808
809 static void virt_acpi_build_update(void *build_opaque)
810 {
811 AcpiBuildState *build_state = build_opaque;
812 AcpiBuildTables tables;
813
814 /* No state to update or already patched? Nothing to do. */
815 if (!build_state || build_state->patched) {
816 return;
817 }
818 build_state->patched = true;
819
820 acpi_build_tables_init(&tables);
821
822 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
823
824 acpi_ram_update(build_state->table_mr, tables.table_data);
825 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
826 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
827
828 acpi_build_tables_cleanup(&tables, true);
829 }
830
831 static void virt_acpi_build_reset(void *build_opaque)
832 {
833 AcpiBuildState *build_state = build_opaque;
834 build_state->patched = false;
835 }
836
837 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
838 GArray *blob, const char *name,
839 uint64_t max_size)
840 {
841 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
842 name, virt_acpi_build_update, build_state, NULL);
843 }
844
845 static const VMStateDescription vmstate_virt_acpi_build = {
846 .name = "virt_acpi_build",
847 .version_id = 1,
848 .minimum_version_id = 1,
849 .fields = (VMStateField[]) {
850 VMSTATE_BOOL(patched, AcpiBuildState),
851 VMSTATE_END_OF_LIST()
852 },
853 };
854
855 void virt_acpi_setup(VirtMachineState *vms)
856 {
857 AcpiBuildTables tables;
858 AcpiBuildState *build_state;
859
860 if (!vms->fw_cfg) {
861 trace_virt_acpi_setup();
862 return;
863 }
864
865 if (!acpi_enabled) {
866 trace_virt_acpi_setup();
867 return;
868 }
869
870 build_state = g_malloc0(sizeof *build_state);
871
872 acpi_build_tables_init(&tables);
873 virt_acpi_build(vms, &tables);
874
875 /* Now expose it all to Guest */
876 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
877 ACPI_BUILD_TABLE_FILE,
878 ACPI_BUILD_TABLE_MAX_SIZE);
879 assert(build_state->table_mr != NULL);
880
881 build_state->linker_mr =
882 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
883 "etc/table-loader", 0);
884
885 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
886 acpi_data_len(tables.tcpalog));
887
888 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
889 ACPI_BUILD_RSDP_FILE, 0);
890
891 qemu_register_reset(virt_acpi_build_reset, build_state);
892 virt_acpi_build_reset(build_state);
893 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
894
895 /* Cleanup tables but don't free the memory: we track it
896 * in build_state.
897 */
898 acpi_build_tables_cleanup(&tables, false);
899 }
AR7 emulation for QEMU