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virtio-gpu: don't clear QemuUIInfo information on reset
[qemu/ar7.git] / hw / ppc / mac_newworld.c
blob3056d5f07588540f88753fca16cbaf955dda0413
1 /*
2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 *
25 * PCI bus layout on a real G5 (U3 based):
26 *
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47 *
48 */
49 #include "qemu/osdep.h"
50 #include "qapi/error.h"
51 #include "hw/hw.h"
52 #include "hw/ppc/ppc.h"
53 #include "hw/ppc/mac.h"
54 #include "hw/input/adb.h"
55 #include "hw/ppc/mac_dbdma.h"
56 #include "hw/timer/m48t59.h"
57 #include "hw/pci/pci.h"
58 #include "net/net.h"
59 #include "sysemu/sysemu.h"
60 #include "hw/boards.h"
61 #include "hw/nvram/fw_cfg.h"
62 #include "hw/char/escc.h"
63 #include "hw/ppc/openpic.h"
64 #include "hw/ide.h"
65 #include "hw/loader.h"
66 #include "elf.h"
67 #include "qemu/error-report.h"
68 #include "sysemu/kvm.h"
69 #include "kvm_ppc.h"
70 #include "hw/usb.h"
71 #include "sysemu/block-backend.h"
72 #include "exec/address-spaces.h"
73 #include "hw/sysbus.h"
74 #include "qemu/cutils.h"
75 #include "trace.h"
76
77 #define MAX_IDE_BUS 2
78 #define CFG_ADDR 0xf0000510
79 #define TBFREQ (100UL * 1000UL * 1000UL)
80 #define CLOCKFREQ (266UL * 1000UL * 1000UL)
81 #define BUSFREQ (100UL * 1000UL * 1000UL)
82
83 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
84
85 /* UniN device */
86 static void unin_write(void *opaque, hwaddr addr, uint64_t value,
87 unsigned size)
88 {
89 trace_mac99_uninorth_write(addr, value);
90 if (addr == 0x0) {
91 *(int*)opaque = value;
92 }
93 }
94
95 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
96 {
97 uint32_t value;
98
99 value = 0;
100 switch (addr) {
101 case 0:
102 value = *(int*)opaque;
103 }
104
105 trace_mac99_uninorth_read(addr, value);
106
107 return value;
108 }
109
110 static const MemoryRegionOps unin_ops = {
111 .read = unin_read,
112 .write = unin_write,
113 .endianness = DEVICE_NATIVE_ENDIAN,
114 };
115
116 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
117 Error **errp)
118 {
119 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
120 }
121
122 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
123 {
124 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
125 }
126
127 static hwaddr round_page(hwaddr addr)
128 {
129 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
130 }
131
132 static void ppc_core99_reset(void *opaque)
133 {
134 PowerPCCPU *cpu = opaque;
135
136 cpu_reset(CPU(cpu));
137 /* 970 CPUs want to get their initial IP as part of their boot protocol */
138 cpu->env.nip = PROM_ADDR + 0x100;
139 }
140
141 /* PowerPC Mac99 hardware initialisation */
142 static void ppc_core99_init(MachineState *machine)
143 {
144 ram_addr_t ram_size = machine->ram_size;
145 const char *kernel_filename = machine->kernel_filename;
146 const char *kernel_cmdline = machine->kernel_cmdline;
147 const char *initrd_filename = machine->initrd_filename;
148 const char *boot_device = machine->boot_order;
149 PowerPCCPU *cpu = NULL;
150 CPUPPCState *env = NULL;
151 char *filename;
152 qemu_irq *pic, **openpic_irqs;
153 MemoryRegion *isa = g_new(MemoryRegion, 1);
154 MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
155 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
156 int linux_boot, i, j, k;
157 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
158 hwaddr kernel_base, initrd_base, cmdline_base = 0;
159 long kernel_size, initrd_size;
160 PCIBus *pci_bus;
161 PCIDevice *macio;
162 MACIOIDEState *macio_ide;
163 BusState *adb_bus;
164 MacIONVRAMState *nvr;
165 int bios_size, ndrv_size;
166 uint8_t *ndrv_file;
167 MemoryRegion *pic_mem, *escc_mem;
168 MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
169 int ppc_boot_device;
170 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
171 void *fw_cfg;
172 int machine_arch;
173 SysBusDevice *s;
174 DeviceState *dev;
175 int *token = g_new(int, 1);
176 hwaddr nvram_addr = 0xFFF04000;
177 uint64_t tbfreq;
178
179 linux_boot = (kernel_filename != NULL);
180
181 /* init CPUs */
182 if (machine->cpu_model == NULL) {
183 #ifdef TARGET_PPC64
184 machine->cpu_model = "970fx";
185 #else
186 machine->cpu_model = "G4";
187 #endif
188 }
189 for (i = 0; i < smp_cpus; i++) {
190 cpu = cpu_ppc_init(machine->cpu_model);
191 if (cpu == NULL) {
192 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
193 exit(1);
194 }
195 env = &cpu->env;
196
197 /* Set time-base frequency to 100 Mhz */
198 cpu_ppc_tb_init(env, TBFREQ);
199 qemu_register_reset(ppc_core99_reset, cpu);
200 }
201
202 /* allocate RAM */
203 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
204 memory_region_add_subregion(get_system_memory(), 0, ram);
205
206 /* allocate and load BIOS */
207 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
208 &error_fatal);
209
210 if (bios_name == NULL)
211 bios_name = PROM_FILENAME;
212 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
213 memory_region_set_readonly(bios, true);
214 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
215
216 /* Load OpenBIOS (ELF) */
217 if (filename) {
218 bios_size = load_elf(filename, NULL, NULL, NULL,
219 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
220
221 g_free(filename);
222 } else {
223 bios_size = -1;
224 }
225 if (bios_size < 0 || bios_size > BIOS_SIZE) {
226 error_report("could not load PowerPC bios '%s'", bios_name);
227 exit(1);
228 }
229
230 if (linux_boot) {
231 uint64_t lowaddr = 0;
232 int bswap_needed;
233
234 #ifdef BSWAP_NEEDED
235 bswap_needed = 1;
236 #else
237 bswap_needed = 0;
238 #endif
239 kernel_base = KERNEL_LOAD_ADDR;
240
241 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
242 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
243 0, 0);
244 if (kernel_size < 0)
245 kernel_size = load_aout(kernel_filename, kernel_base,
246 ram_size - kernel_base, bswap_needed,
247 TARGET_PAGE_SIZE);
248 if (kernel_size < 0)
249 kernel_size = load_image_targphys(kernel_filename,
250 kernel_base,
251 ram_size - kernel_base);
252 if (kernel_size < 0) {
253 error_report("could not load kernel '%s'", kernel_filename);
254 exit(1);
255 }
256 /* load initrd */
257 if (initrd_filename) {
258 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
259 initrd_size = load_image_targphys(initrd_filename, initrd_base,
260 ram_size - initrd_base);
261 if (initrd_size < 0) {
262 error_report("could not load initial ram disk '%s'",
263 initrd_filename);
264 exit(1);
265 }
266 cmdline_base = round_page(initrd_base + initrd_size);
267 } else {
268 initrd_base = 0;
269 initrd_size = 0;
270 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
271 }
272 ppc_boot_device = 'm';
273 } else {
274 kernel_base = 0;
275 kernel_size = 0;
276 initrd_base = 0;
277 initrd_size = 0;
278 ppc_boot_device = '\0';
279 /* We consider that NewWorld PowerMac never have any floppy drive
280 * For now, OHW cannot boot from the network.
281 */
282 for (i = 0; boot_device[i] != '\0'; i++) {
283 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
284 ppc_boot_device = boot_device[i];
285 break;
286 }
287 }
288 if (ppc_boot_device == '\0') {
289 fprintf(stderr, "No valid boot device for Mac99 machine\n");
290 exit(1);
291 }
292 }
293
294 /* Register 8 MB of ISA IO space */
295 memory_region_init_alias(isa, NULL, "isa_mmio",
296 get_system_io(), 0, 0x00800000);
297 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
298
299 /* UniN init: XXX should be a real device */
300 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
301 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
302
303 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
304 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
305
306 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
307 openpic_irqs[0] =
308 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
309 for (i = 0; i < smp_cpus; i++) {
310 /* Mac99 IRQ connection between OpenPIC outputs pins
311 * and PowerPC input pins
312 */
313 switch (PPC_INPUT(env)) {
314 case PPC_FLAGS_INPUT_6xx:
315 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
316 openpic_irqs[i][OPENPIC_OUTPUT_INT] =
317 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
318 openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
319 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
320 openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
321 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
322 /* Not connected ? */
323 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
324 /* Check this */
325 openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
326 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
327 break;
328 #if defined(TARGET_PPC64)
329 case PPC_FLAGS_INPUT_970:
330 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
331 openpic_irqs[i][OPENPIC_OUTPUT_INT] =
332 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
333 openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
334 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
335 openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
336 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
337 /* Not connected ? */
338 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
339 /* Check this */
340 openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
341 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
342 break;
343 #endif /* defined(TARGET_PPC64) */
344 default:
345 error_report("Bus model not supported on mac99 machine");
346 exit(1);
347 }
348 }
349
350 pic = g_new0(qemu_irq, 64);
351
352 dev = qdev_create(NULL, TYPE_OPENPIC);
353 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
354 qdev_init_nofail(dev);
355 s = SYS_BUS_DEVICE(dev);
356 pic_mem = s->mmio[0].memory;
357 k = 0;
358 for (i = 0; i < smp_cpus; i++) {
359 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
360 sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
361 }
362 }
363
364 for (i = 0; i < 64; i++) {
365 pic[i] = qdev_get_gpio_in(dev, i);
366 }
367
368 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
369 /* 970 gets a U3 bus */
370 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
371 machine_arch = ARCH_MAC99_U3;
372 } else {
373 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
374 machine_arch = ARCH_MAC99;
375 }
376 object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort);
377
378 machine->usb |= defaults_enabled() && !machine->usb_disabled;
379
380 /* Timebase Frequency */
381 if (kvm_enabled()) {
382 tbfreq = kvmppc_get_tbfreq();
383 } else {
384 tbfreq = TBFREQ;
385 }
386
387 /* init basic PC hardware */
388 escc_mem = escc_init(0, pic[0x25], pic[0x24],
389 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
390 memory_region_init_alias(escc_bar, NULL, "escc-bar",
391 escc_mem, 0, memory_region_size(escc_mem));
392
393 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO);
394 dev = DEVICE(macio);
395 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
396 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
397 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
398 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
399 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
400 qdev_prop_set_uint64(dev, "frequency", tbfreq);
401 macio_init(macio, pic_mem, escc_bar);
402
403 /* We only emulate 2 out of 3 IDE controllers for now */
404 ide_drive_get(hd, ARRAY_SIZE(hd));
405
406 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
407 "ide[0]"));
408 macio_ide_init_drives(macio_ide, hd);
409
410 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
411 "ide[1]"));
412 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
413
414 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
415 adb_bus = qdev_get_child_bus(dev, "adb.0");
416 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
417 qdev_init_nofail(dev);
418 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
419 qdev_init_nofail(dev);
420
421 if (machine->usb) {
422 pci_create_simple(pci_bus, -1, "pci-ohci");
423
424 /* U3 needs to use USB for input because Linux doesn't support via-cuda
425 on PPC64 */
426 if (machine_arch == ARCH_MAC99_U3) {
427 USBBus *usb_bus = usb_bus_find(-1);
428
429 usb_create_simple(usb_bus, "usb-kbd");
430 usb_create_simple(usb_bus, "usb-mouse");
431 }
432 }
433
434 pci_vga_init(pci_bus);
435
436 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
437 graphic_depth = 15;
438 }
439
440 for (i = 0; i < nb_nics; i++) {
441 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
442 }
443
444 /* The NewWorld NVRAM is not located in the MacIO device */
445 #ifdef CONFIG_KVM
446 if (kvm_enabled() && getpagesize() > 4096) {
447 /* We can't combine read-write and read-only in a single page, so
448 move the NVRAM out of ROM again for KVM */
449 nvram_addr = 0xFFE00000;
450 }
451 #endif
452 dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
453 qdev_prop_set_uint32(dev, "size", 0x2000);
454 qdev_prop_set_uint32(dev, "it_shift", 1);
455 qdev_init_nofail(dev);
456 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
457 nvr = MACIO_NVRAM(dev);
458 pmac_format_nvram_partition(nvr, 0x2000);
459 /* No PCI init: the BIOS will do it */
460
461 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
462 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
463 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
464 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
465 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
466 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
468 if (kernel_cmdline) {
469 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
470 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
471 } else {
472 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
473 }
474 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
475 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
476 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
477
478 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
479 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
480 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
481
482 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
483 if (kvm_enabled()) {
484 #ifdef CONFIG_KVM
485 uint8_t *hypercall;
486
487 hypercall = g_malloc(16);
488 kvmppc_get_hypercall(env, hypercall, 16);
489 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
490 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
491 #endif
492 }
493 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
494 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
495 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
496 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
497 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
498
499 /* MacOS NDRV VGA driver */
500 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
501 if (filename) {
502 ndrv_size = get_image_size(filename);
503 if (ndrv_size != -1) {
504 ndrv_file = g_malloc(ndrv_size);
505 ndrv_size = load_image(filename, ndrv_file);
506
507 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
508 }
509 g_free(filename);
510 }
511
512 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
513 }
514
515 static int core99_kvm_type(const char *arg)
516 {
517 /* Always force PR KVM */
518 return 2;
519 }
520
521 static void core99_machine_class_init(ObjectClass *oc, void *data)
522 {
523 MachineClass *mc = MACHINE_CLASS(oc);
524
525 mc->desc = "Mac99 based PowerMAC";
526 mc->init = ppc_core99_init;
527 mc->block_default_type = IF_IDE;
528 mc->max_cpus = MAX_CPUS;
529 mc->default_boot_order = "cd";
530 mc->kvm_type = core99_kvm_type;
531 }
532
533 static const TypeInfo core99_machine_info = {
534 .name = MACHINE_TYPE_NAME("mac99"),
535 .parent = TYPE_MACHINE,
536 .class_init = core99_machine_class_init,
537 };
538
539 static void mac_machine_register_types(void)
540 {
541 type_register_static(&core99_machine_info);
542 }
543
544 type_init(mac_machine_register_types)
AR7 emulation for QEMU