2 * MIPS emulation for QEMU - main translation routines
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
27 #include "disas/disas.h"
28 #include "exec/exec-all.h"
29 #include "tcg/tcg-op.h"
30 #include "exec/cpu_ldst.h"
31 #include "hw/mips/cpudevs.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
35 #include "hw/semihosting/semihost.h"
37 #include "target/mips/trace.h"
38 #include "trace-tcg.h"
39 #include "exec/translator.h"
41 #include "qemu/qemu-print.h"
43 #define MIPS_DEBUG_DISAS 0
45 /* MIPS major opcodes */
46 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
49 /* indirect opcode tables */
50 OPC_SPECIAL
= (0x00 << 26),
51 OPC_REGIMM
= (0x01 << 26),
52 OPC_CP0
= (0x10 << 26),
53 OPC_CP1
= (0x11 << 26),
54 OPC_CP2
= (0x12 << 26),
55 OPC_CP3
= (0x13 << 26),
56 OPC_SPECIAL2
= (0x1C << 26),
57 OPC_SPECIAL3
= (0x1F << 26),
58 /* arithmetic with immediate */
59 OPC_ADDI
= (0x08 << 26),
60 OPC_ADDIU
= (0x09 << 26),
61 OPC_SLTI
= (0x0A << 26),
62 OPC_SLTIU
= (0x0B << 26),
63 /* logic with immediate */
64 OPC_ANDI
= (0x0C << 26),
65 OPC_ORI
= (0x0D << 26),
66 OPC_XORI
= (0x0E << 26),
67 OPC_LUI
= (0x0F << 26),
68 /* arithmetic with immediate */
69 OPC_DADDI
= (0x18 << 26),
70 OPC_DADDIU
= (0x19 << 26),
71 /* Jump and branches */
73 OPC_JAL
= (0x03 << 26),
74 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
75 OPC_BEQL
= (0x14 << 26),
76 OPC_BNE
= (0x05 << 26),
77 OPC_BNEL
= (0x15 << 26),
78 OPC_BLEZ
= (0x06 << 26),
79 OPC_BLEZL
= (0x16 << 26),
80 OPC_BGTZ
= (0x07 << 26),
81 OPC_BGTZL
= (0x17 << 26),
82 OPC_JALX
= (0x1D << 26),
83 OPC_DAUI
= (0x1D << 26),
85 OPC_LDL
= (0x1A << 26),
86 OPC_LDR
= (0x1B << 26),
87 OPC_LB
= (0x20 << 26),
88 OPC_LH
= (0x21 << 26),
89 OPC_LWL
= (0x22 << 26),
90 OPC_LW
= (0x23 << 26),
91 OPC_LWPC
= OPC_LW
| 0x5,
92 OPC_LBU
= (0x24 << 26),
93 OPC_LHU
= (0x25 << 26),
94 OPC_LWR
= (0x26 << 26),
95 OPC_LWU
= (0x27 << 26),
96 OPC_SB
= (0x28 << 26),
97 OPC_SH
= (0x29 << 26),
98 OPC_SWL
= (0x2A << 26),
99 OPC_SW
= (0x2B << 26),
100 OPC_SDL
= (0x2C << 26),
101 OPC_SDR
= (0x2D << 26),
102 OPC_SWR
= (0x2E << 26),
103 OPC_LL
= (0x30 << 26),
104 OPC_LLD
= (0x34 << 26),
105 OPC_LD
= (0x37 << 26),
106 OPC_LDPC
= OPC_LD
| 0x5,
107 OPC_SC
= (0x38 << 26),
108 OPC_SCD
= (0x3C << 26),
109 OPC_SD
= (0x3F << 26),
110 /* Floating point load/store */
111 OPC_LWC1
= (0x31 << 26),
112 OPC_LWC2
= (0x32 << 26),
113 OPC_LDC1
= (0x35 << 26),
114 OPC_LDC2
= (0x36 << 26),
115 OPC_SWC1
= (0x39 << 26),
116 OPC_SWC2
= (0x3A << 26),
117 OPC_SDC1
= (0x3D << 26),
118 OPC_SDC2
= (0x3E << 26),
119 /* Compact Branches */
120 OPC_BLEZALC
= (0x06 << 26),
121 OPC_BGEZALC
= (0x06 << 26),
122 OPC_BGEUC
= (0x06 << 26),
123 OPC_BGTZALC
= (0x07 << 26),
124 OPC_BLTZALC
= (0x07 << 26),
125 OPC_BLTUC
= (0x07 << 26),
126 OPC_BOVC
= (0x08 << 26),
127 OPC_BEQZALC
= (0x08 << 26),
128 OPC_BEQC
= (0x08 << 26),
129 OPC_BLEZC
= (0x16 << 26),
130 OPC_BGEZC
= (0x16 << 26),
131 OPC_BGEC
= (0x16 << 26),
132 OPC_BGTZC
= (0x17 << 26),
133 OPC_BLTZC
= (0x17 << 26),
134 OPC_BLTC
= (0x17 << 26),
135 OPC_BNVC
= (0x18 << 26),
136 OPC_BNEZALC
= (0x18 << 26),
137 OPC_BNEC
= (0x18 << 26),
138 OPC_BC
= (0x32 << 26),
139 OPC_BEQZC
= (0x36 << 26),
140 OPC_JIC
= (0x36 << 26),
141 OPC_BALC
= (0x3A << 26),
142 OPC_BNEZC
= (0x3E << 26),
143 OPC_JIALC
= (0x3E << 26),
144 /* MDMX ASE specific */
145 OPC_MDMX
= (0x1E << 26),
146 /* MSA ASE, same as MDMX */
148 /* Cache and prefetch */
149 OPC_CACHE
= (0x2F << 26),
150 OPC_PREF
= (0x33 << 26),
151 /* PC-relative address computation / loads */
152 OPC_PCREL
= (0x3B << 26),
155 /* PC-relative address computation / loads */
156 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
157 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
159 /* Instructions determined by bits 19 and 20 */
160 OPC_ADDIUPC
= OPC_PCREL
| (0 << 19),
161 R6_OPC_LWPC
= OPC_PCREL
| (1 << 19),
162 OPC_LWUPC
= OPC_PCREL
| (2 << 19),
164 /* Instructions determined by bits 16 ... 20 */
165 OPC_AUIPC
= OPC_PCREL
| (0x1e << 16),
166 OPC_ALUIPC
= OPC_PCREL
| (0x1f << 16),
169 R6_OPC_LDPC
= OPC_PCREL
| (6 << 18),
172 /* MIPS special opcodes */
173 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
177 OPC_SLL
= 0x00 | OPC_SPECIAL
,
178 /* NOP is SLL r0, r0, 0 */
179 /* SSNOP is SLL r0, r0, 1 */
180 /* EHB is SLL r0, r0, 3 */
181 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
182 OPC_ROTR
= OPC_SRL
| (1 << 21),
183 OPC_SRA
= 0x03 | OPC_SPECIAL
,
184 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
185 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
186 OPC_ROTRV
= OPC_SRLV
| (1 << 6),
187 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
188 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
189 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
190 OPC_DROTRV
= OPC_DSRLV
| (1 << 6),
191 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
192 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
193 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
194 OPC_DROTR
= OPC_DSRL
| (1 << 21),
195 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
196 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
197 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
198 OPC_DROTR32
= OPC_DSRL32
| (1 << 21),
199 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
200 /* Multiplication / division */
201 OPC_MULT
= 0x18 | OPC_SPECIAL
,
202 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
203 OPC_DIV
= 0x1A | OPC_SPECIAL
,
204 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
205 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
206 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
207 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
208 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
210 /* 2 registers arithmetic / logic */
211 OPC_ADD
= 0x20 | OPC_SPECIAL
,
212 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
213 OPC_SUB
= 0x22 | OPC_SPECIAL
,
214 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
215 OPC_AND
= 0x24 | OPC_SPECIAL
,
216 OPC_OR
= 0x25 | OPC_SPECIAL
,
217 OPC_XOR
= 0x26 | OPC_SPECIAL
,
218 OPC_NOR
= 0x27 | OPC_SPECIAL
,
219 OPC_SLT
= 0x2A | OPC_SPECIAL
,
220 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
221 OPC_DADD
= 0x2C | OPC_SPECIAL
,
222 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
223 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
224 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
226 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
227 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
229 OPC_TGE
= 0x30 | OPC_SPECIAL
,
230 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
231 OPC_TLT
= 0x32 | OPC_SPECIAL
,
232 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
233 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
234 OPC_TNE
= 0x36 | OPC_SPECIAL
,
235 /* HI / LO registers load & stores */
236 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
237 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
238 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
239 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
240 /* Conditional moves */
241 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
242 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
244 OPC_SELEQZ
= 0x35 | OPC_SPECIAL
,
245 OPC_SELNEZ
= 0x37 | OPC_SPECIAL
,
247 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
250 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
251 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
252 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
253 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
254 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
256 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
257 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
258 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
259 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
263 * R6 Multiply and Divide instructions have the same opcode
264 * and function field as legacy OPC_MULT[U]/OPC_DIV[U]
266 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
269 R6_OPC_MUL
= OPC_MULT
| (2 << 6),
270 R6_OPC_MUH
= OPC_MULT
| (3 << 6),
271 R6_OPC_MULU
= OPC_MULTU
| (2 << 6),
272 R6_OPC_MUHU
= OPC_MULTU
| (3 << 6),
273 R6_OPC_DIV
= OPC_DIV
| (2 << 6),
274 R6_OPC_MOD
= OPC_DIV
| (3 << 6),
275 R6_OPC_DIVU
= OPC_DIVU
| (2 << 6),
276 R6_OPC_MODU
= OPC_DIVU
| (3 << 6),
278 R6_OPC_DMUL
= OPC_DMULT
| (2 << 6),
279 R6_OPC_DMUH
= OPC_DMULT
| (3 << 6),
280 R6_OPC_DMULU
= OPC_DMULTU
| (2 << 6),
281 R6_OPC_DMUHU
= OPC_DMULTU
| (3 << 6),
282 R6_OPC_DDIV
= OPC_DDIV
| (2 << 6),
283 R6_OPC_DMOD
= OPC_DDIV
| (3 << 6),
284 R6_OPC_DDIVU
= OPC_DDIVU
| (2 << 6),
285 R6_OPC_DMODU
= OPC_DDIVU
| (3 << 6),
287 R6_OPC_CLZ
= 0x10 | OPC_SPECIAL
,
288 R6_OPC_CLO
= 0x11 | OPC_SPECIAL
,
289 R6_OPC_DCLZ
= 0x12 | OPC_SPECIAL
,
290 R6_OPC_DCLO
= 0x13 | OPC_SPECIAL
,
291 R6_OPC_SDBBP
= 0x0e | OPC_SPECIAL
,
293 OPC_LSA
= 0x05 | OPC_SPECIAL
,
294 OPC_DLSA
= 0x15 | OPC_SPECIAL
,
297 /* Multiplication variants of the vr54xx. */
298 #define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
301 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
302 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
303 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
304 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
305 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
306 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
307 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
308 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
309 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
310 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
311 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
312 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
313 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
314 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
317 /* REGIMM (rt field) opcodes */
318 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
321 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
322 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
323 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
324 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
325 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
326 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
327 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
328 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
329 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
330 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
331 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
332 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
333 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
334 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
335 OPC_SIGRIE
= (0x17 << 16) | OPC_REGIMM
,
336 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
338 OPC_DAHI
= (0x06 << 16) | OPC_REGIMM
,
339 OPC_DATI
= (0x1e << 16) | OPC_REGIMM
,
342 /* Special2 opcodes */
343 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
346 /* Multiply & xxx operations */
347 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
348 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
349 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
350 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
351 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
353 OPC_MULT_G_2F
= 0x10 | OPC_SPECIAL2
,
354 OPC_DMULT_G_2F
= 0x11 | OPC_SPECIAL2
,
355 OPC_MULTU_G_2F
= 0x12 | OPC_SPECIAL2
,
356 OPC_DMULTU_G_2F
= 0x13 | OPC_SPECIAL2
,
357 OPC_DIV_G_2F
= 0x14 | OPC_SPECIAL2
,
358 OPC_DDIV_G_2F
= 0x15 | OPC_SPECIAL2
,
359 OPC_DIVU_G_2F
= 0x16 | OPC_SPECIAL2
,
360 OPC_DDIVU_G_2F
= 0x17 | OPC_SPECIAL2
,
361 OPC_MOD_G_2F
= 0x1c | OPC_SPECIAL2
,
362 OPC_DMOD_G_2F
= 0x1d | OPC_SPECIAL2
,
363 OPC_MODU_G_2F
= 0x1e | OPC_SPECIAL2
,
364 OPC_DMODU_G_2F
= 0x1f | OPC_SPECIAL2
,
366 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
367 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
368 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
369 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
371 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
374 /* Special3 opcodes */
375 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
378 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
379 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
380 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
381 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
382 OPC_INS
= 0x04 | OPC_SPECIAL3
,
383 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
384 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
385 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
386 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
387 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
388 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
389 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
390 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
393 OPC_MULT_G_2E
= 0x18 | OPC_SPECIAL3
,
394 OPC_MULTU_G_2E
= 0x19 | OPC_SPECIAL3
,
395 OPC_DIV_G_2E
= 0x1A | OPC_SPECIAL3
,
396 OPC_DIVU_G_2E
= 0x1B | OPC_SPECIAL3
,
397 OPC_DMULT_G_2E
= 0x1C | OPC_SPECIAL3
,
398 OPC_DMULTU_G_2E
= 0x1D | OPC_SPECIAL3
,
399 OPC_DDIV_G_2E
= 0x1E | OPC_SPECIAL3
,
400 OPC_DDIVU_G_2E
= 0x1F | OPC_SPECIAL3
,
401 OPC_MOD_G_2E
= 0x22 | OPC_SPECIAL3
,
402 OPC_MODU_G_2E
= 0x23 | OPC_SPECIAL3
,
403 OPC_DMOD_G_2E
= 0x26 | OPC_SPECIAL3
,
404 OPC_DMODU_G_2E
= 0x27 | OPC_SPECIAL3
,
407 OPC_LX_DSP
= 0x0A | OPC_SPECIAL3
,
408 /* MIPS DSP Arithmetic */
409 OPC_ADDU_QB_DSP
= 0x10 | OPC_SPECIAL3
,
410 OPC_ADDU_OB_DSP
= 0x14 | OPC_SPECIAL3
,
411 OPC_ABSQ_S_PH_DSP
= 0x12 | OPC_SPECIAL3
,
412 OPC_ABSQ_S_QH_DSP
= 0x16 | OPC_SPECIAL3
,
413 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
414 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
415 OPC_CMPU_EQ_QB_DSP
= 0x11 | OPC_SPECIAL3
,
416 OPC_CMPU_EQ_OB_DSP
= 0x15 | OPC_SPECIAL3
,
417 /* MIPS DSP GPR-Based Shift Sub-class */
418 OPC_SHLL_QB_DSP
= 0x13 | OPC_SPECIAL3
,
419 OPC_SHLL_OB_DSP
= 0x17 | OPC_SPECIAL3
,
420 /* MIPS DSP Multiply Sub-class insns */
421 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
422 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
423 OPC_DPA_W_PH_DSP
= 0x30 | OPC_SPECIAL3
,
424 OPC_DPAQ_W_QH_DSP
= 0x34 | OPC_SPECIAL3
,
425 /* DSP Bit/Manipulation Sub-class */
426 OPC_INSV_DSP
= 0x0C | OPC_SPECIAL3
,
427 OPC_DINSV_DSP
= 0x0D | OPC_SPECIAL3
,
428 /* MIPS DSP Append Sub-class */
429 OPC_APPEND_DSP
= 0x31 | OPC_SPECIAL3
,
430 OPC_DAPPEND_DSP
= 0x35 | OPC_SPECIAL3
,
431 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
432 OPC_EXTR_W_DSP
= 0x38 | OPC_SPECIAL3
,
433 OPC_DEXTR_W_DSP
= 0x3C | OPC_SPECIAL3
,
436 OPC_LWLE
= 0x19 | OPC_SPECIAL3
,
437 OPC_LWRE
= 0x1A | OPC_SPECIAL3
,
438 OPC_CACHEE
= 0x1B | OPC_SPECIAL3
,
439 OPC_SBE
= 0x1C | OPC_SPECIAL3
,
440 OPC_SHE
= 0x1D | OPC_SPECIAL3
,
441 OPC_SCE
= 0x1E | OPC_SPECIAL3
,
442 OPC_SWE
= 0x1F | OPC_SPECIAL3
,
443 OPC_SWLE
= 0x21 | OPC_SPECIAL3
,
444 OPC_SWRE
= 0x22 | OPC_SPECIAL3
,
445 OPC_PREFE
= 0x23 | OPC_SPECIAL3
,
446 OPC_LBUE
= 0x28 | OPC_SPECIAL3
,
447 OPC_LHUE
= 0x29 | OPC_SPECIAL3
,
448 OPC_LBE
= 0x2C | OPC_SPECIAL3
,
449 OPC_LHE
= 0x2D | OPC_SPECIAL3
,
450 OPC_LLE
= 0x2E | OPC_SPECIAL3
,
451 OPC_LWE
= 0x2F | OPC_SPECIAL3
,
454 R6_OPC_PREF
= 0x35 | OPC_SPECIAL3
,
455 R6_OPC_CACHE
= 0x25 | OPC_SPECIAL3
,
456 R6_OPC_LL
= 0x36 | OPC_SPECIAL3
,
457 R6_OPC_SC
= 0x26 | OPC_SPECIAL3
,
458 R6_OPC_LLD
= 0x37 | OPC_SPECIAL3
,
459 R6_OPC_SCD
= 0x27 | OPC_SPECIAL3
,
463 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
466 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
467 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
468 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
469 OPC_ALIGN
= (0x08 << 6) | OPC_BSHFL
, /* 010.bp (010.00 to 010.11) */
470 OPC_ALIGN_1
= (0x09 << 6) | OPC_BSHFL
,
471 OPC_ALIGN_2
= (0x0A << 6) | OPC_BSHFL
,
472 OPC_ALIGN_3
= (0x0B << 6) | OPC_BSHFL
,
473 OPC_BITSWAP
= (0x00 << 6) | OPC_BSHFL
/* 00000 */
477 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
480 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
481 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
482 OPC_DALIGN
= (0x08 << 6) | OPC_DBSHFL
, /* 01.bp (01.000 to 01.111) */
483 OPC_DALIGN_1
= (0x09 << 6) | OPC_DBSHFL
,
484 OPC_DALIGN_2
= (0x0A << 6) | OPC_DBSHFL
,
485 OPC_DALIGN_3
= (0x0B << 6) | OPC_DBSHFL
,
486 OPC_DALIGN_4
= (0x0C << 6) | OPC_DBSHFL
,
487 OPC_DALIGN_5
= (0x0D << 6) | OPC_DBSHFL
,
488 OPC_DALIGN_6
= (0x0E << 6) | OPC_DBSHFL
,
489 OPC_DALIGN_7
= (0x0F << 6) | OPC_DBSHFL
,
490 OPC_DBITSWAP
= (0x00 << 6) | OPC_DBSHFL
, /* 00000 */
493 /* MIPS DSP REGIMM opcodes */
495 OPC_BPOSGE32
= (0x1C << 16) | OPC_REGIMM
,
496 OPC_BPOSGE64
= (0x1D << 16) | OPC_REGIMM
,
499 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
502 OPC_LBUX
= (0x06 << 6) | OPC_LX_DSP
,
503 OPC_LHX
= (0x04 << 6) | OPC_LX_DSP
,
504 OPC_LWX
= (0x00 << 6) | OPC_LX_DSP
,
505 OPC_LDX
= (0x08 << 6) | OPC_LX_DSP
,
508 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
510 /* MIPS DSP Arithmetic Sub-class */
511 OPC_ADDQ_PH
= (0x0A << 6) | OPC_ADDU_QB_DSP
,
512 OPC_ADDQ_S_PH
= (0x0E << 6) | OPC_ADDU_QB_DSP
,
513 OPC_ADDQ_S_W
= (0x16 << 6) | OPC_ADDU_QB_DSP
,
514 OPC_ADDU_QB
= (0x00 << 6) | OPC_ADDU_QB_DSP
,
515 OPC_ADDU_S_QB
= (0x04 << 6) | OPC_ADDU_QB_DSP
,
516 OPC_ADDU_PH
= (0x08 << 6) | OPC_ADDU_QB_DSP
,
517 OPC_ADDU_S_PH
= (0x0C << 6) | OPC_ADDU_QB_DSP
,
518 OPC_SUBQ_PH
= (0x0B << 6) | OPC_ADDU_QB_DSP
,
519 OPC_SUBQ_S_PH
= (0x0F << 6) | OPC_ADDU_QB_DSP
,
520 OPC_SUBQ_S_W
= (0x17 << 6) | OPC_ADDU_QB_DSP
,
521 OPC_SUBU_QB
= (0x01 << 6) | OPC_ADDU_QB_DSP
,
522 OPC_SUBU_S_QB
= (0x05 << 6) | OPC_ADDU_QB_DSP
,
523 OPC_SUBU_PH
= (0x09 << 6) | OPC_ADDU_QB_DSP
,
524 OPC_SUBU_S_PH
= (0x0D << 6) | OPC_ADDU_QB_DSP
,
525 OPC_ADDSC
= (0x10 << 6) | OPC_ADDU_QB_DSP
,
526 OPC_ADDWC
= (0x11 << 6) | OPC_ADDU_QB_DSP
,
527 OPC_MODSUB
= (0x12 << 6) | OPC_ADDU_QB_DSP
,
528 OPC_RADDU_W_QB
= (0x14 << 6) | OPC_ADDU_QB_DSP
,
529 /* MIPS DSP Multiply Sub-class insns */
530 OPC_MULEU_S_PH_QBL
= (0x06 << 6) | OPC_ADDU_QB_DSP
,
531 OPC_MULEU_S_PH_QBR
= (0x07 << 6) | OPC_ADDU_QB_DSP
,
532 OPC_MULQ_RS_PH
= (0x1F << 6) | OPC_ADDU_QB_DSP
,
533 OPC_MULEQ_S_W_PHL
= (0x1C << 6) | OPC_ADDU_QB_DSP
,
534 OPC_MULEQ_S_W_PHR
= (0x1D << 6) | OPC_ADDU_QB_DSP
,
535 OPC_MULQ_S_PH
= (0x1E << 6) | OPC_ADDU_QB_DSP
,
538 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
539 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
541 /* MIPS DSP Arithmetic Sub-class */
542 OPC_ADDUH_QB
= (0x00 << 6) | OPC_ADDUH_QB_DSP
,
543 OPC_ADDUH_R_QB
= (0x02 << 6) | OPC_ADDUH_QB_DSP
,
544 OPC_ADDQH_PH
= (0x08 << 6) | OPC_ADDUH_QB_DSP
,
545 OPC_ADDQH_R_PH
= (0x0A << 6) | OPC_ADDUH_QB_DSP
,
546 OPC_ADDQH_W
= (0x10 << 6) | OPC_ADDUH_QB_DSP
,
547 OPC_ADDQH_R_W
= (0x12 << 6) | OPC_ADDUH_QB_DSP
,
548 OPC_SUBUH_QB
= (0x01 << 6) | OPC_ADDUH_QB_DSP
,
549 OPC_SUBUH_R_QB
= (0x03 << 6) | OPC_ADDUH_QB_DSP
,
550 OPC_SUBQH_PH
= (0x09 << 6) | OPC_ADDUH_QB_DSP
,
551 OPC_SUBQH_R_PH
= (0x0B << 6) | OPC_ADDUH_QB_DSP
,
552 OPC_SUBQH_W
= (0x11 << 6) | OPC_ADDUH_QB_DSP
,
553 OPC_SUBQH_R_W
= (0x13 << 6) | OPC_ADDUH_QB_DSP
,
554 /* MIPS DSP Multiply Sub-class insns */
555 OPC_MUL_PH
= (0x0C << 6) | OPC_ADDUH_QB_DSP
,
556 OPC_MUL_S_PH
= (0x0E << 6) | OPC_ADDUH_QB_DSP
,
557 OPC_MULQ_S_W
= (0x16 << 6) | OPC_ADDUH_QB_DSP
,
558 OPC_MULQ_RS_W
= (0x17 << 6) | OPC_ADDUH_QB_DSP
,
561 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
563 /* MIPS DSP Arithmetic Sub-class */
564 OPC_ABSQ_S_QB
= (0x01 << 6) | OPC_ABSQ_S_PH_DSP
,
565 OPC_ABSQ_S_PH
= (0x09 << 6) | OPC_ABSQ_S_PH_DSP
,
566 OPC_ABSQ_S_W
= (0x11 << 6) | OPC_ABSQ_S_PH_DSP
,
567 OPC_PRECEQ_W_PHL
= (0x0C << 6) | OPC_ABSQ_S_PH_DSP
,
568 OPC_PRECEQ_W_PHR
= (0x0D << 6) | OPC_ABSQ_S_PH_DSP
,
569 OPC_PRECEQU_PH_QBL
= (0x04 << 6) | OPC_ABSQ_S_PH_DSP
,
570 OPC_PRECEQU_PH_QBR
= (0x05 << 6) | OPC_ABSQ_S_PH_DSP
,
571 OPC_PRECEQU_PH_QBLA
= (0x06 << 6) | OPC_ABSQ_S_PH_DSP
,
572 OPC_PRECEQU_PH_QBRA
= (0x07 << 6) | OPC_ABSQ_S_PH_DSP
,
573 OPC_PRECEU_PH_QBL
= (0x1C << 6) | OPC_ABSQ_S_PH_DSP
,
574 OPC_PRECEU_PH_QBR
= (0x1D << 6) | OPC_ABSQ_S_PH_DSP
,
575 OPC_PRECEU_PH_QBLA
= (0x1E << 6) | OPC_ABSQ_S_PH_DSP
,
576 OPC_PRECEU_PH_QBRA
= (0x1F << 6) | OPC_ABSQ_S_PH_DSP
,
577 /* DSP Bit/Manipulation Sub-class */
578 OPC_BITREV
= (0x1B << 6) | OPC_ABSQ_S_PH_DSP
,
579 OPC_REPL_QB
= (0x02 << 6) | OPC_ABSQ_S_PH_DSP
,
580 OPC_REPLV_QB
= (0x03 << 6) | OPC_ABSQ_S_PH_DSP
,
581 OPC_REPL_PH
= (0x0A << 6) | OPC_ABSQ_S_PH_DSP
,
582 OPC_REPLV_PH
= (0x0B << 6) | OPC_ABSQ_S_PH_DSP
,
585 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
587 /* MIPS DSP Arithmetic Sub-class */
588 OPC_PRECR_QB_PH
= (0x0D << 6) | OPC_CMPU_EQ_QB_DSP
,
589 OPC_PRECRQ_QB_PH
= (0x0C << 6) | OPC_CMPU_EQ_QB_DSP
,
590 OPC_PRECR_SRA_PH_W
= (0x1E << 6) | OPC_CMPU_EQ_QB_DSP
,
591 OPC_PRECR_SRA_R_PH_W
= (0x1F << 6) | OPC_CMPU_EQ_QB_DSP
,
592 OPC_PRECRQ_PH_W
= (0x14 << 6) | OPC_CMPU_EQ_QB_DSP
,
593 OPC_PRECRQ_RS_PH_W
= (0x15 << 6) | OPC_CMPU_EQ_QB_DSP
,
594 OPC_PRECRQU_S_QB_PH
= (0x0F << 6) | OPC_CMPU_EQ_QB_DSP
,
595 /* DSP Compare-Pick Sub-class */
596 OPC_CMPU_EQ_QB
= (0x00 << 6) | OPC_CMPU_EQ_QB_DSP
,
597 OPC_CMPU_LT_QB
= (0x01 << 6) | OPC_CMPU_EQ_QB_DSP
,
598 OPC_CMPU_LE_QB
= (0x02 << 6) | OPC_CMPU_EQ_QB_DSP
,
599 OPC_CMPGU_EQ_QB
= (0x04 << 6) | OPC_CMPU_EQ_QB_DSP
,
600 OPC_CMPGU_LT_QB
= (0x05 << 6) | OPC_CMPU_EQ_QB_DSP
,
601 OPC_CMPGU_LE_QB
= (0x06 << 6) | OPC_CMPU_EQ_QB_DSP
,
602 OPC_CMPGDU_EQ_QB
= (0x18 << 6) | OPC_CMPU_EQ_QB_DSP
,
603 OPC_CMPGDU_LT_QB
= (0x19 << 6) | OPC_CMPU_EQ_QB_DSP
,
604 OPC_CMPGDU_LE_QB
= (0x1A << 6) | OPC_CMPU_EQ_QB_DSP
,
605 OPC_CMP_EQ_PH
= (0x08 << 6) | OPC_CMPU_EQ_QB_DSP
,
606 OPC_CMP_LT_PH
= (0x09 << 6) | OPC_CMPU_EQ_QB_DSP
,
607 OPC_CMP_LE_PH
= (0x0A << 6) | OPC_CMPU_EQ_QB_DSP
,
608 OPC_PICK_QB
= (0x03 << 6) | OPC_CMPU_EQ_QB_DSP
,
609 OPC_PICK_PH
= (0x0B << 6) | OPC_CMPU_EQ_QB_DSP
,
610 OPC_PACKRL_PH
= (0x0E << 6) | OPC_CMPU_EQ_QB_DSP
,
613 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
615 /* MIPS DSP GPR-Based Shift Sub-class */
616 OPC_SHLL_QB
= (0x00 << 6) | OPC_SHLL_QB_DSP
,
617 OPC_SHLLV_QB
= (0x02 << 6) | OPC_SHLL_QB_DSP
,
618 OPC_SHLL_PH
= (0x08 << 6) | OPC_SHLL_QB_DSP
,
619 OPC_SHLLV_PH
= (0x0A << 6) | OPC_SHLL_QB_DSP
,
620 OPC_SHLL_S_PH
= (0x0C << 6) | OPC_SHLL_QB_DSP
,
621 OPC_SHLLV_S_PH
= (0x0E << 6) | OPC_SHLL_QB_DSP
,
622 OPC_SHLL_S_W
= (0x14 << 6) | OPC_SHLL_QB_DSP
,
623 OPC_SHLLV_S_W
= (0x16 << 6) | OPC_SHLL_QB_DSP
,
624 OPC_SHRL_QB
= (0x01 << 6) | OPC_SHLL_QB_DSP
,
625 OPC_SHRLV_QB
= (0x03 << 6) | OPC_SHLL_QB_DSP
,
626 OPC_SHRL_PH
= (0x19 << 6) | OPC_SHLL_QB_DSP
,
627 OPC_SHRLV_PH
= (0x1B << 6) | OPC_SHLL_QB_DSP
,
628 OPC_SHRA_QB
= (0x04 << 6) | OPC_SHLL_QB_DSP
,
629 OPC_SHRA_R_QB
= (0x05 << 6) | OPC_SHLL_QB_DSP
,
630 OPC_SHRAV_QB
= (0x06 << 6) | OPC_SHLL_QB_DSP
,
631 OPC_SHRAV_R_QB
= (0x07 << 6) | OPC_SHLL_QB_DSP
,
632 OPC_SHRA_PH
= (0x09 << 6) | OPC_SHLL_QB_DSP
,
633 OPC_SHRAV_PH
= (0x0B << 6) | OPC_SHLL_QB_DSP
,
634 OPC_SHRA_R_PH
= (0x0D << 6) | OPC_SHLL_QB_DSP
,
635 OPC_SHRAV_R_PH
= (0x0F << 6) | OPC_SHLL_QB_DSP
,
636 OPC_SHRA_R_W
= (0x15 << 6) | OPC_SHLL_QB_DSP
,
637 OPC_SHRAV_R_W
= (0x17 << 6) | OPC_SHLL_QB_DSP
,
640 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
642 /* MIPS DSP Multiply Sub-class insns */
643 OPC_DPAU_H_QBL
= (0x03 << 6) | OPC_DPA_W_PH_DSP
,
644 OPC_DPAU_H_QBR
= (0x07 << 6) | OPC_DPA_W_PH_DSP
,
645 OPC_DPSU_H_QBL
= (0x0B << 6) | OPC_DPA_W_PH_DSP
,
646 OPC_DPSU_H_QBR
= (0x0F << 6) | OPC_DPA_W_PH_DSP
,
647 OPC_DPA_W_PH
= (0x00 << 6) | OPC_DPA_W_PH_DSP
,
648 OPC_DPAX_W_PH
= (0x08 << 6) | OPC_DPA_W_PH_DSP
,
649 OPC_DPAQ_S_W_PH
= (0x04 << 6) | OPC_DPA_W_PH_DSP
,
650 OPC_DPAQX_S_W_PH
= (0x18 << 6) | OPC_DPA_W_PH_DSP
,
651 OPC_DPAQX_SA_W_PH
= (0x1A << 6) | OPC_DPA_W_PH_DSP
,
652 OPC_DPS_W_PH
= (0x01 << 6) | OPC_DPA_W_PH_DSP
,
653 OPC_DPSX_W_PH
= (0x09 << 6) | OPC_DPA_W_PH_DSP
,
654 OPC_DPSQ_S_W_PH
= (0x05 << 6) | OPC_DPA_W_PH_DSP
,
655 OPC_DPSQX_S_W_PH
= (0x19 << 6) | OPC_DPA_W_PH_DSP
,
656 OPC_DPSQX_SA_W_PH
= (0x1B << 6) | OPC_DPA_W_PH_DSP
,
657 OPC_MULSAQ_S_W_PH
= (0x06 << 6) | OPC_DPA_W_PH_DSP
,
658 OPC_DPAQ_SA_L_W
= (0x0C << 6) | OPC_DPA_W_PH_DSP
,
659 OPC_DPSQ_SA_L_W
= (0x0D << 6) | OPC_DPA_W_PH_DSP
,
660 OPC_MAQ_S_W_PHL
= (0x14 << 6) | OPC_DPA_W_PH_DSP
,
661 OPC_MAQ_S_W_PHR
= (0x16 << 6) | OPC_DPA_W_PH_DSP
,
662 OPC_MAQ_SA_W_PHL
= (0x10 << 6) | OPC_DPA_W_PH_DSP
,
663 OPC_MAQ_SA_W_PHR
= (0x12 << 6) | OPC_DPA_W_PH_DSP
,
664 OPC_MULSA_W_PH
= (0x02 << 6) | OPC_DPA_W_PH_DSP
,
667 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
669 /* DSP Bit/Manipulation Sub-class */
670 OPC_INSV
= (0x00 << 6) | OPC_INSV_DSP
,
673 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
675 /* MIPS DSP Append Sub-class */
676 OPC_APPEND
= (0x00 << 6) | OPC_APPEND_DSP
,
677 OPC_PREPEND
= (0x01 << 6) | OPC_APPEND_DSP
,
678 OPC_BALIGN
= (0x10 << 6) | OPC_APPEND_DSP
,
681 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
683 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
684 OPC_EXTR_W
= (0x00 << 6) | OPC_EXTR_W_DSP
,
685 OPC_EXTR_R_W
= (0x04 << 6) | OPC_EXTR_W_DSP
,
686 OPC_EXTR_RS_W
= (0x06 << 6) | OPC_EXTR_W_DSP
,
687 OPC_EXTR_S_H
= (0x0E << 6) | OPC_EXTR_W_DSP
,
688 OPC_EXTRV_S_H
= (0x0F << 6) | OPC_EXTR_W_DSP
,
689 OPC_EXTRV_W
= (0x01 << 6) | OPC_EXTR_W_DSP
,
690 OPC_EXTRV_R_W
= (0x05 << 6) | OPC_EXTR_W_DSP
,
691 OPC_EXTRV_RS_W
= (0x07 << 6) | OPC_EXTR_W_DSP
,
692 OPC_EXTP
= (0x02 << 6) | OPC_EXTR_W_DSP
,
693 OPC_EXTPV
= (0x03 << 6) | OPC_EXTR_W_DSP
,
694 OPC_EXTPDP
= (0x0A << 6) | OPC_EXTR_W_DSP
,
695 OPC_EXTPDPV
= (0x0B << 6) | OPC_EXTR_W_DSP
,
696 OPC_SHILO
= (0x1A << 6) | OPC_EXTR_W_DSP
,
697 OPC_SHILOV
= (0x1B << 6) | OPC_EXTR_W_DSP
,
698 OPC_MTHLIP
= (0x1F << 6) | OPC_EXTR_W_DSP
,
699 OPC_WRDSP
= (0x13 << 6) | OPC_EXTR_W_DSP
,
700 OPC_RDDSP
= (0x12 << 6) | OPC_EXTR_W_DSP
,
703 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
705 /* MIPS DSP Arithmetic Sub-class */
706 OPC_PRECEQ_L_PWL
= (0x14 << 6) | OPC_ABSQ_S_QH_DSP
,
707 OPC_PRECEQ_L_PWR
= (0x15 << 6) | OPC_ABSQ_S_QH_DSP
,
708 OPC_PRECEQ_PW_QHL
= (0x0C << 6) | OPC_ABSQ_S_QH_DSP
,
709 OPC_PRECEQ_PW_QHR
= (0x0D << 6) | OPC_ABSQ_S_QH_DSP
,
710 OPC_PRECEQ_PW_QHLA
= (0x0E << 6) | OPC_ABSQ_S_QH_DSP
,
711 OPC_PRECEQ_PW_QHRA
= (0x0F << 6) | OPC_ABSQ_S_QH_DSP
,
712 OPC_PRECEQU_QH_OBL
= (0x04 << 6) | OPC_ABSQ_S_QH_DSP
,
713 OPC_PRECEQU_QH_OBR
= (0x05 << 6) | OPC_ABSQ_S_QH_DSP
,
714 OPC_PRECEQU_QH_OBLA
= (0x06 << 6) | OPC_ABSQ_S_QH_DSP
,
715 OPC_PRECEQU_QH_OBRA
= (0x07 << 6) | OPC_ABSQ_S_QH_DSP
,
716 OPC_PRECEU_QH_OBL
= (0x1C << 6) | OPC_ABSQ_S_QH_DSP
,
717 OPC_PRECEU_QH_OBR
= (0x1D << 6) | OPC_ABSQ_S_QH_DSP
,
718 OPC_PRECEU_QH_OBLA
= (0x1E << 6) | OPC_ABSQ_S_QH_DSP
,
719 OPC_PRECEU_QH_OBRA
= (0x1F << 6) | OPC_ABSQ_S_QH_DSP
,
720 OPC_ABSQ_S_OB
= (0x01 << 6) | OPC_ABSQ_S_QH_DSP
,
721 OPC_ABSQ_S_PW
= (0x11 << 6) | OPC_ABSQ_S_QH_DSP
,
722 OPC_ABSQ_S_QH
= (0x09 << 6) | OPC_ABSQ_S_QH_DSP
,
723 /* DSP Bit/Manipulation Sub-class */
724 OPC_REPL_OB
= (0x02 << 6) | OPC_ABSQ_S_QH_DSP
,
725 OPC_REPL_PW
= (0x12 << 6) | OPC_ABSQ_S_QH_DSP
,
726 OPC_REPL_QH
= (0x0A << 6) | OPC_ABSQ_S_QH_DSP
,
727 OPC_REPLV_OB
= (0x03 << 6) | OPC_ABSQ_S_QH_DSP
,
728 OPC_REPLV_PW
= (0x13 << 6) | OPC_ABSQ_S_QH_DSP
,
729 OPC_REPLV_QH
= (0x0B << 6) | OPC_ABSQ_S_QH_DSP
,
732 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
734 /* MIPS DSP Multiply Sub-class insns */
735 OPC_MULEQ_S_PW_QHL
= (0x1C << 6) | OPC_ADDU_OB_DSP
,
736 OPC_MULEQ_S_PW_QHR
= (0x1D << 6) | OPC_ADDU_OB_DSP
,
737 OPC_MULEU_S_QH_OBL
= (0x06 << 6) | OPC_ADDU_OB_DSP
,
738 OPC_MULEU_S_QH_OBR
= (0x07 << 6) | OPC_ADDU_OB_DSP
,
739 OPC_MULQ_RS_QH
= (0x1F << 6) | OPC_ADDU_OB_DSP
,
740 /* MIPS DSP Arithmetic Sub-class */
741 OPC_RADDU_L_OB
= (0x14 << 6) | OPC_ADDU_OB_DSP
,
742 OPC_SUBQ_PW
= (0x13 << 6) | OPC_ADDU_OB_DSP
,
743 OPC_SUBQ_S_PW
= (0x17 << 6) | OPC_ADDU_OB_DSP
,
744 OPC_SUBQ_QH
= (0x0B << 6) | OPC_ADDU_OB_DSP
,
745 OPC_SUBQ_S_QH
= (0x0F << 6) | OPC_ADDU_OB_DSP
,
746 OPC_SUBU_OB
= (0x01 << 6) | OPC_ADDU_OB_DSP
,
747 OPC_SUBU_S_OB
= (0x05 << 6) | OPC_ADDU_OB_DSP
,
748 OPC_SUBU_QH
= (0x09 << 6) | OPC_ADDU_OB_DSP
,
749 OPC_SUBU_S_QH
= (0x0D << 6) | OPC_ADDU_OB_DSP
,
750 OPC_SUBUH_OB
= (0x19 << 6) | OPC_ADDU_OB_DSP
,
751 OPC_SUBUH_R_OB
= (0x1B << 6) | OPC_ADDU_OB_DSP
,
752 OPC_ADDQ_PW
= (0x12 << 6) | OPC_ADDU_OB_DSP
,
753 OPC_ADDQ_S_PW
= (0x16 << 6) | OPC_ADDU_OB_DSP
,
754 OPC_ADDQ_QH
= (0x0A << 6) | OPC_ADDU_OB_DSP
,
755 OPC_ADDQ_S_QH
= (0x0E << 6) | OPC_ADDU_OB_DSP
,
756 OPC_ADDU_OB
= (0x00 << 6) | OPC_ADDU_OB_DSP
,
757 OPC_ADDU_S_OB
= (0x04 << 6) | OPC_ADDU_OB_DSP
,
758 OPC_ADDU_QH
= (0x08 << 6) | OPC_ADDU_OB_DSP
,
759 OPC_ADDU_S_QH
= (0x0C << 6) | OPC_ADDU_OB_DSP
,
760 OPC_ADDUH_OB
= (0x18 << 6) | OPC_ADDU_OB_DSP
,
761 OPC_ADDUH_R_OB
= (0x1A << 6) | OPC_ADDU_OB_DSP
,
764 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
766 /* DSP Compare-Pick Sub-class */
767 OPC_CMP_EQ_PW
= (0x10 << 6) | OPC_CMPU_EQ_OB_DSP
,
768 OPC_CMP_LT_PW
= (0x11 << 6) | OPC_CMPU_EQ_OB_DSP
,
769 OPC_CMP_LE_PW
= (0x12 << 6) | OPC_CMPU_EQ_OB_DSP
,
770 OPC_CMP_EQ_QH
= (0x08 << 6) | OPC_CMPU_EQ_OB_DSP
,
771 OPC_CMP_LT_QH
= (0x09 << 6) | OPC_CMPU_EQ_OB_DSP
,
772 OPC_CMP_LE_QH
= (0x0A << 6) | OPC_CMPU_EQ_OB_DSP
,
773 OPC_CMPGDU_EQ_OB
= (0x18 << 6) | OPC_CMPU_EQ_OB_DSP
,
774 OPC_CMPGDU_LT_OB
= (0x19 << 6) | OPC_CMPU_EQ_OB_DSP
,
775 OPC_CMPGDU_LE_OB
= (0x1A << 6) | OPC_CMPU_EQ_OB_DSP
,
776 OPC_CMPGU_EQ_OB
= (0x04 << 6) | OPC_CMPU_EQ_OB_DSP
,
777 OPC_CMPGU_LT_OB
= (0x05 << 6) | OPC_CMPU_EQ_OB_DSP
,
778 OPC_CMPGU_LE_OB
= (0x06 << 6) | OPC_CMPU_EQ_OB_DSP
,
779 OPC_CMPU_EQ_OB
= (0x00 << 6) | OPC_CMPU_EQ_OB_DSP
,
780 OPC_CMPU_LT_OB
= (0x01 << 6) | OPC_CMPU_EQ_OB_DSP
,
781 OPC_CMPU_LE_OB
= (0x02 << 6) | OPC_CMPU_EQ_OB_DSP
,
782 OPC_PACKRL_PW
= (0x0E << 6) | OPC_CMPU_EQ_OB_DSP
,
783 OPC_PICK_OB
= (0x03 << 6) | OPC_CMPU_EQ_OB_DSP
,
784 OPC_PICK_PW
= (0x13 << 6) | OPC_CMPU_EQ_OB_DSP
,
785 OPC_PICK_QH
= (0x0B << 6) | OPC_CMPU_EQ_OB_DSP
,
786 /* MIPS DSP Arithmetic Sub-class */
787 OPC_PRECR_OB_QH
= (0x0D << 6) | OPC_CMPU_EQ_OB_DSP
,
788 OPC_PRECR_SRA_QH_PW
= (0x1E << 6) | OPC_CMPU_EQ_OB_DSP
,
789 OPC_PRECR_SRA_R_QH_PW
= (0x1F << 6) | OPC_CMPU_EQ_OB_DSP
,
790 OPC_PRECRQ_OB_QH
= (0x0C << 6) | OPC_CMPU_EQ_OB_DSP
,
791 OPC_PRECRQ_PW_L
= (0x1C << 6) | OPC_CMPU_EQ_OB_DSP
,
792 OPC_PRECRQ_QH_PW
= (0x14 << 6) | OPC_CMPU_EQ_OB_DSP
,
793 OPC_PRECRQ_RS_QH_PW
= (0x15 << 6) | OPC_CMPU_EQ_OB_DSP
,
794 OPC_PRECRQU_S_OB_QH
= (0x0F << 6) | OPC_CMPU_EQ_OB_DSP
,
797 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
799 /* DSP Append Sub-class */
800 OPC_DAPPEND
= (0x00 << 6) | OPC_DAPPEND_DSP
,
801 OPC_PREPENDD
= (0x03 << 6) | OPC_DAPPEND_DSP
,
802 OPC_PREPENDW
= (0x01 << 6) | OPC_DAPPEND_DSP
,
803 OPC_DBALIGN
= (0x10 << 6) | OPC_DAPPEND_DSP
,
806 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
808 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
809 OPC_DMTHLIP
= (0x1F << 6) | OPC_DEXTR_W_DSP
,
810 OPC_DSHILO
= (0x1A << 6) | OPC_DEXTR_W_DSP
,
811 OPC_DEXTP
= (0x02 << 6) | OPC_DEXTR_W_DSP
,
812 OPC_DEXTPDP
= (0x0A << 6) | OPC_DEXTR_W_DSP
,
813 OPC_DEXTPDPV
= (0x0B << 6) | OPC_DEXTR_W_DSP
,
814 OPC_DEXTPV
= (0x03 << 6) | OPC_DEXTR_W_DSP
,
815 OPC_DEXTR_L
= (0x10 << 6) | OPC_DEXTR_W_DSP
,
816 OPC_DEXTR_R_L
= (0x14 << 6) | OPC_DEXTR_W_DSP
,
817 OPC_DEXTR_RS_L
= (0x16 << 6) | OPC_DEXTR_W_DSP
,
818 OPC_DEXTR_W
= (0x00 << 6) | OPC_DEXTR_W_DSP
,
819 OPC_DEXTR_R_W
= (0x04 << 6) | OPC_DEXTR_W_DSP
,
820 OPC_DEXTR_RS_W
= (0x06 << 6) | OPC_DEXTR_W_DSP
,
821 OPC_DEXTR_S_H
= (0x0E << 6) | OPC_DEXTR_W_DSP
,
822 OPC_DEXTRV_L
= (0x11 << 6) | OPC_DEXTR_W_DSP
,
823 OPC_DEXTRV_R_L
= (0x15 << 6) | OPC_DEXTR_W_DSP
,
824 OPC_DEXTRV_RS_L
= (0x17 << 6) | OPC_DEXTR_W_DSP
,
825 OPC_DEXTRV_S_H
= (0x0F << 6) | OPC_DEXTR_W_DSP
,
826 OPC_DEXTRV_W
= (0x01 << 6) | OPC_DEXTR_W_DSP
,
827 OPC_DEXTRV_R_W
= (0x05 << 6) | OPC_DEXTR_W_DSP
,
828 OPC_DEXTRV_RS_W
= (0x07 << 6) | OPC_DEXTR_W_DSP
,
829 OPC_DSHILOV
= (0x1B << 6) | OPC_DEXTR_W_DSP
,
832 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
834 /* DSP Bit/Manipulation Sub-class */
835 OPC_DINSV
= (0x00 << 6) | OPC_DINSV_DSP
,
838 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
840 /* MIPS DSP Multiply Sub-class insns */
841 OPC_DMADD
= (0x19 << 6) | OPC_DPAQ_W_QH_DSP
,
842 OPC_DMADDU
= (0x1D << 6) | OPC_DPAQ_W_QH_DSP
,
843 OPC_DMSUB
= (0x1B << 6) | OPC_DPAQ_W_QH_DSP
,
844 OPC_DMSUBU
= (0x1F << 6) | OPC_DPAQ_W_QH_DSP
,
845 OPC_DPA_W_QH
= (0x00 << 6) | OPC_DPAQ_W_QH_DSP
,
846 OPC_DPAQ_S_W_QH
= (0x04 << 6) | OPC_DPAQ_W_QH_DSP
,
847 OPC_DPAQ_SA_L_PW
= (0x0C << 6) | OPC_DPAQ_W_QH_DSP
,
848 OPC_DPAU_H_OBL
= (0x03 << 6) | OPC_DPAQ_W_QH_DSP
,
849 OPC_DPAU_H_OBR
= (0x07 << 6) | OPC_DPAQ_W_QH_DSP
,
850 OPC_DPS_W_QH
= (0x01 << 6) | OPC_DPAQ_W_QH_DSP
,
851 OPC_DPSQ_S_W_QH
= (0x05 << 6) | OPC_DPAQ_W_QH_DSP
,
852 OPC_DPSQ_SA_L_PW
= (0x0D << 6) | OPC_DPAQ_W_QH_DSP
,
853 OPC_DPSU_H_OBL
= (0x0B << 6) | OPC_DPAQ_W_QH_DSP
,
854 OPC_DPSU_H_OBR
= (0x0F << 6) | OPC_DPAQ_W_QH_DSP
,
855 OPC_MAQ_S_L_PWL
= (0x1C << 6) | OPC_DPAQ_W_QH_DSP
,
856 OPC_MAQ_S_L_PWR
= (0x1E << 6) | OPC_DPAQ_W_QH_DSP
,
857 OPC_MAQ_S_W_QHLL
= (0x14 << 6) | OPC_DPAQ_W_QH_DSP
,
858 OPC_MAQ_SA_W_QHLL
= (0x10 << 6) | OPC_DPAQ_W_QH_DSP
,
859 OPC_MAQ_S_W_QHLR
= (0x15 << 6) | OPC_DPAQ_W_QH_DSP
,
860 OPC_MAQ_SA_W_QHLR
= (0x11 << 6) | OPC_DPAQ_W_QH_DSP
,
861 OPC_MAQ_S_W_QHRL
= (0x16 << 6) | OPC_DPAQ_W_QH_DSP
,
862 OPC_MAQ_SA_W_QHRL
= (0x12 << 6) | OPC_DPAQ_W_QH_DSP
,
863 OPC_MAQ_S_W_QHRR
= (0x17 << 6) | OPC_DPAQ_W_QH_DSP
,
864 OPC_MAQ_SA_W_QHRR
= (0x13 << 6) | OPC_DPAQ_W_QH_DSP
,
865 OPC_MULSAQ_S_L_PW
= (0x0E << 6) | OPC_DPAQ_W_QH_DSP
,
866 OPC_MULSAQ_S_W_QH
= (0x06 << 6) | OPC_DPAQ_W_QH_DSP
,
869 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
871 /* MIPS DSP GPR-Based Shift Sub-class */
872 OPC_SHLL_PW
= (0x10 << 6) | OPC_SHLL_OB_DSP
,
873 OPC_SHLL_S_PW
= (0x14 << 6) | OPC_SHLL_OB_DSP
,
874 OPC_SHLLV_OB
= (0x02 << 6) | OPC_SHLL_OB_DSP
,
875 OPC_SHLLV_PW
= (0x12 << 6) | OPC_SHLL_OB_DSP
,
876 OPC_SHLLV_S_PW
= (0x16 << 6) | OPC_SHLL_OB_DSP
,
877 OPC_SHLLV_QH
= (0x0A << 6) | OPC_SHLL_OB_DSP
,
878 OPC_SHLLV_S_QH
= (0x0E << 6) | OPC_SHLL_OB_DSP
,
879 OPC_SHRA_PW
= (0x11 << 6) | OPC_SHLL_OB_DSP
,
880 OPC_SHRA_R_PW
= (0x15 << 6) | OPC_SHLL_OB_DSP
,
881 OPC_SHRAV_OB
= (0x06 << 6) | OPC_SHLL_OB_DSP
,
882 OPC_SHRAV_R_OB
= (0x07 << 6) | OPC_SHLL_OB_DSP
,
883 OPC_SHRAV_PW
= (0x13 << 6) | OPC_SHLL_OB_DSP
,
884 OPC_SHRAV_R_PW
= (0x17 << 6) | OPC_SHLL_OB_DSP
,
885 OPC_SHRAV_QH
= (0x0B << 6) | OPC_SHLL_OB_DSP
,
886 OPC_SHRAV_R_QH
= (0x0F << 6) | OPC_SHLL_OB_DSP
,
887 OPC_SHRLV_OB
= (0x03 << 6) | OPC_SHLL_OB_DSP
,
888 OPC_SHRLV_QH
= (0x1B << 6) | OPC_SHLL_OB_DSP
,
889 OPC_SHLL_OB
= (0x00 << 6) | OPC_SHLL_OB_DSP
,
890 OPC_SHLL_QH
= (0x08 << 6) | OPC_SHLL_OB_DSP
,
891 OPC_SHLL_S_QH
= (0x0C << 6) | OPC_SHLL_OB_DSP
,
892 OPC_SHRA_OB
= (0x04 << 6) | OPC_SHLL_OB_DSP
,
893 OPC_SHRA_R_OB
= (0x05 << 6) | OPC_SHLL_OB_DSP
,
894 OPC_SHRA_QH
= (0x09 << 6) | OPC_SHLL_OB_DSP
,
895 OPC_SHRA_R_QH
= (0x0D << 6) | OPC_SHLL_OB_DSP
,
896 OPC_SHRL_OB
= (0x01 << 6) | OPC_SHLL_OB_DSP
,
897 OPC_SHRL_QH
= (0x19 << 6) | OPC_SHLL_OB_DSP
,
900 /* Coprocessor 0 (rs field) */
901 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
904 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
905 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
906 OPC_MFHC0
= (0x02 << 21) | OPC_CP0
,
907 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
908 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
909 OPC_MTHC0
= (0x06 << 21) | OPC_CP0
,
910 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
911 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
912 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
913 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
914 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
915 OPC_C0
= (0x10 << 21) | OPC_CP0
,
916 OPC_C0_1
= (0x11 << 21) | OPC_CP0
,
917 OPC_C0_2
= (0x12 << 21) | OPC_CP0
,
918 OPC_C0_3
= (0x13 << 21) | OPC_CP0
,
919 OPC_C0_4
= (0x14 << 21) | OPC_CP0
,
920 OPC_C0_5
= (0x15 << 21) | OPC_CP0
,
921 OPC_C0_6
= (0x16 << 21) | OPC_CP0
,
922 OPC_C0_7
= (0x17 << 21) | OPC_CP0
,
923 OPC_C0_8
= (0x18 << 21) | OPC_CP0
,
924 OPC_C0_9
= (0x19 << 21) | OPC_CP0
,
925 OPC_C0_A
= (0x1A << 21) | OPC_CP0
,
926 OPC_C0_B
= (0x1B << 21) | OPC_CP0
,
927 OPC_C0_C
= (0x1C << 21) | OPC_CP0
,
928 OPC_C0_D
= (0x1D << 21) | OPC_CP0
,
929 OPC_C0_E
= (0x1E << 21) | OPC_CP0
,
930 OPC_C0_F
= (0x1F << 21) | OPC_CP0
,
934 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
937 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
938 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
939 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
940 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
941 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
942 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
943 OPC_DVP
= 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0
,
944 OPC_EVP
= 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0
,
947 /* Coprocessor 0 (with rs == C0) */
948 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
951 OPC_TLBR
= 0x01 | OPC_C0
,
952 OPC_TLBWI
= 0x02 | OPC_C0
,
953 OPC_TLBINV
= 0x03 | OPC_C0
,
954 OPC_TLBINVF
= 0x04 | OPC_C0
,
955 OPC_TLBWR
= 0x06 | OPC_C0
,
956 OPC_TLBP
= 0x08 | OPC_C0
,
957 OPC_RFE
= 0x10 | OPC_C0
,
958 OPC_ERET
= 0x18 | OPC_C0
,
959 OPC_DERET
= 0x1F | OPC_C0
,
960 OPC_WAIT
= 0x20 | OPC_C0
,
963 /* Coprocessor 1 (rs field) */
964 #define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
966 /* Values for the fmt field in FP instructions */
968 /* 0 - 15 are reserved */
969 FMT_S
= 16, /* single fp */
970 FMT_D
= 17, /* double fp */
971 FMT_E
= 18, /* extended fp */
972 FMT_Q
= 19, /* quad fp */
973 FMT_W
= 20, /* 32-bit fixed */
974 FMT_L
= 21, /* 64-bit fixed */
975 FMT_PS
= 22, /* paired single fp */
976 /* 23 - 31 are reserved */
980 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
981 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
982 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
983 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
984 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
985 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
986 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
987 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
988 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
989 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
990 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
991 OPC_BZ_V
= (0x0B << 21) | OPC_CP1
,
992 OPC_BNZ_V
= (0x0F << 21) | OPC_CP1
,
993 OPC_S_FMT
= (FMT_S
<< 21) | OPC_CP1
,
994 OPC_D_FMT
= (FMT_D
<< 21) | OPC_CP1
,
995 OPC_E_FMT
= (FMT_E
<< 21) | OPC_CP1
,
996 OPC_Q_FMT
= (FMT_Q
<< 21) | OPC_CP1
,
997 OPC_W_FMT
= (FMT_W
<< 21) | OPC_CP1
,
998 OPC_L_FMT
= (FMT_L
<< 21) | OPC_CP1
,
999 OPC_PS_FMT
= (FMT_PS
<< 21) | OPC_CP1
,
1000 OPC_BC1EQZ
= (0x09 << 21) | OPC_CP1
,
1001 OPC_BC1NEZ
= (0x0D << 21) | OPC_CP1
,
1002 OPC_BZ_B
= (0x18 << 21) | OPC_CP1
,
1003 OPC_BZ_H
= (0x19 << 21) | OPC_CP1
,
1004 OPC_BZ_W
= (0x1A << 21) | OPC_CP1
,
1005 OPC_BZ_D
= (0x1B << 21) | OPC_CP1
,
1006 OPC_BNZ_B
= (0x1C << 21) | OPC_CP1
,
1007 OPC_BNZ_H
= (0x1D << 21) | OPC_CP1
,
1008 OPC_BNZ_W
= (0x1E << 21) | OPC_CP1
,
1009 OPC_BNZ_D
= (0x1F << 21) | OPC_CP1
,
1012 #define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
1013 #define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
1016 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
1017 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
1018 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
1019 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
1023 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
1024 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
1028 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
1029 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
1032 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
1035 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
1036 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
1037 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
1038 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
1039 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
1040 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
1041 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
1042 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
1043 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
1044 OPC_BC2EQZ
= (0x09 << 21) | OPC_CP2
,
1045 OPC_BC2NEZ
= (0x0D << 21) | OPC_CP2
,
1048 #define MASK_LMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1051 OPC_PADDSH
= (24 << 21) | (0x00) | OPC_CP2
,
1052 OPC_PADDUSH
= (25 << 21) | (0x00) | OPC_CP2
,
1053 OPC_PADDH
= (26 << 21) | (0x00) | OPC_CP2
,
1054 OPC_PADDW
= (27 << 21) | (0x00) | OPC_CP2
,
1055 OPC_PADDSB
= (28 << 21) | (0x00) | OPC_CP2
,
1056 OPC_PADDUSB
= (29 << 21) | (0x00) | OPC_CP2
,
1057 OPC_PADDB
= (30 << 21) | (0x00) | OPC_CP2
,
1058 OPC_PADDD
= (31 << 21) | (0x00) | OPC_CP2
,
1060 OPC_PSUBSH
= (24 << 21) | (0x01) | OPC_CP2
,
1061 OPC_PSUBUSH
= (25 << 21) | (0x01) | OPC_CP2
,
1062 OPC_PSUBH
= (26 << 21) | (0x01) | OPC_CP2
,
1063 OPC_PSUBW
= (27 << 21) | (0x01) | OPC_CP2
,
1064 OPC_PSUBSB
= (28 << 21) | (0x01) | OPC_CP2
,
1065 OPC_PSUBUSB
= (29 << 21) | (0x01) | OPC_CP2
,
1066 OPC_PSUBB
= (30 << 21) | (0x01) | OPC_CP2
,
1067 OPC_PSUBD
= (31 << 21) | (0x01) | OPC_CP2
,
1069 OPC_PSHUFH
= (24 << 21) | (0x02) | OPC_CP2
,
1070 OPC_PACKSSWH
= (25 << 21) | (0x02) | OPC_CP2
,
1071 OPC_PACKSSHB
= (26 << 21) | (0x02) | OPC_CP2
,
1072 OPC_PACKUSHB
= (27 << 21) | (0x02) | OPC_CP2
,
1073 OPC_XOR_CP2
= (28 << 21) | (0x02) | OPC_CP2
,
1074 OPC_NOR_CP2
= (29 << 21) | (0x02) | OPC_CP2
,
1075 OPC_AND_CP2
= (30 << 21) | (0x02) | OPC_CP2
,
1076 OPC_PANDN
= (31 << 21) | (0x02) | OPC_CP2
,
1078 OPC_PUNPCKLHW
= (24 << 21) | (0x03) | OPC_CP2
,
1079 OPC_PUNPCKHHW
= (25 << 21) | (0x03) | OPC_CP2
,
1080 OPC_PUNPCKLBH
= (26 << 21) | (0x03) | OPC_CP2
,
1081 OPC_PUNPCKHBH
= (27 << 21) | (0x03) | OPC_CP2
,
1082 OPC_PINSRH_0
= (28 << 21) | (0x03) | OPC_CP2
,
1083 OPC_PINSRH_1
= (29 << 21) | (0x03) | OPC_CP2
,
1084 OPC_PINSRH_2
= (30 << 21) | (0x03) | OPC_CP2
,
1085 OPC_PINSRH_3
= (31 << 21) | (0x03) | OPC_CP2
,
1087 OPC_PAVGH
= (24 << 21) | (0x08) | OPC_CP2
,
1088 OPC_PAVGB
= (25 << 21) | (0x08) | OPC_CP2
,
1089 OPC_PMAXSH
= (26 << 21) | (0x08) | OPC_CP2
,
1090 OPC_PMINSH
= (27 << 21) | (0x08) | OPC_CP2
,
1091 OPC_PMAXUB
= (28 << 21) | (0x08) | OPC_CP2
,
1092 OPC_PMINUB
= (29 << 21) | (0x08) | OPC_CP2
,
1094 OPC_PCMPEQW
= (24 << 21) | (0x09) | OPC_CP2
,
1095 OPC_PCMPGTW
= (25 << 21) | (0x09) | OPC_CP2
,
1096 OPC_PCMPEQH
= (26 << 21) | (0x09) | OPC_CP2
,
1097 OPC_PCMPGTH
= (27 << 21) | (0x09) | OPC_CP2
,
1098 OPC_PCMPEQB
= (28 << 21) | (0x09) | OPC_CP2
,
1099 OPC_PCMPGTB
= (29 << 21) | (0x09) | OPC_CP2
,
1101 OPC_PSLLW
= (24 << 21) | (0x0A) | OPC_CP2
,
1102 OPC_PSLLH
= (25 << 21) | (0x0A) | OPC_CP2
,
1103 OPC_PMULLH
= (26 << 21) | (0x0A) | OPC_CP2
,
1104 OPC_PMULHH
= (27 << 21) | (0x0A) | OPC_CP2
,
1105 OPC_PMULUW
= (28 << 21) | (0x0A) | OPC_CP2
,
1106 OPC_PMULHUH
= (29 << 21) | (0x0A) | OPC_CP2
,
1108 OPC_PSRLW
= (24 << 21) | (0x0B) | OPC_CP2
,
1109 OPC_PSRLH
= (25 << 21) | (0x0B) | OPC_CP2
,
1110 OPC_PSRAW
= (26 << 21) | (0x0B) | OPC_CP2
,
1111 OPC_PSRAH
= (27 << 21) | (0x0B) | OPC_CP2
,
1112 OPC_PUNPCKLWD
= (28 << 21) | (0x0B) | OPC_CP2
,
1113 OPC_PUNPCKHWD
= (29 << 21) | (0x0B) | OPC_CP2
,
1115 OPC_ADDU_CP2
= (24 << 21) | (0x0C) | OPC_CP2
,
1116 OPC_OR_CP2
= (25 << 21) | (0x0C) | OPC_CP2
,
1117 OPC_ADD_CP2
= (26 << 21) | (0x0C) | OPC_CP2
,
1118 OPC_DADD_CP2
= (27 << 21) | (0x0C) | OPC_CP2
,
1119 OPC_SEQU_CP2
= (28 << 21) | (0x0C) | OPC_CP2
,
1120 OPC_SEQ_CP2
= (29 << 21) | (0x0C) | OPC_CP2
,
1122 OPC_SUBU_CP2
= (24 << 21) | (0x0D) | OPC_CP2
,
1123 OPC_PASUBUB
= (25 << 21) | (0x0D) | OPC_CP2
,
1124 OPC_SUB_CP2
= (26 << 21) | (0x0D) | OPC_CP2
,
1125 OPC_DSUB_CP2
= (27 << 21) | (0x0D) | OPC_CP2
,
1126 OPC_SLTU_CP2
= (28 << 21) | (0x0D) | OPC_CP2
,
1127 OPC_SLT_CP2
= (29 << 21) | (0x0D) | OPC_CP2
,
1129 OPC_SLL_CP2
= (24 << 21) | (0x0E) | OPC_CP2
,
1130 OPC_DSLL_CP2
= (25 << 21) | (0x0E) | OPC_CP2
,
1131 OPC_PEXTRH
= (26 << 21) | (0x0E) | OPC_CP2
,
1132 OPC_PMADDHW
= (27 << 21) | (0x0E) | OPC_CP2
,
1133 OPC_SLEU_CP2
= (28 << 21) | (0x0E) | OPC_CP2
,
1134 OPC_SLE_CP2
= (29 << 21) | (0x0E) | OPC_CP2
,
1136 OPC_SRL_CP2
= (24 << 21) | (0x0F) | OPC_CP2
,
1137 OPC_DSRL_CP2
= (25 << 21) | (0x0F) | OPC_CP2
,
1138 OPC_SRA_CP2
= (26 << 21) | (0x0F) | OPC_CP2
,
1139 OPC_DSRA_CP2
= (27 << 21) | (0x0F) | OPC_CP2
,
1140 OPC_BIADD
= (28 << 21) | (0x0F) | OPC_CP2
,
1141 OPC_PMOVMSKB
= (29 << 21) | (0x0F) | OPC_CP2
,
1145 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1148 OPC_LWXC1
= 0x00 | OPC_CP3
,
1149 OPC_LDXC1
= 0x01 | OPC_CP3
,
1150 OPC_LUXC1
= 0x05 | OPC_CP3
,
1151 OPC_SWXC1
= 0x08 | OPC_CP3
,
1152 OPC_SDXC1
= 0x09 | OPC_CP3
,
1153 OPC_SUXC1
= 0x0D | OPC_CP3
,
1154 OPC_PREFX
= 0x0F | OPC_CP3
,
1155 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
1156 OPC_MADD_S
= 0x20 | OPC_CP3
,
1157 OPC_MADD_D
= 0x21 | OPC_CP3
,
1158 OPC_MADD_PS
= 0x26 | OPC_CP3
,
1159 OPC_MSUB_S
= 0x28 | OPC_CP3
,
1160 OPC_MSUB_D
= 0x29 | OPC_CP3
,
1161 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
1162 OPC_NMADD_S
= 0x30 | OPC_CP3
,
1163 OPC_NMADD_D
= 0x31 | OPC_CP3
,
1164 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
1165 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
1166 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
1167 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
1171 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1173 OPC_MSA_I8_00
= 0x00 | OPC_MSA
,
1174 OPC_MSA_I8_01
= 0x01 | OPC_MSA
,
1175 OPC_MSA_I8_02
= 0x02 | OPC_MSA
,
1176 OPC_MSA_I5_06
= 0x06 | OPC_MSA
,
1177 OPC_MSA_I5_07
= 0x07 | OPC_MSA
,
1178 OPC_MSA_BIT_09
= 0x09 | OPC_MSA
,
1179 OPC_MSA_BIT_0A
= 0x0A | OPC_MSA
,
1180 OPC_MSA_3R_0D
= 0x0D | OPC_MSA
,
1181 OPC_MSA_3R_0E
= 0x0E | OPC_MSA
,
1182 OPC_MSA_3R_0F
= 0x0F | OPC_MSA
,
1183 OPC_MSA_3R_10
= 0x10 | OPC_MSA
,
1184 OPC_MSA_3R_11
= 0x11 | OPC_MSA
,
1185 OPC_MSA_3R_12
= 0x12 | OPC_MSA
,
1186 OPC_MSA_3R_13
= 0x13 | OPC_MSA
,
1187 OPC_MSA_3R_14
= 0x14 | OPC_MSA
,
1188 OPC_MSA_3R_15
= 0x15 | OPC_MSA
,
1189 OPC_MSA_ELM
= 0x19 | OPC_MSA
,
1190 OPC_MSA_3RF_1A
= 0x1A | OPC_MSA
,
1191 OPC_MSA_3RF_1B
= 0x1B | OPC_MSA
,
1192 OPC_MSA_3RF_1C
= 0x1C | OPC_MSA
,
1193 OPC_MSA_VEC
= 0x1E | OPC_MSA
,
1195 /* MI10 instruction */
1196 OPC_LD_B
= (0x20) | OPC_MSA
,
1197 OPC_LD_H
= (0x21) | OPC_MSA
,
1198 OPC_LD_W
= (0x22) | OPC_MSA
,
1199 OPC_LD_D
= (0x23) | OPC_MSA
,
1200 OPC_ST_B
= (0x24) | OPC_MSA
,
1201 OPC_ST_H
= (0x25) | OPC_MSA
,
1202 OPC_ST_W
= (0x26) | OPC_MSA
,
1203 OPC_ST_D
= (0x27) | OPC_MSA
,
1207 /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
1208 OPC_ADDVI_df
= (0x0 << 23) | OPC_MSA_I5_06
,
1209 OPC_CEQI_df
= (0x0 << 23) | OPC_MSA_I5_07
,
1210 OPC_SUBVI_df
= (0x1 << 23) | OPC_MSA_I5_06
,
1211 OPC_MAXI_S_df
= (0x2 << 23) | OPC_MSA_I5_06
,
1212 OPC_CLTI_S_df
= (0x2 << 23) | OPC_MSA_I5_07
,
1213 OPC_MAXI_U_df
= (0x3 << 23) | OPC_MSA_I5_06
,
1214 OPC_CLTI_U_df
= (0x3 << 23) | OPC_MSA_I5_07
,
1215 OPC_MINI_S_df
= (0x4 << 23) | OPC_MSA_I5_06
,
1216 OPC_CLEI_S_df
= (0x4 << 23) | OPC_MSA_I5_07
,
1217 OPC_MINI_U_df
= (0x5 << 23) | OPC_MSA_I5_06
,
1218 OPC_CLEI_U_df
= (0x5 << 23) | OPC_MSA_I5_07
,
1219 OPC_LDI_df
= (0x6 << 23) | OPC_MSA_I5_07
,
1221 /* I8 instruction */
1222 OPC_ANDI_B
= (0x0 << 24) | OPC_MSA_I8_00
,
1223 OPC_BMNZI_B
= (0x0 << 24) | OPC_MSA_I8_01
,
1224 OPC_SHF_B
= (0x0 << 24) | OPC_MSA_I8_02
,
1225 OPC_ORI_B
= (0x1 << 24) | OPC_MSA_I8_00
,
1226 OPC_BMZI_B
= (0x1 << 24) | OPC_MSA_I8_01
,
1227 OPC_SHF_H
= (0x1 << 24) | OPC_MSA_I8_02
,
1228 OPC_NORI_B
= (0x2 << 24) | OPC_MSA_I8_00
,
1229 OPC_BSELI_B
= (0x2 << 24) | OPC_MSA_I8_01
,
1230 OPC_SHF_W
= (0x2 << 24) | OPC_MSA_I8_02
,
1231 OPC_XORI_B
= (0x3 << 24) | OPC_MSA_I8_00
,
1233 /* VEC/2R/2RF instruction */
1234 OPC_AND_V
= (0x00 << 21) | OPC_MSA_VEC
,
1235 OPC_OR_V
= (0x01 << 21) | OPC_MSA_VEC
,
1236 OPC_NOR_V
= (0x02 << 21) | OPC_MSA_VEC
,
1237 OPC_XOR_V
= (0x03 << 21) | OPC_MSA_VEC
,
1238 OPC_BMNZ_V
= (0x04 << 21) | OPC_MSA_VEC
,
1239 OPC_BMZ_V
= (0x05 << 21) | OPC_MSA_VEC
,
1240 OPC_BSEL_V
= (0x06 << 21) | OPC_MSA_VEC
,
1242 OPC_MSA_2R
= (0x18 << 21) | OPC_MSA_VEC
,
1243 OPC_MSA_2RF
= (0x19 << 21) | OPC_MSA_VEC
,
1245 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
1246 OPC_FILL_df
= (0x00 << 18) | OPC_MSA_2R
,
1247 OPC_PCNT_df
= (0x01 << 18) | OPC_MSA_2R
,
1248 OPC_NLOC_df
= (0x02 << 18) | OPC_MSA_2R
,
1249 OPC_NLZC_df
= (0x03 << 18) | OPC_MSA_2R
,
1251 /* 2RF instruction df(bit 16) = _w, _d */
1252 OPC_FCLASS_df
= (0x00 << 17) | OPC_MSA_2RF
,
1253 OPC_FTRUNC_S_df
= (0x01 << 17) | OPC_MSA_2RF
,
1254 OPC_FTRUNC_U_df
= (0x02 << 17) | OPC_MSA_2RF
,
1255 OPC_FSQRT_df
= (0x03 << 17) | OPC_MSA_2RF
,
1256 OPC_FRSQRT_df
= (0x04 << 17) | OPC_MSA_2RF
,
1257 OPC_FRCP_df
= (0x05 << 17) | OPC_MSA_2RF
,
1258 OPC_FRINT_df
= (0x06 << 17) | OPC_MSA_2RF
,
1259 OPC_FLOG2_df
= (0x07 << 17) | OPC_MSA_2RF
,
1260 OPC_FEXUPL_df
= (0x08 << 17) | OPC_MSA_2RF
,
1261 OPC_FEXUPR_df
= (0x09 << 17) | OPC_MSA_2RF
,
1262 OPC_FFQL_df
= (0x0A << 17) | OPC_MSA_2RF
,
1263 OPC_FFQR_df
= (0x0B << 17) | OPC_MSA_2RF
,
1264 OPC_FTINT_S_df
= (0x0C << 17) | OPC_MSA_2RF
,
1265 OPC_FTINT_U_df
= (0x0D << 17) | OPC_MSA_2RF
,
1266 OPC_FFINT_S_df
= (0x0E << 17) | OPC_MSA_2RF
,
1267 OPC_FFINT_U_df
= (0x0F << 17) | OPC_MSA_2RF
,
1269 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
1270 OPC_SLL_df
= (0x0 << 23) | OPC_MSA_3R_0D
,
1271 OPC_ADDV_df
= (0x0 << 23) | OPC_MSA_3R_0E
,
1272 OPC_CEQ_df
= (0x0 << 23) | OPC_MSA_3R_0F
,
1273 OPC_ADD_A_df
= (0x0 << 23) | OPC_MSA_3R_10
,
1274 OPC_SUBS_S_df
= (0x0 << 23) | OPC_MSA_3R_11
,
1275 OPC_MULV_df
= (0x0 << 23) | OPC_MSA_3R_12
,
1276 OPC_DOTP_S_df
= (0x0 << 23) | OPC_MSA_3R_13
,
1277 OPC_SLD_df
= (0x0 << 23) | OPC_MSA_3R_14
,
1278 OPC_VSHF_df
= (0x0 << 23) | OPC_MSA_3R_15
,
1279 OPC_SRA_df
= (0x1 << 23) | OPC_MSA_3R_0D
,
1280 OPC_SUBV_df
= (0x1 << 23) | OPC_MSA_3R_0E
,
1281 OPC_ADDS_A_df
= (0x1 << 23) | OPC_MSA_3R_10
,
1282 OPC_SUBS_U_df
= (0x1 << 23) | OPC_MSA_3R_11
,
1283 OPC_MADDV_df
= (0x1 << 23) | OPC_MSA_3R_12
,
1284 OPC_DOTP_U_df
= (0x1 << 23) | OPC_MSA_3R_13
,
1285 OPC_SPLAT_df
= (0x1 << 23) | OPC_MSA_3R_14
,
1286 OPC_SRAR_df
= (0x1 << 23) | OPC_MSA_3R_15
,
1287 OPC_SRL_df
= (0x2 << 23) | OPC_MSA_3R_0D
,
1288 OPC_MAX_S_df
= (0x2 << 23) | OPC_MSA_3R_0E
,
1289 OPC_CLT_S_df
= (0x2 << 23) | OPC_MSA_3R_0F
,
1290 OPC_ADDS_S_df
= (0x2 << 23) | OPC_MSA_3R_10
,
1291 OPC_SUBSUS_U_df
= (0x2 << 23) | OPC_MSA_3R_11
,
1292 OPC_MSUBV_df
= (0x2 << 23) | OPC_MSA_3R_12
,
1293 OPC_DPADD_S_df
= (0x2 << 23) | OPC_MSA_3R_13
,
1294 OPC_PCKEV_df
= (0x2 << 23) | OPC_MSA_3R_14
,
1295 OPC_SRLR_df
= (0x2 << 23) | OPC_MSA_3R_15
,
1296 OPC_BCLR_df
= (0x3 << 23) | OPC_MSA_3R_0D
,
1297 OPC_MAX_U_df
= (0x3 << 23) | OPC_MSA_3R_0E
,
1298 OPC_CLT_U_df
= (0x3 << 23) | OPC_MSA_3R_0F
,
1299 OPC_ADDS_U_df
= (0x3 << 23) | OPC_MSA_3R_10
,
1300 OPC_SUBSUU_S_df
= (0x3 << 23) | OPC_MSA_3R_11
,
1301 OPC_DPADD_U_df
= (0x3 << 23) | OPC_MSA_3R_13
,
1302 OPC_PCKOD_df
= (0x3 << 23) | OPC_MSA_3R_14
,
1303 OPC_BSET_df
= (0x4 << 23) | OPC_MSA_3R_0D
,
1304 OPC_MIN_S_df
= (0x4 << 23) | OPC_MSA_3R_0E
,
1305 OPC_CLE_S_df
= (0x4 << 23) | OPC_MSA_3R_0F
,
1306 OPC_AVE_S_df
= (0x4 << 23) | OPC_MSA_3R_10
,
1307 OPC_ASUB_S_df
= (0x4 << 23) | OPC_MSA_3R_11
,
1308 OPC_DIV_S_df
= (0x4 << 23) | OPC_MSA_3R_12
,
1309 OPC_DPSUB_S_df
= (0x4 << 23) | OPC_MSA_3R_13
,
1310 OPC_ILVL_df
= (0x4 << 23) | OPC_MSA_3R_14
,
1311 OPC_HADD_S_df
= (0x4 << 23) | OPC_MSA_3R_15
,
1312 OPC_BNEG_df
= (0x5 << 23) | OPC_MSA_3R_0D
,
1313 OPC_MIN_U_df
= (0x5 << 23) | OPC_MSA_3R_0E
,
1314 OPC_CLE_U_df
= (0x5 << 23) | OPC_MSA_3R_0F
,
1315 OPC_AVE_U_df
= (0x5 << 23) | OPC_MSA_3R_10
,
1316 OPC_ASUB_U_df
= (0x5 << 23) | OPC_MSA_3R_11
,
1317 OPC_DIV_U_df
= (0x5 << 23) | OPC_MSA_3R_12
,
1318 OPC_DPSUB_U_df
= (0x5 << 23) | OPC_MSA_3R_13
,
1319 OPC_ILVR_df
= (0x5 << 23) | OPC_MSA_3R_14
,
1320 OPC_HADD_U_df
= (0x5 << 23) | OPC_MSA_3R_15
,
1321 OPC_BINSL_df
= (0x6 << 23) | OPC_MSA_3R_0D
,
1322 OPC_MAX_A_df
= (0x6 << 23) | OPC_MSA_3R_0E
,
1323 OPC_AVER_S_df
= (0x6 << 23) | OPC_MSA_3R_10
,
1324 OPC_MOD_S_df
= (0x6 << 23) | OPC_MSA_3R_12
,
1325 OPC_ILVEV_df
= (0x6 << 23) | OPC_MSA_3R_14
,
1326 OPC_HSUB_S_df
= (0x6 << 23) | OPC_MSA_3R_15
,
1327 OPC_BINSR_df
= (0x7 << 23) | OPC_MSA_3R_0D
,
1328 OPC_MIN_A_df
= (0x7 << 23) | OPC_MSA_3R_0E
,
1329 OPC_AVER_U_df
= (0x7 << 23) | OPC_MSA_3R_10
,
1330 OPC_MOD_U_df
= (0x7 << 23) | OPC_MSA_3R_12
,
1331 OPC_ILVOD_df
= (0x7 << 23) | OPC_MSA_3R_14
,
1332 OPC_HSUB_U_df
= (0x7 << 23) | OPC_MSA_3R_15
,
1334 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
1335 OPC_SLDI_df
= (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1336 OPC_CTCMSA
= (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
1337 OPC_SPLATI_df
= (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1338 OPC_CFCMSA
= (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
1339 OPC_COPY_S_df
= (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1340 OPC_MOVE_V
= (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
1341 OPC_COPY_U_df
= (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1342 OPC_INSERT_df
= (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1343 OPC_INSVE_df
= (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1345 /* 3RF instruction _df(bit 21) = _w, _d */
1346 OPC_FCAF_df
= (0x0 << 22) | OPC_MSA_3RF_1A
,
1347 OPC_FADD_df
= (0x0 << 22) | OPC_MSA_3RF_1B
,
1348 OPC_FCUN_df
= (0x1 << 22) | OPC_MSA_3RF_1A
,
1349 OPC_FSUB_df
= (0x1 << 22) | OPC_MSA_3RF_1B
,
1350 OPC_FCOR_df
= (0x1 << 22) | OPC_MSA_3RF_1C
,
1351 OPC_FCEQ_df
= (0x2 << 22) | OPC_MSA_3RF_1A
,
1352 OPC_FMUL_df
= (0x2 << 22) | OPC_MSA_3RF_1B
,
1353 OPC_FCUNE_df
= (0x2 << 22) | OPC_MSA_3RF_1C
,
1354 OPC_FCUEQ_df
= (0x3 << 22) | OPC_MSA_3RF_1A
,
1355 OPC_FDIV_df
= (0x3 << 22) | OPC_MSA_3RF_1B
,
1356 OPC_FCNE_df
= (0x3 << 22) | OPC_MSA_3RF_1C
,
1357 OPC_FCLT_df
= (0x4 << 22) | OPC_MSA_3RF_1A
,
1358 OPC_FMADD_df
= (0x4 << 22) | OPC_MSA_3RF_1B
,
1359 OPC_MUL_Q_df
= (0x4 << 22) | OPC_MSA_3RF_1C
,
1360 OPC_FCULT_df
= (0x5 << 22) | OPC_MSA_3RF_1A
,
1361 OPC_FMSUB_df
= (0x5 << 22) | OPC_MSA_3RF_1B
,
1362 OPC_MADD_Q_df
= (0x5 << 22) | OPC_MSA_3RF_1C
,
1363 OPC_FCLE_df
= (0x6 << 22) | OPC_MSA_3RF_1A
,
1364 OPC_MSUB_Q_df
= (0x6 << 22) | OPC_MSA_3RF_1C
,
1365 OPC_FCULE_df
= (0x7 << 22) | OPC_MSA_3RF_1A
,
1366 OPC_FEXP2_df
= (0x7 << 22) | OPC_MSA_3RF_1B
,
1367 OPC_FSAF_df
= (0x8 << 22) | OPC_MSA_3RF_1A
,
1368 OPC_FEXDO_df
= (0x8 << 22) | OPC_MSA_3RF_1B
,
1369 OPC_FSUN_df
= (0x9 << 22) | OPC_MSA_3RF_1A
,
1370 OPC_FSOR_df
= (0x9 << 22) | OPC_MSA_3RF_1C
,
1371 OPC_FSEQ_df
= (0xA << 22) | OPC_MSA_3RF_1A
,
1372 OPC_FTQ_df
= (0xA << 22) | OPC_MSA_3RF_1B
,
1373 OPC_FSUNE_df
= (0xA << 22) | OPC_MSA_3RF_1C
,
1374 OPC_FSUEQ_df
= (0xB << 22) | OPC_MSA_3RF_1A
,
1375 OPC_FSNE_df
= (0xB << 22) | OPC_MSA_3RF_1C
,
1376 OPC_FSLT_df
= (0xC << 22) | OPC_MSA_3RF_1A
,
1377 OPC_FMIN_df
= (0xC << 22) | OPC_MSA_3RF_1B
,
1378 OPC_MULR_Q_df
= (0xC << 22) | OPC_MSA_3RF_1C
,
1379 OPC_FSULT_df
= (0xD << 22) | OPC_MSA_3RF_1A
,
1380 OPC_FMIN_A_df
= (0xD << 22) | OPC_MSA_3RF_1B
,
1381 OPC_MADDR_Q_df
= (0xD << 22) | OPC_MSA_3RF_1C
,
1382 OPC_FSLE_df
= (0xE << 22) | OPC_MSA_3RF_1A
,
1383 OPC_FMAX_df
= (0xE << 22) | OPC_MSA_3RF_1B
,
1384 OPC_MSUBR_Q_df
= (0xE << 22) | OPC_MSA_3RF_1C
,
1385 OPC_FSULE_df
= (0xF << 22) | OPC_MSA_3RF_1A
,
1386 OPC_FMAX_A_df
= (0xF << 22) | OPC_MSA_3RF_1B
,
1388 /* BIT instruction df(bits 22..16) = _B _H _W _D */
1389 OPC_SLLI_df
= (0x0 << 23) | OPC_MSA_BIT_09
,
1390 OPC_SAT_S_df
= (0x0 << 23) | OPC_MSA_BIT_0A
,
1391 OPC_SRAI_df
= (0x1 << 23) | OPC_MSA_BIT_09
,
1392 OPC_SAT_U_df
= (0x1 << 23) | OPC_MSA_BIT_0A
,
1393 OPC_SRLI_df
= (0x2 << 23) | OPC_MSA_BIT_09
,
1394 OPC_SRARI_df
= (0x2 << 23) | OPC_MSA_BIT_0A
,
1395 OPC_BCLRI_df
= (0x3 << 23) | OPC_MSA_BIT_09
,
1396 OPC_SRLRI_df
= (0x3 << 23) | OPC_MSA_BIT_0A
,
1397 OPC_BSETI_df
= (0x4 << 23) | OPC_MSA_BIT_09
,
1398 OPC_BNEGI_df
= (0x5 << 23) | OPC_MSA_BIT_09
,
1399 OPC_BINSLI_df
= (0x6 << 23) | OPC_MSA_BIT_09
,
1400 OPC_BINSRI_df
= (0x7 << 23) | OPC_MSA_BIT_09
,
1406 * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
1407 * ============================================
1410 * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MIPS32
1411 * instructions set. It is designed to fit the needs of signal, graphical and
1412 * video processing applications. MXU instruction set is used in Xburst family
1413 * of microprocessors by Ingenic.
1415 * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
1416 * the control register.
1419 * The notation used in MXU assembler mnemonics
1420 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1422 * Register operands:
1424 * XRa, XRb, XRc, XRd - MXU registers
1425 * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
1427 * Non-register operands:
1429 * aptn1 - 1-bit accumulate add/subtract pattern
1430 * aptn2 - 2-bit accumulate add/subtract pattern
1431 * eptn2 - 2-bit execute add/subtract pattern
1432 * optn2 - 2-bit operand pattern
1433 * optn3 - 3-bit operand pattern
1434 * sft4 - 4-bit shift amount
1435 * strd2 - 2-bit stride amount
1439 * Level of parallelism: Operand size:
1440 * S - single operation at a time 32 - word
1441 * D - two operations in parallel 16 - half word
1442 * Q - four operations in parallel 8 - byte
1446 * ADD - Add or subtract
1447 * ADDC - Add with carry-in
1449 * ASUM - Sum together then accumulate (add or subtract)
1450 * ASUMC - Sum together then accumulate (add or subtract) with carry-in
1451 * AVG - Average between 2 operands
1452 * ABD - Absolute difference
1454 * AND - Logical bitwise 'and' operation
1456 * EXTR - Extract bits
1457 * I2M - Move from GPR register to MXU register
1458 * LDD - Load data from memory to XRF
1459 * LDI - Load data from memory to XRF (and increase the address base)
1460 * LUI - Load unsigned immediate
1462 * MULU - Unsigned multiply
1463 * MADD - 64-bit operand add 32x32 product
1464 * MSUB - 64-bit operand subtract 32x32 product
1465 * MAC - Multiply and accumulate (add or subtract)
1466 * MAD - Multiply and add or subtract
1467 * MAX - Maximum between 2 operands
1468 * MIN - Minimum between 2 operands
1469 * M2I - Move from MXU register to GPR register
1470 * MOVZ - Move if zero
1471 * MOVN - Move if non-zero
1472 * NOR - Logical bitwise 'nor' operation
1473 * OR - Logical bitwise 'or' operation
1474 * STD - Store data from XRF to memory
1475 * SDI - Store data from XRF to memory (and increase the address base)
1476 * SLT - Set of less than comparison
1477 * SAD - Sum of absolute differences
1478 * SLL - Logical shift left
1479 * SLR - Logical shift right
1480 * SAR - Arithmetic shift right
1483 * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0)
1484 * XOR - Logical bitwise 'exclusive or' operation
1488 * E - Expand results
1489 * F - Fixed point multiplication
1490 * L - Low part result
1491 * R - Doing rounding
1492 * V - Variable instead of immediate
1493 * W - Combine above L and V
1496 * The list of MXU instructions grouped by functionality
1497 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1499 * Load/Store instructions Multiplication instructions
1500 * ----------------------- ---------------------------
1502 * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt
1503 * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt
1504 * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt
1505 * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt
1506 * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt
1507 * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt
1508 * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2
1509 * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2
1510 * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2
1511 * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, optn2
1512 * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, optn2
1513 * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, optn2
1514 * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, optn2
1515 * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, optn2
1516 * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd
1517 * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd
1518 * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2
1519 * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2
1520 * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2
1521 * S16SDI XRa, Rb, s10, eptn2
1522 * S8LDD XRa, Rb, s8, eptn3
1523 * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions
1524 * S8LDI XRa, Rb, s8, eptn3 -------------------------------------
1525 * S8SDI XRa, Rb, s8, eptn3
1526 * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2
1527 * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd
1528 * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2
1529 * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2
1530 * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2
1531 * S32CPS XRa, XRb, XRc
1532 * Q16ADD XRa, XRb, XRc, XRd, eptn2, optn2
1533 * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2
1534 * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2
1535 * D16ASUM XRa, XRb, XRc, XRd, eptn2
1536 * S32MAX XRa, XRb, XRc D16CPS XRa, XRb,
1537 * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc
1538 * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc
1539 * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2
1540 * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2
1541 * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2
1542 * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc
1543 * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd
1544 * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc
1545 * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc
1546 * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd
1547 * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd
1548 * Q8SLT XRa, XRb, XRc
1549 * Q8SLTU XRa, XRb, XRc
1550 * Q8MOVZ XRa, XRb, XRc Shift instructions
1551 * Q8MOVN XRa, XRb, XRc ------------------
1553 * D32SLL XRa, XRb, XRc, XRd, sft4
1554 * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4
1555 * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4
1556 * D32SARL XRa, XRb, XRc, sft4
1557 * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb
1558 * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb
1559 * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb
1560 * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb
1561 * Q16SLL XRa, XRb, XRc, XRd, sft4
1562 * Q16SLR XRa, XRb, XRc, XRd, sft4
1563 * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4
1564 * ------------------------- Q16SLLV XRa, XRb, Rb
1565 * Q16SLRV XRa, XRb, Rb
1566 * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb
1567 * S32ALN XRa, XRb, XRc, Rb
1568 * S32ALNI XRa, XRb, XRc, s3
1569 * S32LUI XRa, s8, optn3 Move instructions
1570 * S32EXTR XRa, XRb, Rb, bits5 -----------------
1571 * S32EXTRV XRa, XRb, Rs, Rt
1572 * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
1573 * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
1576 * The opcode organization of MXU instructions
1577 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1579 * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred
1580 * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of
1581 * other bits up to the instruction level is as follows:
1586 * ┌─ 000000 ─ OPC_MXU_S32MADD
1587 * ├─ 000001 ─ OPC_MXU_S32MADDU
1588 * ├─ 000010 ─ <not assigned> (non-MXU OPC_MUL)
1591 * ├─ 000011 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
1592 * │ ├─ 001 ─ OPC_MXU_S32MIN
1593 * │ ├─ 010 ─ OPC_MXU_D16MAX
1594 * │ ├─ 011 ─ OPC_MXU_D16MIN
1595 * │ ├─ 100 ─ OPC_MXU_Q8MAX
1596 * │ ├─ 101 ─ OPC_MXU_Q8MIN
1597 * │ ├─ 110 ─ OPC_MXU_Q8SLT
1598 * │ └─ 111 ─ OPC_MXU_Q8SLTU
1599 * ├─ 000100 ─ OPC_MXU_S32MSUB
1600 * ├─ 000101 ─ OPC_MXU_S32MSUBU 20..18
1601 * ├─ 000110 ─ OPC_MXU__POOL01 ─┬─ 000 ─ OPC_MXU_S32SLT
1602 * │ ├─ 001 ─ OPC_MXU_D16SLT
1603 * │ ├─ 010 ─ OPC_MXU_D16AVG
1604 * │ ├─ 011 ─ OPC_MXU_D16AVGR
1605 * │ ├─ 100 ─ OPC_MXU_Q8AVG
1606 * │ ├─ 101 ─ OPC_MXU_Q8AVGR
1607 * │ └─ 111 ─ OPC_MXU_Q8ADD
1610 * ├─ 000111 ─ OPC_MXU__POOL02 ─┬─ 000 ─ OPC_MXU_S32CPS
1611 * │ ├─ 010 ─ OPC_MXU_D16CPS
1612 * │ ├─ 100 ─ OPC_MXU_Q8ABD
1613 * │ └─ 110 ─ OPC_MXU_Q16SAT
1614 * ├─ 001000 ─ OPC_MXU_D16MUL
1616 * ├─ 001001 ─ OPC_MXU__POOL03 ─┬─ 00 ─ OPC_MXU_D16MULF
1617 * │ └─ 01 ─ OPC_MXU_D16MULE
1618 * ├─ 001010 ─ OPC_MXU_D16MAC
1619 * ├─ 001011 ─ OPC_MXU_D16MACF
1620 * ├─ 001100 ─ OPC_MXU_D16MADL
1621 * ├─ 001101 ─ OPC_MXU_S16MAD
1622 * ├─ 001110 ─ OPC_MXU_Q16ADD
1623 * ├─ 001111 ─ OPC_MXU_D16MACE 23
1624 * │ ┌─ 0 ─ OPC_MXU_S32LDD
1625 * ├─ 010000 ─ OPC_MXU__POOL04 ─┴─ 1 ─ OPC_MXU_S32LDDR
1628 * ├─ 010001 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32STD
1629 * │ └─ 1 ─ OPC_MXU_S32STDR
1632 * ├─ 010010 ─ OPC_MXU__POOL06 ─┬─ 0000 ─ OPC_MXU_S32LDDV
1633 * │ └─ 0001 ─ OPC_MXU_S32LDDVR
1636 * ├─ 010011 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32STDV
1637 * │ └─ 0001 ─ OPC_MXU_S32STDVR
1640 * ├─ 010100 ─ OPC_MXU__POOL08 ─┬─ 0 ─ OPC_MXU_S32LDI
1641 * │ └─ 1 ─ OPC_MXU_S32LDIR
1644 * ├─ 010101 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32SDI
1645 * │ └─ 1 ─ OPC_MXU_S32SDIR
1648 * ├─ 010110 ─ OPC_MXU__POOL10 ─┬─ 0000 ─ OPC_MXU_S32LDIV
1649 * │ └─ 0001 ─ OPC_MXU_S32LDIVR
1652 * ├─ 010111 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32SDIV
1653 * │ └─ 0001 ─ OPC_MXU_S32SDIVR
1654 * ├─ 011000 ─ OPC_MXU_D32ADD
1656 * MXU ├─ 011001 ─ OPC_MXU__POOL12 ─┬─ 00 ─ OPC_MXU_D32ACC
1657 * opcodes ─┤ ├─ 01 ─ OPC_MXU_D32ACCM
1658 * │ └─ 10 ─ OPC_MXU_D32ASUM
1659 * ├─ 011010 ─ <not assigned>
1661 * ├─ 011011 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_Q16ACC
1662 * │ ├─ 01 ─ OPC_MXU_Q16ACCM
1663 * │ └─ 10 ─ OPC_MXU_Q16ASUM
1666 * ├─ 011100 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q8ADDE
1667 * │ ├─ 01 ─ OPC_MXU_D8SUM
1668 * ├─ 011101 ─ OPC_MXU_Q8ACCE └─ 10 ─ OPC_MXU_D8SUMC
1669 * ├─ 011110 ─ <not assigned>
1670 * ├─ 011111 ─ <not assigned>
1671 * ├─ 100000 ─ <not assigned> (overlaps with CLZ)
1672 * ├─ 100001 ─ <not assigned> (overlaps with CLO)
1673 * ├─ 100010 ─ OPC_MXU_S8LDD
1674 * ├─ 100011 ─ OPC_MXU_S8STD 15..14
1675 * ├─ 100100 ─ OPC_MXU_S8LDI ┌─ 00 ─ OPC_MXU_S32MUL
1676 * ├─ 100101 ─ OPC_MXU_S8SDI ├─ 00 ─ OPC_MXU_S32MULU
1677 * │ ├─ 00 ─ OPC_MXU_S32EXTR
1678 * ├─ 100110 ─ OPC_MXU__POOL15 ─┴─ 00 ─ OPC_MXU_S32EXTRV
1681 * ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW
1682 * │ ├─ 001 ─ OPC_MXU_S32ALN
1683 * │ ├─ 010 ─ OPC_MXU_S32ALNI
1684 * │ ├─ 011 ─ OPC_MXU_S32LUI
1685 * │ ├─ 100 ─ OPC_MXU_S32NOR
1686 * │ ├─ 101 ─ OPC_MXU_S32AND
1687 * │ ├─ 110 ─ OPC_MXU_S32OR
1688 * │ └─ 111 ─ OPC_MXU_S32XOR
1691 * ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB
1692 * │ ├─ 001 ─ OPC_MXU_LXH
1693 * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_LXW
1694 * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_LXBU
1695 * ├─ 101011 ─ OPC_MXU_S16STD └─ 101 ─ OPC_MXU_LXHU
1696 * ├─ 101100 ─ OPC_MXU_S16LDI
1697 * ├─ 101101 ─ OPC_MXU_S16SDI
1698 * ├─ 101110 ─ OPC_MXU_S32M2I
1699 * ├─ 101111 ─ OPC_MXU_S32I2M
1700 * ├─ 110000 ─ OPC_MXU_D32SLL
1701 * ├─ 110001 ─ OPC_MXU_D32SLR 20..18
1702 * ├─ 110010 ─ OPC_MXU_D32SARL ┌─ 000 ─ OPC_MXU_D32SLLV
1703 * ├─ 110011 ─ OPC_MXU_D32SAR ├─ 001 ─ OPC_MXU_D32SLRV
1704 * ├─ 110100 ─ OPC_MXU_Q16SLL ├─ 010 ─ OPC_MXU_D32SARV
1705 * ├─ 110101 ─ OPC_MXU_Q16SLR ├─ 011 ─ OPC_MXU_Q16SLLV
1706 * │ ├─ 100 ─ OPC_MXU_Q16SLRV
1707 * ├─ 110110 ─ OPC_MXU__POOL18 ─┴─ 101 ─ OPC_MXU_Q16SARV
1709 * ├─ 110111 ─ OPC_MXU_Q16SAR
1711 * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
1712 * │ └─ 01 ─ OPC_MXU_Q8MULSU
1715 * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
1716 * │ ├─ 001 ─ OPC_MXU_Q8MOVN
1717 * │ ├─ 010 ─ OPC_MXU_D16MOVZ
1718 * │ ├─ 011 ─ OPC_MXU_D16MOVN
1719 * │ ├─ 100 ─ OPC_MXU_S32MOVZ
1720 * │ └─ 101 ─ OPC_MXU_S32MOVN
1723 * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
1724 * │ └─ 10 ─ OPC_MXU_Q8MACSU
1725 * ├─ 111011 ─ OPC_MXU_Q16SCOP
1726 * ├─ 111100 ─ OPC_MXU_Q8MADL
1727 * ├─ 111101 ─ OPC_MXU_S32SFL
1728 * ├─ 111110 ─ OPC_MXU_Q8SAD
1729 * └─ 111111 ─ <not assigned> (overlaps with SDBBP)
1734 * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
1735 * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2, 2017
1739 OPC_MXU_S32MADD
= 0x00,
1740 OPC_MXU_S32MADDU
= 0x01,
1741 OPC__MXU_MUL
= 0x02,
1742 OPC_MXU__POOL00
= 0x03,
1743 OPC_MXU_S32MSUB
= 0x04,
1744 OPC_MXU_S32MSUBU
= 0x05,
1745 OPC_MXU__POOL01
= 0x06,
1746 OPC_MXU__POOL02
= 0x07,
1747 OPC_MXU_D16MUL
= 0x08,
1748 OPC_MXU__POOL03
= 0x09,
1749 OPC_MXU_D16MAC
= 0x0A,
1750 OPC_MXU_D16MACF
= 0x0B,
1751 OPC_MXU_D16MADL
= 0x0C,
1752 OPC_MXU_S16MAD
= 0x0D,
1753 OPC_MXU_Q16ADD
= 0x0E,
1754 OPC_MXU_D16MACE
= 0x0F,
1755 OPC_MXU__POOL04
= 0x10,
1756 OPC_MXU__POOL05
= 0x11,
1757 OPC_MXU__POOL06
= 0x12,
1758 OPC_MXU__POOL07
= 0x13,
1759 OPC_MXU__POOL08
= 0x14,
1760 OPC_MXU__POOL09
= 0x15,
1761 OPC_MXU__POOL10
= 0x16,
1762 OPC_MXU__POOL11
= 0x17,
1763 OPC_MXU_D32ADD
= 0x18,
1764 OPC_MXU__POOL12
= 0x19,
1765 /* not assigned 0x1A */
1766 OPC_MXU__POOL13
= 0x1B,
1767 OPC_MXU__POOL14
= 0x1C,
1768 OPC_MXU_Q8ACCE
= 0x1D,
1769 /* not assigned 0x1E */
1770 /* not assigned 0x1F */
1771 /* not assigned 0x20 */
1772 /* not assigned 0x21 */
1773 OPC_MXU_S8LDD
= 0x22,
1774 OPC_MXU_S8STD
= 0x23,
1775 OPC_MXU_S8LDI
= 0x24,
1776 OPC_MXU_S8SDI
= 0x25,
1777 OPC_MXU__POOL15
= 0x26,
1778 OPC_MXU__POOL16
= 0x27,
1779 OPC_MXU__POOL17
= 0x28,
1780 /* not assigned 0x29 */
1781 OPC_MXU_S16LDD
= 0x2A,
1782 OPC_MXU_S16STD
= 0x2B,
1783 OPC_MXU_S16LDI
= 0x2C,
1784 OPC_MXU_S16SDI
= 0x2D,
1785 OPC_MXU_S32M2I
= 0x2E,
1786 OPC_MXU_S32I2M
= 0x2F,
1787 OPC_MXU_D32SLL
= 0x30,
1788 OPC_MXU_D32SLR
= 0x31,
1789 OPC_MXU_D32SARL
= 0x32,
1790 OPC_MXU_D32SAR
= 0x33,
1791 OPC_MXU_Q16SLL
= 0x34,
1792 OPC_MXU_Q16SLR
= 0x35,
1793 OPC_MXU__POOL18
= 0x36,
1794 OPC_MXU_Q16SAR
= 0x37,
1795 OPC_MXU__POOL19
= 0x38,
1796 OPC_MXU__POOL20
= 0x39,
1797 OPC_MXU__POOL21
= 0x3A,
1798 OPC_MXU_Q16SCOP
= 0x3B,
1799 OPC_MXU_Q8MADL
= 0x3C,
1800 OPC_MXU_S32SFL
= 0x3D,
1801 OPC_MXU_Q8SAD
= 0x3E,
1802 /* not assigned 0x3F */
1810 OPC_MXU_S32MAX
= 0x00,
1811 OPC_MXU_S32MIN
= 0x01,
1812 OPC_MXU_D16MAX
= 0x02,
1813 OPC_MXU_D16MIN
= 0x03,
1814 OPC_MXU_Q8MAX
= 0x04,
1815 OPC_MXU_Q8MIN
= 0x05,
1816 OPC_MXU_Q8SLT
= 0x06,
1817 OPC_MXU_Q8SLTU
= 0x07,
1824 OPC_MXU_S32SLT
= 0x00,
1825 OPC_MXU_D16SLT
= 0x01,
1826 OPC_MXU_D16AVG
= 0x02,
1827 OPC_MXU_D16AVGR
= 0x03,
1828 OPC_MXU_Q8AVG
= 0x04,
1829 OPC_MXU_Q8AVGR
= 0x05,
1830 OPC_MXU_Q8ADD
= 0x07,
1837 OPC_MXU_S32CPS
= 0x00,
1838 OPC_MXU_D16CPS
= 0x02,
1839 OPC_MXU_Q8ABD
= 0x04,
1840 OPC_MXU_Q16SAT
= 0x06,
1847 OPC_MXU_D16MULF
= 0x00,
1848 OPC_MXU_D16MULE
= 0x01,
1855 OPC_MXU_S32LDD
= 0x00,
1856 OPC_MXU_S32LDDR
= 0x01,
1863 OPC_MXU_S32STD
= 0x00,
1864 OPC_MXU_S32STDR
= 0x01,
1871 OPC_MXU_S32LDDV
= 0x00,
1872 OPC_MXU_S32LDDVR
= 0x01,
1879 OPC_MXU_S32STDV
= 0x00,
1880 OPC_MXU_S32STDVR
= 0x01,
1887 OPC_MXU_S32LDI
= 0x00,
1888 OPC_MXU_S32LDIR
= 0x01,
1895 OPC_MXU_S32SDI
= 0x00,
1896 OPC_MXU_S32SDIR
= 0x01,
1903 OPC_MXU_S32LDIV
= 0x00,
1904 OPC_MXU_S32LDIVR
= 0x01,
1911 OPC_MXU_S32SDIV
= 0x00,
1912 OPC_MXU_S32SDIVR
= 0x01,
1919 OPC_MXU_D32ACC
= 0x00,
1920 OPC_MXU_D32ACCM
= 0x01,
1921 OPC_MXU_D32ASUM
= 0x02,
1928 OPC_MXU_Q16ACC
= 0x00,
1929 OPC_MXU_Q16ACCM
= 0x01,
1930 OPC_MXU_Q16ASUM
= 0x02,
1937 OPC_MXU_Q8ADDE
= 0x00,
1938 OPC_MXU_D8SUM
= 0x01,
1939 OPC_MXU_D8SUMC
= 0x02,
1946 OPC_MXU_S32MUL
= 0x00,
1947 OPC_MXU_S32MULU
= 0x01,
1948 OPC_MXU_S32EXTR
= 0x02,
1949 OPC_MXU_S32EXTRV
= 0x03,
1956 OPC_MXU_D32SARW
= 0x00,
1957 OPC_MXU_S32ALN
= 0x01,
1958 OPC_MXU_S32ALNI
= 0x02,
1959 OPC_MXU_S32LUI
= 0x03,
1960 OPC_MXU_S32NOR
= 0x04,
1961 OPC_MXU_S32AND
= 0x05,
1962 OPC_MXU_S32OR
= 0x06,
1963 OPC_MXU_S32XOR
= 0x07,
1973 OPC_MXU_LXBU
= 0x04,
1974 OPC_MXU_LXHU
= 0x05,
1981 OPC_MXU_D32SLLV
= 0x00,
1982 OPC_MXU_D32SLRV
= 0x01,
1983 OPC_MXU_D32SARV
= 0x03,
1984 OPC_MXU_Q16SLLV
= 0x04,
1985 OPC_MXU_Q16SLRV
= 0x05,
1986 OPC_MXU_Q16SARV
= 0x07,
1993 OPC_MXU_Q8MUL
= 0x00,
1994 OPC_MXU_Q8MULSU
= 0x01,
2001 OPC_MXU_Q8MOVZ
= 0x00,
2002 OPC_MXU_Q8MOVN
= 0x01,
2003 OPC_MXU_D16MOVZ
= 0x02,
2004 OPC_MXU_D16MOVN
= 0x03,
2005 OPC_MXU_S32MOVZ
= 0x04,
2006 OPC_MXU_S32MOVN
= 0x05,
2013 OPC_MXU_Q8MAC
= 0x00,
2014 OPC_MXU_Q8MACSU
= 0x01,
2018 * Overview of the TX79-specific instruction set
2019 * =============================================
2021 * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
2022 * are only used by the specific quadword (128-bit) LQ/SQ load/store
2023 * instructions and certain multimedia instructions (MMIs). These MMIs
2024 * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
2025 * or sixteen 8-bit paths.
2029 * The Toshiba TX System RISC TX79 Core Architecture manual,
2030 * https://wiki.qemu.org/File:C790.pdf
2032 * Three-Operand Multiply and Multiply-Add (4 instructions)
2033 * --------------------------------------------------------
2034 * MADD [rd,] rs, rt Multiply/Add
2035 * MADDU [rd,] rs, rt Multiply/Add Unsigned
2036 * MULT [rd,] rs, rt Multiply (3-operand)
2037 * MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
2039 * Multiply Instructions for Pipeline 1 (10 instructions)
2040 * ------------------------------------------------------
2041 * MULT1 [rd,] rs, rt Multiply Pipeline 1
2042 * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
2043 * DIV1 rs, rt Divide Pipeline 1
2044 * DIVU1 rs, rt Divide Unsigned Pipeline 1
2045 * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
2046 * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
2047 * MFHI1 rd Move From HI1 Register
2048 * MFLO1 rd Move From LO1 Register
2049 * MTHI1 rs Move To HI1 Register
2050 * MTLO1 rs Move To LO1 Register
2052 * Arithmetic (19 instructions)
2053 * ----------------------------
2054 * PADDB rd, rs, rt Parallel Add Byte
2055 * PSUBB rd, rs, rt Parallel Subtract Byte
2056 * PADDH rd, rs, rt Parallel Add Halfword
2057 * PSUBH rd, rs, rt Parallel Subtract Halfword
2058 * PADDW rd, rs, rt Parallel Add Word
2059 * PSUBW rd, rs, rt Parallel Subtract Word
2060 * PADSBH rd, rs, rt Parallel Add/Subtract Halfword
2061 * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
2062 * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
2063 * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
2064 * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
2065 * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
2066 * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
2067 * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
2068 * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
2069 * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
2070 * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
2071 * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
2072 * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
2074 * Min/Max (4 instructions)
2075 * ------------------------
2076 * PMAXH rd, rs, rt Parallel Maximum Halfword
2077 * PMINH rd, rs, rt Parallel Minimum Halfword
2078 * PMAXW rd, rs, rt Parallel Maximum Word
2079 * PMINW rd, rs, rt Parallel Minimum Word
2081 * Absolute (2 instructions)
2082 * -------------------------
2083 * PABSH rd, rt Parallel Absolute Halfword
2084 * PABSW rd, rt Parallel Absolute Word
2086 * Logical (4 instructions)
2087 * ------------------------
2088 * PAND rd, rs, rt Parallel AND
2089 * POR rd, rs, rt Parallel OR
2090 * PXOR rd, rs, rt Parallel XOR
2091 * PNOR rd, rs, rt Parallel NOR
2093 * Shift (9 instructions)
2094 * ----------------------
2095 * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
2096 * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
2097 * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
2098 * PSLLW rd, rt, sa Parallel Shift Left Logical Word
2099 * PSRLW rd, rt, sa Parallel Shift Right Logical Word
2100 * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
2101 * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
2102 * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
2103 * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
2105 * Compare (6 instructions)
2106 * ------------------------
2107 * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
2108 * PCEQB rd, rs, rt Parallel Compare for Equal Byte
2109 * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
2110 * PCEQH rd, rs, rt Parallel Compare for Equal Halfword
2111 * PCGTW rd, rs, rt Parallel Compare for Greater Than Word
2112 * PCEQW rd, rs, rt Parallel Compare for Equal Word
2114 * LZC (1 instruction)
2115 * -------------------
2116 * PLZCW rd, rs Parallel Leading Zero or One Count Word
2118 * Quadword Load and Store (2 instructions)
2119 * ----------------------------------------
2120 * LQ rt, offset(base) Load Quadword
2121 * SQ rt, offset(base) Store Quadword
2123 * Multiply and Divide (19 instructions)
2124 * -------------------------------------
2125 * PMULTW rd, rs, rt Parallel Multiply Word
2126 * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
2127 * PDIVW rs, rt Parallel Divide Word
2128 * PDIVUW rs, rt Parallel Divide Unsigned Word
2129 * PMADDW rd, rs, rt Parallel Multiply-Add Word
2130 * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
2131 * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
2132 * PMULTH rd, rs, rt Parallel Multiply Halfword
2133 * PMADDH rd, rs, rt Parallel Multiply-Add Halfword
2134 * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
2135 * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
2136 * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
2137 * PDIVBW rs, rt Parallel Divide Broadcast Word
2138 * PMFHI rd Parallel Move From HI Register
2139 * PMFLO rd Parallel Move From LO Register
2140 * PMTHI rs Parallel Move To HI Register
2141 * PMTLO rs Parallel Move To LO Register
2142 * PMFHL rd Parallel Move From HI/LO Register
2143 * PMTHL rs Parallel Move To HI/LO Register
2145 * Pack/Extend (11 instructions)
2146 * -----------------------------
2147 * PPAC5 rd, rt Parallel Pack to 5 bits
2148 * PPACB rd, rs, rt Parallel Pack to Byte
2149 * PPACH rd, rs, rt Parallel Pack to Halfword
2150 * PPACW rd, rs, rt Parallel Pack to Word
2151 * PEXT5 rd, rt Parallel Extend Upper from 5 bits
2152 * PEXTUB rd, rs, rt Parallel Extend Upper from Byte
2153 * PEXTLB rd, rs, rt Parallel Extend Lower from Byte
2154 * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
2155 * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
2156 * PEXTUW rd, rs, rt Parallel Extend Upper from Word
2157 * PEXTLW rd, rs, rt Parallel Extend Lower from Word
2159 * Others (16 instructions)
2160 * ------------------------
2161 * PCPYH rd, rt Parallel Copy Halfword
2162 * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
2163 * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
2164 * PREVH rd, rt Parallel Reverse Halfword
2165 * PINTH rd, rs, rt Parallel Interleave Halfword
2166 * PINTEH rd, rs, rt Parallel Interleave Even Halfword
2167 * PEXEH rd, rt Parallel Exchange Even Halfword
2168 * PEXCH rd, rt Parallel Exchange Center Halfword
2169 * PEXEW rd, rt Parallel Exchange Even Word
2170 * PEXCW rd, rt Parallel Exchange Center Word
2171 * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
2172 * MFSA rd Move from Shift Amount Register
2173 * MTSA rs Move to Shift Amount Register
2174 * MTSAB rs, immediate Move Byte Count to Shift Amount Register
2175 * MTSAH rs, immediate Move Halfword Count to Shift Amount Register
2176 * PROT3W rd, rt Parallel Rotate 3 Words
2178 * MMI (MultiMedia Instruction) encodings
2179 * ======================================
2181 * MMI instructions encoding table keys:
2183 * * This code is reserved for future use. An attempt to execute it
2184 * causes a Reserved Instruction exception.
2185 * % This code indicates an instruction class. The instruction word
2186 * must be further decoded by examining additional tables that show
2187 * the values for other instruction fields.
2188 * # This code is reserved for the unsupported instructions DMULT,
2189 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
2190 * to execute it causes a Reserved Instruction exception.
2192 * MMI instructions encoded by opcode field (MMI, LQ, SQ):
2195 * +--------+----------------------------------------+
2197 * +--------+----------------------------------------+
2199 * opcode bits 28..26
2200 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
2201 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
2202 * -------+-------+-------+-------+-------+-------+-------+-------+-------
2203 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
2204 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
2205 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
2206 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
2207 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
2208 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
2209 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
2210 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
2214 MMI_OPC_CLASS_MMI
= 0x1C << 26, /* Same as OPC_SPECIAL2 */
2215 MMI_OPC_LQ
= 0x1E << 26, /* Same as OPC_MSA */
2216 MMI_OPC_SQ
= 0x1F << 26, /* Same as OPC_SPECIAL3 */
2220 * MMI instructions with opcode field = MMI:
2223 * +--------+-------------------------------+--------+
2224 * | MMI | |function|
2225 * +--------+-------------------------------+--------+
2227 * function bits 2..0
2228 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
2229 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
2230 * -------+-------+-------+-------+-------+-------+-------+-------+-------
2231 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
2232 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
2233 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
2234 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
2235 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
2236 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
2237 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
2238 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
2241 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
2243 MMI_OPC_MADD
= 0x00 | MMI_OPC_CLASS_MMI
, /* Same as OPC_MADD */
2244 MMI_OPC_MADDU
= 0x01 | MMI_OPC_CLASS_MMI
, /* Same as OPC_MADDU */
2245 MMI_OPC_PLZCW
= 0x04 | MMI_OPC_CLASS_MMI
,
2246 MMI_OPC_CLASS_MMI0
= 0x08 | MMI_OPC_CLASS_MMI
,
2247 MMI_OPC_CLASS_MMI2
= 0x09 | MMI_OPC_CLASS_MMI
,
2248 MMI_OPC_MFHI1
= 0x10 | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_MFHI */
2249 MMI_OPC_MTHI1
= 0x11 | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_MTHI */
2250 MMI_OPC_MFLO1
= 0x12 | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_MFLO */
2251 MMI_OPC_MTLO1
= 0x13 | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_MTLO */
2252 MMI_OPC_MULT1
= 0x18 | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_MULT */
2253 MMI_OPC_MULTU1
= 0x19 | MMI_OPC_CLASS_MMI
, /* Same min. as OPC_MULTU */
2254 MMI_OPC_DIV1
= 0x1A | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_DIV */
2255 MMI_OPC_DIVU1
= 0x1B | MMI_OPC_CLASS_MMI
, /* Same minor as OPC_DIVU */
2256 MMI_OPC_MADD1
= 0x20 | MMI_OPC_CLASS_MMI
,
2257 MMI_OPC_MADDU1
= 0x21 | MMI_OPC_CLASS_MMI
,
2258 MMI_OPC_CLASS_MMI1
= 0x28 | MMI_OPC_CLASS_MMI
,
2259 MMI_OPC_CLASS_MMI3
= 0x29 | MMI_OPC_CLASS_MMI
,
2260 MMI_OPC_PMFHL
= 0x30 | MMI_OPC_CLASS_MMI
,
2261 MMI_OPC_PMTHL
= 0x31 | MMI_OPC_CLASS_MMI
,
2262 MMI_OPC_PSLLH
= 0x34 | MMI_OPC_CLASS_MMI
,
2263 MMI_OPC_PSRLH
= 0x36 | MMI_OPC_CLASS_MMI
,
2264 MMI_OPC_PSRAH
= 0x37 | MMI_OPC_CLASS_MMI
,
2265 MMI_OPC_PSLLW
= 0x3C | MMI_OPC_CLASS_MMI
,
2266 MMI_OPC_PSRLW
= 0x3E | MMI_OPC_CLASS_MMI
,
2267 MMI_OPC_PSRAW
= 0x3F | MMI_OPC_CLASS_MMI
,
2271 * MMI instructions with opcode field = MMI and bits 5..0 = MMI0:
2274 * +--------+----------------------+--------+--------+
2275 * | MMI | |function| MMI0 |
2276 * +--------+----------------------+--------+--------+
2278 * function bits 7..6
2279 * bits | 0 | 1 | 2 | 3
2280 * 10..8 | 00 | 01 | 10 | 11
2281 * -------+-------+-------+-------+-------
2282 * 0 000 | PADDW | PSUBW | PCGTW | PMAXW
2283 * 1 001 | PADDH | PSUBH | PCGTH | PMAXH
2284 * 2 010 | PADDB | PSUBB | PCGTB | *
2285 * 3 011 | * | * | * | *
2286 * 4 100 | PADDSW| PSUBSW| PEXTLW| PPACW
2287 * 5 101 | PADDSH| PSUBSH| PEXTLH| PPACH
2288 * 6 110 | PADDSB| PSUBSB| PEXTLB| PPACB
2289 * 7 111 | * | * | PEXT5 | PPAC5
2292 #define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2294 MMI_OPC_0_PADDW
= (0x00 << 6) | MMI_OPC_CLASS_MMI0
,
2295 MMI_OPC_0_PSUBW
= (0x01 << 6) | MMI_OPC_CLASS_MMI0
,
2296 MMI_OPC_0_PCGTW
= (0x02 << 6) | MMI_OPC_CLASS_MMI0
,
2297 MMI_OPC_0_PMAXW
= (0x03 << 6) | MMI_OPC_CLASS_MMI0
,
2298 MMI_OPC_0_PADDH
= (0x04 << 6) | MMI_OPC_CLASS_MMI0
,
2299 MMI_OPC_0_PSUBH
= (0x05 << 6) | MMI_OPC_CLASS_MMI0
,
2300 MMI_OPC_0_PCGTH
= (0x06 << 6) | MMI_OPC_CLASS_MMI0
,
2301 MMI_OPC_0_PMAXH
= (0x07 << 6) | MMI_OPC_CLASS_MMI0
,
2302 MMI_OPC_0_PADDB
= (0x08 << 6) | MMI_OPC_CLASS_MMI0
,
2303 MMI_OPC_0_PSUBB
= (0x09 << 6) | MMI_OPC_CLASS_MMI0
,
2304 MMI_OPC_0_PCGTB
= (0x0A << 6) | MMI_OPC_CLASS_MMI0
,
2305 MMI_OPC_0_PADDSW
= (0x10 << 6) | MMI_OPC_CLASS_MMI0
,
2306 MMI_OPC_0_PSUBSW
= (0x11 << 6) | MMI_OPC_CLASS_MMI0
,
2307 MMI_OPC_0_PEXTLW
= (0x12 << 6) | MMI_OPC_CLASS_MMI0
,
2308 MMI_OPC_0_PPACW
= (0x13 << 6) | MMI_OPC_CLASS_MMI0
,
2309 MMI_OPC_0_PADDSH
= (0x14 << 6) | MMI_OPC_CLASS_MMI0
,
2310 MMI_OPC_0_PSUBSH
= (0x15 << 6) | MMI_OPC_CLASS_MMI0
,
2311 MMI_OPC_0_PEXTLH
= (0x16 << 6) | MMI_OPC_CLASS_MMI0
,
2312 MMI_OPC_0_PPACH
= (0x17 << 6) | MMI_OPC_CLASS_MMI0
,
2313 MMI_OPC_0_PADDSB
= (0x18 << 6) | MMI_OPC_CLASS_MMI0
,
2314 MMI_OPC_0_PSUBSB
= (0x19 << 6) | MMI_OPC_CLASS_MMI0
,
2315 MMI_OPC_0_PEXTLB
= (0x1A << 6) | MMI_OPC_CLASS_MMI0
,
2316 MMI_OPC_0_PPACB
= (0x1B << 6) | MMI_OPC_CLASS_MMI0
,
2317 MMI_OPC_0_PEXT5
= (0x1E << 6) | MMI_OPC_CLASS_MMI0
,
2318 MMI_OPC_0_PPAC5
= (0x1F << 6) | MMI_OPC_CLASS_MMI0
,
2322 * MMI instructions with opcode field = MMI and bits 5..0 = MMI1:
2325 * +--------+----------------------+--------+--------+
2326 * | MMI | |function| MMI1 |
2327 * +--------+----------------------+--------+--------+
2329 * function bits 7..6
2330 * bits | 0 | 1 | 2 | 3
2331 * 10..8 | 00 | 01 | 10 | 11
2332 * -------+-------+-------+-------+-------
2333 * 0 000 | * | PABSW | PCEQW | PMINW
2334 * 1 001 | PADSBH| PABSH | PCEQH | PMINH
2335 * 2 010 | * | * | PCEQB | *
2336 * 3 011 | * | * | * | *
2337 * 4 100 | PADDUW| PSUBUW| PEXTUW| *
2338 * 5 101 | PADDUH| PSUBUH| PEXTUH| *
2339 * 6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV
2340 * 7 111 | * | * | * | *
2343 #define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2345 MMI_OPC_1_PABSW
= (0x01 << 6) | MMI_OPC_CLASS_MMI1
,
2346 MMI_OPC_1_PCEQW
= (0x02 << 6) | MMI_OPC_CLASS_MMI1
,
2347 MMI_OPC_1_PMINW
= (0x03 << 6) | MMI_OPC_CLASS_MMI1
,
2348 MMI_OPC_1_PADSBH
= (0x04 << 6) | MMI_OPC_CLASS_MMI1
,
2349 MMI_OPC_1_PABSH
= (0x05 << 6) | MMI_OPC_CLASS_MMI1
,
2350 MMI_OPC_1_PCEQH
= (0x06 << 6) | MMI_OPC_CLASS_MMI1
,
2351 MMI_OPC_1_PMINH
= (0x07 << 6) | MMI_OPC_CLASS_MMI1
,
2352 MMI_OPC_1_PCEQB
= (0x0A << 6) | MMI_OPC_CLASS_MMI1
,
2353 MMI_OPC_1_PADDUW
= (0x10 << 6) | MMI_OPC_CLASS_MMI1
,
2354 MMI_OPC_1_PSUBUW
= (0x11 << 6) | MMI_OPC_CLASS_MMI1
,
2355 MMI_OPC_1_PEXTUW
= (0x12 << 6) | MMI_OPC_CLASS_MMI1
,
2356 MMI_OPC_1_PADDUH
= (0x14 << 6) | MMI_OPC_CLASS_MMI1
,
2357 MMI_OPC_1_PSUBUH
= (0x15 << 6) | MMI_OPC_CLASS_MMI1
,
2358 MMI_OPC_1_PEXTUH
= (0x16 << 6) | MMI_OPC_CLASS_MMI1
,
2359 MMI_OPC_1_PADDUB
= (0x18 << 6) | MMI_OPC_CLASS_MMI1
,
2360 MMI_OPC_1_PSUBUB
= (0x19 << 6) | MMI_OPC_CLASS_MMI1
,
2361 MMI_OPC_1_PEXTUB
= (0x1A << 6) | MMI_OPC_CLASS_MMI1
,
2362 MMI_OPC_1_QFSRV
= (0x1B << 6) | MMI_OPC_CLASS_MMI1
,
2366 * MMI instructions with opcode field = MMI and bits 5..0 = MMI2:
2369 * +--------+----------------------+--------+--------+
2370 * | MMI | |function| MMI2 |
2371 * +--------+----------------------+--------+--------+
2373 * function bits 7..6
2374 * bits | 0 | 1 | 2 | 3
2375 * 10..8 | 00 | 01 | 10 | 11
2376 * -------+-------+-------+-------+-------
2377 * 0 000 | PMADDW| * | PSLLVW| PSRLVW
2378 * 1 001 | PMSUBW| * | * | *
2379 * 2 010 | PMFHI | PMFLO | PINTH | *
2380 * 3 011 | PMULTW| PDIVW | PCPYLD| *
2381 * 4 100 | PMADDH| PHMADH| PAND | PXOR
2382 * 5 101 | PMSUBH| PHMSBH| * | *
2383 * 6 110 | * | * | PEXEH | PREVH
2384 * 7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
2387 #define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2389 MMI_OPC_2_PMADDW
= (0x00 << 6) | MMI_OPC_CLASS_MMI2
,
2390 MMI_OPC_2_PSLLVW
= (0x02 << 6) | MMI_OPC_CLASS_MMI2
,
2391 MMI_OPC_2_PSRLVW
= (0x03 << 6) | MMI_OPC_CLASS_MMI2
,
2392 MMI_OPC_2_PMSUBW
= (0x04 << 6) | MMI_OPC_CLASS_MMI2
,
2393 MMI_OPC_2_PMFHI
= (0x08 << 6) | MMI_OPC_CLASS_MMI2
,
2394 MMI_OPC_2_PMFLO
= (0x09 << 6) | MMI_OPC_CLASS_MMI2
,
2395 MMI_OPC_2_PINTH
= (0x0A << 6) | MMI_OPC_CLASS_MMI2
,
2396 MMI_OPC_2_PMULTW
= (0x0C << 6) | MMI_OPC_CLASS_MMI2
,
2397 MMI_OPC_2_PDIVW
= (0x0D << 6) | MMI_OPC_CLASS_MMI2
,
2398 MMI_OPC_2_PCPYLD
= (0x0E << 6) | MMI_OPC_CLASS_MMI2
,
2399 MMI_OPC_2_PMADDH
= (0x10 << 6) | MMI_OPC_CLASS_MMI2
,
2400 MMI_OPC_2_PHMADH
= (0x11 << 6) | MMI_OPC_CLASS_MMI2
,
2401 MMI_OPC_2_PAND
= (0x12 << 6) | MMI_OPC_CLASS_MMI2
,
2402 MMI_OPC_2_PXOR
= (0x13 << 6) | MMI_OPC_CLASS_MMI2
,
2403 MMI_OPC_2_PMSUBH
= (0x14 << 6) | MMI_OPC_CLASS_MMI2
,
2404 MMI_OPC_2_PHMSBH
= (0x15 << 6) | MMI_OPC_CLASS_MMI2
,
2405 MMI_OPC_2_PEXEH
= (0x1A << 6) | MMI_OPC_CLASS_MMI2
,
2406 MMI_OPC_2_PREVH
= (0x1B << 6) | MMI_OPC_CLASS_MMI2
,
2407 MMI_OPC_2_PMULTH
= (0x1C << 6) | MMI_OPC_CLASS_MMI2
,
2408 MMI_OPC_2_PDIVBW
= (0x1D << 6) | MMI_OPC_CLASS_MMI2
,
2409 MMI_OPC_2_PEXEW
= (0x1E << 6) | MMI_OPC_CLASS_MMI2
,
2410 MMI_OPC_2_PROT3W
= (0x1F << 6) | MMI_OPC_CLASS_MMI2
,
2414 * MMI instructions with opcode field = MMI and bits 5..0 = MMI3:
2417 * +--------+----------------------+--------+--------+
2418 * | MMI | |function| MMI3 |
2419 * +--------+----------------------+--------+--------+
2421 * function bits 7..6
2422 * bits | 0 | 1 | 2 | 3
2423 * 10..8 | 00 | 01 | 10 | 11
2424 * -------+-------+-------+-------+-------
2425 * 0 000 |PMADDUW| * | * | PSRAVW
2426 * 1 001 | * | * | * | *
2427 * 2 010 | PMTHI | PMTLO | PINTEH| *
2428 * 3 011 |PMULTUW| PDIVUW| PCPYUD| *
2429 * 4 100 | * | * | POR | PNOR
2430 * 5 101 | * | * | * | *
2431 * 6 110 | * | * | PEXCH | PCPYH
2432 * 7 111 | * | * | PEXCW | *
2435 #define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
2437 MMI_OPC_3_PMADDUW
= (0x00 << 6) | MMI_OPC_CLASS_MMI3
,
2438 MMI_OPC_3_PSRAVW
= (0x03 << 6) | MMI_OPC_CLASS_MMI3
,
2439 MMI_OPC_3_PMTHI
= (0x08 << 6) | MMI_OPC_CLASS_MMI3
,
2440 MMI_OPC_3_PMTLO
= (0x09 << 6) | MMI_OPC_CLASS_MMI3
,
2441 MMI_OPC_3_PINTEH
= (0x0A << 6) | MMI_OPC_CLASS_MMI3
,
2442 MMI_OPC_3_PMULTUW
= (0x0C << 6) | MMI_OPC_CLASS_MMI3
,
2443 MMI_OPC_3_PDIVUW
= (0x0D << 6) | MMI_OPC_CLASS_MMI3
,
2444 MMI_OPC_3_PCPYUD
= (0x0E << 6) | MMI_OPC_CLASS_MMI3
,
2445 MMI_OPC_3_POR
= (0x12 << 6) | MMI_OPC_CLASS_MMI3
,
2446 MMI_OPC_3_PNOR
= (0x13 << 6) | MMI_OPC_CLASS_MMI3
,
2447 MMI_OPC_3_PEXCH
= (0x1A << 6) | MMI_OPC_CLASS_MMI3
,
2448 MMI_OPC_3_PCPYH
= (0x1B << 6) | MMI_OPC_CLASS_MMI3
,
2449 MMI_OPC_3_PEXCW
= (0x1E << 6) | MMI_OPC_CLASS_MMI3
,
2452 /* global register indices */
2453 static TCGv cpu_gpr
[32], cpu_PC
;
2454 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
];
2455 static TCGv cpu_dspctrl
, btarget
, bcond
;
2456 static TCGv cpu_lladdr
, cpu_llval
;
2457 static TCGv_i32 hflags
;
2458 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
2459 static TCGv_i64 fpu_f64
[32];
2460 static TCGv_i64 msa_wr_d
[64];
2462 #if defined(TARGET_MIPS64)
2463 /* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
2464 static TCGv_i64 cpu_mmr
[32];
2467 #if !defined(TARGET_MIPS64)
2469 static TCGv mxu_gpr
[NUMBER_OF_MXU_REGISTERS
- 1];
2473 #include "exec/gen-icount.h"
2475 #define gen_helper_0e0i(name, arg) do { \
2476 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
2477 gen_helper_##name(cpu_env, helper_tmp); \
2478 tcg_temp_free_i32(helper_tmp); \
2481 #define gen_helper_0e1i(name, arg1, arg2) do { \
2482 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
2483 gen_helper_##name(cpu_env, arg1, helper_tmp); \
2484 tcg_temp_free_i32(helper_tmp); \
2487 #define gen_helper_1e0i(name, ret, arg1) do { \
2488 TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
2489 gen_helper_##name(ret, cpu_env, helper_tmp); \
2490 tcg_temp_free_i32(helper_tmp); \
2493 #define gen_helper_1e1i(name, ret, arg1, arg2) do { \
2494 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
2495 gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
2496 tcg_temp_free_i32(helper_tmp); \
2499 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
2500 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
2501 gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
2502 tcg_temp_free_i32(helper_tmp); \
2505 #define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
2506 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
2507 gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
2508 tcg_temp_free_i32(helper_tmp); \
2511 #define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
2512 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
2513 gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
2514 tcg_temp_free_i32(helper_tmp); \
2517 typedef struct DisasContext
{
2518 DisasContextBase base
;
2519 target_ulong saved_pc
;
2520 target_ulong page_start
;
2522 uint64_t insn_flags
;
2523 int32_t CP0_Config1
;
2524 int32_t CP0_Config2
;
2525 int32_t CP0_Config3
;
2526 int32_t CP0_Config5
;
2527 /* Routine used to access memory */
2529 MemOp default_tcg_memop_mask
;
2530 uint32_t hflags
, saved_hflags
;
2531 target_ulong btarget
;
2542 int CP0_LLAddr_shift
;
2552 #define DISAS_STOP DISAS_TARGET_0
2553 #define DISAS_EXIT DISAS_TARGET_1
2555 static const char * const regnames
[] = {
2556 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2559 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
2562 static const char * const regnames_HI
[] = {
2563 "HI0", "HI1", "HI2", "HI3",
2566 static const char * const regnames_LO
[] = {
2567 "LO0", "LO1", "LO2", "LO3",
2570 static const char * const fregnames
[] = {
2571 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2572 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2573 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2574 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2577 static const char * const msaregnames
[] = {
2578 "w0.d0", "w0.d1", "w1.d0", "w1.d1",
2579 "w2.d0", "w2.d1", "w3.d0", "w3.d1",
2580 "w4.d0", "w4.d1", "w5.d0", "w5.d1",
2581 "w6.d0", "w6.d1", "w7.d0", "w7.d1",
2582 "w8.d0", "w8.d1", "w9.d0", "w9.d1",
2583 "w10.d0", "w10.d1", "w11.d0", "w11.d1",
2584 "w12.d0", "w12.d1", "w13.d0", "w13.d1",
2585 "w14.d0", "w14.d1", "w15.d0", "w15.d1",
2586 "w16.d0", "w16.d1", "w17.d0", "w17.d1",
2587 "w18.d0", "w18.d1", "w19.d0", "w19.d1",
2588 "w20.d0", "w20.d1", "w21.d0", "w21.d1",
2589 "w22.d0", "w22.d1", "w23.d0", "w23.d1",
2590 "w24.d0", "w24.d1", "w25.d0", "w25.d1",
2591 "w26.d0", "w26.d1", "w27.d0", "w27.d1",
2592 "w28.d0", "w28.d1", "w29.d0", "w29.d1",
2593 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
2596 #if !defined(TARGET_MIPS64)
2597 static const char * const mxuregnames
[] = {
2598 "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
2599 "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
2603 #define LOG_DISAS(...) \
2605 if (MIPS_DEBUG_DISAS) { \
2606 qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
2610 #define MIPS_INVAL(op) \
2612 if (MIPS_DEBUG_DISAS) { \
2613 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
2614 TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
2615 ctx->base.pc_next, ctx->opcode, op, \
2616 ctx->opcode >> 26, ctx->opcode & 0x3F, \
2617 ((ctx->opcode >> 16) & 0x1F)); \
2621 /* General purpose registers moves. */
2622 static inline void gen_load_gpr(TCGv t
, int reg
)
2625 tcg_gen_movi_tl(t
, 0);
2627 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
2631 static inline void gen_store_gpr(TCGv t
, int reg
)
2634 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
2638 /* Moves to/from shadow registers. */
2639 static inline void gen_load_srsgpr(int from
, int to
)
2641 TCGv t0
= tcg_temp_new();
2644 tcg_gen_movi_tl(t0
, 0);
2646 TCGv_i32 t2
= tcg_temp_new_i32();
2647 TCGv_ptr addr
= tcg_temp_new_ptr();
2649 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
2650 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
2651 tcg_gen_andi_i32(t2
, t2
, 0xf);
2652 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
2653 tcg_gen_ext_i32_ptr(addr
, t2
);
2654 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
2656 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
2657 tcg_temp_free_ptr(addr
);
2658 tcg_temp_free_i32(t2
);
2660 gen_store_gpr(t0
, to
);
2664 static inline void gen_store_srsgpr(int from
, int to
)
2667 TCGv t0
= tcg_temp_new();
2668 TCGv_i32 t2
= tcg_temp_new_i32();
2669 TCGv_ptr addr
= tcg_temp_new_ptr();
2671 gen_load_gpr(t0
, from
);
2672 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
2673 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
2674 tcg_gen_andi_i32(t2
, t2
, 0xf);
2675 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
2676 tcg_gen_ext_i32_ptr(addr
, t2
);
2677 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
2679 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
2680 tcg_temp_free_ptr(addr
);
2681 tcg_temp_free_i32(t2
);
2686 #if !defined(TARGET_MIPS64)
2687 /* MXU General purpose registers moves. */
2688 static inline void gen_load_mxu_gpr(TCGv t
, unsigned int reg
)
2691 tcg_gen_movi_tl(t
, 0);
2692 } else if (reg
<= 15) {
2693 tcg_gen_mov_tl(t
, mxu_gpr
[reg
- 1]);
2697 static inline void gen_store_mxu_gpr(TCGv t
, unsigned int reg
)
2699 if (reg
> 0 && reg
<= 15) {
2700 tcg_gen_mov_tl(mxu_gpr
[reg
- 1], t
);
2704 /* MXU control register moves. */
2705 static inline void gen_load_mxu_cr(TCGv t
)
2707 tcg_gen_mov_tl(t
, mxu_CR
);
2710 static inline void gen_store_mxu_cr(TCGv t
)
2712 /* TODO: Add handling of RW rules for MXU_CR. */
2713 tcg_gen_mov_tl(mxu_CR
, t
);
2719 static inline void gen_save_pc(target_ulong pc
)
2721 tcg_gen_movi_tl(cpu_PC
, pc
);
2724 static inline void save_cpu_state(DisasContext
*ctx
, int do_save_pc
)
2726 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
2727 if (do_save_pc
&& ctx
->base
.pc_next
!= ctx
->saved_pc
) {
2728 gen_save_pc(ctx
->base
.pc_next
);
2729 ctx
->saved_pc
= ctx
->base
.pc_next
;
2731 if (ctx
->hflags
!= ctx
->saved_hflags
) {
2732 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
2733 ctx
->saved_hflags
= ctx
->hflags
;
2734 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
2740 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
2746 static inline void restore_cpu_state(CPUMIPSState
*env
, DisasContext
*ctx
)
2748 ctx
->saved_hflags
= ctx
->hflags
;
2749 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
2755 ctx
->btarget
= env
->btarget
;
2760 static inline void generate_exception_err(DisasContext
*ctx
, int excp
, int err
)
2762 TCGv_i32 texcp
= tcg_const_i32(excp
);
2763 TCGv_i32 terr
= tcg_const_i32(err
);
2764 save_cpu_state(ctx
, 1);
2765 gen_helper_raise_exception_err(cpu_env
, texcp
, terr
);
2766 tcg_temp_free_i32(terr
);
2767 tcg_temp_free_i32(texcp
);
2768 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2771 static inline void generate_exception(DisasContext
*ctx
, int excp
)
2773 gen_helper_0e0i(raise_exception
, excp
);
2776 static inline void generate_exception_end(DisasContext
*ctx
, int excp
)
2778 generate_exception_err(ctx
, excp
, 0);
2781 /* Floating point register moves. */
2782 static void gen_load_fpr32(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
2784 if (ctx
->hflags
& MIPS_HFLAG_FRE
) {
2785 generate_exception(ctx
, EXCP_RI
);
2787 tcg_gen_extrl_i64_i32(t
, fpu_f64
[reg
]);
2790 static void gen_store_fpr32(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
2793 if (ctx
->hflags
& MIPS_HFLAG_FRE
) {
2794 generate_exception(ctx
, EXCP_RI
);
2796 t64
= tcg_temp_new_i64();
2797 tcg_gen_extu_i32_i64(t64
, t
);
2798 tcg_gen_deposit_i64(fpu_f64
[reg
], fpu_f64
[reg
], t64
, 0, 32);
2799 tcg_temp_free_i64(t64
);
2802 static void gen_load_fpr32h(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
2804 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
2805 tcg_gen_extrh_i64_i32(t
, fpu_f64
[reg
]);
2807 gen_load_fpr32(ctx
, t
, reg
| 1);
2811 static void gen_store_fpr32h(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
2813 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
2814 TCGv_i64 t64
= tcg_temp_new_i64();
2815 tcg_gen_extu_i32_i64(t64
, t
);
2816 tcg_gen_deposit_i64(fpu_f64
[reg
], fpu_f64
[reg
], t64
, 32, 32);
2817 tcg_temp_free_i64(t64
);
2819 gen_store_fpr32(ctx
, t
, reg
| 1);
2823 static void gen_load_fpr64(DisasContext
*ctx
, TCGv_i64 t
, int reg
)
2825 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
2826 tcg_gen_mov_i64(t
, fpu_f64
[reg
]);
2828 tcg_gen_concat32_i64(t
, fpu_f64
[reg
& ~1], fpu_f64
[reg
| 1]);
2832 static void gen_store_fpr64(DisasContext
*ctx
, TCGv_i64 t
, int reg
)
2834 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
2835 tcg_gen_mov_i64(fpu_f64
[reg
], t
);
2838 tcg_gen_deposit_i64(fpu_f64
[reg
& ~1], fpu_f64
[reg
& ~1], t
, 0, 32);
2839 t0
= tcg_temp_new_i64();
2840 tcg_gen_shri_i64(t0
, t
, 32);
2841 tcg_gen_deposit_i64(fpu_f64
[reg
| 1], fpu_f64
[reg
| 1], t0
, 0, 32);
2842 tcg_temp_free_i64(t0
);
2846 static inline int get_fp_bit(int cc
)
2855 /* Addresses computation */
2856 static inline void gen_op_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg0
,
2859 tcg_gen_add_tl(ret
, arg0
, arg1
);
2861 #if defined(TARGET_MIPS64)
2862 if (ctx
->hflags
& MIPS_HFLAG_AWRAP
) {
2863 tcg_gen_ext32s_i64(ret
, ret
);
2868 static inline void gen_op_addr_addi(DisasContext
*ctx
, TCGv ret
, TCGv base
,
2871 tcg_gen_addi_tl(ret
, base
, ofs
);
2873 #if defined(TARGET_MIPS64)
2874 if (ctx
->hflags
& MIPS_HFLAG_AWRAP
) {
2875 tcg_gen_ext32s_i64(ret
, ret
);
2880 /* Addresses computation (translation time) */
2881 static target_long
addr_add(DisasContext
*ctx
, target_long base
,
2884 target_long sum
= base
+ offset
;
2886 #if defined(TARGET_MIPS64)
2887 if (ctx
->hflags
& MIPS_HFLAG_AWRAP
) {
2894 /* Sign-extract the low 32-bits to a target_long. */
2895 static inline void gen_move_low32(TCGv ret
, TCGv_i64 arg
)
2897 #if defined(TARGET_MIPS64)
2898 tcg_gen_ext32s_i64(ret
, arg
);
2900 tcg_gen_extrl_i64_i32(ret
, arg
);
2904 /* Sign-extract the high 32-bits to a target_long. */
2905 static inline void gen_move_high32(TCGv ret
, TCGv_i64 arg
)
2907 #if defined(TARGET_MIPS64)
2908 tcg_gen_sari_i64(ret
, arg
, 32);
2910 tcg_gen_extrh_i64_i32(ret
, arg
);
2914 static inline void check_cp0_enabled(DisasContext
*ctx
)
2916 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
))) {
2917 generate_exception_err(ctx
, EXCP_CpU
, 0);
2921 static inline void check_cp1_enabled(DisasContext
*ctx
)
2923 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
))) {
2924 generate_exception_err(ctx
, EXCP_CpU
, 1);
2929 * Verify that the processor is running with COP1X instructions enabled.
2930 * This is associated with the nabla symbol in the MIPS32 and MIPS64
2933 static inline void check_cop1x(DisasContext
*ctx
)
2935 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
))) {
2936 generate_exception_end(ctx
, EXCP_RI
);
2941 * Verify that the processor is running with 64-bit floating-point
2942 * operations enabled.
2944 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
2946 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
))) {
2947 generate_exception_end(ctx
, EXCP_RI
);
2952 * Verify if floating point register is valid; an operation is not defined
2953 * if bit 0 of any register specification is set and the FR bit in the
2954 * Status register equals zero, since the register numbers specify an
2955 * even-odd pair of adjacent coprocessor general registers. When the FR bit
2956 * in the Status register equals one, both even and odd register numbers
2957 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
2959 * Multiple 64 bit wide registers can be checked by calling
2960 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
2962 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
2964 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1))) {
2965 generate_exception_end(ctx
, EXCP_RI
);
2970 * Verify that the processor is running with DSP instructions enabled.
2971 * This is enabled by CP0 Status register MX(24) bit.
2973 static inline void check_dsp(DisasContext
*ctx
)
2975 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_DSP
))) {
2976 if (ctx
->insn_flags
& ASE_DSP
) {
2977 generate_exception_end(ctx
, EXCP_DSPDIS
);
2979 generate_exception_end(ctx
, EXCP_RI
);
2984 static inline void check_dsp_r2(DisasContext
*ctx
)
2986 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_DSP_R2
))) {
2987 if (ctx
->insn_flags
& ASE_DSP
) {
2988 generate_exception_end(ctx
, EXCP_DSPDIS
);
2990 generate_exception_end(ctx
, EXCP_RI
);
2995 static inline void check_dsp_r3(DisasContext
*ctx
)
2997 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_DSP_R3
))) {
2998 if (ctx
->insn_flags
& ASE_DSP
) {
2999 generate_exception_end(ctx
, EXCP_DSPDIS
);
3001 generate_exception_end(ctx
, EXCP_RI
);
3007 * This code generates a "reserved instruction" exception if the
3008 * CPU does not support the instruction set corresponding to flags.
3010 static inline void check_insn(DisasContext
*ctx
, uint64_t flags
)
3012 if (unlikely(!(ctx
->insn_flags
& flags
))) {
3013 generate_exception_end(ctx
, EXCP_RI
);
3018 * This code generates a "reserved instruction" exception if the
3019 * CPU has corresponding flag set which indicates that the instruction
3022 static inline void check_insn_opc_removed(DisasContext
*ctx
, uint64_t flags
)
3024 if (unlikely(ctx
->insn_flags
& flags
)) {
3025 generate_exception_end(ctx
, EXCP_RI
);
3030 * The Linux kernel traps certain reserved instruction exceptions to
3031 * emulate the corresponding instructions. QEMU is the kernel in user
3032 * mode, so those traps are emulated by accepting the instructions.
3034 * A reserved instruction exception is generated for flagged CPUs if
3035 * QEMU runs in system mode.
3037 static inline void check_insn_opc_user_only(DisasContext
*ctx
, uint64_t flags
)
3039 #ifndef CONFIG_USER_ONLY
3040 check_insn_opc_removed(ctx
, flags
);
3045 * This code generates a "reserved instruction" exception if the
3046 * CPU does not support 64-bit paired-single (PS) floating point data type.
3048 static inline void check_ps(DisasContext
*ctx
)
3050 if (unlikely(!ctx
->ps
)) {
3051 generate_exception(ctx
, EXCP_RI
);
3053 check_cp1_64bitmode(ctx
);
3056 #ifdef TARGET_MIPS64
3058 * This code generates a "reserved instruction" exception if 64-bit
3059 * instructions are not enabled.
3061 static inline void check_mips_64(DisasContext
*ctx
)
3063 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
))) {
3064 generate_exception_end(ctx
, EXCP_RI
);
3069 #ifndef CONFIG_USER_ONLY
3070 static inline void check_mvh(DisasContext
*ctx
)
3072 if (unlikely(!ctx
->mvh
)) {
3073 generate_exception(ctx
, EXCP_RI
);
3079 * This code generates a "reserved instruction" exception if the
3080 * Config5 XNP bit is set.
3082 static inline void check_xnp(DisasContext
*ctx
)
3084 if (unlikely(ctx
->CP0_Config5
& (1 << CP0C5_XNP
))) {
3085 generate_exception_end(ctx
, EXCP_RI
);
3089 #ifndef CONFIG_USER_ONLY
3091 * This code generates a "reserved instruction" exception if the
3092 * Config3 PW bit is NOT set.
3094 static inline void check_pw(DisasContext
*ctx
)
3096 if (unlikely(!(ctx
->CP0_Config3
& (1 << CP0C3_PW
)))) {
3097 generate_exception_end(ctx
, EXCP_RI
);
3103 * This code generates a "reserved instruction" exception if the
3104 * Config3 MT bit is NOT set.
3106 static inline void check_mt(DisasContext
*ctx
)
3108 if (unlikely(!(ctx
->CP0_Config3
& (1 << CP0C3_MT
)))) {
3109 generate_exception_end(ctx
, EXCP_RI
);
3113 #ifndef CONFIG_USER_ONLY
3115 * This code generates a "coprocessor unusable" exception if CP0 is not
3116 * available, and, if that is not the case, generates a "reserved instruction"
3117 * exception if the Config5 MT bit is NOT set. This is needed for availability
3118 * control of some of MT ASE instructions.
3120 static inline void check_cp0_mt(DisasContext
*ctx
)
3122 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
))) {
3123 generate_exception_err(ctx
, EXCP_CpU
, 0);
3125 if (unlikely(!(ctx
->CP0_Config3
& (1 << CP0C3_MT
)))) {
3126 generate_exception_err(ctx
, EXCP_RI
, 0);
3133 * This code generates a "reserved instruction" exception if the
3134 * Config5 NMS bit is set.
3136 static inline void check_nms(DisasContext
*ctx
)
3138 if (unlikely(ctx
->CP0_Config5
& (1 << CP0C5_NMS
))) {
3139 generate_exception_end(ctx
, EXCP_RI
);
3144 * This code generates a "reserved instruction" exception if the
3145 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
3146 * Config2 TL, and Config5 L2C are unset.
3148 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext
*ctx
)
3150 if (unlikely((ctx
->CP0_Config5
& (1 << CP0C5_NMS
)) &&
3151 !(ctx
->CP0_Config1
& (1 << CP0C1_DL
)) &&
3152 !(ctx
->CP0_Config1
& (1 << CP0C1_IL
)) &&
3153 !(ctx
->CP0_Config2
& (1 << CP0C2_SL
)) &&
3154 !(ctx
->CP0_Config2
& (1 << CP0C2_TL
)) &&
3155 !(ctx
->CP0_Config5
& (1 << CP0C5_L2C
)))) {
3156 generate_exception_end(ctx
, EXCP_RI
);
3161 * This code generates a "reserved instruction" exception if the
3162 * Config5 EVA bit is NOT set.
3164 static inline void check_eva(DisasContext
*ctx
)
3166 if (unlikely(!(ctx
->CP0_Config5
& (1 << CP0C5_EVA
)))) {
3167 generate_exception_end(ctx
, EXCP_RI
);
3173 * Define small wrappers for gen_load_fpr* so that we have a uniform
3174 * calling interface for 32 and 64-bit FPRs. No sense in changing
3175 * all callers for gen_load_fpr32 when we need the CTX parameter for
3178 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
3179 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
3180 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
3181 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
3182 int ft, int fs, int cc) \
3184 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \
3185 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \
3194 check_cp1_registers(ctx, fs | ft); \
3202 gen_ldcmp_fpr##bits(ctx, fp0, fs); \
3203 gen_ldcmp_fpr##bits(ctx, fp1, ft); \
3206 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
3209 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
3212 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
3215 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
3218 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
3221 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
3224 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
3227 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
3230 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
3233 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
3236 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
3239 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
3242 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
3245 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
3248 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
3251 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
3256 tcg_temp_free_i##bits(fp0); \
3257 tcg_temp_free_i##bits(fp1); \
3260 FOP_CONDS(, 0, d
, FMT_D
, 64)
3261 FOP_CONDS(abs
, 1, d
, FMT_D
, 64)
3262 FOP_CONDS(, 0, s
, FMT_S
, 32)
3263 FOP_CONDS(abs
, 1, s
, FMT_S
, 32)
3264 FOP_CONDS(, 0, ps
, FMT_PS
, 64)
3265 FOP_CONDS(abs
, 1, ps
, FMT_PS
, 64)
3268 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
3269 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
3270 int ft, int fs, int fd) \
3272 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
3273 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
3274 if (ifmt == FMT_D) { \
3275 check_cp1_registers(ctx, fs | ft | fd); \
3277 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
3278 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
3281 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
3284 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
3287 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
3290 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
3293 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
3296 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
3299 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
3302 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
3305 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
3308 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
3311 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
3314 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
3317 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
3320 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
3323 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
3326 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
3329 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
3332 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
3335 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
3338 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
3341 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
3344 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
3350 tcg_temp_free_i ## bits(fp0); \
3351 tcg_temp_free_i ## bits(fp1); \
3354 FOP_CONDNS(d
, FMT_D
, 64, gen_store_fpr64(ctx
, fp0
, fd
))
3355 FOP_CONDNS(s
, FMT_S
, 32, gen_store_fpr32(ctx
, fp0
, fd
))
3357 #undef gen_ldcmp_fpr32
3358 #undef gen_ldcmp_fpr64
3360 /* load/store instructions. */
3361 #ifdef CONFIG_USER_ONLY
3362 #define OP_LD_ATOMIC(insn, fname) \
3363 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
3364 DisasContext *ctx) \
3366 TCGv t0 = tcg_temp_new(); \
3367 tcg_gen_mov_tl(t0, arg1); \
3368 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
3369 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
3370 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
3371 tcg_temp_free(t0); \
3374 #define OP_LD_ATOMIC(insn, fname) \
3375 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
3376 DisasContext *ctx) \
3378 gen_helper_1e1i(insn, ret, arg1, mem_idx); \
3381 OP_LD_ATOMIC(ll
, ld32s
);
3382 #if defined(TARGET_MIPS64)
3383 OP_LD_ATOMIC(lld
, ld64
);
3387 static void gen_base_offset_addr(DisasContext
*ctx
, TCGv addr
,
3388 int base
, int offset
)
3391 tcg_gen_movi_tl(addr
, offset
);
3392 } else if (offset
== 0) {
3393 gen_load_gpr(addr
, base
);
3395 tcg_gen_movi_tl(addr
, offset
);
3396 gen_op_addr_add(ctx
, addr
, cpu_gpr
[base
], addr
);
3400 static target_ulong
pc_relative_pc(DisasContext
*ctx
)
3402 target_ulong pc
= ctx
->base
.pc_next
;
3404 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
3405 int branch_bytes
= ctx
->hflags
& MIPS_HFLAG_BDS16
? 2 : 4;
3410 pc
&= ~(target_ulong
)3;
3415 static void gen_ld(DisasContext
*ctx
, uint32_t opc
,
3416 int rt
, int base
, int offset
)
3419 int mem_idx
= ctx
->mem_idx
;
3421 if (rt
== 0 && ctx
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)) {
3423 * Loongson CPU uses a load to zero register for prefetch.
3424 * We emulate it as a NOP. On other CPU we must perform the
3425 * actual memory access.
3430 t0
= tcg_temp_new();
3431 gen_base_offset_addr(ctx
, t0
, base
, offset
);
3434 #if defined(TARGET_MIPS64)
3436 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEUL
|
3437 ctx
->default_tcg_memop_mask
);
3438 gen_store_gpr(t0
, rt
);
3441 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEQ
|
3442 ctx
->default_tcg_memop_mask
);
3443 gen_store_gpr(t0
, rt
);
3447 op_ld_lld(t0
, t0
, mem_idx
, ctx
);
3448 gen_store_gpr(t0
, rt
);
3451 t1
= tcg_temp_new();
3453 * Do a byte access to possibly trigger a page
3454 * fault with the unaligned address.
3456 tcg_gen_qemu_ld_tl(t1
, t0
, mem_idx
, MO_UB
);
3457 tcg_gen_andi_tl(t1
, t0
, 7);
3458 #ifndef TARGET_WORDS_BIGENDIAN
3459 tcg_gen_xori_tl(t1
, t1
, 7);
3461 tcg_gen_shli_tl(t1
, t1
, 3);
3462 tcg_gen_andi_tl(t0
, t0
, ~7);
3463 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEQ
);
3464 tcg_gen_shl_tl(t0
, t0
, t1
);
3465 t2
= tcg_const_tl(-1);
3466 tcg_gen_shl_tl(t2
, t2
, t1
);
3467 gen_load_gpr(t1
, rt
);
3468 tcg_gen_andc_tl(t1
, t1
, t2
);
3470 tcg_gen_or_tl(t0
, t0
, t1
);
3472 gen_store_gpr(t0
, rt
);
3475 t1
= tcg_temp_new();
3477 * Do a byte access to possibly trigger a page
3478 * fault with the unaligned address.
3480 tcg_gen_qemu_ld_tl(t1
, t0
, mem_idx
, MO_UB
);
3481 tcg_gen_andi_tl(t1
, t0
, 7);
3482 #ifdef TARGET_WORDS_BIGENDIAN
3483 tcg_gen_xori_tl(t1
, t1
, 7);
3485 tcg_gen_shli_tl(t1
, t1
, 3);
3486 tcg_gen_andi_tl(t0
, t0
, ~7);
3487 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEQ
);
3488 tcg_gen_shr_tl(t0
, t0
, t1
);
3489 tcg_gen_xori_tl(t1
, t1
, 63);
3490 t2
= tcg_const_tl(0xfffffffffffffffeull
);
3491 tcg_gen_shl_tl(t2
, t2
, t1
);
3492 gen_load_gpr(t1
, rt
);
3493 tcg_gen_and_tl(t1
, t1
, t2
);
3495 tcg_gen_or_tl(t0
, t0
, t1
);
3497 gen_store_gpr(t0
, rt
);
3500 t1
= tcg_const_tl(pc_relative_pc(ctx
));
3501 gen_op_addr_add(ctx
, t0
, t0
, t1
);
3503 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEQ
);
3504 gen_store_gpr(t0
, rt
);
3508 t1
= tcg_const_tl(pc_relative_pc(ctx
));
3509 gen_op_addr_add(ctx
, t0
, t0
, t1
);
3511 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TESL
);
3512 gen_store_gpr(t0
, rt
);
3515 mem_idx
= MIPS_HFLAG_UM
;
3518 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TESL
|
3519 ctx
->default_tcg_memop_mask
);
3520 gen_store_gpr(t0
, rt
);
3523 mem_idx
= MIPS_HFLAG_UM
;
3526 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TESW
|
3527 ctx
->default_tcg_memop_mask
);
3528 gen_store_gpr(t0
, rt
);
3531 mem_idx
= MIPS_HFLAG_UM
;
3534 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEUW
|
3535 ctx
->default_tcg_memop_mask
);
3536 gen_store_gpr(t0
, rt
);
3539 mem_idx
= MIPS_HFLAG_UM
;
3542 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_SB
);
3543 gen_store_gpr(t0
, rt
);
3546 mem_idx
= MIPS_HFLAG_UM
;
3549 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_UB
);
3550 gen_store_gpr(t0
, rt
);
3553 mem_idx
= MIPS_HFLAG_UM
;
3556 t1
= tcg_temp_new();
3558 * Do a byte access to possibly trigger a page
3559 * fault with the unaligned address.
3561 tcg_gen_qemu_ld_tl(t1
, t0
, mem_idx
, MO_UB
);
3562 tcg_gen_andi_tl(t1
, t0
, 3);
3563 #ifndef TARGET_WORDS_BIGENDIAN
3564 tcg_gen_xori_tl(t1
, t1
, 3);
3566 tcg_gen_shli_tl(t1
, t1
, 3);
3567 tcg_gen_andi_tl(t0
, t0
, ~3);
3568 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEUL
);
3569 tcg_gen_shl_tl(t0
, t0
, t1
);
3570 t2
= tcg_const_tl(-1);
3571 tcg_gen_shl_tl(t2
, t2
, t1
);
3572 gen_load_gpr(t1
, rt
);
3573 tcg_gen_andc_tl(t1
, t1
, t2
);
3575 tcg_gen_or_tl(t0
, t0
, t1
);
3577 tcg_gen_ext32s_tl(t0
, t0
);
3578 gen_store_gpr(t0
, rt
);
3581 mem_idx
= MIPS_HFLAG_UM
;
3584 t1
= tcg_temp_new();
3586 * Do a byte access to possibly trigger a page
3587 * fault with the unaligned address.
3589 tcg_gen_qemu_ld_tl(t1
, t0
, mem_idx
, MO_UB
);
3590 tcg_gen_andi_tl(t1
, t0
, 3);
3591 #ifdef TARGET_WORDS_BIGENDIAN
3592 tcg_gen_xori_tl(t1
, t1
, 3);
3594 tcg_gen_shli_tl(t1
, t1
, 3);
3595 tcg_gen_andi_tl(t0
, t0
, ~3);
3596 tcg_gen_qemu_ld_tl(t0
, t0
, mem_idx
, MO_TEUL
);
3597 tcg_gen_shr_tl(t0
, t0
, t1
);
3598 tcg_gen_xori_tl(t1
, t1
, 31);
3599 t2
= tcg_const_tl(0xfffffffeull
);
3600 tcg_gen_shl_tl(t2
, t2
, t1
);
3601 gen_load_gpr(t1
, rt
);
3602 tcg_gen_and_tl(t1
, t1
, t2
);
3604 tcg_gen_or_tl(t0
, t0
, t1
);
3606 tcg_gen_ext32s_tl(t0
, t0
);
3607 gen_store_gpr(t0
, rt
);
3610 mem_idx
= MIPS_HFLAG_UM
;
3614 op_ld_ll(t0
, t0
, mem_idx
, ctx
);
3615 gen_store_gpr(t0
, rt
);
3621 static void gen_llwp(DisasContext
*ctx
, uint32_t base
, int16_t offset
,
3622 uint32_t reg1
, uint32_t reg2
)
3624 TCGv taddr
= tcg_temp_new();
3625 TCGv_i64 tval
= tcg_temp_new_i64();
3626 TCGv tmp1
= tcg_temp_new();
3627 TCGv tmp2
= tcg_temp_new();
3629 gen_base_offset_addr(ctx
, taddr
, base
, offset
);
3630 tcg_gen_qemu_ld64(tval
, taddr
, ctx
->mem_idx
);
3631 #ifdef TARGET_WORDS_BIGENDIAN
3632 tcg_gen_extr_i64_tl(tmp2
, tmp1
, tval
);
3634 tcg_gen_extr_i64_tl(tmp1
, tmp2
, tval
);
3636 gen_store_gpr(tmp1
, reg1
);
3637 tcg_temp_free(tmp1
);
3638 gen_store_gpr(tmp2
, reg2
);
3639 tcg_temp_free(tmp2
);
3640 tcg_gen_st_i64(tval
, cpu_env
, offsetof(CPUMIPSState
, llval_wp
));
3641 tcg_temp_free_i64(tval
);
3642 tcg_gen_st_tl(taddr
, cpu_env
, offsetof(CPUMIPSState
, lladdr
));
3643 tcg_temp_free(taddr
);
3647 static void gen_st(DisasContext
*ctx
, uint32_t opc
, int rt
,
3648 int base
, int offset
)
3650 TCGv t0
= tcg_temp_new();
3651 TCGv t1
= tcg_temp_new();
3652 int mem_idx
= ctx
->mem_idx
;
3654 gen_base_offset_addr(ctx
, t0
, base
, offset
);
3655 gen_load_gpr(t1
, rt
);
3657 #if defined(TARGET_MIPS64)
3659 tcg_gen_qemu_st_tl(t1
, t0
, mem_idx
, MO_TEQ
|
3660 ctx
->default_tcg_memop_mask
);
3663 gen_helper_0e2i(sdl
, t1
, t0
, mem_idx
);
3666 gen_helper_0e2i(sdr
, t1
, t0
, mem_idx
);
3670 mem_idx
= MIPS_HFLAG_UM
;
3673 tcg_gen_qemu_st_tl(t1
, t0
, mem_idx
, MO_TEUL
|
3674 ctx
->default_tcg_memop_mask
);
3677 mem_idx
= MIPS_HFLAG_UM
;
3680 tcg_gen_qemu_st_tl(t1
, t0
, mem_idx
, MO_TEUW
|
3681 ctx
->default_tcg_memop_mask
);
3684 mem_idx
= MIPS_HFLAG_UM
;
3687 tcg_gen_qemu_st_tl(t1
, t0
, mem_idx
, MO_8
);
3690 mem_idx
= MIPS_HFLAG_UM
;
3693 gen_helper_0e2i(swl
, t1
, t0
, mem_idx
);
3696 mem_idx
= MIPS_HFLAG_UM
;
3699 gen_helper_0e2i(swr
, t1
, t0
, mem_idx
);
3707 /* Store conditional */
3708 static void gen_st_cond(DisasContext
*ctx
, int rt
, int base
, int offset
,
3709 MemOp tcg_mo
, bool eva
)
3712 TCGLabel
*l1
= gen_new_label();
3713 TCGLabel
*done
= gen_new_label();
3715 t0
= tcg_temp_new();
3716 addr
= tcg_temp_new();
3717 /* compare the address against that of the preceeding LL */
3718 gen_base_offset_addr(ctx
, addr
, base
, offset
);
3719 tcg_gen_brcond_tl(TCG_COND_EQ
, addr
, cpu_lladdr
, l1
);
3720 tcg_temp_free(addr
);
3721 tcg_gen_movi_tl(t0
, 0);
3722 gen_store_gpr(t0
, rt
);
3726 /* generate cmpxchg */
3727 val
= tcg_temp_new();
3728 gen_load_gpr(val
, rt
);
3729 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_lladdr
, cpu_llval
, val
,
3730 eva
? MIPS_HFLAG_UM
: ctx
->mem_idx
, tcg_mo
);
3731 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_llval
);
3732 gen_store_gpr(t0
, rt
);
3735 gen_set_label(done
);
3740 static void gen_scwp(DisasContext
*ctx
, uint32_t base
, int16_t offset
,
3741 uint32_t reg1
, uint32_t reg2
, bool eva
)
3743 TCGv taddr
= tcg_temp_local_new();
3744 TCGv lladdr
= tcg_temp_local_new();
3745 TCGv_i64 tval
= tcg_temp_new_i64();
3746 TCGv_i64 llval
= tcg_temp_new_i64();
3747 TCGv_i64 val
= tcg_temp_new_i64();
3748 TCGv tmp1
= tcg_temp_new();
3749 TCGv tmp2
= tcg_temp_new();
3750 TCGLabel
*lab_fail
= gen_new_label();
3751 TCGLabel
*lab_done
= gen_new_label();
3753 gen_base_offset_addr(ctx
, taddr
, base
, offset
);
3755 tcg_gen_ld_tl(lladdr
, cpu_env
, offsetof(CPUMIPSState
, lladdr
));
3756 tcg_gen_brcond_tl(TCG_COND_NE
, taddr
, lladdr
, lab_fail
);
3758 gen_load_gpr(tmp1
, reg1
);
3759 gen_load_gpr(tmp2
, reg2
);
3761 #ifdef TARGET_WORDS_BIGENDIAN
3762 tcg_gen_concat_tl_i64(tval
, tmp2
, tmp1
);
3764 tcg_gen_concat_tl_i64(tval
, tmp1
, tmp2
);
3767 tcg_gen_ld_i64(llval
, cpu_env
, offsetof(CPUMIPSState
, llval_wp
));
3768 tcg_gen_atomic_cmpxchg_i64(val
, taddr
, llval
, tval
,
3769 eva
? MIPS_HFLAG_UM
: ctx
->mem_idx
, MO_64
);
3771 tcg_gen_movi_tl(cpu_gpr
[reg1
], 1);
3773 tcg_gen_brcond_i64(TCG_COND_EQ
, val
, llval
, lab_done
);
3775 gen_set_label(lab_fail
);
3778 tcg_gen_movi_tl(cpu_gpr
[reg1
], 0);
3780 gen_set_label(lab_done
);
3781 tcg_gen_movi_tl(lladdr
, -1);
3782 tcg_gen_st_tl(lladdr
, cpu_env
, offsetof(CPUMIPSState
, lladdr
));
3785 /* Load and store */
3786 static void gen_flt_ldst(DisasContext
*ctx
, uint32_t opc
, int ft
,
3790 * Don't do NOP if destination is zero: we must perform the actual
3796 TCGv_i32 fp0
= tcg_temp_new_i32();
3797 tcg_gen_qemu_ld_i32(fp0
, t0
, ctx
->mem_idx
, MO_TESL
|
3798 ctx
->default_tcg_memop_mask
);
3799 gen_store_fpr32(ctx
, fp0
, ft
);
3800 tcg_temp_free_i32(fp0
);
3805 TCGv_i32 fp0
= tcg_temp_new_i32();
3806 gen_load_fpr32(ctx
, fp0
, ft
);
3807 tcg_gen_qemu_st_i32(fp0
, t0
, ctx
->mem_idx
, MO_TEUL
|
3808 ctx
->default_tcg_memop_mask
);
3809 tcg_temp_free_i32(fp0
);
3814 TCGv_i64 fp0
= tcg_temp_new_i64();
3815 tcg_gen_qemu_ld_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
|
3816 ctx
->default_tcg_memop_mask
);
3817 gen_store_fpr64(ctx
, fp0
, ft
);
3818 tcg_temp_free_i64(fp0
);
3823 TCGv_i64 fp0
= tcg_temp_new_i64();
3824 gen_load_fpr64(ctx
, fp0
, ft
);
3825 tcg_gen_qemu_st_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
|
3826 ctx
->default_tcg_memop_mask
);
3827 tcg_temp_free_i64(fp0
);
3831 MIPS_INVAL("flt_ldst");
3832 generate_exception_end(ctx
, EXCP_RI
);
3837 static void gen_cop1_ldst(DisasContext
*ctx
, uint32_t op
, int rt
,
3838 int rs
, int16_t imm
)
3840 TCGv t0
= tcg_temp_new();
3842 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
3843 check_cp1_enabled(ctx
);
3847 check_insn(ctx
, ISA_MIPS2
);
3850 gen_base_offset_addr(ctx
, t0
, rs
, imm
);
3851 gen_flt_ldst(ctx
, op
, rt
, t0
);
3854 generate_exception_err(ctx
, EXCP_CpU
, 1);
3859 /* Arithmetic with immediate operand */
3860 static void gen_arith_imm(DisasContext
*ctx
, uint32_t opc
,
3861 int rt
, int rs
, int imm
)
3863 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
3865 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
3867 * If no destination, treat it as a NOP.
3868 * For addi, we must generate the overflow exception when needed.
3875 TCGv t0
= tcg_temp_local_new();
3876 TCGv t1
= tcg_temp_new();
3877 TCGv t2
= tcg_temp_new();
3878 TCGLabel
*l1
= gen_new_label();
3880 gen_load_gpr(t1
, rs
);
3881 tcg_gen_addi_tl(t0
, t1
, uimm
);
3882 tcg_gen_ext32s_tl(t0
, t0
);
3884 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
3885 tcg_gen_xori_tl(t2
, t0
, uimm
);
3886 tcg_gen_and_tl(t1
, t1
, t2
);
3888 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
3890 /* operands of same sign, result different sign */
3891 generate_exception(ctx
, EXCP_OVERFLOW
);
3893 tcg_gen_ext32s_tl(t0
, t0
);
3894 gen_store_gpr(t0
, rt
);
3900 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
3901 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
3903 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
3906 #if defined(TARGET_MIPS64)
3909 TCGv t0
= tcg_temp_local_new();
3910 TCGv t1
= tcg_temp_new();
3911 TCGv t2
= tcg_temp_new();
3912 TCGLabel
*l1
= gen_new_label();
3914 gen_load_gpr(t1
, rs
);
3915 tcg_gen_addi_tl(t0
, t1
, uimm
);
3917 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
3918 tcg_gen_xori_tl(t2
, t0
, uimm
);
3919 tcg_gen_and_tl(t1
, t1
, t2
);
3921 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
3923 /* operands of same sign, result different sign */
3924 generate_exception(ctx
, EXCP_OVERFLOW
);
3926 gen_store_gpr(t0
, rt
);
3932 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
3934 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
3941 /* Logic with immediate operand */
3942 static void gen_logic_imm(DisasContext
*ctx
, uint32_t opc
,
3943 int rt
, int rs
, int16_t imm
)
3948 /* If no destination, treat it as a NOP. */
3951 uimm
= (uint16_t)imm
;
3954 if (likely(rs
!= 0)) {
3955 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
3957 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
3962 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
3964 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
3968 if (likely(rs
!= 0)) {
3969 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
3971 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
3975 if (rs
!= 0 && (ctx
->insn_flags
& ISA_MIPS32R6
)) {
3977 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], imm
<< 16);
3978 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
3980 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
3989 /* Set on less than with immediate operand */
3990 static void gen_slt_imm(DisasContext
*ctx
, uint32_t opc
,
3991 int rt
, int rs
, int16_t imm
)
3993 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
3997 /* If no destination, treat it as a NOP. */
4000 t0
= tcg_temp_new();
4001 gen_load_gpr(t0
, rs
);
4004 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr
[rt
], t0
, uimm
);
4007 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr
[rt
], t0
, uimm
);
4013 /* Shifts with immediate operand */
4014 static void gen_shift_imm(DisasContext
*ctx
, uint32_t opc
,
4015 int rt
, int rs
, int16_t imm
)
4017 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
4021 /* If no destination, treat it as a NOP. */
4025 t0
= tcg_temp_new();
4026 gen_load_gpr(t0
, rs
);
4029 tcg_gen_shli_tl(t0
, t0
, uimm
);
4030 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
4033 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
4037 tcg_gen_ext32u_tl(t0
, t0
);
4038 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
4040 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
4045 TCGv_i32 t1
= tcg_temp_new_i32();
4047 tcg_gen_trunc_tl_i32(t1
, t0
);
4048 tcg_gen_rotri_i32(t1
, t1
, uimm
);
4049 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
4050 tcg_temp_free_i32(t1
);
4052 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
4055 #if defined(TARGET_MIPS64)
4057 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
4060 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
4063 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
4067 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
4069 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
4073 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
4076 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
4079 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
4082 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
4090 static void gen_arith(DisasContext
*ctx
, uint32_t opc
,
4091 int rd
, int rs
, int rt
)
4093 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
4094 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
4096 * If no destination, treat it as a NOP.
4097 * For add & sub, we must generate the overflow exception when needed.
4105 TCGv t0
= tcg_temp_local_new();
4106 TCGv t1
= tcg_temp_new();
4107 TCGv t2
= tcg_temp_new();
4108 TCGLabel
*l1
= gen_new_label();
4110 gen_load_gpr(t1
, rs
);
4111 gen_load_gpr(t2
, rt
);
4112 tcg_gen_add_tl(t0
, t1
, t2
);
4113 tcg_gen_ext32s_tl(t0
, t0
);
4114 tcg_gen_xor_tl(t1
, t1
, t2
);
4115 tcg_gen_xor_tl(t2
, t0
, t2
);
4116 tcg_gen_andc_tl(t1
, t2
, t1
);
4118 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
4120 /* operands of same sign, result different sign */
4121 generate_exception(ctx
, EXCP_OVERFLOW
);
4123 gen_store_gpr(t0
, rd
);
4128 if (rs
!= 0 && rt
!= 0) {
4129 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4130 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4131 } else if (rs
== 0 && rt
!= 0) {
4132 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4133 } else if (rs
!= 0 && rt
== 0) {
4134 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4136 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4141 TCGv t0
= tcg_temp_local_new();
4142 TCGv t1
= tcg_temp_new();
4143 TCGv t2
= tcg_temp_new();
4144 TCGLabel
*l1
= gen_new_label();
4146 gen_load_gpr(t1
, rs
);
4147 gen_load_gpr(t2
, rt
);
4148 tcg_gen_sub_tl(t0
, t1
, t2
);
4149 tcg_gen_ext32s_tl(t0
, t0
);
4150 tcg_gen_xor_tl(t2
, t1
, t2
);
4151 tcg_gen_xor_tl(t1
, t0
, t1
);
4152 tcg_gen_and_tl(t1
, t1
, t2
);
4154 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
4157 * operands of different sign, first operand and the result
4160 generate_exception(ctx
, EXCP_OVERFLOW
);
4162 gen_store_gpr(t0
, rd
);
4167 if (rs
!= 0 && rt
!= 0) {
4168 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4169 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4170 } else if (rs
== 0 && rt
!= 0) {
4171 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4172 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4173 } else if (rs
!= 0 && rt
== 0) {
4174 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4176 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4179 #if defined(TARGET_MIPS64)
4182 TCGv t0
= tcg_temp_local_new();
4183 TCGv t1
= tcg_temp_new();
4184 TCGv t2
= tcg_temp_new();
4185 TCGLabel
*l1
= gen_new_label();
4187 gen_load_gpr(t1
, rs
);
4188 gen_load_gpr(t2
, rt
);
4189 tcg_gen_add_tl(t0
, t1
, t2
);
4190 tcg_gen_xor_tl(t1
, t1
, t2
);
4191 tcg_gen_xor_tl(t2
, t0
, t2
);
4192 tcg_gen_andc_tl(t1
, t2
, t1
);
4194 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
4196 /* operands of same sign, result different sign */
4197 generate_exception(ctx
, EXCP_OVERFLOW
);
4199 gen_store_gpr(t0
, rd
);
4204 if (rs
!= 0 && rt
!= 0) {
4205 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4206 } else if (rs
== 0 && rt
!= 0) {
4207 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4208 } else if (rs
!= 0 && rt
== 0) {
4209 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4211 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4216 TCGv t0
= tcg_temp_local_new();
4217 TCGv t1
= tcg_temp_new();
4218 TCGv t2
= tcg_temp_new();
4219 TCGLabel
*l1
= gen_new_label();
4221 gen_load_gpr(t1
, rs
);
4222 gen_load_gpr(t2
, rt
);
4223 tcg_gen_sub_tl(t0
, t1
, t2
);
4224 tcg_gen_xor_tl(t2
, t1
, t2
);
4225 tcg_gen_xor_tl(t1
, t0
, t1
);
4226 tcg_gen_and_tl(t1
, t1
, t2
);
4228 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
4231 * Operands of different sign, first operand and result different
4234 generate_exception(ctx
, EXCP_OVERFLOW
);
4236 gen_store_gpr(t0
, rd
);
4241 if (rs
!= 0 && rt
!= 0) {
4242 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4243 } else if (rs
== 0 && rt
!= 0) {
4244 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4245 } else if (rs
!= 0 && rt
== 0) {
4246 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4248 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4253 if (likely(rs
!= 0 && rt
!= 0)) {
4254 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4255 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4257 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4263 /* Conditional move */
4264 static void gen_cond_move(DisasContext
*ctx
, uint32_t opc
,
4265 int rd
, int rs
, int rt
)
4270 /* If no destination, treat it as a NOP. */
4274 t0
= tcg_temp_new();
4275 gen_load_gpr(t0
, rt
);
4276 t1
= tcg_const_tl(0);
4277 t2
= tcg_temp_new();
4278 gen_load_gpr(t2
, rs
);
4281 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rd
], t0
, t1
, t2
, cpu_gpr
[rd
]);
4284 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr
[rd
], t0
, t1
, t2
, cpu_gpr
[rd
]);
4287 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rd
], t0
, t1
, t2
, t1
);
4290 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr
[rd
], t0
, t1
, t2
, t1
);
4299 static void gen_logic(DisasContext
*ctx
, uint32_t opc
,
4300 int rd
, int rs
, int rt
)
4303 /* If no destination, treat it as a NOP. */
4309 if (likely(rs
!= 0 && rt
!= 0)) {
4310 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4312 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4316 if (rs
!= 0 && rt
!= 0) {
4317 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4318 } else if (rs
== 0 && rt
!= 0) {
4319 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4320 } else if (rs
!= 0 && rt
== 0) {
4321 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4323 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
4327 if (likely(rs
!= 0 && rt
!= 0)) {
4328 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4329 } else if (rs
== 0 && rt
!= 0) {
4330 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4331 } else if (rs
!= 0 && rt
== 0) {
4332 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4334 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4338 if (likely(rs
!= 0 && rt
!= 0)) {
4339 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
4340 } else if (rs
== 0 && rt
!= 0) {
4341 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
4342 } else if (rs
!= 0 && rt
== 0) {
4343 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
4345 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4351 /* Set on lower than */
4352 static void gen_slt(DisasContext
*ctx
, uint32_t opc
,
4353 int rd
, int rs
, int rt
)
4358 /* If no destination, treat it as a NOP. */
4362 t0
= tcg_temp_new();
4363 t1
= tcg_temp_new();
4364 gen_load_gpr(t0
, rs
);
4365 gen_load_gpr(t1
, rt
);
4368 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr
[rd
], t0
, t1
);
4371 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr
[rd
], t0
, t1
);
4379 static void gen_shift(DisasContext
*ctx
, uint32_t opc
,
4380 int rd
, int rs
, int rt
)
4386 * If no destination, treat it as a NOP.
4387 * For add & sub, we must generate the overflow exception when needed.
4392 t0
= tcg_temp_new();
4393 t1
= tcg_temp_new();
4394 gen_load_gpr(t0
, rs
);
4395 gen_load_gpr(t1
, rt
);
4398 tcg_gen_andi_tl(t0
, t0
, 0x1f);
4399 tcg_gen_shl_tl(t0
, t1
, t0
);
4400 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
4403 tcg_gen_andi_tl(t0
, t0
, 0x1f);
4404 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
4407 tcg_gen_ext32u_tl(t1
, t1
);
4408 tcg_gen_andi_tl(t0
, t0
, 0x1f);
4409 tcg_gen_shr_tl(t0
, t1
, t0
);
4410 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
4414 TCGv_i32 t2
= tcg_temp_new_i32();
4415 TCGv_i32 t3
= tcg_temp_new_i32();
4417 tcg_gen_trunc_tl_i32(t2
, t0
);
4418 tcg_gen_trunc_tl_i32(t3
, t1
);
4419 tcg_gen_andi_i32(t2
, t2
, 0x1f);
4420 tcg_gen_rotr_i32(t2
, t3
, t2
);
4421 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
4422 tcg_temp_free_i32(t2
);
4423 tcg_temp_free_i32(t3
);
4426 #if defined(TARGET_MIPS64)
4428 tcg_gen_andi_tl(t0
, t0
, 0x3f);
4429 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
4432 tcg_gen_andi_tl(t0
, t0
, 0x3f);
4433 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
4436 tcg_gen_andi_tl(t0
, t0
, 0x3f);
4437 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
4440 tcg_gen_andi_tl(t0
, t0
, 0x3f);
4441 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
4449 #if defined(TARGET_MIPS64)
4450 /* Copy GPR to and from TX79 HI1/LO1 register. */
4451 static void gen_HILO1_tx79(DisasContext
*ctx
, uint32_t opc
, int reg
)
4453 if (reg
== 0 && (opc
== MMI_OPC_MFHI1
|| opc
== MMI_OPC_MFLO1
)) {
4460 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[1]);
4463 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[1]);
4467 tcg_gen_mov_tl(cpu_HI
[1], cpu_gpr
[reg
]);
4469 tcg_gen_movi_tl(cpu_HI
[1], 0);
4474 tcg_gen_mov_tl(cpu_LO
[1], cpu_gpr
[reg
]);
4476 tcg_gen_movi_tl(cpu_LO
[1], 0);
4480 MIPS_INVAL("mfthilo1 TX79");
4481 generate_exception_end(ctx
, EXCP_RI
);
4487 /* Arithmetic on HI/LO registers */
4488 static void gen_HILO(DisasContext
*ctx
, uint32_t opc
, int acc
, int reg
)
4490 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
4501 #if defined(TARGET_MIPS64)
4503 tcg_gen_ext32s_tl(cpu_gpr
[reg
], cpu_HI
[acc
]);
4507 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[acc
]);
4511 #if defined(TARGET_MIPS64)
4513 tcg_gen_ext32s_tl(cpu_gpr
[reg
], cpu_LO
[acc
]);
4517 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[acc
]);
4522 #if defined(TARGET_MIPS64)
4524 tcg_gen_ext32s_tl(cpu_HI
[acc
], cpu_gpr
[reg
]);
4528 tcg_gen_mov_tl(cpu_HI
[acc
], cpu_gpr
[reg
]);
4531 tcg_gen_movi_tl(cpu_HI
[acc
], 0);
4536 #if defined(TARGET_MIPS64)
4538 tcg_gen_ext32s_tl(cpu_LO
[acc
], cpu_gpr
[reg
]);
4542 tcg_gen_mov_tl(cpu_LO
[acc
], cpu_gpr
[reg
]);
4545 tcg_gen_movi_tl(cpu_LO
[acc
], 0);
4551 static inline void gen_r6_ld(target_long addr
, int reg
, int memidx
,
4554 TCGv t0
= tcg_const_tl(addr
);
4555 tcg_gen_qemu_ld_tl(t0
, t0
, memidx
, memop
);
4556 gen_store_gpr(t0
, reg
);
4560 static inline void gen_pcrel(DisasContext
*ctx
, int opc
, target_ulong pc
,
4566 switch (MASK_OPC_PCREL_TOP2BITS(opc
)) {
4569 offset
= sextract32(ctx
->opcode
<< 2, 0, 21);
4570 addr
= addr_add(ctx
, pc
, offset
);
4571 tcg_gen_movi_tl(cpu_gpr
[rs
], addr
);
4575 offset
= sextract32(ctx
->opcode
<< 2, 0, 21);
4576 addr
= addr_add(ctx
, pc
, offset
);
4577 gen_r6_ld(addr
, rs
, ctx
->mem_idx
, MO_TESL
);
4579 #if defined(TARGET_MIPS64)
4582 offset
= sextract32(ctx
->opcode
<< 2, 0, 21);
4583 addr
= addr_add(ctx
, pc
, offset
);
4584 gen_r6_ld(addr
, rs
, ctx
->mem_idx
, MO_TEUL
);
4588 switch (MASK_OPC_PCREL_TOP5BITS(opc
)) {
4591 offset
= sextract32(ctx
->opcode
, 0, 16) << 16;
4592 addr
= addr_add(ctx
, pc
, offset
);
4593 tcg_gen_movi_tl(cpu_gpr
[rs
], addr
);
4598 offset
= sextract32(ctx
->opcode
, 0, 16) << 16;
4599 addr
= ~0xFFFF & addr_add(ctx
, pc
, offset
);
4600 tcg_gen_movi_tl(cpu_gpr
[rs
], addr
);
4603 #if defined(TARGET_MIPS64)
4604 case R6_OPC_LDPC
: /* bits 16 and 17 are part of immediate */
4605 case R6_OPC_LDPC
+ (1 << 16):
4606 case R6_OPC_LDPC
+ (2 << 16):
4607 case R6_OPC_LDPC
+ (3 << 16):
4609 offset
= sextract32(ctx
->opcode
<< 3, 0, 21);
4610 addr
= addr_add(ctx
, (pc
& ~0x7), offset
);
4611 gen_r6_ld(addr
, rs
, ctx
->mem_idx
, MO_TEQ
);
4615 MIPS_INVAL("OPC_PCREL");
4616 generate_exception_end(ctx
, EXCP_RI
);
4623 static void gen_r6_muldiv(DisasContext
*ctx
, int opc
, int rd
, int rs
, int rt
)
4632 t0
= tcg_temp_new();
4633 t1
= tcg_temp_new();
4635 gen_load_gpr(t0
, rs
);
4636 gen_load_gpr(t1
, rt
);
4641 TCGv t2
= tcg_temp_new();
4642 TCGv t3
= tcg_temp_new();
4643 tcg_gen_ext32s_tl(t0
, t0
);
4644 tcg_gen_ext32s_tl(t1
, t1
);
4645 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
4646 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
4647 tcg_gen_and_tl(t2
, t2
, t3
);
4648 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4649 tcg_gen_or_tl(t2
, t2
, t3
);
4650 tcg_gen_movi_tl(t3
, 0);
4651 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4652 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
4653 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4660 TCGv t2
= tcg_temp_new();
4661 TCGv t3
= tcg_temp_new();
4662 tcg_gen_ext32s_tl(t0
, t0
);
4663 tcg_gen_ext32s_tl(t1
, t1
);
4664 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
4665 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
4666 tcg_gen_and_tl(t2
, t2
, t3
);
4667 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4668 tcg_gen_or_tl(t2
, t2
, t3
);
4669 tcg_gen_movi_tl(t3
, 0);
4670 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4671 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
4672 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4679 TCGv t2
= tcg_const_tl(0);
4680 TCGv t3
= tcg_const_tl(1);
4681 tcg_gen_ext32u_tl(t0
, t0
);
4682 tcg_gen_ext32u_tl(t1
, t1
);
4683 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4684 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
4685 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4692 TCGv t2
= tcg_const_tl(0);
4693 TCGv t3
= tcg_const_tl(1);
4694 tcg_gen_ext32u_tl(t0
, t0
);
4695 tcg_gen_ext32u_tl(t1
, t1
);
4696 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4697 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
4698 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
4705 TCGv_i32 t2
= tcg_temp_new_i32();
4706 TCGv_i32 t3
= tcg_temp_new_i32();
4707 tcg_gen_trunc_tl_i32(t2
, t0
);
4708 tcg_gen_trunc_tl_i32(t3
, t1
);
4709 tcg_gen_mul_i32(t2
, t2
, t3
);
4710 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
4711 tcg_temp_free_i32(t2
);
4712 tcg_temp_free_i32(t3
);
4717 TCGv_i32 t2
= tcg_temp_new_i32();
4718 TCGv_i32 t3
= tcg_temp_new_i32();
4719 tcg_gen_trunc_tl_i32(t2
, t0
);
4720 tcg_gen_trunc_tl_i32(t3
, t1
);
4721 tcg_gen_muls2_i32(t2
, t3
, t2
, t3
);
4722 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t3
);
4723 tcg_temp_free_i32(t2
);
4724 tcg_temp_free_i32(t3
);
4729 TCGv_i32 t2
= tcg_temp_new_i32();
4730 TCGv_i32 t3
= tcg_temp_new_i32();
4731 tcg_gen_trunc_tl_i32(t2
, t0
);
4732 tcg_gen_trunc_tl_i32(t3
, t1
);
4733 tcg_gen_mul_i32(t2
, t2
, t3
);
4734 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
4735 tcg_temp_free_i32(t2
);
4736 tcg_temp_free_i32(t3
);
4741 TCGv_i32 t2
= tcg_temp_new_i32();
4742 TCGv_i32 t3
= tcg_temp_new_i32();
4743 tcg_gen_trunc_tl_i32(t2
, t0
);
4744 tcg_gen_trunc_tl_i32(t3
, t1
);
4745 tcg_gen_mulu2_i32(t2
, t3
, t2
, t3
);
4746 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t3
);
4747 tcg_temp_free_i32(t2
);
4748 tcg_temp_free_i32(t3
);
4751 #if defined(TARGET_MIPS64)
4754 TCGv t2
= tcg_temp_new();
4755 TCGv t3
= tcg_temp_new();
4756 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, -1LL << 63);
4757 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1LL);
4758 tcg_gen_and_tl(t2
, t2
, t3
);
4759 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4760 tcg_gen_or_tl(t2
, t2
, t3
);
4761 tcg_gen_movi_tl(t3
, 0);
4762 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4763 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
4770 TCGv t2
= tcg_temp_new();
4771 TCGv t3
= tcg_temp_new();
4772 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, -1LL << 63);
4773 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1LL);
4774 tcg_gen_and_tl(t2
, t2
, t3
);
4775 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4776 tcg_gen_or_tl(t2
, t2
, t3
);
4777 tcg_gen_movi_tl(t3
, 0);
4778 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4779 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
4786 TCGv t2
= tcg_const_tl(0);
4787 TCGv t3
= tcg_const_tl(1);
4788 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4789 tcg_gen_divu_i64(cpu_gpr
[rd
], t0
, t1
);
4796 TCGv t2
= tcg_const_tl(0);
4797 TCGv t3
= tcg_const_tl(1);
4798 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4799 tcg_gen_remu_i64(cpu_gpr
[rd
], t0
, t1
);
4805 tcg_gen_mul_i64(cpu_gpr
[rd
], t0
, t1
);
4809 TCGv t2
= tcg_temp_new();
4810 tcg_gen_muls2_i64(t2
, cpu_gpr
[rd
], t0
, t1
);
4815 tcg_gen_mul_i64(cpu_gpr
[rd
], t0
, t1
);
4819 TCGv t2
= tcg_temp_new();
4820 tcg_gen_mulu2_i64(t2
, cpu_gpr
[rd
], t0
, t1
);
4826 MIPS_INVAL("r6 mul/div");
4827 generate_exception_end(ctx
, EXCP_RI
);
4835 #if defined(TARGET_MIPS64)
4836 static void gen_div1_tx79(DisasContext
*ctx
, uint32_t opc
, int rs
, int rt
)
4840 t0
= tcg_temp_new();
4841 t1
= tcg_temp_new();
4843 gen_load_gpr(t0
, rs
);
4844 gen_load_gpr(t1
, rt
);
4849 TCGv t2
= tcg_temp_new();
4850 TCGv t3
= tcg_temp_new();
4851 tcg_gen_ext32s_tl(t0
, t0
);
4852 tcg_gen_ext32s_tl(t1
, t1
);
4853 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
4854 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
4855 tcg_gen_and_tl(t2
, t2
, t3
);
4856 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4857 tcg_gen_or_tl(t2
, t2
, t3
);
4858 tcg_gen_movi_tl(t3
, 0);
4859 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4860 tcg_gen_div_tl(cpu_LO
[1], t0
, t1
);
4861 tcg_gen_rem_tl(cpu_HI
[1], t0
, t1
);
4862 tcg_gen_ext32s_tl(cpu_LO
[1], cpu_LO
[1]);
4863 tcg_gen_ext32s_tl(cpu_HI
[1], cpu_HI
[1]);
4870 TCGv t2
= tcg_const_tl(0);
4871 TCGv t3
= tcg_const_tl(1);
4872 tcg_gen_ext32u_tl(t0
, t0
);
4873 tcg_gen_ext32u_tl(t1
, t1
);
4874 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4875 tcg_gen_divu_tl(cpu_LO
[1], t0
, t1
);
4876 tcg_gen_remu_tl(cpu_HI
[1], t0
, t1
);
4877 tcg_gen_ext32s_tl(cpu_LO
[1], cpu_LO
[1]);
4878 tcg_gen_ext32s_tl(cpu_HI
[1], cpu_HI
[1]);
4884 MIPS_INVAL("div1 TX79");
4885 generate_exception_end(ctx
, EXCP_RI
);
4894 static void gen_muldiv(DisasContext
*ctx
, uint32_t opc
,
4895 int acc
, int rs
, int rt
)
4899 t0
= tcg_temp_new();
4900 t1
= tcg_temp_new();
4902 gen_load_gpr(t0
, rs
);
4903 gen_load_gpr(t1
, rt
);
4912 TCGv t2
= tcg_temp_new();
4913 TCGv t3
= tcg_temp_new();
4914 tcg_gen_ext32s_tl(t0
, t0
);
4915 tcg_gen_ext32s_tl(t1
, t1
);
4916 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
4917 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
4918 tcg_gen_and_tl(t2
, t2
, t3
);
4919 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4920 tcg_gen_or_tl(t2
, t2
, t3
);
4921 tcg_gen_movi_tl(t3
, 0);
4922 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4923 tcg_gen_div_tl(cpu_LO
[acc
], t0
, t1
);
4924 tcg_gen_rem_tl(cpu_HI
[acc
], t0
, t1
);
4925 tcg_gen_ext32s_tl(cpu_LO
[acc
], cpu_LO
[acc
]);
4926 tcg_gen_ext32s_tl(cpu_HI
[acc
], cpu_HI
[acc
]);
4933 TCGv t2
= tcg_const_tl(0);
4934 TCGv t3
= tcg_const_tl(1);
4935 tcg_gen_ext32u_tl(t0
, t0
);
4936 tcg_gen_ext32u_tl(t1
, t1
);
4937 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4938 tcg_gen_divu_tl(cpu_LO
[acc
], t0
, t1
);
4939 tcg_gen_remu_tl(cpu_HI
[acc
], t0
, t1
);
4940 tcg_gen_ext32s_tl(cpu_LO
[acc
], cpu_LO
[acc
]);
4941 tcg_gen_ext32s_tl(cpu_HI
[acc
], cpu_HI
[acc
]);
4948 TCGv_i32 t2
= tcg_temp_new_i32();
4949 TCGv_i32 t3
= tcg_temp_new_i32();
4950 tcg_gen_trunc_tl_i32(t2
, t0
);
4951 tcg_gen_trunc_tl_i32(t3
, t1
);
4952 tcg_gen_muls2_i32(t2
, t3
, t2
, t3
);
4953 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
4954 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
4955 tcg_temp_free_i32(t2
);
4956 tcg_temp_free_i32(t3
);
4961 TCGv_i32 t2
= tcg_temp_new_i32();
4962 TCGv_i32 t3
= tcg_temp_new_i32();
4963 tcg_gen_trunc_tl_i32(t2
, t0
);
4964 tcg_gen_trunc_tl_i32(t3
, t1
);
4965 tcg_gen_mulu2_i32(t2
, t3
, t2
, t3
);
4966 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
4967 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
4968 tcg_temp_free_i32(t2
);
4969 tcg_temp_free_i32(t3
);
4972 #if defined(TARGET_MIPS64)
4975 TCGv t2
= tcg_temp_new();
4976 TCGv t3
= tcg_temp_new();
4977 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, -1LL << 63);
4978 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1LL);
4979 tcg_gen_and_tl(t2
, t2
, t3
);
4980 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
4981 tcg_gen_or_tl(t2
, t2
, t3
);
4982 tcg_gen_movi_tl(t3
, 0);
4983 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
4984 tcg_gen_div_tl(cpu_LO
[acc
], t0
, t1
);
4985 tcg_gen_rem_tl(cpu_HI
[acc
], t0
, t1
);
4992 TCGv t2
= tcg_const_tl(0);
4993 TCGv t3
= tcg_const_tl(1);
4994 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
4995 tcg_gen_divu_i64(cpu_LO
[acc
], t0
, t1
);
4996 tcg_gen_remu_i64(cpu_HI
[acc
], t0
, t1
);
5002 tcg_gen_muls2_i64(cpu_LO
[acc
], cpu_HI
[acc
], t0
, t1
);
5005 tcg_gen_mulu2_i64(cpu_LO
[acc
], cpu_HI
[acc
], t0
, t1
);
5010 TCGv_i64 t2
= tcg_temp_new_i64();
5011 TCGv_i64 t3
= tcg_temp_new_i64();
5013 tcg_gen_ext_tl_i64(t2
, t0
);
5014 tcg_gen_ext_tl_i64(t3
, t1
);
5015 tcg_gen_mul_i64(t2
, t2
, t3
);
5016 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
5017 tcg_gen_add_i64(t2
, t2
, t3
);
5018 tcg_temp_free_i64(t3
);
5019 gen_move_low32(cpu_LO
[acc
], t2
);
5020 gen_move_high32(cpu_HI
[acc
], t2
);
5021 tcg_temp_free_i64(t2
);
5026 TCGv_i64 t2
= tcg_temp_new_i64();
5027 TCGv_i64 t3
= tcg_temp_new_i64();
5029 tcg_gen_ext32u_tl(t0
, t0
);
5030 tcg_gen_ext32u_tl(t1
, t1
);
5031 tcg_gen_extu_tl_i64(t2
, t0
);
5032 tcg_gen_extu_tl_i64(t3
, t1
);
5033 tcg_gen_mul_i64(t2
, t2
, t3
);
5034 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
5035 tcg_gen_add_i64(t2
, t2
, t3
);
5036 tcg_temp_free_i64(t3
);
5037 gen_move_low32(cpu_LO
[acc
], t2
);
5038 gen_move_high32(cpu_HI
[acc
], t2
);
5039 tcg_temp_free_i64(t2
);
5044 TCGv_i64 t2
= tcg_temp_new_i64();
5045 TCGv_i64 t3
= tcg_temp_new_i64();
5047 tcg_gen_ext_tl_i64(t2
, t0
);
5048 tcg_gen_ext_tl_i64(t3
, t1
);
5049 tcg_gen_mul_i64(t2
, t2
, t3
);
5050 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
5051 tcg_gen_sub_i64(t2
, t3
, t2
);
5052 tcg_temp_free_i64(t3
);
5053 gen_move_low32(cpu_LO
[acc
], t2
);
5054 gen_move_high32(cpu_HI
[acc
], t2
);
5055 tcg_temp_free_i64(t2
);
5060 TCGv_i64 t2
= tcg_temp_new_i64();
5061 TCGv_i64 t3
= tcg_temp_new_i64();
5063 tcg_gen_ext32u_tl(t0
, t0
);
5064 tcg_gen_ext32u_tl(t1
, t1
);
5065 tcg_gen_extu_tl_i64(t2
, t0
);
5066 tcg_gen_extu_tl_i64(t3
, t1
);
5067 tcg_gen_mul_i64(t2
, t2
, t3
);
5068 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
5069 tcg_gen_sub_i64(t2
, t3
, t2
);
5070 tcg_temp_free_i64(t3
);
5071 gen_move_low32(cpu_LO
[acc
], t2
);
5072 gen_move_high32(cpu_HI
[acc
], t2
);
5073 tcg_temp_free_i64(t2
);
5077 MIPS_INVAL("mul/div");
5078 generate_exception_end(ctx
, EXCP_RI
);
5087 * These MULT[U] and MADD[U] instructions implemented in for example
5088 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
5089 * architectures are special three-operand variants with the syntax
5091 * MULT[U][1] rd, rs, rt
5095 * (rd, LO, HI) <- rs * rt
5099 * MADD[U][1] rd, rs, rt
5103 * (rd, LO, HI) <- (LO, HI) + rs * rt
5105 * where the low-order 32-bits of the result is placed into both the
5106 * GPR rd and the special register LO. The high-order 32-bits of the
5107 * result is placed into the special register HI.
5109 * If the GPR rd is omitted in assembly language, it is taken to be 0,
5110 * which is the zero register that always reads as 0.
5112 static void gen_mul_txx9(DisasContext
*ctx
, uint32_t opc
,
5113 int rd
, int rs
, int rt
)
5115 TCGv t0
= tcg_temp_new();
5116 TCGv t1
= tcg_temp_new();
5119 gen_load_gpr(t0
, rs
);
5120 gen_load_gpr(t1
, rt
);
5128 TCGv_i32 t2
= tcg_temp_new_i32();
5129 TCGv_i32 t3
= tcg_temp_new_i32();
5130 tcg_gen_trunc_tl_i32(t2
, t0
);
5131 tcg_gen_trunc_tl_i32(t3
, t1
);
5132 tcg_gen_muls2_i32(t2
, t3
, t2
, t3
);
5134 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
5136 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
5137 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
5138 tcg_temp_free_i32(t2
);
5139 tcg_temp_free_i32(t3
);
5142 case MMI_OPC_MULTU1
:
5147 TCGv_i32 t2
= tcg_temp_new_i32();
5148 TCGv_i32 t3
= tcg_temp_new_i32();
5149 tcg_gen_trunc_tl_i32(t2
, t0
);
5150 tcg_gen_trunc_tl_i32(t3
, t1
);
5151 tcg_gen_mulu2_i32(t2
, t3
, t2
, t3
);
5153 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
5155 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
5156 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
5157 tcg_temp_free_i32(t2
);
5158 tcg_temp_free_i32(t3
);
5166 TCGv_i64 t2
= tcg_temp_new_i64();
5167 TCGv_i64 t3
= tcg_temp_new_i64();
5169 tcg_gen_ext_tl_i64(t2
, t0
);
5170 tcg_gen_ext_tl_i64(t3
, t1
);
5171 tcg_gen_mul_i64(t2
, t2
, t3
);
5172 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
5173 tcg_gen_add_i64(t2
, t2
, t3
);
5174 tcg_temp_free_i64(t3
);
5175 gen_move_low32(cpu_LO
[acc
], t2
);
5176 gen_move_high32(cpu_HI
[acc
], t2
);
5178 gen_move_low32(cpu_gpr
[rd
], t2
);
5180 tcg_temp_free_i64(t2
);
5183 case MMI_OPC_MADDU1
:
5188 TCGv_i64 t2
= tcg_temp_new_i64();
5189 TCGv_i64 t3
= tcg_temp_new_i64();
5191 tcg_gen_ext32u_tl(t0
, t0
);
5192 tcg_gen_ext32u_tl(t1
, t1
);
5193 tcg_gen_extu_tl_i64(t2
, t0
);
5194 tcg_gen_extu_tl_i64(t3
, t1
);
5195 tcg_gen_mul_i64(t2
, t2
, t3
);
5196 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
5197 tcg_gen_add_i64(t2
, t2
, t3
);
5198 tcg_temp_free_i64(t3
);
5199 gen_move_low32(cpu_LO
[acc
], t2
);
5200 gen_move_high32(cpu_HI
[acc
], t2
);
5202 gen_move_low32(cpu_gpr
[rd
], t2
);
5204 tcg_temp_free_i64(t2
);
5208 MIPS_INVAL("mul/madd TXx9");
5209 generate_exception_end(ctx
, EXCP_RI
);
5218 static void gen_mul_vr54xx(DisasContext
*ctx
, uint32_t opc
,
5219 int rd
, int rs
, int rt
)
5221 TCGv t0
= tcg_temp_new();
5222 TCGv t1
= tcg_temp_new();
5224 gen_load_gpr(t0
, rs
);
5225 gen_load_gpr(t1
, rt
);
5228 case OPC_VR54XX_MULS
:
5229 gen_helper_muls(t0
, cpu_env
, t0
, t1
);
5231 case OPC_VR54XX_MULSU
:
5232 gen_helper_mulsu(t0
, cpu_env
, t0
, t1
);
5234 case OPC_VR54XX_MACC
:
5235 gen_helper_macc(t0
, cpu_env
, t0
, t1
);
5237 case OPC_VR54XX_MACCU
:
5238 gen_helper_maccu(t0
, cpu_env
, t0
, t1
);
5240 case OPC_VR54XX_MSAC
:
5241 gen_helper_msac(t0
, cpu_env
, t0
, t1
);
5243 case OPC_VR54XX_MSACU
:
5244 gen_helper_msacu(t0
, cpu_env
, t0
, t1
);
5246 case OPC_VR54XX_MULHI
:
5247 gen_helper_mulhi(t0
, cpu_env
, t0
, t1
);
5249 case OPC_VR54XX_MULHIU
:
5250 gen_helper_mulhiu(t0
, cpu_env
, t0
, t1
);
5252 case OPC_VR54XX_MULSHI
:
5253 gen_helper_mulshi(t0
, cpu_env
, t0
, t1
);
5255 case OPC_VR54XX_MULSHIU
:
5256 gen_helper_mulshiu(t0
, cpu_env
, t0
, t1
);
5258 case OPC_VR54XX_MACCHI
:
5259 gen_helper_macchi(t0
, cpu_env
, t0
, t1
);
5261 case OPC_VR54XX_MACCHIU
:
5262 gen_helper_macchiu(t0
, cpu_env
, t0
, t1
);
5264 case OPC_VR54XX_MSACHI
:
5265 gen_helper_msachi(t0
, cpu_env
, t0
, t1
);
5267 case OPC_VR54XX_MSACHIU
:
5268 gen_helper_msachiu(t0
, cpu_env
, t0
, t1
);
5271 MIPS_INVAL("mul vr54xx");
5272 generate_exception_end(ctx
, EXCP_RI
);
5275 gen_store_gpr(t0
, rd
);
5282 static void gen_cl(DisasContext
*ctx
, uint32_t opc
,
5292 gen_load_gpr(t0
, rs
);
5297 #if defined(TARGET_MIPS64)
5301 tcg_gen_not_tl(t0
, t0
);
5310 tcg_gen_ext32u_tl(t0
, t0
);
5311 tcg_gen_clzi_tl(t0
, t0
, TARGET_LONG_BITS
);
5312 tcg_gen_subi_tl(t0
, t0
, TARGET_LONG_BITS
- 32);
5314 #if defined(TARGET_MIPS64)
5319 tcg_gen_clzi_i64(t0
, t0
, 64);
5325 /* Godson integer instructions */
5326 static void gen_loongson_integer(DisasContext
*ctx
, uint32_t opc
,
5327 int rd
, int rs
, int rt
)
5339 case OPC_MULTU_G_2E
:
5340 case OPC_MULTU_G_2F
:
5341 #if defined(TARGET_MIPS64)
5342 case OPC_DMULT_G_2E
:
5343 case OPC_DMULT_G_2F
:
5344 case OPC_DMULTU_G_2E
:
5345 case OPC_DMULTU_G_2F
:
5347 t0
= tcg_temp_new();
5348 t1
= tcg_temp_new();
5351 t0
= tcg_temp_local_new();
5352 t1
= tcg_temp_local_new();
5356 gen_load_gpr(t0
, rs
);
5357 gen_load_gpr(t1
, rt
);
5362 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
5363 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
5365 case OPC_MULTU_G_2E
:
5366 case OPC_MULTU_G_2F
:
5367 tcg_gen_ext32u_tl(t0
, t0
);
5368 tcg_gen_ext32u_tl(t1
, t1
);
5369 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
5370 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
5375 TCGLabel
*l1
= gen_new_label();
5376 TCGLabel
*l2
= gen_new_label();
5377 TCGLabel
*l3
= gen_new_label();
5378 tcg_gen_ext32s_tl(t0
, t0
);
5379 tcg_gen_ext32s_tl(t1
, t1
);
5380 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
5381 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5384 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
5385 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
5386 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
5389 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
5390 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
5397 TCGLabel
*l1
= gen_new_label();
5398 TCGLabel
*l2
= gen_new_label();
5399 tcg_gen_ext32u_tl(t0
, t0
);
5400 tcg_gen_ext32u_tl(t1
, t1
);
5401 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
5402 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5405 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
5406 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
5413 TCGLabel
*l1
= gen_new_label();
5414 TCGLabel
*l2
= gen_new_label();
5415 TCGLabel
*l3
= gen_new_label();
5416 tcg_gen_ext32u_tl(t0
, t0
);
5417 tcg_gen_ext32u_tl(t1
, t1
);
5418 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5419 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
5420 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
5422 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5425 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
5426 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
5433 TCGLabel
*l1
= gen_new_label();
5434 TCGLabel
*l2
= gen_new_label();
5435 tcg_gen_ext32u_tl(t0
, t0
);
5436 tcg_gen_ext32u_tl(t1
, t1
);
5437 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
5438 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5441 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
5442 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
5446 #if defined(TARGET_MIPS64)
5447 case OPC_DMULT_G_2E
:
5448 case OPC_DMULT_G_2F
:
5449 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
5451 case OPC_DMULTU_G_2E
:
5452 case OPC_DMULTU_G_2F
:
5453 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
5458 TCGLabel
*l1
= gen_new_label();
5459 TCGLabel
*l2
= gen_new_label();
5460 TCGLabel
*l3
= gen_new_label();
5461 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
5462 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5465 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
5466 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
5467 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
5470 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
5474 case OPC_DDIVU_G_2E
:
5475 case OPC_DDIVU_G_2F
:
5477 TCGLabel
*l1
= gen_new_label();
5478 TCGLabel
*l2
= gen_new_label();
5479 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
5480 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5483 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
5490 TCGLabel
*l1
= gen_new_label();
5491 TCGLabel
*l2
= gen_new_label();
5492 TCGLabel
*l3
= gen_new_label();
5493 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5494 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
5495 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
5497 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5500 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
5504 case OPC_DMODU_G_2E
:
5505 case OPC_DMODU_G_2F
:
5507 TCGLabel
*l1
= gen_new_label();
5508 TCGLabel
*l2
= gen_new_label();
5509 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
5510 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5513 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
5524 /* Loongson multimedia instructions */
5525 static void gen_loongson_multimedia(DisasContext
*ctx
, int rd
, int rs
, int rt
)
5527 uint32_t opc
, shift_max
;
5530 opc
= MASK_LMI(ctx
->opcode
);
5536 t0
= tcg_temp_local_new_i64();
5537 t1
= tcg_temp_local_new_i64();
5540 t0
= tcg_temp_new_i64();
5541 t1
= tcg_temp_new_i64();
5545 check_cp1_enabled(ctx
);
5546 gen_load_fpr64(ctx
, t0
, rs
);
5547 gen_load_fpr64(ctx
, t1
, rt
);
5551 gen_helper_paddsh(t0
, t0
, t1
);
5554 gen_helper_paddush(t0
, t0
, t1
);
5557 gen_helper_paddh(t0
, t0
, t1
);
5560 gen_helper_paddw(t0
, t0
, t1
);
5563 gen_helper_paddsb(t0
, t0
, t1
);
5566 gen_helper_paddusb(t0
, t0
, t1
);
5569 gen_helper_paddb(t0
, t0
, t1
);
5573 gen_helper_psubsh(t0
, t0
, t1
);
5576 gen_helper_psubush(t0
, t0
, t1
);
5579 gen_helper_psubh(t0
, t0
, t1
);
5582 gen_helper_psubw(t0
, t0
, t1
);
5585 gen_helper_psubsb(t0
, t0
, t1
);
5588 gen_helper_psubusb(t0
, t0
, t1
);
5591 gen_helper_psubb(t0
, t0
, t1
);
5595 gen_helper_pshufh(t0
, t0
, t1
);
5598 gen_helper_packsswh(t0
, t0
, t1
);
5601 gen_helper_packsshb(t0
, t0
, t1
);
5604 gen_helper_packushb(t0
, t0
, t1
);
5608 gen_helper_punpcklhw(t0
, t0
, t1
);
5611 gen_helper_punpckhhw(t0
, t0
, t1
);
5614 gen_helper_punpcklbh(t0
, t0
, t1
);
5617 gen_helper_punpckhbh(t0
, t0
, t1
);
5620 gen_helper_punpcklwd(t0
, t0
, t1
);
5623 gen_helper_punpckhwd(t0
, t0
, t1
);
5627 gen_helper_pavgh(t0
, t0
, t1
);
5630 gen_helper_pavgb(t0
, t0
, t1
);
5633 gen_helper_pmaxsh(t0
, t0
, t1
);
5636 gen_helper_pminsh(t0
, t0
, t1
);
5639 gen_helper_pmaxub(t0
, t0
, t1
);
5642 gen_helper_pminub(t0
, t0
, t1
);
5646 gen_helper_pcmpeqw(t0
, t0
, t1
);
5649 gen_helper_pcmpgtw(t0
, t0
, t1
);
5652 gen_helper_pcmpeqh(t0
, t0
, t1
);
5655 gen_helper_pcmpgth(t0
, t0
, t1
);
5658 gen_helper_pcmpeqb(t0
, t0
, t1
);
5661 gen_helper_pcmpgtb(t0
, t0
, t1
);
5665 gen_helper_psllw(t0
, t0
, t1
);
5668 gen_helper_psllh(t0
, t0
, t1
);
5671 gen_helper_psrlw(t0
, t0
, t1
);
5674 gen_helper_psrlh(t0
, t0
, t1
);
5677 gen_helper_psraw(t0
, t0
, t1
);
5680 gen_helper_psrah(t0
, t0
, t1
);
5684 gen_helper_pmullh(t0
, t0
, t1
);
5687 gen_helper_pmulhh(t0
, t0
, t1
);
5690 gen_helper_pmulhuh(t0
, t0
, t1
);
5693 gen_helper_pmaddhw(t0
, t0
, t1
);
5697 gen_helper_pasubub(t0
, t0
, t1
);
5700 gen_helper_biadd(t0
, t0
);
5703 gen_helper_pmovmskb(t0
, t0
);
5707 tcg_gen_add_i64(t0
, t0
, t1
);
5710 tcg_gen_sub_i64(t0
, t0
, t1
);
5713 tcg_gen_xor_i64(t0
, t0
, t1
);
5716 tcg_gen_nor_i64(t0
, t0
, t1
);
5719 tcg_gen_and_i64(t0
, t0
, t1
);
5722 tcg_gen_or_i64(t0
, t0
, t1
);
5726 tcg_gen_andc_i64(t0
, t1
, t0
);
5730 tcg_gen_deposit_i64(t0
, t0
, t1
, 0, 16);
5733 tcg_gen_deposit_i64(t0
, t0
, t1
, 16, 16);
5736 tcg_gen_deposit_i64(t0
, t0
, t1
, 32, 16);
5739 tcg_gen_deposit_i64(t0
, t0
, t1
, 48, 16);
5743 tcg_gen_andi_i64(t1
, t1
, 3);
5744 tcg_gen_shli_i64(t1
, t1
, 4);
5745 tcg_gen_shr_i64(t0
, t0
, t1
);
5746 tcg_gen_ext16u_i64(t0
, t0
);
5750 tcg_gen_add_i64(t0
, t0
, t1
);
5751 tcg_gen_ext32s_i64(t0
, t0
);
5754 tcg_gen_sub_i64(t0
, t0
, t1
);
5755 tcg_gen_ext32s_i64(t0
, t0
);
5777 /* Make sure shift count isn't TCG undefined behaviour. */
5778 tcg_gen_andi_i64(t1
, t1
, shift_max
- 1);
5783 tcg_gen_shl_i64(t0
, t0
, t1
);
5788 * Since SRA is UndefinedResult without sign-extended inputs,
5789 * we can treat SRA and DSRA the same.
5791 tcg_gen_sar_i64(t0
, t0
, t1
);
5794 /* We want to shift in zeros for SRL; zero-extend first. */
5795 tcg_gen_ext32u_i64(t0
, t0
);
5798 tcg_gen_shr_i64(t0
, t0
, t1
);
5802 if (shift_max
== 32) {
5803 tcg_gen_ext32s_i64(t0
, t0
);
5806 /* Shifts larger than MAX produce zero. */
5807 tcg_gen_setcondi_i64(TCG_COND_LTU
, t1
, t1
, shift_max
);
5808 tcg_gen_neg_i64(t1
, t1
);
5809 tcg_gen_and_i64(t0
, t0
, t1
);
5815 TCGv_i64 t2
= tcg_temp_new_i64();
5816 TCGLabel
*lab
= gen_new_label();
5818 tcg_gen_mov_i64(t2
, t0
);
5819 tcg_gen_add_i64(t0
, t1
, t2
);
5820 if (opc
== OPC_ADD_CP2
) {
5821 tcg_gen_ext32s_i64(t0
, t0
);
5823 tcg_gen_xor_i64(t1
, t1
, t2
);
5824 tcg_gen_xor_i64(t2
, t2
, t0
);
5825 tcg_gen_andc_i64(t1
, t2
, t1
);
5826 tcg_temp_free_i64(t2
);
5827 tcg_gen_brcondi_i64(TCG_COND_GE
, t1
, 0, lab
);
5828 generate_exception(ctx
, EXCP_OVERFLOW
);
5836 TCGv_i64 t2
= tcg_temp_new_i64();
5837 TCGLabel
*lab
= gen_new_label();
5839 tcg_gen_mov_i64(t2
, t0
);
5840 tcg_gen_sub_i64(t0
, t1
, t2
);
5841 if (opc
== OPC_SUB_CP2
) {
5842 tcg_gen_ext32s_i64(t0
, t0
);
5844 tcg_gen_xor_i64(t1
, t1
, t2
);
5845 tcg_gen_xor_i64(t2
, t2
, t0
);
5846 tcg_gen_and_i64(t1
, t1
, t2
);
5847 tcg_temp_free_i64(t2
);
5848 tcg_gen_brcondi_i64(TCG_COND_GE
, t1
, 0, lab
);
5849 generate_exception(ctx
, EXCP_OVERFLOW
);
5855 tcg_gen_ext32u_i64(t0
, t0
);
5856 tcg_gen_ext32u_i64(t1
, t1
);
5857 tcg_gen_mul_i64(t0
, t0
, t1
);
5867 * ??? Document is unclear: Set FCC[CC]. Does that mean the
5868 * FD field is the CC field?
5871 MIPS_INVAL("loongson_cp2");
5872 generate_exception_end(ctx
, EXCP_RI
);
5876 gen_store_fpr64(ctx
, t0
, rd
);
5878 tcg_temp_free_i64(t0
);
5879 tcg_temp_free_i64(t1
);
5883 static void gen_trap(DisasContext
*ctx
, uint32_t opc
,
5884 int rs
, int rt
, int16_t imm
)
5887 TCGv t0
= tcg_temp_new();
5888 TCGv t1
= tcg_temp_new();
5891 /* Load needed operands */
5899 /* Compare two registers */
5901 gen_load_gpr(t0
, rs
);
5902 gen_load_gpr(t1
, rt
);
5912 /* Compare register to immediate */
5913 if (rs
!= 0 || imm
!= 0) {
5914 gen_load_gpr(t0
, rs
);
5915 tcg_gen_movi_tl(t1
, (int32_t)imm
);
5922 case OPC_TEQ
: /* rs == rs */
5923 case OPC_TEQI
: /* r0 == 0 */
5924 case OPC_TGE
: /* rs >= rs */
5925 case OPC_TGEI
: /* r0 >= 0 */
5926 case OPC_TGEU
: /* rs >= rs unsigned */
5927 case OPC_TGEIU
: /* r0 >= 0 unsigned */
5929 generate_exception_end(ctx
, EXCP_TRAP
);
5931 case OPC_TLT
: /* rs < rs */
5932 case OPC_TLTI
: /* r0 < 0 */
5933 case OPC_TLTU
: /* rs < rs unsigned */
5934 case OPC_TLTIU
: /* r0 < 0 unsigned */
5935 case OPC_TNE
: /* rs != rs */
5936 case OPC_TNEI
: /* r0 != 0 */
5937 /* Never trap: treat as NOP. */
5941 TCGLabel
*l1
= gen_new_label();
5946 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
5950 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
5954 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
5958 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5962 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5966 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
5969 generate_exception(ctx
, EXCP_TRAP
);
5976 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
5978 if (unlikely(ctx
->base
.singlestep_enabled
)) {
5982 #ifndef CONFIG_USER_ONLY
5983 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
5989 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
5991 if (use_goto_tb(ctx
, dest
)) {
5994 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
5997 if (ctx
->base
.singlestep_enabled
) {
5998 save_cpu_state(ctx
, 0);
5999 gen_helper_raise_exception_debug(cpu_env
);
6001 tcg_gen_lookup_and_goto_ptr();
6005 /* Branches (before delay slot) */
6006 static void gen_compute_branch(DisasContext
*ctx
, uint32_t opc
,
6008 int rs
, int rt
, int32_t offset
,
6011 target_ulong btgt
= -1;
6013 int bcond_compute
= 0;
6014 TCGv t0
= tcg_temp_new();
6015 TCGv t1
= tcg_temp_new();
6017 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
6018 #ifdef MIPS_DEBUG_DISAS
6019 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
6020 TARGET_FMT_lx
"\n", ctx
->base
.pc_next
);
6022 generate_exception_end(ctx
, EXCP_RI
);
6026 /* Load needed operands */
6032 /* Compare two registers */
6034 gen_load_gpr(t0
, rs
);
6035 gen_load_gpr(t1
, rt
);
6038 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ offset
;
6052 /* Compare to zero */
6054 gen_load_gpr(t0
, rs
);
6057 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ offset
;
6060 #if defined(TARGET_MIPS64)
6062 tcg_gen_andi_tl(t0
, cpu_dspctrl
, 0x7F);
6064 tcg_gen_andi_tl(t0
, cpu_dspctrl
, 0x3F);
6067 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ offset
;
6072 /* Jump to immediate */
6073 btgt
= ((ctx
->base
.pc_next
+ insn_bytes
) & (int32_t)0xF0000000) |
6078 /* Jump to register */
6079 if (offset
!= 0 && offset
!= 16) {
6081 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
6082 * others are reserved.
6084 MIPS_INVAL("jump hint");
6085 generate_exception_end(ctx
, EXCP_RI
);
6088 gen_load_gpr(btarget
, rs
);
6091 MIPS_INVAL("branch/jump");
6092 generate_exception_end(ctx
, EXCP_RI
);
6095 if (bcond_compute
== 0) {
6096 /* No condition to be computed */
6098 case OPC_BEQ
: /* rx == rx */
6099 case OPC_BEQL
: /* rx == rx likely */
6100 case OPC_BGEZ
: /* 0 >= 0 */
6101 case OPC_BGEZL
: /* 0 >= 0 likely */
6102 case OPC_BLEZ
: /* 0 <= 0 */
6103 case OPC_BLEZL
: /* 0 <= 0 likely */
6105 ctx
->hflags
|= MIPS_HFLAG_B
;
6107 case OPC_BGEZAL
: /* 0 >= 0 */
6108 case OPC_BGEZALL
: /* 0 >= 0 likely */
6109 /* Always take and link */
6111 ctx
->hflags
|= MIPS_HFLAG_B
;
6113 case OPC_BNE
: /* rx != rx */
6114 case OPC_BGTZ
: /* 0 > 0 */
6115 case OPC_BLTZ
: /* 0 < 0 */
6118 case OPC_BLTZAL
: /* 0 < 0 */
6120 * Handle as an unconditional branch to get correct delay
6124 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ delayslot_size
;
6125 ctx
->hflags
|= MIPS_HFLAG_B
;
6127 case OPC_BLTZALL
: /* 0 < 0 likely */
6128 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 8);
6129 /* Skip the instruction in the delay slot */
6130 ctx
->base
.pc_next
+= 4;
6132 case OPC_BNEL
: /* rx != rx likely */
6133 case OPC_BGTZL
: /* 0 > 0 likely */
6134 case OPC_BLTZL
: /* 0 < 0 likely */
6135 /* Skip the instruction in the delay slot */
6136 ctx
->base
.pc_next
+= 4;
6139 ctx
->hflags
|= MIPS_HFLAG_B
;
6142 ctx
->hflags
|= MIPS_HFLAG_BX
;
6146 ctx
->hflags
|= MIPS_HFLAG_B
;
6149 ctx
->hflags
|= MIPS_HFLAG_BR
;
6153 ctx
->hflags
|= MIPS_HFLAG_BR
;
6156 MIPS_INVAL("branch/jump");
6157 generate_exception_end(ctx
, EXCP_RI
);
6163 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
6166 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
6169 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
6172 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
6175 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
6178 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
6181 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
6185 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
6189 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
6192 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
6195 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
6198 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
6201 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
6204 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
6207 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 32);
6209 #if defined(TARGET_MIPS64)
6211 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 64);
6215 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
6218 ctx
->hflags
|= MIPS_HFLAG_BC
;
6221 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
6224 ctx
->hflags
|= MIPS_HFLAG_BL
;
6227 MIPS_INVAL("conditional branch/jump");
6228 generate_exception_end(ctx
, EXCP_RI
);
6233 ctx
->btarget
= btgt
;
6235 switch (delayslot_size
) {
6237 ctx
->hflags
|= MIPS_HFLAG_BDS16
;
6240 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
6245 int post_delay
= insn_bytes
+ delayslot_size
;
6246 int lowbit
= !!(ctx
->hflags
& MIPS_HFLAG_M16
);
6248 tcg_gen_movi_tl(cpu_gpr
[blink
],
6249 ctx
->base
.pc_next
+ post_delay
+ lowbit
);
6253 if (insn_bytes
== 2) {
6254 ctx
->hflags
|= MIPS_HFLAG_B16
;
6261 /* nanoMIPS Branches */
6262 static void gen_compute_branch_nm(DisasContext
*ctx
, uint32_t opc
,
6264 int rs
, int rt
, int32_t offset
)
6266 target_ulong btgt
= -1;
6267 int bcond_compute
= 0;
6268 TCGv t0
= tcg_temp_new();
6269 TCGv t1
= tcg_temp_new();
6271 /* Load needed operands */
6275 /* Compare two registers */
6277 gen_load_gpr(t0
, rs
);
6278 gen_load_gpr(t1
, rt
);
6281 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ offset
;
6284 /* Compare to zero */
6286 gen_load_gpr(t0
, rs
);
6289 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ offset
;
6292 tcg_gen_andi_tl(t0
, cpu_dspctrl
, 0x3F);
6294 btgt
= ctx
->base
.pc_next
+ insn_bytes
+ offset
;
6298 /* Jump to register */
6299 if (offset
!= 0 && offset
!= 16) {
6301 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
6302 * others are reserved.
6304 MIPS_INVAL("jump hint");
6305 generate_exception_end(ctx
, EXCP_RI
);
6308 gen_load_gpr(btarget
, rs
);
6311 MIPS_INVAL("branch/jump");
6312 generate_exception_end(ctx
, EXCP_RI
);
6315 if (bcond_compute
== 0) {
6316 /* No condition to be computed */
6318 case OPC_BEQ
: /* rx == rx */
6320 ctx
->hflags
|= MIPS_HFLAG_B
;
6322 case OPC_BGEZAL
: /* 0 >= 0 */
6323 /* Always take and link */
6324 tcg_gen_movi_tl(cpu_gpr
[31],
6325 ctx
->base
.pc_next
+ insn_bytes
);
6326 ctx
->hflags
|= MIPS_HFLAG_B
;
6328 case OPC_BNE
: /* rx != rx */
6329 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 8);
6330 /* Skip the instruction in the delay slot */
6331 ctx
->base
.pc_next
+= 4;
6334 ctx
->hflags
|= MIPS_HFLAG_BR
;
6338 tcg_gen_movi_tl(cpu_gpr
[rt
],
6339 ctx
->base
.pc_next
+ insn_bytes
);
6341 ctx
->hflags
|= MIPS_HFLAG_BR
;
6344 MIPS_INVAL("branch/jump");
6345 generate_exception_end(ctx
, EXCP_RI
);
6351 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
6354 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
6357 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
6358 tcg_gen_movi_tl(cpu_gpr
[31],
6359 ctx
->base
.pc_next
+ insn_bytes
);
6362 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 32);
6364 ctx
->hflags
|= MIPS_HFLAG_BC
;
6367 MIPS_INVAL("conditional branch/jump");
6368 generate_exception_end(ctx
, EXCP_RI
);
6373 ctx
->btarget
= btgt
;
6376 if (insn_bytes
== 2) {
6377 ctx
->hflags
|= MIPS_HFLAG_B16
;
6384 /* special3 bitfield operations */
6385 static void gen_bitops(DisasContext
*ctx
, uint32_t opc
, int rt
,
6386 int rs
, int lsb
, int msb
)
6388 TCGv t0
= tcg_temp_new();
6389 TCGv t1
= tcg_temp_new();
6391 gen_load_gpr(t1
, rs
);
6394 if (lsb
+ msb
> 31) {
6398 tcg_gen_extract_tl(t0
, t1
, lsb
, msb
+ 1);
6401 * The two checks together imply that lsb == 0,
6402 * so this is a simple sign-extension.
6404 tcg_gen_ext32s_tl(t0
, t1
);
6407 #if defined(TARGET_MIPS64)
6416 if (lsb
+ msb
> 63) {
6419 tcg_gen_extract_tl(t0
, t1
, lsb
, msb
+ 1);
6426 gen_load_gpr(t0
, rt
);
6427 tcg_gen_deposit_tl(t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
6428 tcg_gen_ext32s_tl(t0
, t0
);
6430 #if defined(TARGET_MIPS64)
6441 gen_load_gpr(t0
, rt
);
6442 tcg_gen_deposit_tl(t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
6447 MIPS_INVAL("bitops");
6448 generate_exception_end(ctx
, EXCP_RI
);
6453 gen_store_gpr(t0
, rt
);
6458 static void gen_bshfl(DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
6463 /* If no destination, treat it as a NOP. */
6467 t0
= tcg_temp_new();
6468 gen_load_gpr(t0
, rt
);
6472 TCGv t1
= tcg_temp_new();
6473 TCGv t2
= tcg_const_tl(0x00FF00FF);
6475 tcg_gen_shri_tl(t1
, t0
, 8);
6476 tcg_gen_and_tl(t1
, t1
, t2
);
6477 tcg_gen_and_tl(t0
, t0
, t2
);
6478 tcg_gen_shli_tl(t0
, t0
, 8);
6479 tcg_gen_or_tl(t0
, t0
, t1
);
6482 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
6486 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
6489 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
6491 #if defined(TARGET_MIPS64)
6494 TCGv t1
= tcg_temp_new();
6495 TCGv t2
= tcg_const_tl(0x00FF00FF00FF00FFULL
);
6497 tcg_gen_shri_tl(t1
, t0
, 8);
6498 tcg_gen_and_tl(t1
, t1
, t2
);
6499 tcg_gen_and_tl(t0
, t0
, t2
);
6500 tcg_gen_shli_tl(t0
, t0
, 8);
6501 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
6508 TCGv t1
= tcg_temp_new();
6509 TCGv t2
= tcg_const_tl(0x0000FFFF0000FFFFULL
);
6511 tcg_gen_shri_tl(t1
, t0
, 16);
6512 tcg_gen_and_tl(t1
, t1
, t2
);
6513 tcg_gen_and_tl(t0
, t0
, t2
);
6514 tcg_gen_shli_tl(t0
, t0
, 16);
6515 tcg_gen_or_tl(t0
, t0
, t1
);
6516 tcg_gen_shri_tl(t1
, t0
, 32);
6517 tcg_gen_shli_tl(t0
, t0
, 32);
6518 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
6525 MIPS_INVAL("bsfhl");
6526 generate_exception_end(ctx
, EXCP_RI
);
6533 static void gen_lsa(DisasContext
*ctx
, int opc
, int rd
, int rs
, int rt
,
6542 t0
= tcg_temp_new();
6543 t1
= tcg_temp_new();
6544 gen_load_gpr(t0
, rs
);
6545 gen_load_gpr(t1
, rt
);
6546 tcg_gen_shli_tl(t0
, t0
, imm2
+ 1);
6547 tcg_gen_add_tl(cpu_gpr
[rd
], t0
, t1
);
6548 if (opc
== OPC_LSA
) {
6549 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
6558 static void gen_align_bits(DisasContext
*ctx
, int wordsz
, int rd
, int rs
,
6566 t0
= tcg_temp_new();
6567 if (bits
== 0 || bits
== wordsz
) {
6569 gen_load_gpr(t0
, rt
);
6571 gen_load_gpr(t0
, rs
);
6575 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
6577 #if defined(TARGET_MIPS64)
6579 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
6584 TCGv t1
= tcg_temp_new();
6585 gen_load_gpr(t0
, rt
);
6586 gen_load_gpr(t1
, rs
);
6590 TCGv_i64 t2
= tcg_temp_new_i64();
6591 tcg_gen_concat_tl_i64(t2
, t1
, t0
);
6592 tcg_gen_shri_i64(t2
, t2
, 32 - bits
);
6593 gen_move_low32(cpu_gpr
[rd
], t2
);
6594 tcg_temp_free_i64(t2
);
6597 #if defined(TARGET_MIPS64)
6599 tcg_gen_shli_tl(t0
, t0
, bits
);
6600 tcg_gen_shri_tl(t1
, t1
, 64 - bits
);
6601 tcg_gen_or_tl(cpu_gpr
[rd
], t1
, t0
);
6611 static void gen_align(DisasContext
*ctx
, int wordsz
, int rd
, int rs
, int rt
,
6614 gen_align_bits(ctx
, wordsz
, rd
, rs
, rt
, bp
* 8);
6617 static void gen_ext(DisasContext
*ctx
, int wordsz
, int rd
, int rs
, int rt
,
6620 gen_align_bits(ctx
, wordsz
, rd
, rs
, rt
, wordsz
- shift
);
6623 static void gen_bitswap(DisasContext
*ctx
, int opc
, int rd
, int rt
)
6630 t0
= tcg_temp_new();
6631 gen_load_gpr(t0
, rt
);
6634 gen_helper_bitswap(cpu_gpr
[rd
], t0
);
6636 #if defined(TARGET_MIPS64)
6638 gen_helper_dbitswap(cpu_gpr
[rd
], t0
);
6645 #ifndef CONFIG_USER_ONLY
6646 /* CP0 (MMU and control) */
6647 static inline void gen_mthc0_entrylo(TCGv arg
, target_ulong off
)
6649 TCGv_i64 t0
= tcg_temp_new_i64();
6650 TCGv_i64 t1
= tcg_temp_new_i64();
6652 tcg_gen_ext_tl_i64(t0
, arg
);
6653 tcg_gen_ld_i64(t1
, cpu_env
, off
);
6654 #if defined(TARGET_MIPS64)
6655 tcg_gen_deposit_i64(t1
, t1
, t0
, 30, 32);
6657 tcg_gen_concat32_i64(t1
, t1
, t0
);
6659 tcg_gen_st_i64(t1
, cpu_env
, off
);
6660 tcg_temp_free_i64(t1
);
6661 tcg_temp_free_i64(t0
);
6664 static inline void gen_mthc0_store64(TCGv arg
, target_ulong off
)
6666 TCGv_i64 t0
= tcg_temp_new_i64();
6667 TCGv_i64 t1
= tcg_temp_new_i64();
6669 tcg_gen_ext_tl_i64(t0
, arg
);
6670 tcg_gen_ld_i64(t1
, cpu_env
, off
);
6671 tcg_gen_concat32_i64(t1
, t1
, t0
);
6672 tcg_gen_st_i64(t1
, cpu_env
, off
);
6673 tcg_temp_free_i64(t1
);
6674 tcg_temp_free_i64(t0
);
6677 static inline void gen_mfhc0_entrylo(TCGv arg
, target_ulong off
)
6679 TCGv_i64 t0
= tcg_temp_new_i64();
6681 tcg_gen_ld_i64(t0
, cpu_env
, off
);
6682 #if defined(TARGET_MIPS64)
6683 tcg_gen_shri_i64(t0
, t0
, 30);
6685 tcg_gen_shri_i64(t0
, t0
, 32);
6687 gen_move_low32(arg
, t0
);
6688 tcg_temp_free_i64(t0
);
6691 static inline void gen_mfhc0_load64(TCGv arg
, target_ulong off
, int shift
)
6693 TCGv_i64 t0
= tcg_temp_new_i64();
6695 tcg_gen_ld_i64(t0
, cpu_env
, off
);
6696 tcg_gen_shri_i64(t0
, t0
, 32 + shift
);
6697 gen_move_low32(arg
, t0
);
6698 tcg_temp_free_i64(t0
);
6701 static inline void gen_mfc0_load32(TCGv arg
, target_ulong off
)
6703 TCGv_i32 t0
= tcg_temp_new_i32();
6705 tcg_gen_ld_i32(t0
, cpu_env
, off
);
6706 tcg_gen_ext_i32_tl(arg
, t0
);
6707 tcg_temp_free_i32(t0
);
6710 static inline void gen_mfc0_load64(TCGv arg
, target_ulong off
)
6712 tcg_gen_ld_tl(arg
, cpu_env
, off
);
6713 tcg_gen_ext32s_tl(arg
, arg
);
6716 static inline void gen_mtc0_store32(TCGv arg
, target_ulong off
)
6718 TCGv_i32 t0
= tcg_temp_new_i32();
6720 tcg_gen_trunc_tl_i32(t0
, arg
);
6721 tcg_gen_st_i32(t0
, cpu_env
, off
);
6722 tcg_temp_free_i32(t0
);
6725 #define CP0_CHECK(c) \
6728 goto cp0_unimplemented; \
6732 static void gen_mfhc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
6734 const char *register_name
= "invalid";
6737 case CP0_REGISTER_02
:
6740 CP0_CHECK(ctx
->hflags
& MIPS_HFLAG_ELPA
);
6741 gen_mfhc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo0
));
6742 register_name
= "EntryLo0";
6745 goto cp0_unimplemented
;
6748 case CP0_REGISTER_03
:
6750 case CP0_REG03__ENTRYLO1
:
6751 CP0_CHECK(ctx
->hflags
& MIPS_HFLAG_ELPA
);
6752 gen_mfhc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo1
));
6753 register_name
= "EntryLo1";
6756 goto cp0_unimplemented
;
6759 case CP0_REGISTER_09
:
6761 case CP0_REG09__SAAR
:
6762 CP0_CHECK(ctx
->saar
);
6763 gen_helper_mfhc0_saar(arg
, cpu_env
);
6764 register_name
= "SAAR";
6767 goto cp0_unimplemented
;
6770 case CP0_REGISTER_17
:
6772 case CP0_REG17__LLADDR
:
6773 gen_mfhc0_load64(arg
, offsetof(CPUMIPSState
, CP0_LLAddr
),
6774 ctx
->CP0_LLAddr_shift
);
6775 register_name
= "LLAddr";
6777 case CP0_REG17__MAAR
:
6778 CP0_CHECK(ctx
->mrp
);
6779 gen_helper_mfhc0_maar(arg
, cpu_env
);
6780 register_name
= "MAAR";
6783 goto cp0_unimplemented
;
6786 case CP0_REGISTER_28
:
6792 gen_mfhc0_load64(arg
, offsetof(CPUMIPSState
, CP0_TagLo
), 0);
6793 register_name
= "TagLo";
6796 goto cp0_unimplemented
;
6800 goto cp0_unimplemented
;
6802 trace_mips_translate_c0("mfhc0", register_name
, reg
, sel
);
6806 qemu_log_mask(LOG_UNIMP
, "mfhc0 %s (reg %d sel %d)\n",
6807 register_name
, reg
, sel
);
6808 tcg_gen_movi_tl(arg
, 0);
6811 static void gen_mthc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
6813 const char *register_name
= "invalid";
6814 uint64_t mask
= ctx
->PAMask
>> 36;
6817 case CP0_REGISTER_02
:
6820 CP0_CHECK(ctx
->hflags
& MIPS_HFLAG_ELPA
);
6821 tcg_gen_andi_tl(arg
, arg
, mask
);
6822 gen_mthc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo0
));
6823 register_name
= "EntryLo0";
6826 goto cp0_unimplemented
;
6829 case CP0_REGISTER_03
:
6831 case CP0_REG03__ENTRYLO1
:
6832 CP0_CHECK(ctx
->hflags
& MIPS_HFLAG_ELPA
);
6833 tcg_gen_andi_tl(arg
, arg
, mask
);
6834 gen_mthc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo1
));
6835 register_name
= "EntryLo1";
6838 goto cp0_unimplemented
;
6841 case CP0_REGISTER_09
:
6843 case CP0_REG09__SAAR
:
6844 CP0_CHECK(ctx
->saar
);
6845 gen_helper_mthc0_saar(cpu_env
, arg
);
6846 register_name
= "SAAR";
6849 goto cp0_unimplemented
;
6852 case CP0_REGISTER_17
:
6854 case CP0_REG17__LLADDR
:
6856 * LLAddr is read-only (the only exception is bit 0 if LLB is
6857 * supported); the CP0_LLAddr_rw_bitmask does not seem to be
6858 * relevant for modern MIPS cores supporting MTHC0, therefore
6859 * treating MTHC0 to LLAddr as NOP.
6861 register_name
= "LLAddr";
6863 case CP0_REG17__MAAR
:
6864 CP0_CHECK(ctx
->mrp
);
6865 gen_helper_mthc0_maar(cpu_env
, arg
);
6866 register_name
= "MAAR";
6869 goto cp0_unimplemented
;
6872 case CP0_REGISTER_28
:
6878 tcg_gen_andi_tl(arg
, arg
, mask
);
6879 gen_mthc0_store64(arg
, offsetof(CPUMIPSState
, CP0_TagLo
));
6880 register_name
= "TagLo";
6883 goto cp0_unimplemented
;
6887 goto cp0_unimplemented
;
6889 trace_mips_translate_c0("mthc0", register_name
, reg
, sel
);
6892 qemu_log_mask(LOG_UNIMP
, "mthc0 %s (reg %d sel %d)\n",
6893 register_name
, reg
, sel
);
6896 static inline void gen_mfc0_unimplemented(DisasContext
*ctx
, TCGv arg
)
6898 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
6899 tcg_gen_movi_tl(arg
, 0);
6901 tcg_gen_movi_tl(arg
, ~0);
6905 static void gen_mfc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
6907 const char *register_name
= "invalid";
6910 check_insn(ctx
, ISA_MIPS32
);
6914 case CP0_REGISTER_00
:
6916 case CP0_REG00__INDEX
:
6917 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Index
));
6918 register_name
= "Index";
6920 case CP0_REG00__MVPCONTROL
:
6921 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6922 gen_helper_mfc0_mvpcontrol(arg
, cpu_env
);
6923 register_name
= "MVPControl";
6925 case CP0_REG00__MVPCONF0
:
6926 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6927 gen_helper_mfc0_mvpconf0(arg
, cpu_env
);
6928 register_name
= "MVPConf0";
6930 case CP0_REG00__MVPCONF1
:
6931 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6932 gen_helper_mfc0_mvpconf1(arg
, cpu_env
);
6933 register_name
= "MVPConf1";
6935 case CP0_REG00__VPCONTROL
:
6937 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPControl
));
6938 register_name
= "VPControl";
6941 goto cp0_unimplemented
;
6944 case CP0_REGISTER_01
:
6946 case CP0_REG01__RANDOM
:
6947 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
6948 gen_helper_mfc0_random(arg
, cpu_env
);
6949 register_name
= "Random";
6951 case CP0_REG01__VPECONTROL
:
6952 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6953 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEControl
));
6954 register_name
= "VPEControl";
6956 case CP0_REG01__VPECONF0
:
6957 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6958 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf0
));
6959 register_name
= "VPEConf0";
6961 case CP0_REG01__VPECONF1
:
6962 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6963 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf1
));
6964 register_name
= "VPEConf1";
6966 case CP0_REG01__YQMASK
:
6967 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6968 gen_mfc0_load64(arg
, offsetof(CPUMIPSState
, CP0_YQMask
));
6969 register_name
= "YQMask";
6971 case CP0_REG01__VPESCHEDULE
:
6972 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6973 gen_mfc0_load64(arg
, offsetof(CPUMIPSState
, CP0_VPESchedule
));
6974 register_name
= "VPESchedule";
6976 case CP0_REG01__VPESCHEFBACK
:
6977 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6978 gen_mfc0_load64(arg
, offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
6979 register_name
= "VPEScheFBack";
6981 case CP0_REG01__VPEOPT
:
6982 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6983 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEOpt
));
6984 register_name
= "VPEOpt";
6987 goto cp0_unimplemented
;
6990 case CP0_REGISTER_02
:
6992 case CP0_REG02__ENTRYLO0
:
6994 TCGv_i64 tmp
= tcg_temp_new_i64();
6995 tcg_gen_ld_i64(tmp
, cpu_env
,
6996 offsetof(CPUMIPSState
, CP0_EntryLo0
));
6997 #if defined(TARGET_MIPS64)
6999 /* Move RI/XI fields to bits 31:30 */
7000 tcg_gen_shri_tl(arg
, tmp
, CP0EnLo_XI
);
7001 tcg_gen_deposit_tl(tmp
, tmp
, arg
, 30, 2);
7004 gen_move_low32(arg
, tmp
);
7005 tcg_temp_free_i64(tmp
);
7007 register_name
= "EntryLo0";
7009 case CP0_REG02__TCSTATUS
:
7010 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7011 gen_helper_mfc0_tcstatus(arg
, cpu_env
);
7012 register_name
= "TCStatus";
7014 case CP0_REG02__TCBIND
:
7015 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7016 gen_helper_mfc0_tcbind(arg
, cpu_env
);
7017 register_name
= "TCBind";
7019 case CP0_REG02__TCRESTART
:
7020 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7021 gen_helper_mfc0_tcrestart(arg
, cpu_env
);
7022 register_name
= "TCRestart";
7024 case CP0_REG02__TCHALT
:
7025 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7026 gen_helper_mfc0_tchalt(arg
, cpu_env
);
7027 register_name
= "TCHalt";
7029 case CP0_REG02__TCCONTEXT
:
7030 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7031 gen_helper_mfc0_tccontext(arg
, cpu_env
);
7032 register_name
= "TCContext";
7034 case CP0_REG02__TCSCHEDULE
:
7035 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7036 gen_helper_mfc0_tcschedule(arg
, cpu_env
);
7037 register_name
= "TCSchedule";
7039 case CP0_REG02__TCSCHEFBACK
:
7040 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7041 gen_helper_mfc0_tcschefback(arg
, cpu_env
);
7042 register_name
= "TCScheFBack";
7045 goto cp0_unimplemented
;
7048 case CP0_REGISTER_03
:
7050 case CP0_REG03__ENTRYLO1
:
7052 TCGv_i64 tmp
= tcg_temp_new_i64();
7053 tcg_gen_ld_i64(tmp
, cpu_env
,
7054 offsetof(CPUMIPSState
, CP0_EntryLo1
));
7055 #if defined(TARGET_MIPS64)
7057 /* Move RI/XI fields to bits 31:30 */
7058 tcg_gen_shri_tl(arg
, tmp
, CP0EnLo_XI
);
7059 tcg_gen_deposit_tl(tmp
, tmp
, arg
, 30, 2);
7062 gen_move_low32(arg
, tmp
);
7063 tcg_temp_free_i64(tmp
);
7065 register_name
= "EntryLo1";
7067 case CP0_REG03__GLOBALNUM
:
7069 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_GlobalNumber
));
7070 register_name
= "GlobalNumber";
7073 goto cp0_unimplemented
;
7076 case CP0_REGISTER_04
:
7078 case CP0_REG04__CONTEXT
:
7079 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_Context
));
7080 tcg_gen_ext32s_tl(arg
, arg
);
7081 register_name
= "Context";
7083 case CP0_REG04__CONTEXTCONFIG
:
7085 /* gen_helper_mfc0_contextconfig(arg); */
7086 register_name
= "ContextConfig";
7087 goto cp0_unimplemented
;
7088 case CP0_REG04__USERLOCAL
:
7089 CP0_CHECK(ctx
->ulri
);
7090 tcg_gen_ld_tl(arg
, cpu_env
,
7091 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
7092 tcg_gen_ext32s_tl(arg
, arg
);
7093 register_name
= "UserLocal";
7096 goto cp0_unimplemented
;
7099 case CP0_REGISTER_05
:
7101 case CP0_REG05__PAGEMASK
:
7102 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageMask
));
7103 register_name
= "PageMask";
7105 case CP0_REG05__PAGEGRAIN
:
7106 check_insn(ctx
, ISA_MIPS32R2
);
7107 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageGrain
));
7108 register_name
= "PageGrain";
7110 case CP0_REG05__SEGCTL0
:
7112 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_SegCtl0
));
7113 tcg_gen_ext32s_tl(arg
, arg
);
7114 register_name
= "SegCtl0";
7116 case CP0_REG05__SEGCTL1
:
7118 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_SegCtl1
));
7119 tcg_gen_ext32s_tl(arg
, arg
);
7120 register_name
= "SegCtl1";
7122 case CP0_REG05__SEGCTL2
:
7124 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_SegCtl2
));
7125 tcg_gen_ext32s_tl(arg
, arg
);
7126 register_name
= "SegCtl2";
7128 case CP0_REG05__PWBASE
:
7130 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PWBase
));
7131 register_name
= "PWBase";
7133 case CP0_REG05__PWFIELD
:
7135 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PWField
));
7136 register_name
= "PWField";
7138 case CP0_REG05__PWSIZE
:
7140 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PWSize
));
7141 register_name
= "PWSize";
7144 goto cp0_unimplemented
;
7147 case CP0_REGISTER_06
:
7149 case CP0_REG06__WIRED
:
7150 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Wired
));
7151 register_name
= "Wired";
7153 case CP0_REG06__SRSCONF0
:
7154 check_insn(ctx
, ISA_MIPS32R2
);
7155 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf0
));
7156 register_name
= "SRSConf0";
7158 case CP0_REG06__SRSCONF1
:
7159 check_insn(ctx
, ISA_MIPS32R2
);
7160 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf1
));
7161 register_name
= "SRSConf1";
7163 case CP0_REG06__SRSCONF2
:
7164 check_insn(ctx
, ISA_MIPS32R2
);
7165 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf2
));
7166 register_name
= "SRSConf2";
7168 case CP0_REG06__SRSCONF3
:
7169 check_insn(ctx
, ISA_MIPS32R2
);
7170 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf3
));
7171 register_name
= "SRSConf3";
7173 case CP0_REG06__SRSCONF4
:
7174 check_insn(ctx
, ISA_MIPS32R2
);
7175 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf4
));
7176 register_name
= "SRSConf4";
7178 case CP0_REG06__PWCTL
:
7180 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PWCtl
));
7181 register_name
= "PWCtl";
7184 goto cp0_unimplemented
;
7187 case CP0_REGISTER_07
:
7189 case CP0_REG07__HWRENA
:
7190 check_insn(ctx
, ISA_MIPS32R2
);
7191 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_HWREna
));
7192 register_name
= "HWREna";
7195 goto cp0_unimplemented
;
7198 case CP0_REGISTER_08
:
7200 case CP0_REG08__BADVADDR
:
7201 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_BadVAddr
));
7202 tcg_gen_ext32s_tl(arg
, arg
);
7203 register_name
= "BadVAddr";
7205 case CP0_REG08__BADINSTR
:
7207 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstr
));
7208 register_name
= "BadInstr";
7210 case CP0_REG08__BADINSTRP
:
7212 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstrP
));
7213 register_name
= "BadInstrP";
7215 case CP0_REG08__BADINSTRX
:
7217 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstrX
));
7218 tcg_gen_andi_tl(arg
, arg
, ~0xffff);
7219 register_name
= "BadInstrX";
7222 goto cp0_unimplemented
;
7225 case CP0_REGISTER_09
:
7227 case CP0_REG09__COUNT
:
7228 /* Mark as an IO operation because we read the time. */
7229 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
7232 gen_helper_mfc0_count(arg
, cpu_env
);
7234 * Break the TB to be able to take timer interrupts immediately
7235 * after reading count. DISAS_STOP isn't sufficient, we need to
7236 * ensure we break completely out of translated code.
7238 gen_save_pc(ctx
->base
.pc_next
+ 4);
7239 ctx
->base
.is_jmp
= DISAS_EXIT
;
7240 register_name
= "Count";
7242 case CP0_REG09__SAARI
:
7243 CP0_CHECK(ctx
->saar
);
7244 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SAARI
));
7245 register_name
= "SAARI";
7247 case CP0_REG09__SAAR
:
7248 CP0_CHECK(ctx
->saar
);
7249 gen_helper_mfc0_saar(arg
, cpu_env
);
7250 register_name
= "SAAR";
7253 goto cp0_unimplemented
;
7256 case CP0_REGISTER_10
:
7258 case CP0_REG10__ENTRYHI
:
7259 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryHi
));
7260 tcg_gen_ext32s_tl(arg
, arg
);
7261 register_name
= "EntryHi";
7264 goto cp0_unimplemented
;
7267 case CP0_REGISTER_11
:
7269 case CP0_REG11__COMPARE
:
7270 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Compare
));
7271 register_name
= "Compare";
7273 /* 6,7 are implementation dependent */
7275 goto cp0_unimplemented
;
7278 case CP0_REGISTER_12
:
7280 case CP0_REG12__STATUS
:
7281 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Status
));
7282 register_name
= "Status";
7284 case CP0_REG12__INTCTL
:
7285 check_insn(ctx
, ISA_MIPS32R2
);
7286 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_IntCtl
));
7287 register_name
= "IntCtl";
7289 case CP0_REG12__SRSCTL
:
7290 check_insn(ctx
, ISA_MIPS32R2
);
7291 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
7292 register_name
= "SRSCtl";
7294 case CP0_REG12__SRSMAP
:
7295 check_insn(ctx
, ISA_MIPS32R2
);
7296 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
7297 register_name
= "SRSMap";
7300 goto cp0_unimplemented
;
7303 case CP0_REGISTER_13
:
7305 case CP0_REG13__CAUSE
:
7306 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Cause
));
7307 register_name
= "Cause";
7310 goto cp0_unimplemented
;
7313 case CP0_REGISTER_14
:
7315 case CP0_REG14__EPC
:
7316 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
7317 tcg_gen_ext32s_tl(arg
, arg
);
7318 register_name
= "EPC";
7321 goto cp0_unimplemented
;
7324 case CP0_REGISTER_15
:
7326 case CP0_REG15__PRID
:
7327 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PRid
));
7328 register_name
= "PRid";
7330 case CP0_REG15__EBASE
:
7331 check_insn(ctx
, ISA_MIPS32R2
);
7332 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EBase
));
7333 tcg_gen_ext32s_tl(arg
, arg
);
7334 register_name
= "EBase";
7336 case CP0_REG15__CMGCRBASE
:
7337 check_insn(ctx
, ISA_MIPS32R2
);
7338 CP0_CHECK(ctx
->cmgcr
);
7339 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_CMGCRBase
));
7340 tcg_gen_ext32s_tl(arg
, arg
);
7341 register_name
= "CMGCRBase";
7344 goto cp0_unimplemented
;
7347 case CP0_REGISTER_16
:
7349 case CP0_REG16__CONFIG
:
7350 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config0
));
7351 register_name
= "Config";
7353 case CP0_REG16__CONFIG1
:
7354 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config1
));
7355 register_name
= "Config1";
7357 case CP0_REG16__CONFIG2
:
7358 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config2
));
7359 register_name
= "Config2";
7361 case CP0_REG16__CONFIG3
:
7362 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config3
));
7363 register_name
= "Config3";
7365 case CP0_REG16__CONFIG4
:
7366 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config4
));
7367 register_name
= "Config4";
7369 case CP0_REG16__CONFIG5
:
7370 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config5
));
7371 register_name
= "Config5";
7373 /* 6,7 are implementation dependent */
7374 case CP0_REG16__CONFIG6
:
7375 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config6
));
7376 register_name
= "Config6";
7378 case CP0_REG16__CONFIG7
:
7379 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config7
));
7380 register_name
= "Config7";
7383 goto cp0_unimplemented
;
7386 case CP0_REGISTER_17
:
7388 case CP0_REG17__LLADDR
:
7389 gen_helper_mfc0_lladdr(arg
, cpu_env
);
7390 register_name
= "LLAddr";
7392 case CP0_REG17__MAAR
:
7393 CP0_CHECK(ctx
->mrp
);
7394 gen_helper_mfc0_maar(arg
, cpu_env
);
7395 register_name
= "MAAR";
7397 case CP0_REG17__MAARI
:
7398 CP0_CHECK(ctx
->mrp
);
7399 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_MAARI
));
7400 register_name
= "MAARI";
7403 goto cp0_unimplemented
;
7406 case CP0_REGISTER_18
:
7408 case CP0_REG18__WATCHLO0
:
7409 case CP0_REG18__WATCHLO1
:
7410 case CP0_REG18__WATCHLO2
:
7411 case CP0_REG18__WATCHLO3
:
7412 case CP0_REG18__WATCHLO4
:
7413 case CP0_REG18__WATCHLO5
:
7414 case CP0_REG18__WATCHLO6
:
7415 case CP0_REG18__WATCHLO7
:
7416 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
7417 gen_helper_1e0i(mfc0_watchlo
, arg
, sel
);
7418 register_name
= "WatchLo";
7421 goto cp0_unimplemented
;
7424 case CP0_REGISTER_19
:
7426 case CP0_REG19__WATCHHI0
:
7427 case CP0_REG19__WATCHHI1
:
7428 case CP0_REG19__WATCHHI2
:
7429 case CP0_REG19__WATCHHI3
:
7430 case CP0_REG19__WATCHHI4
:
7431 case CP0_REG19__WATCHHI5
:
7432 case CP0_REG19__WATCHHI6
:
7433 case CP0_REG19__WATCHHI7
:
7434 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
7435 gen_helper_1e0i(mfc0_watchhi
, arg
, sel
);
7436 register_name
= "WatchHi";
7439 goto cp0_unimplemented
;
7442 case CP0_REGISTER_20
:
7444 case CP0_REG20__XCONTEXT
:
7445 #if defined(TARGET_MIPS64)
7446 check_insn(ctx
, ISA_MIPS3
);
7447 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_XContext
));
7448 tcg_gen_ext32s_tl(arg
, arg
);
7449 register_name
= "XContext";
7453 goto cp0_unimplemented
;
7456 case CP0_REGISTER_21
:
7457 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7458 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
7461 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Framemask
));
7462 register_name
= "Framemask";
7465 goto cp0_unimplemented
;
7468 case CP0_REGISTER_22
:
7469 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
7470 register_name
= "'Diagnostic"; /* implementation dependent */
7472 case CP0_REGISTER_23
:
7474 case CP0_REG23__DEBUG
:
7475 gen_helper_mfc0_debug(arg
, cpu_env
); /* EJTAG support */
7476 register_name
= "Debug";
7478 case CP0_REG23__TRACECONTROL
:
7479 /* PDtrace support */
7480 /* gen_helper_mfc0_tracecontrol(arg); */
7481 register_name
= "TraceControl";
7482 goto cp0_unimplemented
;
7483 case CP0_REG23__TRACECONTROL2
:
7484 /* PDtrace support */
7485 /* gen_helper_mfc0_tracecontrol2(arg); */
7486 register_name
= "TraceControl2";
7487 goto cp0_unimplemented
;
7488 case CP0_REG23__USERTRACEDATA1
:
7489 /* PDtrace support */
7490 /* gen_helper_mfc0_usertracedata1(arg);*/
7491 register_name
= "UserTraceData1";
7492 goto cp0_unimplemented
;
7493 case CP0_REG23__TRACEIBPC
:
7494 /* PDtrace support */
7495 /* gen_helper_mfc0_traceibpc(arg); */
7496 register_name
= "TraceIBPC";
7497 goto cp0_unimplemented
;
7498 case CP0_REG23__TRACEDBPC
:
7499 /* PDtrace support */
7500 /* gen_helper_mfc0_tracedbpc(arg); */
7501 register_name
= "TraceDBPC";
7502 goto cp0_unimplemented
;
7504 goto cp0_unimplemented
;
7507 case CP0_REGISTER_24
:
7509 case CP0_REG24__DEPC
:
7511 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
7512 tcg_gen_ext32s_tl(arg
, arg
);
7513 register_name
= "DEPC";
7516 goto cp0_unimplemented
;
7519 case CP0_REGISTER_25
:
7521 case CP0_REG25__PERFCTL0
:
7522 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Performance0
));
7523 register_name
= "Performance0";
7525 case CP0_REG25__PERFCNT0
:
7526 /* gen_helper_mfc0_performance1(arg); */
7527 register_name
= "Performance1";
7528 goto cp0_unimplemented
;
7529 case CP0_REG25__PERFCTL1
:
7530 /* gen_helper_mfc0_performance2(arg); */
7531 register_name
= "Performance2";
7532 goto cp0_unimplemented
;
7533 case CP0_REG25__PERFCNT1
:
7534 /* gen_helper_mfc0_performance3(arg); */
7535 register_name
= "Performance3";
7536 goto cp0_unimplemented
;
7537 case CP0_REG25__PERFCTL2
:
7538 /* gen_helper_mfc0_performance4(arg); */
7539 register_name
= "Performance4";
7540 goto cp0_unimplemented
;
7541 case CP0_REG25__PERFCNT2
:
7542 /* gen_helper_mfc0_performance5(arg); */
7543 register_name
= "Performance5";
7544 goto cp0_unimplemented
;
7545 case CP0_REG25__PERFCTL3
:
7546 /* gen_helper_mfc0_performance6(arg); */
7547 register_name
= "Performance6";
7548 goto cp0_unimplemented
;
7549 case CP0_REG25__PERFCNT3
:
7550 /* gen_helper_mfc0_performance7(arg); */
7551 register_name
= "Performance7";
7552 goto cp0_unimplemented
;
7554 goto cp0_unimplemented
;
7557 case CP0_REGISTER_26
:
7559 case CP0_REG26__ERRCTL
:
7560 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_ErrCtl
));
7561 register_name
= "ErrCtl";
7564 goto cp0_unimplemented
;
7567 case CP0_REGISTER_27
:
7569 case CP0_REG27__CACHERR
:
7570 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
7571 register_name
= "CacheErr";
7574 goto cp0_unimplemented
;
7577 case CP0_REGISTER_28
:
7579 case CP0_REG28__TAGLO
:
7580 case CP0_REG28__TAGLO1
:
7581 case CP0_REG28__TAGLO2
:
7582 case CP0_REG28__TAGLO3
:
7584 TCGv_i64 tmp
= tcg_temp_new_i64();
7585 tcg_gen_ld_i64(tmp
, cpu_env
, offsetof(CPUMIPSState
, CP0_TagLo
));
7586 gen_move_low32(arg
, tmp
);
7587 tcg_temp_free_i64(tmp
);
7589 register_name
= "TagLo";
7591 case CP0_REG28__DATALO
:
7592 case CP0_REG28__DATALO1
:
7593 case CP0_REG28__DATALO2
:
7594 case CP0_REG28__DATALO3
:
7595 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataLo
));
7596 register_name
= "DataLo";
7599 goto cp0_unimplemented
;
7602 case CP0_REGISTER_29
:
7604 case CP0_REG29__TAGHI
:
7605 case CP0_REG29__TAGHI1
:
7606 case CP0_REG29__TAGHI2
:
7607 case CP0_REG29__TAGHI3
:
7608 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_TagHi
));
7609 register_name
= "TagHi";
7611 case CP0_REG29__DATAHI
:
7612 case CP0_REG29__DATAHI1
:
7613 case CP0_REG29__DATAHI2
:
7614 case CP0_REG29__DATAHI3
:
7615 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataHi
));
7616 register_name
= "DataHi";
7619 goto cp0_unimplemented
;
7622 case CP0_REGISTER_30
:
7624 case CP0_REG30__ERROREPC
:
7625 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
7626 tcg_gen_ext32s_tl(arg
, arg
);
7627 register_name
= "ErrorEPC";
7630 goto cp0_unimplemented
;
7633 case CP0_REGISTER_31
:
7635 case CP0_REG31__DESAVE
:
7637 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
7638 register_name
= "DESAVE";
7640 case CP0_REG31__KSCRATCH1
:
7641 case CP0_REG31__KSCRATCH2
:
7642 case CP0_REG31__KSCRATCH3
:
7643 case CP0_REG31__KSCRATCH4
:
7644 case CP0_REG31__KSCRATCH5
:
7645 case CP0_REG31__KSCRATCH6
:
7646 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
7647 tcg_gen_ld_tl(arg
, cpu_env
,
7648 offsetof(CPUMIPSState
, CP0_KScratch
[sel
- 2]));
7649 tcg_gen_ext32s_tl(arg
, arg
);
7650 register_name
= "KScratch";
7653 goto cp0_unimplemented
;
7657 goto cp0_unimplemented
;
7659 trace_mips_translate_c0("mfc0", register_name
, reg
, sel
);
7663 qemu_log_mask(LOG_UNIMP
, "mfc0 %s (reg %d sel %d)\n",
7664 register_name
, reg
, sel
);
7665 gen_mfc0_unimplemented(ctx
, arg
);
7668 static void gen_mtc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
7670 const char *register_name
= "invalid";
7673 check_insn(ctx
, ISA_MIPS32
);
7676 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
7681 case CP0_REGISTER_00
:
7683 case CP0_REG00__INDEX
:
7684 gen_helper_mtc0_index(cpu_env
, arg
);
7685 register_name
= "Index";
7687 case CP0_REG00__MVPCONTROL
:
7688 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7689 gen_helper_mtc0_mvpcontrol(cpu_env
, arg
);
7690 register_name
= "MVPControl";
7692 case CP0_REG00__MVPCONF0
:
7693 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7695 register_name
= "MVPConf0";
7697 case CP0_REG00__MVPCONF1
:
7698 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7700 register_name
= "MVPConf1";
7702 case CP0_REG00__VPCONTROL
:
7705 register_name
= "VPControl";
7708 goto cp0_unimplemented
;
7711 case CP0_REGISTER_01
:
7713 case CP0_REG01__RANDOM
:
7715 register_name
= "Random";
7717 case CP0_REG01__VPECONTROL
:
7718 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7719 gen_helper_mtc0_vpecontrol(cpu_env
, arg
);
7720 register_name
= "VPEControl";
7722 case CP0_REG01__VPECONF0
:
7723 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7724 gen_helper_mtc0_vpeconf0(cpu_env
, arg
);
7725 register_name
= "VPEConf0";
7727 case CP0_REG01__VPECONF1
:
7728 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7729 gen_helper_mtc0_vpeconf1(cpu_env
, arg
);
7730 register_name
= "VPEConf1";
7732 case CP0_REG01__YQMASK
:
7733 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7734 gen_helper_mtc0_yqmask(cpu_env
, arg
);
7735 register_name
= "YQMask";
7737 case CP0_REG01__VPESCHEDULE
:
7738 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7739 tcg_gen_st_tl(arg
, cpu_env
,
7740 offsetof(CPUMIPSState
, CP0_VPESchedule
));
7741 register_name
= "VPESchedule";
7743 case CP0_REG01__VPESCHEFBACK
:
7744 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7745 tcg_gen_st_tl(arg
, cpu_env
,
7746 offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
7747 register_name
= "VPEScheFBack";
7749 case CP0_REG01__VPEOPT
:
7750 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7751 gen_helper_mtc0_vpeopt(cpu_env
, arg
);
7752 register_name
= "VPEOpt";
7755 goto cp0_unimplemented
;
7758 case CP0_REGISTER_02
:
7760 case CP0_REG02__ENTRYLO0
:
7761 gen_helper_mtc0_entrylo0(cpu_env
, arg
);
7762 register_name
= "EntryLo0";
7764 case CP0_REG02__TCSTATUS
:
7765 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7766 gen_helper_mtc0_tcstatus(cpu_env
, arg
);
7767 register_name
= "TCStatus";
7769 case CP0_REG02__TCBIND
:
7770 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7771 gen_helper_mtc0_tcbind(cpu_env
, arg
);
7772 register_name
= "TCBind";
7774 case CP0_REG02__TCRESTART
:
7775 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7776 gen_helper_mtc0_tcrestart(cpu_env
, arg
);
7777 register_name
= "TCRestart";
7779 case CP0_REG02__TCHALT
:
7780 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7781 gen_helper_mtc0_tchalt(cpu_env
, arg
);
7782 register_name
= "TCHalt";
7784 case CP0_REG02__TCCONTEXT
:
7785 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7786 gen_helper_mtc0_tccontext(cpu_env
, arg
);
7787 register_name
= "TCContext";
7789 case CP0_REG02__TCSCHEDULE
:
7790 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7791 gen_helper_mtc0_tcschedule(cpu_env
, arg
);
7792 register_name
= "TCSchedule";
7794 case CP0_REG02__TCSCHEFBACK
:
7795 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7796 gen_helper_mtc0_tcschefback(cpu_env
, arg
);
7797 register_name
= "TCScheFBack";
7800 goto cp0_unimplemented
;
7803 case CP0_REGISTER_03
:
7805 case CP0_REG03__ENTRYLO1
:
7806 gen_helper_mtc0_entrylo1(cpu_env
, arg
);
7807 register_name
= "EntryLo1";
7809 case CP0_REG03__GLOBALNUM
:
7812 register_name
= "GlobalNumber";
7815 goto cp0_unimplemented
;
7818 case CP0_REGISTER_04
:
7820 case CP0_REG04__CONTEXT
:
7821 gen_helper_mtc0_context(cpu_env
, arg
);
7822 register_name
= "Context";
7824 case CP0_REG04__CONTEXTCONFIG
:
7826 /* gen_helper_mtc0_contextconfig(arg); */
7827 register_name
= "ContextConfig";
7828 goto cp0_unimplemented
;
7829 case CP0_REG04__USERLOCAL
:
7830 CP0_CHECK(ctx
->ulri
);
7831 tcg_gen_st_tl(arg
, cpu_env
,
7832 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
7833 register_name
= "UserLocal";
7836 goto cp0_unimplemented
;
7839 case CP0_REGISTER_05
:
7841 case CP0_REG05__PAGEMASK
:
7842 gen_helper_mtc0_pagemask(cpu_env
, arg
);
7843 register_name
= "PageMask";
7845 case CP0_REG05__PAGEGRAIN
:
7846 check_insn(ctx
, ISA_MIPS32R2
);
7847 gen_helper_mtc0_pagegrain(cpu_env
, arg
);
7848 register_name
= "PageGrain";
7849 ctx
->base
.is_jmp
= DISAS_STOP
;
7851 case CP0_REG05__SEGCTL0
:
7853 gen_helper_mtc0_segctl0(cpu_env
, arg
);
7854 register_name
= "SegCtl0";
7856 case CP0_REG05__SEGCTL1
:
7858 gen_helper_mtc0_segctl1(cpu_env
, arg
);
7859 register_name
= "SegCtl1";
7861 case CP0_REG05__SEGCTL2
:
7863 gen_helper_mtc0_segctl2(cpu_env
, arg
);
7864 register_name
= "SegCtl2";
7866 case CP0_REG05__PWBASE
:
7868 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_PWBase
));
7869 register_name
= "PWBase";
7871 case CP0_REG05__PWFIELD
:
7873 gen_helper_mtc0_pwfield(cpu_env
, arg
);
7874 register_name
= "PWField";
7876 case CP0_REG05__PWSIZE
:
7878 gen_helper_mtc0_pwsize(cpu_env
, arg
);
7879 register_name
= "PWSize";
7882 goto cp0_unimplemented
;
7885 case CP0_REGISTER_06
:
7887 case CP0_REG06__WIRED
:
7888 gen_helper_mtc0_wired(cpu_env
, arg
);
7889 register_name
= "Wired";
7891 case CP0_REG06__SRSCONF0
:
7892 check_insn(ctx
, ISA_MIPS32R2
);
7893 gen_helper_mtc0_srsconf0(cpu_env
, arg
);
7894 register_name
= "SRSConf0";
7896 case CP0_REG06__SRSCONF1
:
7897 check_insn(ctx
, ISA_MIPS32R2
);
7898 gen_helper_mtc0_srsconf1(cpu_env
, arg
);
7899 register_name
= "SRSConf1";
7901 case CP0_REG06__SRSCONF2
:
7902 check_insn(ctx
, ISA_MIPS32R2
);
7903 gen_helper_mtc0_srsconf2(cpu_env
, arg
);
7904 register_name
= "SRSConf2";
7906 case CP0_REG06__SRSCONF3
:
7907 check_insn(ctx
, ISA_MIPS32R2
);
7908 gen_helper_mtc0_srsconf3(cpu_env
, arg
);
7909 register_name
= "SRSConf3";
7911 case CP0_REG06__SRSCONF4
:
7912 check_insn(ctx
, ISA_MIPS32R2
);
7913 gen_helper_mtc0_srsconf4(cpu_env
, arg
);
7914 register_name
= "SRSConf4";
7916 case CP0_REG06__PWCTL
:
7918 gen_helper_mtc0_pwctl(cpu_env
, arg
);
7919 register_name
= "PWCtl";
7922 goto cp0_unimplemented
;
7925 case CP0_REGISTER_07
:
7927 case CP0_REG07__HWRENA
:
7928 check_insn(ctx
, ISA_MIPS32R2
);
7929 gen_helper_mtc0_hwrena(cpu_env
, arg
);
7930 ctx
->base
.is_jmp
= DISAS_STOP
;
7931 register_name
= "HWREna";
7934 goto cp0_unimplemented
;
7937 case CP0_REGISTER_08
:
7939 case CP0_REG08__BADVADDR
:
7941 register_name
= "BadVAddr";
7943 case CP0_REG08__BADINSTR
:
7945 register_name
= "BadInstr";
7947 case CP0_REG08__BADINSTRP
:
7949 register_name
= "BadInstrP";
7951 case CP0_REG08__BADINSTRX
:
7953 register_name
= "BadInstrX";
7956 goto cp0_unimplemented
;
7959 case CP0_REGISTER_09
:
7961 case CP0_REG09__COUNT
:
7962 gen_helper_mtc0_count(cpu_env
, arg
);
7963 register_name
= "Count";
7965 case CP0_REG09__SAARI
:
7966 CP0_CHECK(ctx
->saar
);
7967 gen_helper_mtc0_saari(cpu_env
, arg
);
7968 register_name
= "SAARI";
7970 case CP0_REG09__SAAR
:
7971 CP0_CHECK(ctx
->saar
);
7972 gen_helper_mtc0_saar(cpu_env
, arg
);
7973 register_name
= "SAAR";
7976 goto cp0_unimplemented
;
7979 case CP0_REGISTER_10
:
7981 case CP0_REG10__ENTRYHI
:
7982 gen_helper_mtc0_entryhi(cpu_env
, arg
);
7983 register_name
= "EntryHi";
7986 goto cp0_unimplemented
;
7989 case CP0_REGISTER_11
:
7991 case CP0_REG11__COMPARE
:
7992 gen_helper_mtc0_compare(cpu_env
, arg
);
7993 register_name
= "Compare";
7995 /* 6,7 are implementation dependent */
7997 goto cp0_unimplemented
;
8000 case CP0_REGISTER_12
:
8002 case CP0_REG12__STATUS
:
8003 save_cpu_state(ctx
, 1);
8004 gen_helper_mtc0_status(cpu_env
, arg
);
8005 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8006 gen_save_pc(ctx
->base
.pc_next
+ 4);
8007 ctx
->base
.is_jmp
= DISAS_EXIT
;
8008 register_name
= "Status";
8010 case CP0_REG12__INTCTL
:
8011 check_insn(ctx
, ISA_MIPS32R2
);
8012 gen_helper_mtc0_intctl(cpu_env
, arg
);
8013 /* Stop translation as we may have switched the execution mode */
8014 ctx
->base
.is_jmp
= DISAS_STOP
;
8015 register_name
= "IntCtl";
8017 case CP0_REG12__SRSCTL
:
8018 check_insn(ctx
, ISA_MIPS32R2
);
8019 gen_helper_mtc0_srsctl(cpu_env
, arg
);
8020 /* Stop translation as we may have switched the execution mode */
8021 ctx
->base
.is_jmp
= DISAS_STOP
;
8022 register_name
= "SRSCtl";
8024 case CP0_REG12__SRSMAP
:
8025 check_insn(ctx
, ISA_MIPS32R2
);
8026 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
8027 /* Stop translation as we may have switched the execution mode */
8028 ctx
->base
.is_jmp
= DISAS_STOP
;
8029 register_name
= "SRSMap";
8032 goto cp0_unimplemented
;
8035 case CP0_REGISTER_13
:
8037 case CP0_REG13__CAUSE
:
8038 save_cpu_state(ctx
, 1);
8039 gen_helper_mtc0_cause(cpu_env
, arg
);
8041 * Stop translation as we may have triggered an interrupt.
8042 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8043 * translated code to check for pending interrupts.
8045 gen_save_pc(ctx
->base
.pc_next
+ 4);
8046 ctx
->base
.is_jmp
= DISAS_EXIT
;
8047 register_name
= "Cause";
8050 goto cp0_unimplemented
;
8053 case CP0_REGISTER_14
:
8055 case CP0_REG14__EPC
:
8056 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
8057 register_name
= "EPC";
8060 goto cp0_unimplemented
;
8063 case CP0_REGISTER_15
:
8065 case CP0_REG15__PRID
:
8067 register_name
= "PRid";
8069 case CP0_REG15__EBASE
:
8070 check_insn(ctx
, ISA_MIPS32R2
);
8071 gen_helper_mtc0_ebase(cpu_env
, arg
);
8072 register_name
= "EBase";
8075 goto cp0_unimplemented
;
8078 case CP0_REGISTER_16
:
8080 case CP0_REG16__CONFIG
:
8081 gen_helper_mtc0_config0(cpu_env
, arg
);
8082 register_name
= "Config";
8083 /* Stop translation as we may have switched the execution mode */
8084 ctx
->base
.is_jmp
= DISAS_STOP
;
8086 case CP0_REG16__CONFIG1
:
8087 /* ignored, read only */
8088 register_name
= "Config1";
8090 case CP0_REG16__CONFIG2
:
8091 gen_helper_mtc0_config2(cpu_env
, arg
);
8092 register_name
= "Config2";
8093 /* Stop translation as we may have switched the execution mode */
8094 ctx
->base
.is_jmp
= DISAS_STOP
;
8096 case CP0_REG16__CONFIG3
:
8097 gen_helper_mtc0_config3(cpu_env
, arg
);
8098 register_name
= "Config3";
8099 /* Stop translation as we may have switched the execution mode */
8100 ctx
->base
.is_jmp
= DISAS_STOP
;
8102 case CP0_REG16__CONFIG4
:
8103 gen_helper_mtc0_config4(cpu_env
, arg
);
8104 register_name
= "Config4";
8105 ctx
->base
.is_jmp
= DISAS_STOP
;
8107 case CP0_REG16__CONFIG5
:
8108 gen_helper_mtc0_config5(cpu_env
, arg
);
8109 register_name
= "Config5";
8110 /* Stop translation as we may have switched the execution mode */
8111 ctx
->base
.is_jmp
= DISAS_STOP
;
8113 /* 6,7 are implementation dependent */
8114 case CP0_REG16__CONFIG6
:
8116 register_name
= "Config6";
8118 case CP0_REG16__CONFIG7
:
8120 register_name
= "Config7";
8123 register_name
= "Invalid config selector";
8124 goto cp0_unimplemented
;
8127 case CP0_REGISTER_17
:
8129 case CP0_REG17__LLADDR
:
8130 gen_helper_mtc0_lladdr(cpu_env
, arg
);
8131 register_name
= "LLAddr";
8133 case CP0_REG17__MAAR
:
8134 CP0_CHECK(ctx
->mrp
);
8135 gen_helper_mtc0_maar(cpu_env
, arg
);
8136 register_name
= "MAAR";
8138 case CP0_REG17__MAARI
:
8139 CP0_CHECK(ctx
->mrp
);
8140 gen_helper_mtc0_maari(cpu_env
, arg
);
8141 register_name
= "MAARI";
8144 goto cp0_unimplemented
;
8147 case CP0_REGISTER_18
:
8149 case CP0_REG18__WATCHLO0
:
8150 case CP0_REG18__WATCHLO1
:
8151 case CP0_REG18__WATCHLO2
:
8152 case CP0_REG18__WATCHLO3
:
8153 case CP0_REG18__WATCHLO4
:
8154 case CP0_REG18__WATCHLO5
:
8155 case CP0_REG18__WATCHLO6
:
8156 case CP0_REG18__WATCHLO7
:
8157 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
8158 gen_helper_0e1i(mtc0_watchlo
, arg
, sel
);
8159 register_name
= "WatchLo";
8162 goto cp0_unimplemented
;
8165 case CP0_REGISTER_19
:
8167 case CP0_REG19__WATCHHI0
:
8168 case CP0_REG19__WATCHHI1
:
8169 case CP0_REG19__WATCHHI2
:
8170 case CP0_REG19__WATCHHI3
:
8171 case CP0_REG19__WATCHHI4
:
8172 case CP0_REG19__WATCHHI5
:
8173 case CP0_REG19__WATCHHI6
:
8174 case CP0_REG19__WATCHHI7
:
8175 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
8176 gen_helper_0e1i(mtc0_watchhi
, arg
, sel
);
8177 register_name
= "WatchHi";
8180 goto cp0_unimplemented
;
8183 case CP0_REGISTER_20
:
8185 case CP0_REG20__XCONTEXT
:
8186 #if defined(TARGET_MIPS64)
8187 check_insn(ctx
, ISA_MIPS3
);
8188 gen_helper_mtc0_xcontext(cpu_env
, arg
);
8189 register_name
= "XContext";
8193 goto cp0_unimplemented
;
8196 case CP0_REGISTER_21
:
8197 /* Officially reserved, but sel 0 is used for R1x000 framemask */
8198 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
8201 gen_helper_mtc0_framemask(cpu_env
, arg
);
8202 register_name
= "Framemask";
8205 goto cp0_unimplemented
;
8208 case CP0_REGISTER_22
:
8210 register_name
= "Diagnostic"; /* implementation dependent */
8212 case CP0_REGISTER_23
:
8214 case CP0_REG23__DEBUG
:
8215 gen_helper_mtc0_debug(cpu_env
, arg
); /* EJTAG support */
8216 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8217 gen_save_pc(ctx
->base
.pc_next
+ 4);
8218 ctx
->base
.is_jmp
= DISAS_EXIT
;
8219 register_name
= "Debug";
8221 case CP0_REG23__TRACECONTROL
:
8222 /* PDtrace support */
8223 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
8224 register_name
= "TraceControl";
8225 /* Stop translation as we may have switched the execution mode */
8226 ctx
->base
.is_jmp
= DISAS_STOP
;
8227 goto cp0_unimplemented
;
8228 case CP0_REG23__TRACECONTROL2
:
8229 /* PDtrace support */
8230 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
8231 register_name
= "TraceControl2";
8232 /* Stop translation as we may have switched the execution mode */
8233 ctx
->base
.is_jmp
= DISAS_STOP
;
8234 goto cp0_unimplemented
;
8235 case CP0_REG23__USERTRACEDATA1
:
8236 /* Stop translation as we may have switched the execution mode */
8237 ctx
->base
.is_jmp
= DISAS_STOP
;
8238 /* PDtrace support */
8239 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
8240 register_name
= "UserTraceData";
8241 /* Stop translation as we may have switched the execution mode */
8242 ctx
->base
.is_jmp
= DISAS_STOP
;
8243 goto cp0_unimplemented
;
8244 case CP0_REG23__TRACEIBPC
:
8245 /* PDtrace support */
8246 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
8247 /* Stop translation as we may have switched the execution mode */
8248 ctx
->base
.is_jmp
= DISAS_STOP
;
8249 register_name
= "TraceIBPC";
8250 goto cp0_unimplemented
;
8251 case CP0_REG23__TRACEDBPC
:
8252 /* PDtrace support */
8253 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
8254 /* Stop translation as we may have switched the execution mode */
8255 ctx
->base
.is_jmp
= DISAS_STOP
;
8256 register_name
= "TraceDBPC";
8257 goto cp0_unimplemented
;
8259 goto cp0_unimplemented
;
8262 case CP0_REGISTER_24
:
8264 case CP0_REG24__DEPC
:
8266 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
8267 register_name
= "DEPC";
8270 goto cp0_unimplemented
;
8273 case CP0_REGISTER_25
:
8275 case CP0_REG25__PERFCTL0
:
8276 gen_helper_mtc0_performance0(cpu_env
, arg
);
8277 register_name
= "Performance0";
8279 case CP0_REG25__PERFCNT0
:
8280 /* gen_helper_mtc0_performance1(arg); */
8281 register_name
= "Performance1";
8282 goto cp0_unimplemented
;
8283 case CP0_REG25__PERFCTL1
:
8284 /* gen_helper_mtc0_performance2(arg); */
8285 register_name
= "Performance2";
8286 goto cp0_unimplemented
;
8287 case CP0_REG25__PERFCNT1
:
8288 /* gen_helper_mtc0_performance3(arg); */
8289 register_name
= "Performance3";
8290 goto cp0_unimplemented
;
8291 case CP0_REG25__PERFCTL2
:
8292 /* gen_helper_mtc0_performance4(arg); */
8293 register_name
= "Performance4";
8294 goto cp0_unimplemented
;
8295 case CP0_REG25__PERFCNT2
:
8296 /* gen_helper_mtc0_performance5(arg); */
8297 register_name
= "Performance5";
8298 goto cp0_unimplemented
;
8299 case CP0_REG25__PERFCTL3
:
8300 /* gen_helper_mtc0_performance6(arg); */
8301 register_name
= "Performance6";
8302 goto cp0_unimplemented
;
8303 case CP0_REG25__PERFCNT3
:
8304 /* gen_helper_mtc0_performance7(arg); */
8305 register_name
= "Performance7";
8306 goto cp0_unimplemented
;
8308 goto cp0_unimplemented
;
8311 case CP0_REGISTER_26
:
8313 case CP0_REG26__ERRCTL
:
8314 gen_helper_mtc0_errctl(cpu_env
, arg
);
8315 ctx
->base
.is_jmp
= DISAS_STOP
;
8316 register_name
= "ErrCtl";
8319 goto cp0_unimplemented
;
8322 case CP0_REGISTER_27
:
8324 case CP0_REG27__CACHERR
:
8326 register_name
= "CacheErr";
8329 goto cp0_unimplemented
;
8332 case CP0_REGISTER_28
:
8334 case CP0_REG28__TAGLO
:
8335 case CP0_REG28__TAGLO1
:
8336 case CP0_REG28__TAGLO2
:
8337 case CP0_REG28__TAGLO3
:
8338 gen_helper_mtc0_taglo(cpu_env
, arg
);
8339 register_name
= "TagLo";
8341 case CP0_REG28__DATALO
:
8342 case CP0_REG28__DATALO1
:
8343 case CP0_REG28__DATALO2
:
8344 case CP0_REG28__DATALO3
:
8345 gen_helper_mtc0_datalo(cpu_env
, arg
);
8346 register_name
= "DataLo";
8349 goto cp0_unimplemented
;
8352 case CP0_REGISTER_29
:
8354 case CP0_REG29__TAGHI
:
8355 case CP0_REG29__TAGHI1
:
8356 case CP0_REG29__TAGHI2
:
8357 case CP0_REG29__TAGHI3
:
8358 gen_helper_mtc0_taghi(cpu_env
, arg
);
8359 register_name
= "TagHi";
8361 case CP0_REG29__DATAHI
:
8362 case CP0_REG29__DATAHI1
:
8363 case CP0_REG29__DATAHI2
:
8364 case CP0_REG29__DATAHI3
:
8365 gen_helper_mtc0_datahi(cpu_env
, arg
);
8366 register_name
= "DataHi";
8369 register_name
= "invalid sel";
8370 goto cp0_unimplemented
;
8373 case CP0_REGISTER_30
:
8375 case CP0_REG30__ERROREPC
:
8376 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
8377 register_name
= "ErrorEPC";
8380 goto cp0_unimplemented
;
8383 case CP0_REGISTER_31
:
8385 case CP0_REG31__DESAVE
:
8387 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
8388 register_name
= "DESAVE";
8390 case CP0_REG31__KSCRATCH1
:
8391 case CP0_REG31__KSCRATCH2
:
8392 case CP0_REG31__KSCRATCH3
:
8393 case CP0_REG31__KSCRATCH4
:
8394 case CP0_REG31__KSCRATCH5
:
8395 case CP0_REG31__KSCRATCH6
:
8396 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
8397 tcg_gen_st_tl(arg
, cpu_env
,
8398 offsetof(CPUMIPSState
, CP0_KScratch
[sel
- 2]));
8399 register_name
= "KScratch";
8402 goto cp0_unimplemented
;
8406 goto cp0_unimplemented
;
8408 trace_mips_translate_c0("mtc0", register_name
, reg
, sel
);
8410 /* For simplicity assume that all writes can cause interrupts. */
8411 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
8413 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8414 * translated code to check for pending interrupts.
8416 gen_save_pc(ctx
->base
.pc_next
+ 4);
8417 ctx
->base
.is_jmp
= DISAS_EXIT
;
8422 qemu_log_mask(LOG_UNIMP
, "mtc0 %s (reg %d sel %d)\n",
8423 register_name
, reg
, sel
);
8426 #if defined(TARGET_MIPS64)
8427 static void gen_dmfc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
8429 const char *register_name
= "invalid";
8432 check_insn(ctx
, ISA_MIPS64
);
8436 case CP0_REGISTER_00
:
8438 case CP0_REG00__INDEX
:
8439 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Index
));
8440 register_name
= "Index";
8442 case CP0_REG00__MVPCONTROL
:
8443 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8444 gen_helper_mfc0_mvpcontrol(arg
, cpu_env
);
8445 register_name
= "MVPControl";
8447 case CP0_REG00__MVPCONF0
:
8448 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8449 gen_helper_mfc0_mvpconf0(arg
, cpu_env
);
8450 register_name
= "MVPConf0";
8452 case CP0_REG00__MVPCONF1
:
8453 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8454 gen_helper_mfc0_mvpconf1(arg
, cpu_env
);
8455 register_name
= "MVPConf1";
8457 case CP0_REG00__VPCONTROL
:
8459 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPControl
));
8460 register_name
= "VPControl";
8463 goto cp0_unimplemented
;
8466 case CP0_REGISTER_01
:
8468 case CP0_REG01__RANDOM
:
8469 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
8470 gen_helper_mfc0_random(arg
, cpu_env
);
8471 register_name
= "Random";
8473 case CP0_REG01__VPECONTROL
:
8474 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8475 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEControl
));
8476 register_name
= "VPEControl";
8478 case CP0_REG01__VPECONF0
:
8479 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8480 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf0
));
8481 register_name
= "VPEConf0";
8483 case CP0_REG01__VPECONF1
:
8484 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8485 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf1
));
8486 register_name
= "VPEConf1";
8488 case CP0_REG01__YQMASK
:
8489 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8490 tcg_gen_ld_tl(arg
, cpu_env
,
8491 offsetof(CPUMIPSState
, CP0_YQMask
));
8492 register_name
= "YQMask";
8494 case CP0_REG01__VPESCHEDULE
:
8495 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8496 tcg_gen_ld_tl(arg
, cpu_env
,
8497 offsetof(CPUMIPSState
, CP0_VPESchedule
));
8498 register_name
= "VPESchedule";
8500 case CP0_REG01__VPESCHEFBACK
:
8501 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8502 tcg_gen_ld_tl(arg
, cpu_env
,
8503 offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
8504 register_name
= "VPEScheFBack";
8506 case CP0_REG01__VPEOPT
:
8507 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8508 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEOpt
));
8509 register_name
= "VPEOpt";
8512 goto cp0_unimplemented
;
8515 case CP0_REGISTER_02
:
8517 case CP0_REG02__ENTRYLO0
:
8518 tcg_gen_ld_tl(arg
, cpu_env
,
8519 offsetof(CPUMIPSState
, CP0_EntryLo0
));
8520 register_name
= "EntryLo0";
8522 case CP0_REG02__TCSTATUS
:
8523 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8524 gen_helper_mfc0_tcstatus(arg
, cpu_env
);
8525 register_name
= "TCStatus";
8527 case CP0_REG02__TCBIND
:
8528 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8529 gen_helper_mfc0_tcbind(arg
, cpu_env
);
8530 register_name
= "TCBind";
8532 case CP0_REG02__TCRESTART
:
8533 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8534 gen_helper_dmfc0_tcrestart(arg
, cpu_env
);
8535 register_name
= "TCRestart";
8537 case CP0_REG02__TCHALT
:
8538 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8539 gen_helper_dmfc0_tchalt(arg
, cpu_env
);
8540 register_name
= "TCHalt";
8542 case CP0_REG02__TCCONTEXT
:
8543 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8544 gen_helper_dmfc0_tccontext(arg
, cpu_env
);
8545 register_name
= "TCContext";
8547 case CP0_REG02__TCSCHEDULE
:
8548 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8549 gen_helper_dmfc0_tcschedule(arg
, cpu_env
);
8550 register_name
= "TCSchedule";
8552 case CP0_REG02__TCSCHEFBACK
:
8553 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
8554 gen_helper_dmfc0_tcschefback(arg
, cpu_env
);
8555 register_name
= "TCScheFBack";
8558 goto cp0_unimplemented
;
8561 case CP0_REGISTER_03
:
8563 case CP0_REG03__ENTRYLO1
:
8564 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryLo1
));
8565 register_name
= "EntryLo1";
8567 case CP0_REG03__GLOBALNUM
:
8569 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_GlobalNumber
));
8570 register_name
= "GlobalNumber";
8573 goto cp0_unimplemented
;
8576 case CP0_REGISTER_04
:
8578 case CP0_REG04__CONTEXT
:
8579 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_Context
));
8580 register_name
= "Context";
8582 case CP0_REG04__CONTEXTCONFIG
:
8584 /* gen_helper_dmfc0_contextconfig(arg); */
8585 register_name
= "ContextConfig";
8586 goto cp0_unimplemented
;
8587 case CP0_REG04__USERLOCAL
:
8588 CP0_CHECK(ctx
->ulri
);
8589 tcg_gen_ld_tl(arg
, cpu_env
,
8590 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
8591 register_name
= "UserLocal";
8594 goto cp0_unimplemented
;
8597 case CP0_REGISTER_05
:
8599 case CP0_REG05__PAGEMASK
:
8600 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageMask
));
8601 register_name
= "PageMask";
8603 case CP0_REG05__PAGEGRAIN
:
8604 check_insn(ctx
, ISA_MIPS32R2
);
8605 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageGrain
));
8606 register_name
= "PageGrain";
8608 case CP0_REG05__SEGCTL0
:
8610 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_SegCtl0
));
8611 register_name
= "SegCtl0";
8613 case CP0_REG05__SEGCTL1
:
8615 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_SegCtl1
));
8616 register_name
= "SegCtl1";
8618 case CP0_REG05__SEGCTL2
:
8620 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_SegCtl2
));
8621 register_name
= "SegCtl2";
8623 case CP0_REG05__PWBASE
:
8625 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_PWBase
));
8626 register_name
= "PWBase";
8628 case CP0_REG05__PWFIELD
:
8630 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_PWField
));
8631 register_name
= "PWField";
8633 case CP0_REG05__PWSIZE
:
8635 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_PWSize
));
8636 register_name
= "PWSize";
8639 goto cp0_unimplemented
;
8642 case CP0_REGISTER_06
:
8644 case CP0_REG06__WIRED
:
8645 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Wired
));
8646 register_name
= "Wired";
8648 case CP0_REG06__SRSCONF0
:
8649 check_insn(ctx
, ISA_MIPS32R2
);
8650 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf0
));
8651 register_name
= "SRSConf0";
8653 case CP0_REG06__SRSCONF1
:
8654 check_insn(ctx
, ISA_MIPS32R2
);
8655 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf1
));
8656 register_name
= "SRSConf1";
8658 case CP0_REG06__SRSCONF2
:
8659 check_insn(ctx
, ISA_MIPS32R2
);
8660 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf2
));
8661 register_name
= "SRSConf2";
8663 case CP0_REG06__SRSCONF3
:
8664 check_insn(ctx
, ISA_MIPS32R2
);
8665 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf3
));
8666 register_name
= "SRSConf3";
8668 case CP0_REG06__SRSCONF4
:
8669 check_insn(ctx
, ISA_MIPS32R2
);
8670 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf4
));
8671 register_name
= "SRSConf4";
8673 case CP0_REG06__PWCTL
:
8675 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PWCtl
));
8676 register_name
= "PWCtl";
8679 goto cp0_unimplemented
;
8682 case CP0_REGISTER_07
:
8684 case CP0_REG07__HWRENA
:
8685 check_insn(ctx
, ISA_MIPS32R2
);
8686 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_HWREna
));
8687 register_name
= "HWREna";
8690 goto cp0_unimplemented
;
8693 case CP0_REGISTER_08
:
8695 case CP0_REG08__BADVADDR
:
8696 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_BadVAddr
));
8697 register_name
= "BadVAddr";
8699 case CP0_REG08__BADINSTR
:
8701 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstr
));
8702 register_name
= "BadInstr";
8704 case CP0_REG08__BADINSTRP
:
8706 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstrP
));
8707 register_name
= "BadInstrP";
8709 case CP0_REG08__BADINSTRX
:
8711 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstrX
));
8712 tcg_gen_andi_tl(arg
, arg
, ~0xffff);
8713 register_name
= "BadInstrX";
8716 goto cp0_unimplemented
;
8719 case CP0_REGISTER_09
:
8721 case CP0_REG09__COUNT
:
8722 /* Mark as an IO operation because we read the time. */
8723 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
8726 gen_helper_mfc0_count(arg
, cpu_env
);
8728 * Break the TB to be able to take timer interrupts immediately
8729 * after reading count. DISAS_STOP isn't sufficient, we need to
8730 * ensure we break completely out of translated code.
8732 gen_save_pc(ctx
->base
.pc_next
+ 4);
8733 ctx
->base
.is_jmp
= DISAS_EXIT
;
8734 register_name
= "Count";
8736 case CP0_REG09__SAARI
:
8737 CP0_CHECK(ctx
->saar
);
8738 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SAARI
));
8739 register_name
= "SAARI";
8741 case CP0_REG09__SAAR
:
8742 CP0_CHECK(ctx
->saar
);
8743 gen_helper_dmfc0_saar(arg
, cpu_env
);
8744 register_name
= "SAAR";
8747 goto cp0_unimplemented
;
8750 case CP0_REGISTER_10
:
8752 case CP0_REG10__ENTRYHI
:
8753 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryHi
));
8754 register_name
= "EntryHi";
8757 goto cp0_unimplemented
;
8760 case CP0_REGISTER_11
:
8762 case CP0_REG11__COMPARE
:
8763 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Compare
));
8764 register_name
= "Compare";
8766 /* 6,7 are implementation dependent */
8768 goto cp0_unimplemented
;
8771 case CP0_REGISTER_12
:
8773 case CP0_REG12__STATUS
:
8774 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Status
));
8775 register_name
= "Status";
8777 case CP0_REG12__INTCTL
:
8778 check_insn(ctx
, ISA_MIPS32R2
);
8779 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_IntCtl
));
8780 register_name
= "IntCtl";
8782 case CP0_REG12__SRSCTL
:
8783 check_insn(ctx
, ISA_MIPS32R2
);
8784 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
8785 register_name
= "SRSCtl";
8787 case CP0_REG12__SRSMAP
:
8788 check_insn(ctx
, ISA_MIPS32R2
);
8789 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
8790 register_name
= "SRSMap";
8793 goto cp0_unimplemented
;
8796 case CP0_REGISTER_13
:
8798 case CP0_REG13__CAUSE
:
8799 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Cause
));
8800 register_name
= "Cause";
8803 goto cp0_unimplemented
;
8806 case CP0_REGISTER_14
:
8808 case CP0_REG14__EPC
:
8809 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
8810 register_name
= "EPC";
8813 goto cp0_unimplemented
;
8816 case CP0_REGISTER_15
:
8818 case CP0_REG15__PRID
:
8819 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PRid
));
8820 register_name
= "PRid";
8822 case CP0_REG15__EBASE
:
8823 check_insn(ctx
, ISA_MIPS32R2
);
8824 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EBase
));
8825 register_name
= "EBase";
8827 case CP0_REG15__CMGCRBASE
:
8828 check_insn(ctx
, ISA_MIPS32R2
);
8829 CP0_CHECK(ctx
->cmgcr
);
8830 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_CMGCRBase
));
8831 register_name
= "CMGCRBase";
8834 goto cp0_unimplemented
;
8837 case CP0_REGISTER_16
:
8839 case CP0_REG16__CONFIG
:
8840 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config0
));
8841 register_name
= "Config";
8843 case CP0_REG16__CONFIG1
:
8844 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config1
));
8845 register_name
= "Config1";
8847 case CP0_REG16__CONFIG2
:
8848 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config2
));
8849 register_name
= "Config2";
8851 case CP0_REG16__CONFIG3
:
8852 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config3
));
8853 register_name
= "Config3";
8855 case CP0_REG16__CONFIG4
:
8856 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config4
));
8857 register_name
= "Config4";
8859 case CP0_REG16__CONFIG5
:
8860 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config5
));
8861 register_name
= "Config5";
8863 /* 6,7 are implementation dependent */
8864 case CP0_REG16__CONFIG6
:
8865 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config6
));
8866 register_name
= "Config6";
8868 case CP0_REG16__CONFIG7
:
8869 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config7
));
8870 register_name
= "Config7";
8873 goto cp0_unimplemented
;
8876 case CP0_REGISTER_17
:
8878 case CP0_REG17__LLADDR
:
8879 gen_helper_dmfc0_lladdr(arg
, cpu_env
);
8880 register_name
= "LLAddr";
8882 case CP0_REG17__MAAR
:
8883 CP0_CHECK(ctx
->mrp
);
8884 gen_helper_dmfc0_maar(arg
, cpu_env
);
8885 register_name
= "MAAR";
8887 case CP0_REG17__MAARI
:
8888 CP0_CHECK(ctx
->mrp
);
8889 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_MAARI
));
8890 register_name
= "MAARI";
8893 goto cp0_unimplemented
;
8896 case CP0_REGISTER_18
:
8898 case CP0_REG18__WATCHLO0
:
8899 case CP0_REG18__WATCHLO1
:
8900 case CP0_REG18__WATCHLO2
:
8901 case CP0_REG18__WATCHLO3
:
8902 case CP0_REG18__WATCHLO4
:
8903 case CP0_REG18__WATCHLO5
:
8904 case CP0_REG18__WATCHLO6
:
8905 case CP0_REG18__WATCHLO7
:
8906 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
8907 gen_helper_1e0i(dmfc0_watchlo
, arg
, sel
);
8908 register_name
= "WatchLo";
8911 goto cp0_unimplemented
;
8914 case CP0_REGISTER_19
:
8916 case CP0_REG19__WATCHHI0
:
8917 case CP0_REG19__WATCHHI1
:
8918 case CP0_REG19__WATCHHI2
:
8919 case CP0_REG19__WATCHHI3
:
8920 case CP0_REG19__WATCHHI4
:
8921 case CP0_REG19__WATCHHI5
:
8922 case CP0_REG19__WATCHHI6
:
8923 case CP0_REG19__WATCHHI7
:
8924 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
8925 gen_helper_1e0i(mfc0_watchhi
, arg
, sel
);
8926 register_name
= "WatchHi";
8929 goto cp0_unimplemented
;
8932 case CP0_REGISTER_20
:
8934 case CP0_REG20__XCONTEXT
:
8935 check_insn(ctx
, ISA_MIPS3
);
8936 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_XContext
));
8937 register_name
= "XContext";
8940 goto cp0_unimplemented
;
8943 case CP0_REGISTER_21
:
8944 /* Officially reserved, but sel 0 is used for R1x000 framemask */
8945 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
8948 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Framemask
));
8949 register_name
= "Framemask";
8952 goto cp0_unimplemented
;
8955 case CP0_REGISTER_22
:
8956 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
8957 register_name
= "'Diagnostic"; /* implementation dependent */
8959 case CP0_REGISTER_23
:
8961 case CP0_REG23__DEBUG
:
8962 gen_helper_mfc0_debug(arg
, cpu_env
); /* EJTAG support */
8963 register_name
= "Debug";
8965 case CP0_REG23__TRACECONTROL
:
8966 /* PDtrace support */
8967 /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
8968 register_name
= "TraceControl";
8969 goto cp0_unimplemented
;
8970 case CP0_REG23__TRACECONTROL2
:
8971 /* PDtrace support */
8972 /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
8973 register_name
= "TraceControl2";
8974 goto cp0_unimplemented
;
8975 case CP0_REG23__USERTRACEDATA1
:
8976 /* PDtrace support */
8977 /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
8978 register_name
= "UserTraceData1";
8979 goto cp0_unimplemented
;
8980 case CP0_REG23__TRACEIBPC
:
8981 /* PDtrace support */
8982 /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
8983 register_name
= "TraceIBPC";
8984 goto cp0_unimplemented
;
8985 case CP0_REG23__TRACEDBPC
:
8986 /* PDtrace support */
8987 /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
8988 register_name
= "TraceDBPC";
8989 goto cp0_unimplemented
;
8991 goto cp0_unimplemented
;
8994 case CP0_REGISTER_24
:
8996 case CP0_REG24__DEPC
:
8998 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
8999 register_name
= "DEPC";
9002 goto cp0_unimplemented
;
9005 case CP0_REGISTER_25
:
9007 case CP0_REG25__PERFCTL0
:
9008 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Performance0
));
9009 register_name
= "Performance0";
9011 case CP0_REG25__PERFCNT0
:
9012 /* gen_helper_dmfc0_performance1(arg); */
9013 register_name
= "Performance1";
9014 goto cp0_unimplemented
;
9015 case CP0_REG25__PERFCTL1
:
9016 /* gen_helper_dmfc0_performance2(arg); */
9017 register_name
= "Performance2";
9018 goto cp0_unimplemented
;
9019 case CP0_REG25__PERFCNT1
:
9020 /* gen_helper_dmfc0_performance3(arg); */
9021 register_name
= "Performance3";
9022 goto cp0_unimplemented
;
9023 case CP0_REG25__PERFCTL2
:
9024 /* gen_helper_dmfc0_performance4(arg); */
9025 register_name
= "Performance4";
9026 goto cp0_unimplemented
;
9027 case CP0_REG25__PERFCNT2
:
9028 /* gen_helper_dmfc0_performance5(arg); */
9029 register_name
= "Performance5";
9030 goto cp0_unimplemented
;
9031 case CP0_REG25__PERFCTL3
:
9032 /* gen_helper_dmfc0_performance6(arg); */
9033 register_name
= "Performance6";
9034 goto cp0_unimplemented
;
9035 case CP0_REG25__PERFCNT3
:
9036 /* gen_helper_dmfc0_performance7(arg); */
9037 register_name
= "Performance7";
9038 goto cp0_unimplemented
;
9040 goto cp0_unimplemented
;
9043 case CP0_REGISTER_26
:
9045 case CP0_REG26__ERRCTL
:
9046 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_ErrCtl
));
9047 register_name
= "ErrCtl";
9050 goto cp0_unimplemented
;
9053 case CP0_REGISTER_27
:
9056 case CP0_REG27__CACHERR
:
9057 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
9058 register_name
= "CacheErr";
9061 goto cp0_unimplemented
;
9064 case CP0_REGISTER_28
:
9066 case CP0_REG28__TAGLO
:
9067 case CP0_REG28__TAGLO1
:
9068 case CP0_REG28__TAGLO2
:
9069 case CP0_REG28__TAGLO3
:
9070 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_TagLo
));
9071 register_name
= "TagLo";
9073 case CP0_REG28__DATALO
:
9074 case CP0_REG28__DATALO1
:
9075 case CP0_REG28__DATALO2
:
9076 case CP0_REG28__DATALO3
:
9077 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataLo
));
9078 register_name
= "DataLo";
9081 goto cp0_unimplemented
;
9084 case CP0_REGISTER_29
:
9086 case CP0_REG29__TAGHI
:
9087 case CP0_REG29__TAGHI1
:
9088 case CP0_REG29__TAGHI2
:
9089 case CP0_REG29__TAGHI3
:
9090 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_TagHi
));
9091 register_name
= "TagHi";
9093 case CP0_REG29__DATAHI
:
9094 case CP0_REG29__DATAHI1
:
9095 case CP0_REG29__DATAHI2
:
9096 case CP0_REG29__DATAHI3
:
9097 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataHi
));
9098 register_name
= "DataHi";
9101 goto cp0_unimplemented
;
9104 case CP0_REGISTER_30
:
9106 case CP0_REG30__ERROREPC
:
9107 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
9108 register_name
= "ErrorEPC";
9111 goto cp0_unimplemented
;
9114 case CP0_REGISTER_31
:
9116 case CP0_REG31__DESAVE
:
9118 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
9119 register_name
= "DESAVE";
9121 case CP0_REG31__KSCRATCH1
:
9122 case CP0_REG31__KSCRATCH2
:
9123 case CP0_REG31__KSCRATCH3
:
9124 case CP0_REG31__KSCRATCH4
:
9125 case CP0_REG31__KSCRATCH5
:
9126 case CP0_REG31__KSCRATCH6
:
9127 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
9128 tcg_gen_ld_tl(arg
, cpu_env
,
9129 offsetof(CPUMIPSState
, CP0_KScratch
[sel
- 2]));
9130 register_name
= "KScratch";
9133 goto cp0_unimplemented
;
9137 goto cp0_unimplemented
;
9139 trace_mips_translate_c0("dmfc0", register_name
, reg
, sel
);
9143 qemu_log_mask(LOG_UNIMP
, "dmfc0 %s (reg %d sel %d)\n",
9144 register_name
, reg
, sel
);
9145 gen_mfc0_unimplemented(ctx
, arg
);
9148 static void gen_dmtc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
9150 const char *register_name
= "invalid";
9153 check_insn(ctx
, ISA_MIPS64
);
9156 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
9161 case CP0_REGISTER_00
:
9163 case CP0_REG00__INDEX
:
9164 gen_helper_mtc0_index(cpu_env
, arg
);
9165 register_name
= "Index";
9167 case CP0_REG00__MVPCONTROL
:
9168 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9169 gen_helper_mtc0_mvpcontrol(cpu_env
, arg
);
9170 register_name
= "MVPControl";
9172 case CP0_REG00__MVPCONF0
:
9173 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9175 register_name
= "MVPConf0";
9177 case CP0_REG00__MVPCONF1
:
9178 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9180 register_name
= "MVPConf1";
9182 case CP0_REG00__VPCONTROL
:
9185 register_name
= "VPControl";
9188 goto cp0_unimplemented
;
9191 case CP0_REGISTER_01
:
9193 case CP0_REG01__RANDOM
:
9195 register_name
= "Random";
9197 case CP0_REG01__VPECONTROL
:
9198 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9199 gen_helper_mtc0_vpecontrol(cpu_env
, arg
);
9200 register_name
= "VPEControl";
9202 case CP0_REG01__VPECONF0
:
9203 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9204 gen_helper_mtc0_vpeconf0(cpu_env
, arg
);
9205 register_name
= "VPEConf0";
9207 case CP0_REG01__VPECONF1
:
9208 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9209 gen_helper_mtc0_vpeconf1(cpu_env
, arg
);
9210 register_name
= "VPEConf1";
9212 case CP0_REG01__YQMASK
:
9213 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9214 gen_helper_mtc0_yqmask(cpu_env
, arg
);
9215 register_name
= "YQMask";
9217 case CP0_REG01__VPESCHEDULE
:
9218 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9219 tcg_gen_st_tl(arg
, cpu_env
,
9220 offsetof(CPUMIPSState
, CP0_VPESchedule
));
9221 register_name
= "VPESchedule";
9223 case CP0_REG01__VPESCHEFBACK
:
9224 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9225 tcg_gen_st_tl(arg
, cpu_env
,
9226 offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
9227 register_name
= "VPEScheFBack";
9229 case CP0_REG01__VPEOPT
:
9230 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9231 gen_helper_mtc0_vpeopt(cpu_env
, arg
);
9232 register_name
= "VPEOpt";
9235 goto cp0_unimplemented
;
9238 case CP0_REGISTER_02
:
9240 case CP0_REG02__ENTRYLO0
:
9241 gen_helper_dmtc0_entrylo0(cpu_env
, arg
);
9242 register_name
= "EntryLo0";
9244 case CP0_REG02__TCSTATUS
:
9245 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9246 gen_helper_mtc0_tcstatus(cpu_env
, arg
);
9247 register_name
= "TCStatus";
9249 case CP0_REG02__TCBIND
:
9250 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9251 gen_helper_mtc0_tcbind(cpu_env
, arg
);
9252 register_name
= "TCBind";
9254 case CP0_REG02__TCRESTART
:
9255 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9256 gen_helper_mtc0_tcrestart(cpu_env
, arg
);
9257 register_name
= "TCRestart";
9259 case CP0_REG02__TCHALT
:
9260 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9261 gen_helper_mtc0_tchalt(cpu_env
, arg
);
9262 register_name
= "TCHalt";
9264 case CP0_REG02__TCCONTEXT
:
9265 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9266 gen_helper_mtc0_tccontext(cpu_env
, arg
);
9267 register_name
= "TCContext";
9269 case CP0_REG02__TCSCHEDULE
:
9270 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9271 gen_helper_mtc0_tcschedule(cpu_env
, arg
);
9272 register_name
= "TCSchedule";
9274 case CP0_REG02__TCSCHEFBACK
:
9275 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
9276 gen_helper_mtc0_tcschefback(cpu_env
, arg
);
9277 register_name
= "TCScheFBack";
9280 goto cp0_unimplemented
;
9283 case CP0_REGISTER_03
:
9285 case CP0_REG03__ENTRYLO1
:
9286 gen_helper_dmtc0_entrylo1(cpu_env
, arg
);
9287 register_name
= "EntryLo1";
9289 case CP0_REG03__GLOBALNUM
:
9292 register_name
= "GlobalNumber";
9295 goto cp0_unimplemented
;
9298 case CP0_REGISTER_04
:
9300 case CP0_REG04__CONTEXT
:
9301 gen_helper_mtc0_context(cpu_env
, arg
);
9302 register_name
= "Context";
9304 case CP0_REG04__CONTEXTCONFIG
:
9306 /* gen_helper_dmtc0_contextconfig(arg); */
9307 register_name
= "ContextConfig";
9308 goto cp0_unimplemented
;
9309 case CP0_REG04__USERLOCAL
:
9310 CP0_CHECK(ctx
->ulri
);
9311 tcg_gen_st_tl(arg
, cpu_env
,
9312 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
9313 register_name
= "UserLocal";
9316 goto cp0_unimplemented
;
9319 case CP0_REGISTER_05
:
9321 case CP0_REG05__PAGEMASK
:
9322 gen_helper_mtc0_pagemask(cpu_env
, arg
);
9323 register_name
= "PageMask";
9325 case CP0_REG05__PAGEGRAIN
:
9326 check_insn(ctx
, ISA_MIPS32R2
);
9327 gen_helper_mtc0_pagegrain(cpu_env
, arg
);
9328 register_name
= "PageGrain";
9330 case CP0_REG05__SEGCTL0
:
9332 gen_helper_mtc0_segctl0(cpu_env
, arg
);
9333 register_name
= "SegCtl0";
9335 case CP0_REG05__SEGCTL1
:
9337 gen_helper_mtc0_segctl1(cpu_env
, arg
);
9338 register_name
= "SegCtl1";
9340 case CP0_REG05__SEGCTL2
:
9342 gen_helper_mtc0_segctl2(cpu_env
, arg
);
9343 register_name
= "SegCtl2";
9345 case CP0_REG05__PWBASE
:
9347 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_PWBase
));
9348 register_name
= "PWBase";
9350 case CP0_REG05__PWFIELD
:
9352 gen_helper_mtc0_pwfield(cpu_env
, arg
);
9353 register_name
= "PWField";
9355 case CP0_REG05__PWSIZE
:
9357 gen_helper_mtc0_pwsize(cpu_env
, arg
);
9358 register_name
= "PWSize";
9361 goto cp0_unimplemented
;
9364 case CP0_REGISTER_06
:
9366 case CP0_REG06__WIRED
:
9367 gen_helper_mtc0_wired(cpu_env
, arg
);
9368 register_name
= "Wired";
9370 case CP0_REG06__SRSCONF0
:
9371 check_insn(ctx
, ISA_MIPS32R2
);
9372 gen_helper_mtc0_srsconf0(cpu_env
, arg
);
9373 register_name
= "SRSConf0";
9375 case CP0_REG06__SRSCONF1
:
9376 check_insn(ctx
, ISA_MIPS32R2
);
9377 gen_helper_mtc0_srsconf1(cpu_env
, arg
);
9378 register_name
= "SRSConf1";
9380 case CP0_REG06__SRSCONF2
:
9381 check_insn(ctx
, ISA_MIPS32R2
);
9382 gen_helper_mtc0_srsconf2(cpu_env
, arg
);
9383 register_name
= "SRSConf2";
9385 case CP0_REG06__SRSCONF3
:
9386 check_insn(ctx
, ISA_MIPS32R2
);
9387 gen_helper_mtc0_srsconf3(cpu_env
, arg
);
9388 register_name
= "SRSConf3";
9390 case CP0_REG06__SRSCONF4
:
9391 check_insn(ctx
, ISA_MIPS32R2
);
9392 gen_helper_mtc0_srsconf4(cpu_env
, arg
);
9393 register_name
= "SRSConf4";
9395 case CP0_REG06__PWCTL
:
9397 gen_helper_mtc0_pwctl(cpu_env
, arg
);
9398 register_name
= "PWCtl";
9401 goto cp0_unimplemented
;
9404 case CP0_REGISTER_07
:
9406 case CP0_REG07__HWRENA
:
9407 check_insn(ctx
, ISA_MIPS32R2
);
9408 gen_helper_mtc0_hwrena(cpu_env
, arg
);
9409 ctx
->base
.is_jmp
= DISAS_STOP
;
9410 register_name
= "HWREna";
9413 goto cp0_unimplemented
;
9416 case CP0_REGISTER_08
:
9418 case CP0_REG08__BADVADDR
:
9420 register_name
= "BadVAddr";
9422 case CP0_REG08__BADINSTR
:
9424 register_name
= "BadInstr";
9426 case CP0_REG08__BADINSTRP
:
9428 register_name
= "BadInstrP";
9430 case CP0_REG08__BADINSTRX
:
9432 register_name
= "BadInstrX";
9435 goto cp0_unimplemented
;
9438 case CP0_REGISTER_09
:
9440 case CP0_REG09__COUNT
:
9441 gen_helper_mtc0_count(cpu_env
, arg
);
9442 register_name
= "Count";
9444 case CP0_REG09__SAARI
:
9445 CP0_CHECK(ctx
->saar
);
9446 gen_helper_mtc0_saari(cpu_env
, arg
);
9447 register_name
= "SAARI";
9449 case CP0_REG09__SAAR
:
9450 CP0_CHECK(ctx
->saar
);
9451 gen_helper_mtc0_saar(cpu_env
, arg
);
9452 register_name
= "SAAR";
9455 goto cp0_unimplemented
;
9457 /* Stop translation as we may have switched the execution mode */
9458 ctx
->base
.is_jmp
= DISAS_STOP
;
9460 case CP0_REGISTER_10
:
9462 case CP0_REG10__ENTRYHI
:
9463 gen_helper_mtc0_entryhi(cpu_env
, arg
);
9464 register_name
= "EntryHi";
9467 goto cp0_unimplemented
;
9470 case CP0_REGISTER_11
:
9472 case CP0_REG11__COMPARE
:
9473 gen_helper_mtc0_compare(cpu_env
, arg
);
9474 register_name
= "Compare";
9476 /* 6,7 are implementation dependent */
9478 goto cp0_unimplemented
;
9480 /* Stop translation as we may have switched the execution mode */
9481 ctx
->base
.is_jmp
= DISAS_STOP
;
9483 case CP0_REGISTER_12
:
9485 case CP0_REG12__STATUS
:
9486 save_cpu_state(ctx
, 1);
9487 gen_helper_mtc0_status(cpu_env
, arg
);
9488 /* DISAS_STOP isn't good enough here, hflags may have changed. */
9489 gen_save_pc(ctx
->base
.pc_next
+ 4);
9490 ctx
->base
.is_jmp
= DISAS_EXIT
;
9491 register_name
= "Status";
9493 case CP0_REG12__INTCTL
:
9494 check_insn(ctx
, ISA_MIPS32R2
);
9495 gen_helper_mtc0_intctl(cpu_env
, arg
);
9496 /* Stop translation as we may have switched the execution mode */
9497 ctx
->base
.is_jmp
= DISAS_STOP
;
9498 register_name
= "IntCtl";
9500 case CP0_REG12__SRSCTL
:
9501 check_insn(ctx
, ISA_MIPS32R2
);
9502 gen_helper_mtc0_srsctl(cpu_env
, arg
);
9503 /* Stop translation as we may have switched the execution mode */
9504 ctx
->base
.is_jmp
= DISAS_STOP
;
9505 register_name
= "SRSCtl";
9507 case CP0_REG12__SRSMAP
:
9508 check_insn(ctx
, ISA_MIPS32R2
);
9509 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
9510 /* Stop translation as we may have switched the execution mode */
9511 ctx
->base
.is_jmp
= DISAS_STOP
;
9512 register_name
= "SRSMap";
9515 goto cp0_unimplemented
;
9518 case CP0_REGISTER_13
:
9520 case CP0_REG13__CAUSE
:
9521 save_cpu_state(ctx
, 1);
9522 gen_helper_mtc0_cause(cpu_env
, arg
);
9524 * Stop translation as we may have triggered an interrupt.
9525 * DISAS_STOP isn't sufficient, we need to ensure we break out of
9526 * translated code to check for pending interrupts.
9528 gen_save_pc(ctx
->base
.pc_next
+ 4);
9529 ctx
->base
.is_jmp
= DISAS_EXIT
;
9530 register_name
= "Cause";
9533 goto cp0_unimplemented
;
9536 case CP0_REGISTER_14
:
9538 case CP0_REG14__EPC
:
9539 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
9540 register_name
= "EPC";
9543 goto cp0_unimplemented
;
9546 case CP0_REGISTER_15
:
9548 case CP0_REG15__PRID
:
9550 register_name
= "PRid";
9552 case CP0_REG15__EBASE
:
9553 check_insn(ctx
, ISA_MIPS32R2
);
9554 gen_helper_mtc0_ebase(cpu_env
, arg
);
9555 register_name
= "EBase";
9558 goto cp0_unimplemented
;
9561 case CP0_REGISTER_16
:
9563 case CP0_REG16__CONFIG
:
9564 gen_helper_mtc0_config0(cpu_env
, arg
);
9565 register_name
= "Config";
9566 /* Stop translation as we may have switched the execution mode */
9567 ctx
->base
.is_jmp
= DISAS_STOP
;
9569 case CP0_REG16__CONFIG1
:
9570 /* ignored, read only */
9571 register_name
= "Config1";
9573 case CP0_REG16__CONFIG2
:
9574 gen_helper_mtc0_config2(cpu_env
, arg
);
9575 register_name
= "Config2";
9576 /* Stop translation as we may have switched the execution mode */
9577 ctx
->base
.is_jmp
= DISAS_STOP
;
9579 case CP0_REG16__CONFIG3
:
9580 gen_helper_mtc0_config3(cpu_env
, arg
);
9581 register_name
= "Config3";
9582 /* Stop translation as we may have switched the execution mode */
9583 ctx
->base
.is_jmp
= DISAS_STOP
;
9585 case CP0_REG16__CONFIG4
:
9586 /* currently ignored */
9587 register_name
= "Config4";
9589 case CP0_REG16__CONFIG5
:
9590 gen_helper_mtc0_config5(cpu_env
, arg
);
9591 register_name
= "Config5";
9592 /* Stop translation as we may have switched the execution mode */
9593 ctx
->base
.is_jmp
= DISAS_STOP
;
9595 /* 6,7 are implementation dependent */
9597 register_name
= "Invalid config selector";
9598 goto cp0_unimplemented
;
9601 case CP0_REGISTER_17
:
9603 case CP0_REG17__LLADDR
:
9604 gen_helper_mtc0_lladdr(cpu_env
, arg
);
9605 register_name
= "LLAddr";
9607 case CP0_REG17__MAAR
:
9608 CP0_CHECK(ctx
->mrp
);
9609 gen_helper_mtc0_maar(cpu_env
, arg
);
9610 register_name
= "MAAR";
9612 case CP0_REG17__MAARI
:
9613 CP0_CHECK(ctx
->mrp
);
9614 gen_helper_mtc0_maari(cpu_env
, arg
);
9615 register_name
= "MAARI";
9618 goto cp0_unimplemented
;
9621 case CP0_REGISTER_18
:
9623 case CP0_REG18__WATCHLO0
:
9624 case CP0_REG18__WATCHLO1
:
9625 case CP0_REG18__WATCHLO2
:
9626 case CP0_REG18__WATCHLO3
:
9627 case CP0_REG18__WATCHLO4
:
9628 case CP0_REG18__WATCHLO5
:
9629 case CP0_REG18__WATCHLO6
:
9630 case CP0_REG18__WATCHLO7
:
9631 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
9632 gen_helper_0e1i(mtc0_watchlo
, arg
, sel
);
9633 register_name
= "WatchLo";
9636 goto cp0_unimplemented
;
9639 case CP0_REGISTER_19
:
9641 case CP0_REG19__WATCHHI0
:
9642 case CP0_REG19__WATCHHI1
:
9643 case CP0_REG19__WATCHHI2
:
9644 case CP0_REG19__WATCHHI3
:
9645 case CP0_REG19__WATCHHI4
:
9646 case CP0_REG19__WATCHHI5
:
9647 case CP0_REG19__WATCHHI6
:
9648 case CP0_REG19__WATCHHI7
:
9649 CP0_CHECK(ctx
->CP0_Config1
& (1 << CP0C1_WR
));
9650 gen_helper_0e1i(mtc0_watchhi
, arg
, sel
);
9651 register_name
= "WatchHi";
9654 goto cp0_unimplemented
;
9657 case CP0_REGISTER_20
:
9659 case CP0_REG20__XCONTEXT
:
9660 check_insn(ctx
, ISA_MIPS3
);
9661 gen_helper_mtc0_xcontext(cpu_env
, arg
);
9662 register_name
= "XContext";
9665 goto cp0_unimplemented
;
9668 case CP0_REGISTER_21
:
9669 /* Officially reserved, but sel 0 is used for R1x000 framemask */
9670 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
9673 gen_helper_mtc0_framemask(cpu_env
, arg
);
9674 register_name
= "Framemask";
9677 goto cp0_unimplemented
;
9680 case CP0_REGISTER_22
:
9682 register_name
= "Diagnostic"; /* implementation dependent */
9684 case CP0_REGISTER_23
:
9686 case CP0_REG23__DEBUG
:
9687 gen_helper_mtc0_debug(cpu_env
, arg
); /* EJTAG support */
9688 /* DISAS_STOP isn't good enough here, hflags may have changed. */
9689 gen_save_pc(ctx
->base
.pc_next
+ 4);
9690 ctx
->base
.is_jmp
= DISAS_EXIT
;
9691 register_name
= "Debug";
9693 case CP0_REG23__TRACECONTROL
:
9694 /* PDtrace support */
9695 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
9696 /* Stop translation as we may have switched the execution mode */
9697 ctx
->base
.is_jmp
= DISAS_STOP
;
9698 register_name
= "TraceControl";
9699 goto cp0_unimplemented
;
9700 case CP0_REG23__TRACECONTROL2
:
9701 /* PDtrace support */
9702 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
9703 /* Stop translation as we may have switched the execution mode */
9704 ctx
->base
.is_jmp
= DISAS_STOP
;
9705 register_name
= "TraceControl2";
9706 goto cp0_unimplemented
;
9707 case CP0_REG23__USERTRACEDATA1
:
9708 /* PDtrace support */
9709 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
9710 /* Stop translation as we may have switched the execution mode */
9711 ctx
->base
.is_jmp
= DISAS_STOP
;
9712 register_name
= "UserTraceData1";
9713 goto cp0_unimplemented
;
9714 case CP0_REG23__TRACEIBPC
:
9715 /* PDtrace support */
9716 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
9717 /* Stop translation as we may have switched the execution mode */
9718 ctx
->base
.is_jmp
= DISAS_STOP
;
9719 register_name
= "TraceIBPC";
9720 goto cp0_unimplemented
;
9721 case CP0_REG23__TRACEDBPC
:
9722 /* PDtrace support */
9723 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
9724 /* Stop translation as we may have switched the execution mode */
9725 ctx
->base
.is_jmp
= DISAS_STOP
;
9726 register_name
= "TraceDBPC";
9727 goto cp0_unimplemented
;
9729 goto cp0_unimplemented
;
9732 case CP0_REGISTER_24
:
9734 case CP0_REG24__DEPC
:
9736 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
9737 register_name
= "DEPC";
9740 goto cp0_unimplemented
;
9743 case CP0_REGISTER_25
:
9745 case CP0_REG25__PERFCTL0
:
9746 gen_helper_mtc0_performance0(cpu_env
, arg
);
9747 register_name
= "Performance0";
9749 case CP0_REG25__PERFCNT0
:
9750 /* gen_helper_mtc0_performance1(cpu_env, arg); */
9751 register_name
= "Performance1";
9752 goto cp0_unimplemented
;
9753 case CP0_REG25__PERFCTL1
:
9754 /* gen_helper_mtc0_performance2(cpu_env, arg); */
9755 register_name
= "Performance2";
9756 goto cp0_unimplemented
;
9757 case CP0_REG25__PERFCNT1
:
9758 /* gen_helper_mtc0_performance3(cpu_env, arg); */
9759 register_name
= "Performance3";
9760 goto cp0_unimplemented
;
9761 case CP0_REG25__PERFCTL2
:
9762 /* gen_helper_mtc0_performance4(cpu_env, arg); */
9763 register_name
= "Performance4";
9764 goto cp0_unimplemented
;
9765 case CP0_REG25__PERFCNT2
:
9766 /* gen_helper_mtc0_performance5(cpu_env, arg); */
9767 register_name
= "Performance5";
9768 goto cp0_unimplemented
;
9769 case CP0_REG25__PERFCTL3
:
9770 /* gen_helper_mtc0_performance6(cpu_env, arg); */
9771 register_name
= "Performance6";
9772 goto cp0_unimplemented
;
9773 case CP0_REG25__PERFCNT3
:
9774 /* gen_helper_mtc0_performance7(cpu_env, arg); */
9775 register_name
= "Performance7";
9776 goto cp0_unimplemented
;
9778 goto cp0_unimplemented
;
9781 case CP0_REGISTER_26
:
9783 case CP0_REG26__ERRCTL
:
9784 gen_helper_mtc0_errctl(cpu_env
, arg
);
9785 ctx
->base
.is_jmp
= DISAS_STOP
;
9786 register_name
= "ErrCtl";
9789 goto cp0_unimplemented
;
9792 case CP0_REGISTER_27
:
9794 case CP0_REG27__CACHERR
:
9796 register_name
= "CacheErr";
9799 goto cp0_unimplemented
;
9802 case CP0_REGISTER_28
:
9804 case CP0_REG28__TAGLO
:
9805 case CP0_REG28__TAGLO1
:
9806 case CP0_REG28__TAGLO2
:
9807 case CP0_REG28__TAGLO3
:
9808 gen_helper_mtc0_taglo(cpu_env
, arg
);
9809 register_name
= "TagLo";
9811 case CP0_REG28__DATALO
:
9812 case CP0_REG28__DATALO1
:
9813 case CP0_REG28__DATALO2
:
9814 case CP0_REG28__DATALO3
:
9815 gen_helper_mtc0_datalo(cpu_env
, arg
);
9816 register_name
= "DataLo";
9819 goto cp0_unimplemented
;
9822 case CP0_REGISTER_29
:
9824 case CP0_REG29__TAGHI
:
9825 case CP0_REG29__TAGHI1
:
9826 case CP0_REG29__TAGHI2
:
9827 case CP0_REG29__TAGHI3
:
9828 gen_helper_mtc0_taghi(cpu_env
, arg
);
9829 register_name
= "TagHi";
9831 case CP0_REG29__DATAHI
:
9832 case CP0_REG29__DATAHI1
:
9833 case CP0_REG29__DATAHI2
:
9834 case CP0_REG29__DATAHI3
:
9835 gen_helper_mtc0_datahi(cpu_env
, arg
);
9836 register_name
= "DataHi";
9839 register_name
= "invalid sel";
9840 goto cp0_unimplemented
;
9843 case CP0_REGISTER_30
:
9845 case CP0_REG30__ERROREPC
:
9846 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
9847 register_name
= "ErrorEPC";
9850 goto cp0_unimplemented
;
9853 case CP0_REGISTER_31
:
9855 case CP0_REG31__DESAVE
:
9857 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
9858 register_name
= "DESAVE";
9860 case CP0_REG31__KSCRATCH1
:
9861 case CP0_REG31__KSCRATCH2
:
9862 case CP0_REG31__KSCRATCH3
:
9863 case CP0_REG31__KSCRATCH4
:
9864 case CP0_REG31__KSCRATCH5
:
9865 case CP0_REG31__KSCRATCH6
:
9866 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
9867 tcg_gen_st_tl(arg
, cpu_env
,
9868 offsetof(CPUMIPSState
, CP0_KScratch
[sel
- 2]));
9869 register_name
= "KScratch";
9872 goto cp0_unimplemented
;
9876 goto cp0_unimplemented
;
9878 trace_mips_translate_c0("dmtc0", register_name
, reg
, sel
);
9880 /* For simplicity assume that all writes can cause interrupts. */
9881 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
9883 * DISAS_STOP isn't sufficient, we need to ensure we break out of
9884 * translated code to check for pending interrupts.
9886 gen_save_pc(ctx
->base
.pc_next
+ 4);
9887 ctx
->base
.is_jmp
= DISAS_EXIT
;
9892 qemu_log_mask(LOG_UNIMP
, "dmtc0 %s (reg %d sel %d)\n",
9893 register_name
, reg
, sel
);
9895 #endif /* TARGET_MIPS64 */
9897 static void gen_mftr(CPUMIPSState
*env
, DisasContext
*ctx
, int rt
, int rd
,
9898 int u
, int sel
, int h
)
9900 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
9901 TCGv t0
= tcg_temp_local_new();
9903 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
9904 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
9905 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)))) {
9906 tcg_gen_movi_tl(t0
, -1);
9907 } else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
9908 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
))) {
9909 tcg_gen_movi_tl(t0
, -1);
9910 } else if (u
== 0) {
9915 gen_helper_mftc0_vpecontrol(t0
, cpu_env
);
9918 gen_helper_mftc0_vpeconf0(t0
, cpu_env
);
9928 gen_helper_mftc0_tcstatus(t0
, cpu_env
);
9931 gen_helper_mftc0_tcbind(t0
, cpu_env
);
9934 gen_helper_mftc0_tcrestart(t0
, cpu_env
);
9937 gen_helper_mftc0_tchalt(t0
, cpu_env
);
9940 gen_helper_mftc0_tccontext(t0
, cpu_env
);
9943 gen_helper_mftc0_tcschedule(t0
, cpu_env
);
9946 gen_helper_mftc0_tcschefback(t0
, cpu_env
);
9949 gen_mfc0(ctx
, t0
, rt
, sel
);
9956 gen_helper_mftc0_entryhi(t0
, cpu_env
);
9959 gen_mfc0(ctx
, t0
, rt
, sel
);
9966 gen_helper_mftc0_status(t0
, cpu_env
);
9969 gen_mfc0(ctx
, t0
, rt
, sel
);
9976 gen_helper_mftc0_cause(t0
, cpu_env
);
9986 gen_helper_mftc0_epc(t0
, cpu_env
);
9996 gen_helper_mftc0_ebase(t0
, cpu_env
);
10013 gen_helper_mftc0_configx(t0
, cpu_env
, tcg_const_tl(sel
));
10023 gen_helper_mftc0_debug(t0
, cpu_env
);
10026 gen_mfc0(ctx
, t0
, rt
, sel
);
10031 gen_mfc0(ctx
, t0
, rt
, sel
);
10035 /* GPR registers. */
10037 gen_helper_1e0i(mftgpr
, t0
, rt
);
10039 /* Auxiliary CPU registers */
10043 gen_helper_1e0i(mftlo
, t0
, 0);
10046 gen_helper_1e0i(mfthi
, t0
, 0);
10049 gen_helper_1e0i(mftacx
, t0
, 0);
10052 gen_helper_1e0i(mftlo
, t0
, 1);
10055 gen_helper_1e0i(mfthi
, t0
, 1);
10058 gen_helper_1e0i(mftacx
, t0
, 1);
10061 gen_helper_1e0i(mftlo
, t0
, 2);
10064 gen_helper_1e0i(mfthi
, t0
, 2);
10067 gen_helper_1e0i(mftacx
, t0
, 2);
10070 gen_helper_1e0i(mftlo
, t0
, 3);
10073 gen_helper_1e0i(mfthi
, t0
, 3);
10076 gen_helper_1e0i(mftacx
, t0
, 3);
10079 gen_helper_mftdsp(t0
, cpu_env
);
10085 /* Floating point (COP1). */
10087 /* XXX: For now we support only a single FPU context. */
10089 TCGv_i32 fp0
= tcg_temp_new_i32();
10091 gen_load_fpr32(ctx
, fp0
, rt
);
10092 tcg_gen_ext_i32_tl(t0
, fp0
);
10093 tcg_temp_free_i32(fp0
);
10095 TCGv_i32 fp0
= tcg_temp_new_i32();
10097 gen_load_fpr32h(ctx
, fp0
, rt
);
10098 tcg_gen_ext_i32_tl(t0
, fp0
);
10099 tcg_temp_free_i32(fp0
);
10103 /* XXX: For now we support only a single FPU context. */
10104 gen_helper_1e0i(cfc1
, t0
, rt
);
10106 /* COP2: Not implemented. */
10114 trace_mips_translate_tr("mftr", rt
, u
, sel
, h
);
10115 gen_store_gpr(t0
, rd
);
10121 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
10122 generate_exception_end(ctx
, EXCP_RI
);
10125 static void gen_mttr(CPUMIPSState
*env
, DisasContext
*ctx
, int rd
, int rt
,
10126 int u
, int sel
, int h
)
10128 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
10129 TCGv t0
= tcg_temp_local_new();
10131 gen_load_gpr(t0
, rt
);
10132 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
10133 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
10134 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)))) {
10137 } else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
10138 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
))) {
10141 } else if (u
== 0) {
10146 gen_helper_mttc0_vpecontrol(cpu_env
, t0
);
10149 gen_helper_mttc0_vpeconf0(cpu_env
, t0
);
10159 gen_helper_mttc0_tcstatus(cpu_env
, t0
);
10162 gen_helper_mttc0_tcbind(cpu_env
, t0
);
10165 gen_helper_mttc0_tcrestart(cpu_env
, t0
);
10168 gen_helper_mttc0_tchalt(cpu_env
, t0
);
10171 gen_helper_mttc0_tccontext(cpu_env
, t0
);
10174 gen_helper_mttc0_tcschedule(cpu_env
, t0
);
10177 gen_helper_mttc0_tcschefback(cpu_env
, t0
);
10180 gen_mtc0(ctx
, t0
, rd
, sel
);
10187 gen_helper_mttc0_entryhi(cpu_env
, t0
);
10190 gen_mtc0(ctx
, t0
, rd
, sel
);
10197 gen_helper_mttc0_status(cpu_env
, t0
);
10200 gen_mtc0(ctx
, t0
, rd
, sel
);
10207 gen_helper_mttc0_cause(cpu_env
, t0
);
10217 gen_helper_mttc0_ebase(cpu_env
, t0
);
10227 gen_helper_mttc0_debug(cpu_env
, t0
);
10230 gen_mtc0(ctx
, t0
, rd
, sel
);
10235 gen_mtc0(ctx
, t0
, rd
, sel
);
10239 /* GPR registers. */
10241 gen_helper_0e1i(mttgpr
, t0
, rd
);
10243 /* Auxiliary CPU registers */
10247 gen_helper_0e1i(mttlo
, t0
, 0);
10250 gen_helper_0e1i(mtthi
, t0
, 0);
10253 gen_helper_0e1i(mttacx
, t0
, 0);
10256 gen_helper_0e1i(mttlo
, t0
, 1);
10259 gen_helper_0e1i(mtthi
, t0
, 1);
10262 gen_helper_0e1i(mttacx
, t0
, 1);
10265 gen_helper_0e1i(mttlo
, t0
, 2);
10268 gen_helper_0e1i(mtthi
, t0
, 2);
10271 gen_helper_0e1i(mttacx
, t0
, 2);
10274 gen_helper_0e1i(mttlo
, t0
, 3);
10277 gen_helper_0e1i(mtthi
, t0
, 3);
10280 gen_helper_0e1i(mttacx
, t0
, 3);
10283 gen_helper_mttdsp(cpu_env
, t0
);
10289 /* Floating point (COP1). */
10291 /* XXX: For now we support only a single FPU context. */
10293 TCGv_i32 fp0
= tcg_temp_new_i32();
10295 tcg_gen_trunc_tl_i32(fp0
, t0
);
10296 gen_store_fpr32(ctx
, fp0
, rd
);
10297 tcg_temp_free_i32(fp0
);
10299 TCGv_i32 fp0
= tcg_temp_new_i32();
10301 tcg_gen_trunc_tl_i32(fp0
, t0
);
10302 gen_store_fpr32h(ctx
, fp0
, rd
);
10303 tcg_temp_free_i32(fp0
);
10307 /* XXX: For now we support only a single FPU context. */
10309 TCGv_i32 fs_tmp
= tcg_const_i32(rd
);
10311 gen_helper_0e2i(ctc1
, t0
, fs_tmp
, rt
);
10312 tcg_temp_free_i32(fs_tmp
);
10314 /* Stop translation as we may have changed hflags */
10315 ctx
->base
.is_jmp
= DISAS_STOP
;
10317 /* COP2: Not implemented. */
10325 trace_mips_translate_tr("mttr", rd
, u
, sel
, h
);
10331 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
10332 generate_exception_end(ctx
, EXCP_RI
);
10335 static void gen_cp0(CPUMIPSState
*env
, DisasContext
*ctx
, uint32_t opc
,
10338 const char *opn
= "ldst";
10340 check_cp0_enabled(ctx
);
10344 /* Treat as NOP. */
10347 gen_mfc0(ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
10352 TCGv t0
= tcg_temp_new();
10354 gen_load_gpr(t0
, rt
);
10355 gen_mtc0(ctx
, t0
, rd
, ctx
->opcode
& 0x7);
10360 #if defined(TARGET_MIPS64)
10362 check_insn(ctx
, ISA_MIPS3
);
10364 /* Treat as NOP. */
10367 gen_dmfc0(ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
10371 check_insn(ctx
, ISA_MIPS3
);
10373 TCGv t0
= tcg_temp_new();
10375 gen_load_gpr(t0
, rt
);
10376 gen_dmtc0(ctx
, t0
, rd
, ctx
->opcode
& 0x7);
10385 /* Treat as NOP. */
10388 gen_mfhc0(ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
10394 TCGv t0
= tcg_temp_new();
10395 gen_load_gpr(t0
, rt
);
10396 gen_mthc0(ctx
, t0
, rd
, ctx
->opcode
& 0x7);
10402 check_cp0_enabled(ctx
);
10404 /* Treat as NOP. */
10407 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
10408 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
10412 check_cp0_enabled(ctx
);
10413 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
10414 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
10419 if (!env
->tlb
->helper_tlbwi
) {
10422 gen_helper_tlbwi(cpu_env
);
10426 if (ctx
->ie
>= 2) {
10427 if (!env
->tlb
->helper_tlbinv
) {
10430 gen_helper_tlbinv(cpu_env
);
10431 } /* treat as nop if TLBINV not supported */
10435 if (ctx
->ie
>= 2) {
10436 if (!env
->tlb
->helper_tlbinvf
) {
10439 gen_helper_tlbinvf(cpu_env
);
10440 } /* treat as nop if TLBINV not supported */
10444 if (!env
->tlb
->helper_tlbwr
) {
10447 gen_helper_tlbwr(cpu_env
);
10451 if (!env
->tlb
->helper_tlbp
) {
10454 gen_helper_tlbp(cpu_env
);
10458 if (!env
->tlb
->helper_tlbr
) {
10461 gen_helper_tlbr(cpu_env
);
10463 case OPC_ERET
: /* OPC_ERETNC */
10464 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
10465 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
10468 int bit_shift
= (ctx
->hflags
& MIPS_HFLAG_M16
) ? 16 : 6;
10469 if (ctx
->opcode
& (1 << bit_shift
)) {
10472 check_insn(ctx
, ISA_MIPS32R5
);
10473 gen_helper_eretnc(cpu_env
);
10477 check_insn(ctx
, ISA_MIPS2
);
10478 gen_helper_eret(cpu_env
);
10480 ctx
->base
.is_jmp
= DISAS_EXIT
;
10485 check_insn(ctx
, ISA_MIPS32
);
10486 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
10487 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
10490 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
10492 generate_exception_end(ctx
, EXCP_RI
);
10494 gen_helper_deret(cpu_env
);
10495 ctx
->base
.is_jmp
= DISAS_EXIT
;
10500 check_insn(ctx
, ISA_MIPS3
| ISA_MIPS32
);
10501 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
10502 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
10505 /* If we get an exception, we want to restart at next instruction */
10506 ctx
->base
.pc_next
+= 4;
10507 save_cpu_state(ctx
, 1);
10508 ctx
->base
.pc_next
-= 4;
10509 gen_helper_wait(cpu_env
);
10510 ctx
->base
.is_jmp
= DISAS_NORETURN
;
10515 generate_exception_end(ctx
, EXCP_RI
);
10518 (void)opn
; /* avoid a compiler warning */
10520 #endif /* !CONFIG_USER_ONLY */
10522 /* CP1 Branches (before delay slot) */
10523 static void gen_compute_branch1(DisasContext
*ctx
, uint32_t op
,
10524 int32_t cc
, int32_t offset
)
10526 target_ulong btarget
;
10527 TCGv_i32 t0
= tcg_temp_new_i32();
10529 if ((ctx
->insn_flags
& ISA_MIPS32R6
) && (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
10530 generate_exception_end(ctx
, EXCP_RI
);
10535 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
);
10538 btarget
= ctx
->base
.pc_next
+ 4 + offset
;
10542 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10543 tcg_gen_not_i32(t0
, t0
);
10544 tcg_gen_andi_i32(t0
, t0
, 1);
10545 tcg_gen_extu_i32_tl(bcond
, t0
);
10548 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10549 tcg_gen_not_i32(t0
, t0
);
10550 tcg_gen_andi_i32(t0
, t0
, 1);
10551 tcg_gen_extu_i32_tl(bcond
, t0
);
10554 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10555 tcg_gen_andi_i32(t0
, t0
, 1);
10556 tcg_gen_extu_i32_tl(bcond
, t0
);
10559 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10560 tcg_gen_andi_i32(t0
, t0
, 1);
10561 tcg_gen_extu_i32_tl(bcond
, t0
);
10563 ctx
->hflags
|= MIPS_HFLAG_BL
;
10567 TCGv_i32 t1
= tcg_temp_new_i32();
10568 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10569 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 1));
10570 tcg_gen_nand_i32(t0
, t0
, t1
);
10571 tcg_temp_free_i32(t1
);
10572 tcg_gen_andi_i32(t0
, t0
, 1);
10573 tcg_gen_extu_i32_tl(bcond
, t0
);
10578 TCGv_i32 t1
= tcg_temp_new_i32();
10579 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10580 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 1));
10581 tcg_gen_or_i32(t0
, t0
, t1
);
10582 tcg_temp_free_i32(t1
);
10583 tcg_gen_andi_i32(t0
, t0
, 1);
10584 tcg_gen_extu_i32_tl(bcond
, t0
);
10589 TCGv_i32 t1
= tcg_temp_new_i32();
10590 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10591 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 1));
10592 tcg_gen_and_i32(t0
, t0
, t1
);
10593 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 2));
10594 tcg_gen_and_i32(t0
, t0
, t1
);
10595 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 3));
10596 tcg_gen_nand_i32(t0
, t0
, t1
);
10597 tcg_temp_free_i32(t1
);
10598 tcg_gen_andi_i32(t0
, t0
, 1);
10599 tcg_gen_extu_i32_tl(bcond
, t0
);
10604 TCGv_i32 t1
= tcg_temp_new_i32();
10605 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
10606 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 1));
10607 tcg_gen_or_i32(t0
, t0
, t1
);
10608 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 2));
10609 tcg_gen_or_i32(t0
, t0
, t1
);
10610 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+ 3));
10611 tcg_gen_or_i32(t0
, t0
, t1
);
10612 tcg_temp_free_i32(t1
);
10613 tcg_gen_andi_i32(t0
, t0
, 1);
10614 tcg_gen_extu_i32_tl(bcond
, t0
);
10617 ctx
->hflags
|= MIPS_HFLAG_BC
;
10620 MIPS_INVAL("cp1 cond branch");
10621 generate_exception_end(ctx
, EXCP_RI
);
10624 ctx
->btarget
= btarget
;
10625 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
10627 tcg_temp_free_i32(t0
);
10630 /* R6 CP1 Branches */
10631 static void gen_compute_branch1_r6(DisasContext
*ctx
, uint32_t op
,
10632 int32_t ft
, int32_t offset
,
10633 int delayslot_size
)
10635 target_ulong btarget
;
10636 TCGv_i64 t0
= tcg_temp_new_i64();
10638 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
10639 #ifdef MIPS_DEBUG_DISAS
10640 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
10641 "\n", ctx
->base
.pc_next
);
10643 generate_exception_end(ctx
, EXCP_RI
);
10647 gen_load_fpr64(ctx
, t0
, ft
);
10648 tcg_gen_andi_i64(t0
, t0
, 1);
10650 btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
10654 tcg_gen_xori_i64(t0
, t0
, 1);
10655 ctx
->hflags
|= MIPS_HFLAG_BC
;
10658 /* t0 already set */
10659 ctx
->hflags
|= MIPS_HFLAG_BC
;
10662 MIPS_INVAL("cp1 cond branch");
10663 generate_exception_end(ctx
, EXCP_RI
);
10667 tcg_gen_trunc_i64_tl(bcond
, t0
);
10669 ctx
->btarget
= btarget
;
10671 switch (delayslot_size
) {
10673 ctx
->hflags
|= MIPS_HFLAG_BDS16
;
10676 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
10681 tcg_temp_free_i64(t0
);
10684 /* Coprocessor 1 (FPU) */
10686 #define FOP(func, fmt) (((fmt) << 21) | (func))
10689 OPC_ADD_S
= FOP(0, FMT_S
),
10690 OPC_SUB_S
= FOP(1, FMT_S
),
10691 OPC_MUL_S
= FOP(2, FMT_S
),
10692 OPC_DIV_S
= FOP(3, FMT_S
),
10693 OPC_SQRT_S
= FOP(4, FMT_S
),
10694 OPC_ABS_S
= FOP(5, FMT_S
),
10695 OPC_MOV_S
= FOP(6, FMT_S
),
10696 OPC_NEG_S
= FOP(7, FMT_S
),
10697 OPC_ROUND_L_S
= FOP(8, FMT_S
),
10698 OPC_TRUNC_L_S
= FOP(9, FMT_S
),
10699 OPC_CEIL_L_S
= FOP(10, FMT_S
),
10700 OPC_FLOOR_L_S
= FOP(11, FMT_S
),
10701 OPC_ROUND_W_S
= FOP(12, FMT_S
),
10702 OPC_TRUNC_W_S
= FOP(13, FMT_S
),
10703 OPC_CEIL_W_S
= FOP(14, FMT_S
),
10704 OPC_FLOOR_W_S
= FOP(15, FMT_S
),
10705 OPC_SEL_S
= FOP(16, FMT_S
),
10706 OPC_MOVCF_S
= FOP(17, FMT_S
),
10707 OPC_MOVZ_S
= FOP(18, FMT_S
),
10708 OPC_MOVN_S
= FOP(19, FMT_S
),
10709 OPC_SELEQZ_S
= FOP(20, FMT_S
),
10710 OPC_RECIP_S
= FOP(21, FMT_S
),
10711 OPC_RSQRT_S
= FOP(22, FMT_S
),
10712 OPC_SELNEZ_S
= FOP(23, FMT_S
),
10713 OPC_MADDF_S
= FOP(24, FMT_S
),
10714 OPC_MSUBF_S
= FOP(25, FMT_S
),
10715 OPC_RINT_S
= FOP(26, FMT_S
),
10716 OPC_CLASS_S
= FOP(27, FMT_S
),
10717 OPC_MIN_S
= FOP(28, FMT_S
),
10718 OPC_RECIP2_S
= FOP(28, FMT_S
),
10719 OPC_MINA_S
= FOP(29, FMT_S
),
10720 OPC_RECIP1_S
= FOP(29, FMT_S
),
10721 OPC_MAX_S
= FOP(30, FMT_S
),
10722 OPC_RSQRT1_S
= FOP(30, FMT_S
),
10723 OPC_MAXA_S
= FOP(31, FMT_S
),
10724 OPC_RSQRT2_S
= FOP(31, FMT_S
),
10725 OPC_CVT_D_S
= FOP(33, FMT_S
),
10726 OPC_CVT_W_S
= FOP(36, FMT_S
),
10727 OPC_CVT_L_S
= FOP(37, FMT_S
),
10728 OPC_CVT_PS_S
= FOP(38, FMT_S
),
10729 OPC_CMP_F_S
= FOP(48, FMT_S
),
10730 OPC_CMP_UN_S
= FOP(49, FMT_S
),
10731 OPC_CMP_EQ_S
= FOP(50, FMT_S
),
10732 OPC_CMP_UEQ_S
= FOP(51, FMT_S
),
10733 OPC_CMP_OLT_S
= FOP(52, FMT_S
),
10734 OPC_CMP_ULT_S
= FOP(53, FMT_S
),
10735 OPC_CMP_OLE_S
= FOP(54, FMT_S
),
10736 OPC_CMP_ULE_S
= FOP(55, FMT_S
),
10737 OPC_CMP_SF_S
= FOP(56, FMT_S
),
10738 OPC_CMP_NGLE_S
= FOP(57, FMT_S
),
10739 OPC_CMP_SEQ_S
= FOP(58, FMT_S
),
10740 OPC_CMP_NGL_S
= FOP(59, FMT_S
),
10741 OPC_CMP_LT_S
= FOP(60, FMT_S
),
10742 OPC_CMP_NGE_S
= FOP(61, FMT_S
),
10743 OPC_CMP_LE_S
= FOP(62, FMT_S
),
10744 OPC_CMP_NGT_S
= FOP(63, FMT_S
),
10746 OPC_ADD_D
= FOP(0, FMT_D
),
10747 OPC_SUB_D
= FOP(1, FMT_D
),
10748 OPC_MUL_D
= FOP(2, FMT_D
),
10749 OPC_DIV_D
= FOP(3, FMT_D
),
10750 OPC_SQRT_D
= FOP(4, FMT_D
),
10751 OPC_ABS_D
= FOP(5, FMT_D
),
10752 OPC_MOV_D
= FOP(6, FMT_D
),
10753 OPC_NEG_D
= FOP(7, FMT_D
),
10754 OPC_ROUND_L_D
= FOP(8, FMT_D
),
10755 OPC_TRUNC_L_D
= FOP(9, FMT_D
),
10756 OPC_CEIL_L_D
= FOP(10, FMT_D
),
10757 OPC_FLOOR_L_D
= FOP(11, FMT_D
),
10758 OPC_ROUND_W_D
= FOP(12, FMT_D
),
10759 OPC_TRUNC_W_D
= FOP(13, FMT_D
),
10760 OPC_CEIL_W_D
= FOP(14, FMT_D
),
10761 OPC_FLOOR_W_D
= FOP(15, FMT_D
),
10762 OPC_SEL_D
= FOP(16, FMT_D
),
10763 OPC_MOVCF_D
= FOP(17, FMT_D
),
10764 OPC_MOVZ_D
= FOP(18, FMT_D
),
10765 OPC_MOVN_D
= FOP(19, FMT_D
),
10766 OPC_SELEQZ_D
= FOP(20, FMT_D
),
10767 OPC_RECIP_D
= FOP(21, FMT_D
),
10768 OPC_RSQRT_D
= FOP(22, FMT_D
),
10769 OPC_SELNEZ_D
= FOP(23, FMT_D
),
10770 OPC_MADDF_D
= FOP(24, FMT_D
),
10771 OPC_MSUBF_D
= FOP(25, FMT_D
),
10772 OPC_RINT_D
= FOP(26, FMT_D
),
10773 OPC_CLASS_D
= FOP(27, FMT_D
),
10774 OPC_MIN_D
= FOP(28, FMT_D
),
10775 OPC_RECIP2_D
= FOP(28, FMT_D
),
10776 OPC_MINA_D
= FOP(29, FMT_D
),
10777 OPC_RECIP1_D
= FOP(29, FMT_D
),
10778 OPC_MAX_D
= FOP(30, FMT_D
),
10779 OPC_RSQRT1_D
= FOP(30, FMT_D
),
10780 OPC_MAXA_D
= FOP(31, FMT_D
),
10781 OPC_RSQRT2_D
= FOP(31, FMT_D
),
10782 OPC_CVT_S_D
= FOP(32, FMT_D
),
10783 OPC_CVT_W_D
= FOP(36, FMT_D
),
10784 OPC_CVT_L_D
= FOP(37, FMT_D
),
10785 OPC_CMP_F_D
= FOP(48, FMT_D
),
10786 OPC_CMP_UN_D
= FOP(49, FMT_D
),
10787 OPC_CMP_EQ_D
= FOP(50, FMT_D
),
10788 OPC_CMP_UEQ_D
= FOP(51, FMT_D
),
10789 OPC_CMP_OLT_D
= FOP(52, FMT_D
),
10790 OPC_CMP_ULT_D
= FOP(53, FMT_D
),
10791 OPC_CMP_OLE_D
= FOP(54, FMT_D
),
10792 OPC_CMP_ULE_D
= FOP(55, FMT_D
),
10793 OPC_CMP_SF_D
= FOP(56, FMT_D
),
10794 OPC_CMP_NGLE_D
= FOP(57, FMT_D
),
10795 OPC_CMP_SEQ_D
= FOP(58, FMT_D
),
10796 OPC_CMP_NGL_D
= FOP(59, FMT_D
),
10797 OPC_CMP_LT_D
= FOP(60, FMT_D
),
10798 OPC_CMP_NGE_D
= FOP(61, FMT_D
),
10799 OPC_CMP_LE_D
= FOP(62, FMT_D
),
10800 OPC_CMP_NGT_D
= FOP(63, FMT_D
),
10802 OPC_CVT_S_W
= FOP(32, FMT_W
),
10803 OPC_CVT_D_W
= FOP(33, FMT_W
),
10804 OPC_CVT_S_L
= FOP(32, FMT_L
),
10805 OPC_CVT_D_L
= FOP(33, FMT_L
),
10806 OPC_CVT_PS_PW
= FOP(38, FMT_W
),
10808 OPC_ADD_PS
= FOP(0, FMT_PS
),
10809 OPC_SUB_PS
= FOP(1, FMT_PS
),
10810 OPC_MUL_PS
= FOP(2, FMT_PS
),
10811 OPC_DIV_PS
= FOP(3, FMT_PS
),
10812 OPC_ABS_PS
= FOP(5, FMT_PS
),
10813 OPC_MOV_PS
= FOP(6, FMT_PS
),
10814 OPC_NEG_PS
= FOP(7, FMT_PS
),
10815 OPC_MOVCF_PS
= FOP(17, FMT_PS
),
10816 OPC_MOVZ_PS
= FOP(18, FMT_PS
),
10817 OPC_MOVN_PS
= FOP(19, FMT_PS
),
10818 OPC_ADDR_PS
= FOP(24, FMT_PS
),
10819 OPC_MULR_PS
= FOP(26, FMT_PS
),
10820 OPC_RECIP2_PS
= FOP(28, FMT_PS
),
10821 OPC_RECIP1_PS
= FOP(29, FMT_PS
),
10822 OPC_RSQRT1_PS
= FOP(30, FMT_PS
),
10823 OPC_RSQRT2_PS
= FOP(31, FMT_PS
),
10825 OPC_CVT_S_PU
= FOP(32, FMT_PS
),
10826 OPC_CVT_PW_PS
= FOP(36, FMT_PS
),
10827 OPC_CVT_S_PL
= FOP(40, FMT_PS
),
10828 OPC_PLL_PS
= FOP(44, FMT_PS
),
10829 OPC_PLU_PS
= FOP(45, FMT_PS
),
10830 OPC_PUL_PS
= FOP(46, FMT_PS
),
10831 OPC_PUU_PS
= FOP(47, FMT_PS
),
10832 OPC_CMP_F_PS
= FOP(48, FMT_PS
),
10833 OPC_CMP_UN_PS
= FOP(49, FMT_PS
),
10834 OPC_CMP_EQ_PS
= FOP(50, FMT_PS
),
10835 OPC_CMP_UEQ_PS
= FOP(51, FMT_PS
),
10836 OPC_CMP_OLT_PS
= FOP(52, FMT_PS
),
10837 OPC_CMP_ULT_PS
= FOP(53, FMT_PS
),
10838 OPC_CMP_OLE_PS
= FOP(54, FMT_PS
),
10839 OPC_CMP_ULE_PS
= FOP(55, FMT_PS
),
10840 OPC_CMP_SF_PS
= FOP(56, FMT_PS
),
10841 OPC_CMP_NGLE_PS
= FOP(57, FMT_PS
),
10842 OPC_CMP_SEQ_PS
= FOP(58, FMT_PS
),
10843 OPC_CMP_NGL_PS
= FOP(59, FMT_PS
),
10844 OPC_CMP_LT_PS
= FOP(60, FMT_PS
),
10845 OPC_CMP_NGE_PS
= FOP(61, FMT_PS
),
10846 OPC_CMP_LE_PS
= FOP(62, FMT_PS
),
10847 OPC_CMP_NGT_PS
= FOP(63, FMT_PS
),
10851 R6_OPC_CMP_AF_S
= FOP(0, FMT_W
),
10852 R6_OPC_CMP_UN_S
= FOP(1, FMT_W
),
10853 R6_OPC_CMP_EQ_S
= FOP(2, FMT_W
),
10854 R6_OPC_CMP_UEQ_S
= FOP(3, FMT_W
),
10855 R6_OPC_CMP_LT_S
= FOP(4, FMT_W
),
10856 R6_OPC_CMP_ULT_S
= FOP(5, FMT_W
),
10857 R6_OPC_CMP_LE_S
= FOP(6, FMT_W
),
10858 R6_OPC_CMP_ULE_S
= FOP(7, FMT_W
),
10859 R6_OPC_CMP_SAF_S
= FOP(8, FMT_W
),
10860 R6_OPC_CMP_SUN_S
= FOP(9, FMT_W
),
10861 R6_OPC_CMP_SEQ_S
= FOP(10, FMT_W
),
10862 R6_OPC_CMP_SEUQ_S
= FOP(11, FMT_W
),
10863 R6_OPC_CMP_SLT_S
= FOP(12, FMT_W
),
10864 R6_OPC_CMP_SULT_S
= FOP(13, FMT_W
),
10865 R6_OPC_CMP_SLE_S
= FOP(14, FMT_W
),
10866 R6_OPC_CMP_SULE_S
= FOP(15, FMT_W
),
10867 R6_OPC_CMP_OR_S
= FOP(17, FMT_W
),
10868 R6_OPC_CMP_UNE_S
= FOP(18, FMT_W
),
10869 R6_OPC_CMP_NE_S
= FOP(19, FMT_W
),
10870 R6_OPC_CMP_SOR_S
= FOP(25, FMT_W
),
10871 R6_OPC_CMP_SUNE_S
= FOP(26, FMT_W
),
10872 R6_OPC_CMP_SNE_S
= FOP(27, FMT_W
),
10874 R6_OPC_CMP_AF_D
= FOP(0, FMT_L
),
10875 R6_OPC_CMP_UN_D
= FOP(1, FMT_L
),
10876 R6_OPC_CMP_EQ_D
= FOP(2, FMT_L
),
10877 R6_OPC_CMP_UEQ_D
= FOP(3, FMT_L
),
10878 R6_OPC_CMP_LT_D
= FOP(4, FMT_L
),
10879 R6_OPC_CMP_ULT_D
= FOP(5, FMT_L
),
10880 R6_OPC_CMP_LE_D
= FOP(6, FMT_L
),
10881 R6_OPC_CMP_ULE_D
= FOP(7, FMT_L
),
10882 R6_OPC_CMP_SAF_D
= FOP(8, FMT_L
),
10883 R6_OPC_CMP_SUN_D
= FOP(9, FMT_L
),
10884 R6_OPC_CMP_SEQ_D
= FOP(10, FMT_L
),
10885 R6_OPC_CMP_SEUQ_D
= FOP(11, FMT_L
),
10886 R6_OPC_CMP_SLT_D
= FOP(12, FMT_L
),
10887 R6_OPC_CMP_SULT_D
= FOP(13, FMT_L
),
10888 R6_OPC_CMP_SLE_D
= FOP(14, FMT_L
),
10889 R6_OPC_CMP_SULE_D
= FOP(15, FMT_L
),
10890 R6_OPC_CMP_OR_D
= FOP(17, FMT_L
),
10891 R6_OPC_CMP_UNE_D
= FOP(18, FMT_L
),
10892 R6_OPC_CMP_NE_D
= FOP(19, FMT_L
),
10893 R6_OPC_CMP_SOR_D
= FOP(25, FMT_L
),
10894 R6_OPC_CMP_SUNE_D
= FOP(26, FMT_L
),
10895 R6_OPC_CMP_SNE_D
= FOP(27, FMT_L
),
10898 static void gen_cp1(DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
10900 TCGv t0
= tcg_temp_new();
10905 TCGv_i32 fp0
= tcg_temp_new_i32();
10907 gen_load_fpr32(ctx
, fp0
, fs
);
10908 tcg_gen_ext_i32_tl(t0
, fp0
);
10909 tcg_temp_free_i32(fp0
);
10911 gen_store_gpr(t0
, rt
);
10914 gen_load_gpr(t0
, rt
);
10916 TCGv_i32 fp0
= tcg_temp_new_i32();
10918 tcg_gen_trunc_tl_i32(fp0
, t0
);
10919 gen_store_fpr32(ctx
, fp0
, fs
);
10920 tcg_temp_free_i32(fp0
);
10924 gen_helper_1e0i(cfc1
, t0
, fs
);
10925 gen_store_gpr(t0
, rt
);
10928 gen_load_gpr(t0
, rt
);
10929 save_cpu_state(ctx
, 0);
10931 TCGv_i32 fs_tmp
= tcg_const_i32(fs
);
10933 gen_helper_0e2i(ctc1
, t0
, fs_tmp
, rt
);
10934 tcg_temp_free_i32(fs_tmp
);
10936 /* Stop translation as we may have changed hflags */
10937 ctx
->base
.is_jmp
= DISAS_STOP
;
10939 #if defined(TARGET_MIPS64)
10941 gen_load_fpr64(ctx
, t0
, fs
);
10942 gen_store_gpr(t0
, rt
);
10945 gen_load_gpr(t0
, rt
);
10946 gen_store_fpr64(ctx
, t0
, fs
);
10951 TCGv_i32 fp0
= tcg_temp_new_i32();
10953 gen_load_fpr32h(ctx
, fp0
, fs
);
10954 tcg_gen_ext_i32_tl(t0
, fp0
);
10955 tcg_temp_free_i32(fp0
);
10957 gen_store_gpr(t0
, rt
);
10960 gen_load_gpr(t0
, rt
);
10962 TCGv_i32 fp0
= tcg_temp_new_i32();
10964 tcg_gen_trunc_tl_i32(fp0
, t0
);
10965 gen_store_fpr32h(ctx
, fp0
, fs
);
10966 tcg_temp_free_i32(fp0
);
10970 MIPS_INVAL("cp1 move");
10971 generate_exception_end(ctx
, EXCP_RI
);
10979 static void gen_movci(DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
10986 /* Treat as NOP. */
10991 cond
= TCG_COND_EQ
;
10993 cond
= TCG_COND_NE
;
10996 l1
= gen_new_label();
10997 t0
= tcg_temp_new_i32();
10998 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
10999 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
11000 tcg_temp_free_i32(t0
);
11002 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
11004 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
11009 static inline void gen_movcf_s(DisasContext
*ctx
, int fs
, int fd
, int cc
,
11013 TCGv_i32 t0
= tcg_temp_new_i32();
11014 TCGLabel
*l1
= gen_new_label();
11017 cond
= TCG_COND_EQ
;
11019 cond
= TCG_COND_NE
;
11022 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
11023 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
11024 gen_load_fpr32(ctx
, t0
, fs
);
11025 gen_store_fpr32(ctx
, t0
, fd
);
11027 tcg_temp_free_i32(t0
);
11030 static inline void gen_movcf_d(DisasContext
*ctx
, int fs
, int fd
, int cc
,
11034 TCGv_i32 t0
= tcg_temp_new_i32();
11036 TCGLabel
*l1
= gen_new_label();
11039 cond
= TCG_COND_EQ
;
11041 cond
= TCG_COND_NE
;
11044 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
11045 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
11046 tcg_temp_free_i32(t0
);
11047 fp0
= tcg_temp_new_i64();
11048 gen_load_fpr64(ctx
, fp0
, fs
);
11049 gen_store_fpr64(ctx
, fp0
, fd
);
11050 tcg_temp_free_i64(fp0
);
11054 static inline void gen_movcf_ps(DisasContext
*ctx
, int fs
, int fd
,
11058 TCGv_i32 t0
= tcg_temp_new_i32();
11059 TCGLabel
*l1
= gen_new_label();
11060 TCGLabel
*l2
= gen_new_label();
11063 cond
= TCG_COND_EQ
;
11065 cond
= TCG_COND_NE
;
11068 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
11069 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
11070 gen_load_fpr32(ctx
, t0
, fs
);
11071 gen_store_fpr32(ctx
, t0
, fd
);
11074 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+ 1));
11075 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
11076 gen_load_fpr32h(ctx
, t0
, fs
);
11077 gen_store_fpr32h(ctx
, t0
, fd
);
11078 tcg_temp_free_i32(t0
);
11082 static void gen_sel_s(DisasContext
*ctx
, enum fopcode op1
, int fd
, int ft
,
11085 TCGv_i32 t1
= tcg_const_i32(0);
11086 TCGv_i32 fp0
= tcg_temp_new_i32();
11087 TCGv_i32 fp1
= tcg_temp_new_i32();
11088 TCGv_i32 fp2
= tcg_temp_new_i32();
11089 gen_load_fpr32(ctx
, fp0
, fd
);
11090 gen_load_fpr32(ctx
, fp1
, ft
);
11091 gen_load_fpr32(ctx
, fp2
, fs
);
11095 tcg_gen_andi_i32(fp0
, fp0
, 1);
11096 tcg_gen_movcond_i32(TCG_COND_NE
, fp0
, fp0
, t1
, fp1
, fp2
);
11099 tcg_gen_andi_i32(fp1
, fp1
, 1);
11100 tcg_gen_movcond_i32(TCG_COND_EQ
, fp0
, fp1
, t1
, fp2
, t1
);
11103 tcg_gen_andi_i32(fp1
, fp1
, 1);
11104 tcg_gen_movcond_i32(TCG_COND_NE
, fp0
, fp1
, t1
, fp2
, t1
);
11107 MIPS_INVAL("gen_sel_s");
11108 generate_exception_end(ctx
, EXCP_RI
);
11112 gen_store_fpr32(ctx
, fp0
, fd
);
11113 tcg_temp_free_i32(fp2
);
11114 tcg_temp_free_i32(fp1
);
11115 tcg_temp_free_i32(fp0
);
11116 tcg_temp_free_i32(t1
);
11119 static void gen_sel_d(DisasContext
*ctx
, enum fopcode op1
, int fd
, int ft
,
11122 TCGv_i64 t1
= tcg_const_i64(0);
11123 TCGv_i64 fp0
= tcg_temp_new_i64();
11124 TCGv_i64 fp1
= tcg_temp_new_i64();
11125 TCGv_i64 fp2
= tcg_temp_new_i64();
11126 gen_load_fpr64(ctx
, fp0
, fd
);
11127 gen_load_fpr64(ctx
, fp1
, ft
);
11128 gen_load_fpr64(ctx
, fp2
, fs
);
11132 tcg_gen_andi_i64(fp0
, fp0
, 1);
11133 tcg_gen_movcond_i64(TCG_COND_NE
, fp0
, fp0
, t1
, fp1
, fp2
);
11136 tcg_gen_andi_i64(fp1
, fp1
, 1);
11137 tcg_gen_movcond_i64(TCG_COND_EQ
, fp0
, fp1
, t1
, fp2
, t1
);
11140 tcg_gen_andi_i64(fp1
, fp1
, 1);
11141 tcg_gen_movcond_i64(TCG_COND_NE
, fp0
, fp1
, t1
, fp2
, t1
);
11144 MIPS_INVAL("gen_sel_d");
11145 generate_exception_end(ctx
, EXCP_RI
);
11149 gen_store_fpr64(ctx
, fp0
, fd
);
11150 tcg_temp_free_i64(fp2
);
11151 tcg_temp_free_i64(fp1
);
11152 tcg_temp_free_i64(fp0
);
11153 tcg_temp_free_i64(t1
);
11156 static void gen_farith(DisasContext
*ctx
, enum fopcode op1
,
11157 int ft
, int fs
, int fd
, int cc
)
11159 uint32_t func
= ctx
->opcode
& 0x3f;
11163 TCGv_i32 fp0
= tcg_temp_new_i32();
11164 TCGv_i32 fp1
= tcg_temp_new_i32();
11166 gen_load_fpr32(ctx
, fp0
, fs
);
11167 gen_load_fpr32(ctx
, fp1
, ft
);
11168 gen_helper_float_add_s(fp0
, cpu_env
, fp0
, fp1
);
11169 tcg_temp_free_i32(fp1
);
11170 gen_store_fpr32(ctx
, fp0
, fd
);
11171 tcg_temp_free_i32(fp0
);
11176 TCGv_i32 fp0
= tcg_temp_new_i32();
11177 TCGv_i32 fp1
= tcg_temp_new_i32();
11179 gen_load_fpr32(ctx
, fp0
, fs
);
11180 gen_load_fpr32(ctx
, fp1
, ft
);
11181 gen_helper_float_sub_s(fp0
, cpu_env
, fp0
, fp1
);
11182 tcg_temp_free_i32(fp1
);
11183 gen_store_fpr32(ctx
, fp0
, fd
);
11184 tcg_temp_free_i32(fp0
);
11189 TCGv_i32 fp0
= tcg_temp_new_i32();
11190 TCGv_i32 fp1
= tcg_temp_new_i32();
11192 gen_load_fpr32(ctx
, fp0
, fs
);
11193 gen_load_fpr32(ctx
, fp1
, ft
);
11194 gen_helper_float_mul_s(fp0
, cpu_env
, fp0
, fp1
);
11195 tcg_temp_free_i32(fp1
);
11196 gen_store_fpr32(ctx
, fp0
, fd
);
11197 tcg_temp_free_i32(fp0
);
11202 TCGv_i32 fp0
= tcg_temp_new_i32();
11203 TCGv_i32 fp1
= tcg_temp_new_i32();
11205 gen_load_fpr32(ctx
, fp0
, fs
);
11206 gen_load_fpr32(ctx
, fp1
, ft
);
11207 gen_helper_float_div_s(fp0
, cpu_env
, fp0
, fp1
);
11208 tcg_temp_free_i32(fp1
);
11209 gen_store_fpr32(ctx
, fp0
, fd
);
11210 tcg_temp_free_i32(fp0
);
11215 TCGv_i32 fp0
= tcg_temp_new_i32();
11217 gen_load_fpr32(ctx
, fp0
, fs
);
11218 gen_helper_float_sqrt_s(fp0
, cpu_env
, fp0
);
11219 gen_store_fpr32(ctx
, fp0
, fd
);
11220 tcg_temp_free_i32(fp0
);
11225 TCGv_i32 fp0
= tcg_temp_new_i32();
11227 gen_load_fpr32(ctx
, fp0
, fs
);
11228 if (ctx
->abs2008
) {
11229 tcg_gen_andi_i32(fp0
, fp0
, 0x7fffffffUL
);
11231 gen_helper_float_abs_s(fp0
, fp0
);
11233 gen_store_fpr32(ctx
, fp0
, fd
);
11234 tcg_temp_free_i32(fp0
);
11239 TCGv_i32 fp0
= tcg_temp_new_i32();
11241 gen_load_fpr32(ctx
, fp0
, fs
);
11242 gen_store_fpr32(ctx
, fp0
, fd
);
11243 tcg_temp_free_i32(fp0
);
11248 TCGv_i32 fp0
= tcg_temp_new_i32();
11250 gen_load_fpr32(ctx
, fp0
, fs
);
11251 if (ctx
->abs2008
) {
11252 tcg_gen_xori_i32(fp0
, fp0
, 1UL << 31);
11254 gen_helper_float_chs_s(fp0
, fp0
);
11256 gen_store_fpr32(ctx
, fp0
, fd
);
11257 tcg_temp_free_i32(fp0
);
11260 case OPC_ROUND_L_S
:
11261 check_cp1_64bitmode(ctx
);
11263 TCGv_i32 fp32
= tcg_temp_new_i32();
11264 TCGv_i64 fp64
= tcg_temp_new_i64();
11266 gen_load_fpr32(ctx
, fp32
, fs
);
11267 if (ctx
->nan2008
) {
11268 gen_helper_float_round_2008_l_s(fp64
, cpu_env
, fp32
);
11270 gen_helper_float_round_l_s(fp64
, cpu_env
, fp32
);
11272 tcg_temp_free_i32(fp32
);
11273 gen_store_fpr64(ctx
, fp64
, fd
);
11274 tcg_temp_free_i64(fp64
);
11277 case OPC_TRUNC_L_S
:
11278 check_cp1_64bitmode(ctx
);
11280 TCGv_i32 fp32
= tcg_temp_new_i32();
11281 TCGv_i64 fp64
= tcg_temp_new_i64();
11283 gen_load_fpr32(ctx
, fp32
, fs
);
11284 if (ctx
->nan2008
) {
11285 gen_helper_float_trunc_2008_l_s(fp64
, cpu_env
, fp32
);
11287 gen_helper_float_trunc_l_s(fp64
, cpu_env
, fp32
);
11289 tcg_temp_free_i32(fp32
);
11290 gen_store_fpr64(ctx
, fp64
, fd
);
11291 tcg_temp_free_i64(fp64
);
11295 check_cp1_64bitmode(ctx
);
11297 TCGv_i32 fp32
= tcg_temp_new_i32();
11298 TCGv_i64 fp64
= tcg_temp_new_i64();
11300 gen_load_fpr32(ctx
, fp32
, fs
);
11301 if (ctx
->nan2008
) {
11302 gen_helper_float_ceil_2008_l_s(fp64
, cpu_env
, fp32
);
11304 gen_helper_float_ceil_l_s(fp64
, cpu_env
, fp32
);
11306 tcg_temp_free_i32(fp32
);
11307 gen_store_fpr64(ctx
, fp64
, fd
);
11308 tcg_temp_free_i64(fp64
);
11311 case OPC_FLOOR_L_S
:
11312 check_cp1_64bitmode(ctx
);
11314 TCGv_i32 fp32
= tcg_temp_new_i32();
11315 TCGv_i64 fp64
= tcg_temp_new_i64();
11317 gen_load_fpr32(ctx
, fp32
, fs
);
11318 if (ctx
->nan2008
) {
11319 gen_helper_float_floor_2008_l_s(fp64
, cpu_env
, fp32
);
11321 gen_helper_float_floor_l_s(fp64
, cpu_env
, fp32
);
11323 tcg_temp_free_i32(fp32
);
11324 gen_store_fpr64(ctx
, fp64
, fd
);
11325 tcg_temp_free_i64(fp64
);
11328 case OPC_ROUND_W_S
:
11330 TCGv_i32 fp0
= tcg_temp_new_i32();
11332 gen_load_fpr32(ctx
, fp0
, fs
);
11333 if (ctx
->nan2008
) {
11334 gen_helper_float_round_2008_w_s(fp0
, cpu_env
, fp0
);
11336 gen_helper_float_round_w_s(fp0
, cpu_env
, fp0
);
11338 gen_store_fpr32(ctx
, fp0
, fd
);
11339 tcg_temp_free_i32(fp0
);
11342 case OPC_TRUNC_W_S
:
11344 TCGv_i32 fp0
= tcg_temp_new_i32();
11346 gen_load_fpr32(ctx
, fp0
, fs
);
11347 if (ctx
->nan2008
) {
11348 gen_helper_float_trunc_2008_w_s(fp0
, cpu_env
, fp0
);
11350 gen_helper_float_trunc_w_s(fp0
, cpu_env
, fp0
);
11352 gen_store_fpr32(ctx
, fp0
, fd
);
11353 tcg_temp_free_i32(fp0
);
11358 TCGv_i32 fp0
= tcg_temp_new_i32();
11360 gen_load_fpr32(ctx
, fp0
, fs
);
11361 if (ctx
->nan2008
) {
11362 gen_helper_float_ceil_2008_w_s(fp0
, cpu_env
, fp0
);
11364 gen_helper_float_ceil_w_s(fp0
, cpu_env
, fp0
);
11366 gen_store_fpr32(ctx
, fp0
, fd
);
11367 tcg_temp_free_i32(fp0
);
11370 case OPC_FLOOR_W_S
:
11372 TCGv_i32 fp0
= tcg_temp_new_i32();
11374 gen_load_fpr32(ctx
, fp0
, fs
);
11375 if (ctx
->nan2008
) {
11376 gen_helper_float_floor_2008_w_s(fp0
, cpu_env
, fp0
);
11378 gen_helper_float_floor_w_s(fp0
, cpu_env
, fp0
);
11380 gen_store_fpr32(ctx
, fp0
, fd
);
11381 tcg_temp_free_i32(fp0
);
11385 check_insn(ctx
, ISA_MIPS32R6
);
11386 gen_sel_s(ctx
, op1
, fd
, ft
, fs
);
11389 check_insn(ctx
, ISA_MIPS32R6
);
11390 gen_sel_s(ctx
, op1
, fd
, ft
, fs
);
11393 check_insn(ctx
, ISA_MIPS32R6
);
11394 gen_sel_s(ctx
, op1
, fd
, ft
, fs
);
11397 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11398 gen_movcf_s(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
11401 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11403 TCGLabel
*l1
= gen_new_label();
11407 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
11409 fp0
= tcg_temp_new_i32();
11410 gen_load_fpr32(ctx
, fp0
, fs
);
11411 gen_store_fpr32(ctx
, fp0
, fd
);
11412 tcg_temp_free_i32(fp0
);
11417 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11419 TCGLabel
*l1
= gen_new_label();
11423 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
11424 fp0
= tcg_temp_new_i32();
11425 gen_load_fpr32(ctx
, fp0
, fs
);
11426 gen_store_fpr32(ctx
, fp0
, fd
);
11427 tcg_temp_free_i32(fp0
);
11434 TCGv_i32 fp0
= tcg_temp_new_i32();
11436 gen_load_fpr32(ctx
, fp0
, fs
);
11437 gen_helper_float_recip_s(fp0
, cpu_env
, fp0
);
11438 gen_store_fpr32(ctx
, fp0
, fd
);
11439 tcg_temp_free_i32(fp0
);
11444 TCGv_i32 fp0
= tcg_temp_new_i32();
11446 gen_load_fpr32(ctx
, fp0
, fs
);
11447 gen_helper_float_rsqrt_s(fp0
, cpu_env
, fp0
);
11448 gen_store_fpr32(ctx
, fp0
, fd
);
11449 tcg_temp_free_i32(fp0
);
11453 check_insn(ctx
, ISA_MIPS32R6
);
11455 TCGv_i32 fp0
= tcg_temp_new_i32();
11456 TCGv_i32 fp1
= tcg_temp_new_i32();
11457 TCGv_i32 fp2
= tcg_temp_new_i32();
11458 gen_load_fpr32(ctx
, fp0
, fs
);
11459 gen_load_fpr32(ctx
, fp1
, ft
);
11460 gen_load_fpr32(ctx
, fp2
, fd
);
11461 gen_helper_float_maddf_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
11462 gen_store_fpr32(ctx
, fp2
, fd
);
11463 tcg_temp_free_i32(fp2
);
11464 tcg_temp_free_i32(fp1
);
11465 tcg_temp_free_i32(fp0
);
11469 check_insn(ctx
, ISA_MIPS32R6
);
11471 TCGv_i32 fp0
= tcg_temp_new_i32();
11472 TCGv_i32 fp1
= tcg_temp_new_i32();
11473 TCGv_i32 fp2
= tcg_temp_new_i32();
11474 gen_load_fpr32(ctx
, fp0
, fs
);
11475 gen_load_fpr32(ctx
, fp1
, ft
);
11476 gen_load_fpr32(ctx
, fp2
, fd
);
11477 gen_helper_float_msubf_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
11478 gen_store_fpr32(ctx
, fp2
, fd
);
11479 tcg_temp_free_i32(fp2
);
11480 tcg_temp_free_i32(fp1
);
11481 tcg_temp_free_i32(fp0
);
11485 check_insn(ctx
, ISA_MIPS32R6
);
11487 TCGv_i32 fp0
= tcg_temp_new_i32();
11488 gen_load_fpr32(ctx
, fp0
, fs
);
11489 gen_helper_float_rint_s(fp0
, cpu_env
, fp0
);
11490 gen_store_fpr32(ctx
, fp0
, fd
);
11491 tcg_temp_free_i32(fp0
);
11495 check_insn(ctx
, ISA_MIPS32R6
);
11497 TCGv_i32 fp0
= tcg_temp_new_i32();
11498 gen_load_fpr32(ctx
, fp0
, fs
);
11499 gen_helper_float_class_s(fp0
, cpu_env
, fp0
);
11500 gen_store_fpr32(ctx
, fp0
, fd
);
11501 tcg_temp_free_i32(fp0
);
11504 case OPC_MIN_S
: /* OPC_RECIP2_S */
11505 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
11507 TCGv_i32 fp0
= tcg_temp_new_i32();
11508 TCGv_i32 fp1
= tcg_temp_new_i32();
11509 TCGv_i32 fp2
= tcg_temp_new_i32();
11510 gen_load_fpr32(ctx
, fp0
, fs
);
11511 gen_load_fpr32(ctx
, fp1
, ft
);
11512 gen_helper_float_min_s(fp2
, cpu_env
, fp0
, fp1
);
11513 gen_store_fpr32(ctx
, fp2
, fd
);
11514 tcg_temp_free_i32(fp2
);
11515 tcg_temp_free_i32(fp1
);
11516 tcg_temp_free_i32(fp0
);
11519 check_cp1_64bitmode(ctx
);
11521 TCGv_i32 fp0
= tcg_temp_new_i32();
11522 TCGv_i32 fp1
= tcg_temp_new_i32();
11524 gen_load_fpr32(ctx
, fp0
, fs
);
11525 gen_load_fpr32(ctx
, fp1
, ft
);
11526 gen_helper_float_recip2_s(fp0
, cpu_env
, fp0
, fp1
);
11527 tcg_temp_free_i32(fp1
);
11528 gen_store_fpr32(ctx
, fp0
, fd
);
11529 tcg_temp_free_i32(fp0
);
11533 case OPC_MINA_S
: /* OPC_RECIP1_S */
11534 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
11536 TCGv_i32 fp0
= tcg_temp_new_i32();
11537 TCGv_i32 fp1
= tcg_temp_new_i32();
11538 TCGv_i32 fp2
= tcg_temp_new_i32();
11539 gen_load_fpr32(ctx
, fp0
, fs
);
11540 gen_load_fpr32(ctx
, fp1
, ft
);
11541 gen_helper_float_mina_s(fp2
, cpu_env
, fp0
, fp1
);
11542 gen_store_fpr32(ctx
, fp2
, fd
);
11543 tcg_temp_free_i32(fp2
);
11544 tcg_temp_free_i32(fp1
);
11545 tcg_temp_free_i32(fp0
);
11548 check_cp1_64bitmode(ctx
);
11550 TCGv_i32 fp0
= tcg_temp_new_i32();
11552 gen_load_fpr32(ctx
, fp0
, fs
);
11553 gen_helper_float_recip1_s(fp0
, cpu_env
, fp0
);
11554 gen_store_fpr32(ctx
, fp0
, fd
);
11555 tcg_temp_free_i32(fp0
);
11559 case OPC_MAX_S
: /* OPC_RSQRT1_S */
11560 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
11562 TCGv_i32 fp0
= tcg_temp_new_i32();
11563 TCGv_i32 fp1
= tcg_temp_new_i32();
11564 gen_load_fpr32(ctx
, fp0
, fs
);
11565 gen_load_fpr32(ctx
, fp1
, ft
);
11566 gen_helper_float_max_s(fp1
, cpu_env
, fp0
, fp1
);
11567 gen_store_fpr32(ctx
, fp1
, fd
);
11568 tcg_temp_free_i32(fp1
);
11569 tcg_temp_free_i32(fp0
);
11572 check_cp1_64bitmode(ctx
);
11574 TCGv_i32 fp0
= tcg_temp_new_i32();
11576 gen_load_fpr32(ctx
, fp0
, fs
);
11577 gen_helper_float_rsqrt1_s(fp0
, cpu_env
, fp0
);
11578 gen_store_fpr32(ctx
, fp0
, fd
);
11579 tcg_temp_free_i32(fp0
);
11583 case OPC_MAXA_S
: /* OPC_RSQRT2_S */
11584 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
11586 TCGv_i32 fp0
= tcg_temp_new_i32();
11587 TCGv_i32 fp1
= tcg_temp_new_i32();
11588 gen_load_fpr32(ctx
, fp0
, fs
);
11589 gen_load_fpr32(ctx
, fp1
, ft
);
11590 gen_helper_float_maxa_s(fp1
, cpu_env
, fp0
, fp1
);
11591 gen_store_fpr32(ctx
, fp1
, fd
);
11592 tcg_temp_free_i32(fp1
);
11593 tcg_temp_free_i32(fp0
);
11596 check_cp1_64bitmode(ctx
);
11598 TCGv_i32 fp0
= tcg_temp_new_i32();
11599 TCGv_i32 fp1
= tcg_temp_new_i32();
11601 gen_load_fpr32(ctx
, fp0
, fs
);
11602 gen_load_fpr32(ctx
, fp1
, ft
);
11603 gen_helper_float_rsqrt2_s(fp0
, cpu_env
, fp0
, fp1
);
11604 tcg_temp_free_i32(fp1
);
11605 gen_store_fpr32(ctx
, fp0
, fd
);
11606 tcg_temp_free_i32(fp0
);
11611 check_cp1_registers(ctx
, fd
);
11613 TCGv_i32 fp32
= tcg_temp_new_i32();
11614 TCGv_i64 fp64
= tcg_temp_new_i64();
11616 gen_load_fpr32(ctx
, fp32
, fs
);
11617 gen_helper_float_cvtd_s(fp64
, cpu_env
, fp32
);
11618 tcg_temp_free_i32(fp32
);
11619 gen_store_fpr64(ctx
, fp64
, fd
);
11620 tcg_temp_free_i64(fp64
);
11625 TCGv_i32 fp0
= tcg_temp_new_i32();
11627 gen_load_fpr32(ctx
, fp0
, fs
);
11628 if (ctx
->nan2008
) {
11629 gen_helper_float_cvt_2008_w_s(fp0
, cpu_env
, fp0
);
11631 gen_helper_float_cvt_w_s(fp0
, cpu_env
, fp0
);
11633 gen_store_fpr32(ctx
, fp0
, fd
);
11634 tcg_temp_free_i32(fp0
);
11638 check_cp1_64bitmode(ctx
);
11640 TCGv_i32 fp32
= tcg_temp_new_i32();
11641 TCGv_i64 fp64
= tcg_temp_new_i64();
11643 gen_load_fpr32(ctx
, fp32
, fs
);
11644 if (ctx
->nan2008
) {
11645 gen_helper_float_cvt_2008_l_s(fp64
, cpu_env
, fp32
);
11647 gen_helper_float_cvt_l_s(fp64
, cpu_env
, fp32
);
11649 tcg_temp_free_i32(fp32
);
11650 gen_store_fpr64(ctx
, fp64
, fd
);
11651 tcg_temp_free_i64(fp64
);
11657 TCGv_i64 fp64
= tcg_temp_new_i64();
11658 TCGv_i32 fp32_0
= tcg_temp_new_i32();
11659 TCGv_i32 fp32_1
= tcg_temp_new_i32();
11661 gen_load_fpr32(ctx
, fp32_0
, fs
);
11662 gen_load_fpr32(ctx
, fp32_1
, ft
);
11663 tcg_gen_concat_i32_i64(fp64
, fp32_1
, fp32_0
);
11664 tcg_temp_free_i32(fp32_1
);
11665 tcg_temp_free_i32(fp32_0
);
11666 gen_store_fpr64(ctx
, fp64
, fd
);
11667 tcg_temp_free_i64(fp64
);
11673 case OPC_CMP_UEQ_S
:
11674 case OPC_CMP_OLT_S
:
11675 case OPC_CMP_ULT_S
:
11676 case OPC_CMP_OLE_S
:
11677 case OPC_CMP_ULE_S
:
11679 case OPC_CMP_NGLE_S
:
11680 case OPC_CMP_SEQ_S
:
11681 case OPC_CMP_NGL_S
:
11683 case OPC_CMP_NGE_S
:
11685 case OPC_CMP_NGT_S
:
11686 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11687 if (ctx
->opcode
& (1 << 6)) {
11688 gen_cmpabs_s(ctx
, func
- 48, ft
, fs
, cc
);
11690 gen_cmp_s(ctx
, func
- 48, ft
, fs
, cc
);
11694 check_cp1_registers(ctx
, fs
| ft
| fd
);
11696 TCGv_i64 fp0
= tcg_temp_new_i64();
11697 TCGv_i64 fp1
= tcg_temp_new_i64();
11699 gen_load_fpr64(ctx
, fp0
, fs
);
11700 gen_load_fpr64(ctx
, fp1
, ft
);
11701 gen_helper_float_add_d(fp0
, cpu_env
, fp0
, fp1
);
11702 tcg_temp_free_i64(fp1
);
11703 gen_store_fpr64(ctx
, fp0
, fd
);
11704 tcg_temp_free_i64(fp0
);
11708 check_cp1_registers(ctx
, fs
| ft
| fd
);
11710 TCGv_i64 fp0
= tcg_temp_new_i64();
11711 TCGv_i64 fp1
= tcg_temp_new_i64();
11713 gen_load_fpr64(ctx
, fp0
, fs
);
11714 gen_load_fpr64(ctx
, fp1
, ft
);
11715 gen_helper_float_sub_d(fp0
, cpu_env
, fp0
, fp1
);
11716 tcg_temp_free_i64(fp1
);
11717 gen_store_fpr64(ctx
, fp0
, fd
);
11718 tcg_temp_free_i64(fp0
);
11722 check_cp1_registers(ctx
, fs
| ft
| fd
);
11724 TCGv_i64 fp0
= tcg_temp_new_i64();
11725 TCGv_i64 fp1
= tcg_temp_new_i64();
11727 gen_load_fpr64(ctx
, fp0
, fs
);
11728 gen_load_fpr64(ctx
, fp1
, ft
);
11729 gen_helper_float_mul_d(fp0
, cpu_env
, fp0
, fp1
);
11730 tcg_temp_free_i64(fp1
);
11731 gen_store_fpr64(ctx
, fp0
, fd
);
11732 tcg_temp_free_i64(fp0
);
11736 check_cp1_registers(ctx
, fs
| ft
| fd
);
11738 TCGv_i64 fp0
= tcg_temp_new_i64();
11739 TCGv_i64 fp1
= tcg_temp_new_i64();
11741 gen_load_fpr64(ctx
, fp0
, fs
);
11742 gen_load_fpr64(ctx
, fp1
, ft
);
11743 gen_helper_float_div_d(fp0
, cpu_env
, fp0
, fp1
);
11744 tcg_temp_free_i64(fp1
);
11745 gen_store_fpr64(ctx
, fp0
, fd
);
11746 tcg_temp_free_i64(fp0
);
11750 check_cp1_registers(ctx
, fs
| fd
);
11752 TCGv_i64 fp0
= tcg_temp_new_i64();
11754 gen_load_fpr64(ctx
, fp0
, fs
);
11755 gen_helper_float_sqrt_d(fp0
, cpu_env
, fp0
);
11756 gen_store_fpr64(ctx
, fp0
, fd
);
11757 tcg_temp_free_i64(fp0
);
11761 check_cp1_registers(ctx
, fs
| fd
);
11763 TCGv_i64 fp0
= tcg_temp_new_i64();
11765 gen_load_fpr64(ctx
, fp0
, fs
);
11766 if (ctx
->abs2008
) {
11767 tcg_gen_andi_i64(fp0
, fp0
, 0x7fffffffffffffffULL
);
11769 gen_helper_float_abs_d(fp0
, fp0
);
11771 gen_store_fpr64(ctx
, fp0
, fd
);
11772 tcg_temp_free_i64(fp0
);
11776 check_cp1_registers(ctx
, fs
| fd
);
11778 TCGv_i64 fp0
= tcg_temp_new_i64();
11780 gen_load_fpr64(ctx
, fp0
, fs
);
11781 gen_store_fpr64(ctx
, fp0
, fd
);
11782 tcg_temp_free_i64(fp0
);
11786 check_cp1_registers(ctx
, fs
| fd
);
11788 TCGv_i64 fp0
= tcg_temp_new_i64();
11790 gen_load_fpr64(ctx
, fp0
, fs
);
11791 if (ctx
->abs2008
) {
11792 tcg_gen_xori_i64(fp0
, fp0
, 1ULL << 63);
11794 gen_helper_float_chs_d(fp0
, fp0
);
11796 gen_store_fpr64(ctx
, fp0
, fd
);
11797 tcg_temp_free_i64(fp0
);
11800 case OPC_ROUND_L_D
:
11801 check_cp1_64bitmode(ctx
);
11803 TCGv_i64 fp0
= tcg_temp_new_i64();
11805 gen_load_fpr64(ctx
, fp0
, fs
);
11806 if (ctx
->nan2008
) {
11807 gen_helper_float_round_2008_l_d(fp0
, cpu_env
, fp0
);
11809 gen_helper_float_round_l_d(fp0
, cpu_env
, fp0
);
11811 gen_store_fpr64(ctx
, fp0
, fd
);
11812 tcg_temp_free_i64(fp0
);
11815 case OPC_TRUNC_L_D
:
11816 check_cp1_64bitmode(ctx
);
11818 TCGv_i64 fp0
= tcg_temp_new_i64();
11820 gen_load_fpr64(ctx
, fp0
, fs
);
11821 if (ctx
->nan2008
) {
11822 gen_helper_float_trunc_2008_l_d(fp0
, cpu_env
, fp0
);
11824 gen_helper_float_trunc_l_d(fp0
, cpu_env
, fp0
);
11826 gen_store_fpr64(ctx
, fp0
, fd
);
11827 tcg_temp_free_i64(fp0
);
11831 check_cp1_64bitmode(ctx
);
11833 TCGv_i64 fp0
= tcg_temp_new_i64();
11835 gen_load_fpr64(ctx
, fp0
, fs
);
11836 if (ctx
->nan2008
) {
11837 gen_helper_float_ceil_2008_l_d(fp0
, cpu_env
, fp0
);
11839 gen_helper_float_ceil_l_d(fp0
, cpu_env
, fp0
);
11841 gen_store_fpr64(ctx
, fp0
, fd
);
11842 tcg_temp_free_i64(fp0
);
11845 case OPC_FLOOR_L_D
:
11846 check_cp1_64bitmode(ctx
);
11848 TCGv_i64 fp0
= tcg_temp_new_i64();
11850 gen_load_fpr64(ctx
, fp0
, fs
);
11851 if (ctx
->nan2008
) {
11852 gen_helper_float_floor_2008_l_d(fp0
, cpu_env
, fp0
);
11854 gen_helper_float_floor_l_d(fp0
, cpu_env
, fp0
);
11856 gen_store_fpr64(ctx
, fp0
, fd
);
11857 tcg_temp_free_i64(fp0
);
11860 case OPC_ROUND_W_D
:
11861 check_cp1_registers(ctx
, fs
);
11863 TCGv_i32 fp32
= tcg_temp_new_i32();
11864 TCGv_i64 fp64
= tcg_temp_new_i64();
11866 gen_load_fpr64(ctx
, fp64
, fs
);
11867 if (ctx
->nan2008
) {
11868 gen_helper_float_round_2008_w_d(fp32
, cpu_env
, fp64
);
11870 gen_helper_float_round_w_d(fp32
, cpu_env
, fp64
);
11872 tcg_temp_free_i64(fp64
);
11873 gen_store_fpr32(ctx
, fp32
, fd
);
11874 tcg_temp_free_i32(fp32
);
11877 case OPC_TRUNC_W_D
:
11878 check_cp1_registers(ctx
, fs
);
11880 TCGv_i32 fp32
= tcg_temp_new_i32();
11881 TCGv_i64 fp64
= tcg_temp_new_i64();
11883 gen_load_fpr64(ctx
, fp64
, fs
);
11884 if (ctx
->nan2008
) {
11885 gen_helper_float_trunc_2008_w_d(fp32
, cpu_env
, fp64
);
11887 gen_helper_float_trunc_w_d(fp32
, cpu_env
, fp64
);
11889 tcg_temp_free_i64(fp64
);
11890 gen_store_fpr32(ctx
, fp32
, fd
);
11891 tcg_temp_free_i32(fp32
);
11895 check_cp1_registers(ctx
, fs
);
11897 TCGv_i32 fp32
= tcg_temp_new_i32();
11898 TCGv_i64 fp64
= tcg_temp_new_i64();
11900 gen_load_fpr64(ctx
, fp64
, fs
);
11901 if (ctx
->nan2008
) {
11902 gen_helper_float_ceil_2008_w_d(fp32
, cpu_env
, fp64
);
11904 gen_helper_float_ceil_w_d(fp32
, cpu_env
, fp64
);
11906 tcg_temp_free_i64(fp64
);
11907 gen_store_fpr32(ctx
, fp32
, fd
);
11908 tcg_temp_free_i32(fp32
);
11911 case OPC_FLOOR_W_D
:
11912 check_cp1_registers(ctx
, fs
);
11914 TCGv_i32 fp32
= tcg_temp_new_i32();
11915 TCGv_i64 fp64
= tcg_temp_new_i64();
11917 gen_load_fpr64(ctx
, fp64
, fs
);
11918 if (ctx
->nan2008
) {
11919 gen_helper_float_floor_2008_w_d(fp32
, cpu_env
, fp64
);
11921 gen_helper_float_floor_w_d(fp32
, cpu_env
, fp64
);
11923 tcg_temp_free_i64(fp64
);
11924 gen_store_fpr32(ctx
, fp32
, fd
);
11925 tcg_temp_free_i32(fp32
);
11929 check_insn(ctx
, ISA_MIPS32R6
);
11930 gen_sel_d(ctx
, op1
, fd
, ft
, fs
);
11933 check_insn(ctx
, ISA_MIPS32R6
);
11934 gen_sel_d(ctx
, op1
, fd
, ft
, fs
);
11937 check_insn(ctx
, ISA_MIPS32R6
);
11938 gen_sel_d(ctx
, op1
, fd
, ft
, fs
);
11941 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11942 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
11945 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11947 TCGLabel
*l1
= gen_new_label();
11951 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
11953 fp0
= tcg_temp_new_i64();
11954 gen_load_fpr64(ctx
, fp0
, fs
);
11955 gen_store_fpr64(ctx
, fp0
, fd
);
11956 tcg_temp_free_i64(fp0
);
11961 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
11963 TCGLabel
*l1
= gen_new_label();
11967 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
11968 fp0
= tcg_temp_new_i64();
11969 gen_load_fpr64(ctx
, fp0
, fs
);
11970 gen_store_fpr64(ctx
, fp0
, fd
);
11971 tcg_temp_free_i64(fp0
);
11977 check_cp1_registers(ctx
, fs
| fd
);
11979 TCGv_i64 fp0
= tcg_temp_new_i64();
11981 gen_load_fpr64(ctx
, fp0
, fs
);
11982 gen_helper_float_recip_d(fp0
, cpu_env
, fp0
);
11983 gen_store_fpr64(ctx
, fp0
, fd
);
11984 tcg_temp_free_i64(fp0
);
11988 check_cp1_registers(ctx
, fs
| fd
);
11990 TCGv_i64 fp0
= tcg_temp_new_i64();
11992 gen_load_fpr64(ctx
, fp0
, fs
);
11993 gen_helper_float_rsqrt_d(fp0
, cpu_env
, fp0
);
11994 gen_store_fpr64(ctx
, fp0
, fd
);
11995 tcg_temp_free_i64(fp0
);
11999 check_insn(ctx
, ISA_MIPS32R6
);
12001 TCGv_i64 fp0
= tcg_temp_new_i64();
12002 TCGv_i64 fp1
= tcg_temp_new_i64();
12003 TCGv_i64 fp2
= tcg_temp_new_i64();
12004 gen_load_fpr64(ctx
, fp0
, fs
);
12005 gen_load_fpr64(ctx
, fp1
, ft
);
12006 gen_load_fpr64(ctx
, fp2
, fd
);
12007 gen_helper_float_maddf_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12008 gen_store_fpr64(ctx
, fp2
, fd
);
12009 tcg_temp_free_i64(fp2
);
12010 tcg_temp_free_i64(fp1
);
12011 tcg_temp_free_i64(fp0
);
12015 check_insn(ctx
, ISA_MIPS32R6
);
12017 TCGv_i64 fp0
= tcg_temp_new_i64();
12018 TCGv_i64 fp1
= tcg_temp_new_i64();
12019 TCGv_i64 fp2
= tcg_temp_new_i64();
12020 gen_load_fpr64(ctx
, fp0
, fs
);
12021 gen_load_fpr64(ctx
, fp1
, ft
);
12022 gen_load_fpr64(ctx
, fp2
, fd
);
12023 gen_helper_float_msubf_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12024 gen_store_fpr64(ctx
, fp2
, fd
);
12025 tcg_temp_free_i64(fp2
);
12026 tcg_temp_free_i64(fp1
);
12027 tcg_temp_free_i64(fp0
);
12031 check_insn(ctx
, ISA_MIPS32R6
);
12033 TCGv_i64 fp0
= tcg_temp_new_i64();
12034 gen_load_fpr64(ctx
, fp0
, fs
);
12035 gen_helper_float_rint_d(fp0
, cpu_env
, fp0
);
12036 gen_store_fpr64(ctx
, fp0
, fd
);
12037 tcg_temp_free_i64(fp0
);
12041 check_insn(ctx
, ISA_MIPS32R6
);
12043 TCGv_i64 fp0
= tcg_temp_new_i64();
12044 gen_load_fpr64(ctx
, fp0
, fs
);
12045 gen_helper_float_class_d(fp0
, cpu_env
, fp0
);
12046 gen_store_fpr64(ctx
, fp0
, fd
);
12047 tcg_temp_free_i64(fp0
);
12050 case OPC_MIN_D
: /* OPC_RECIP2_D */
12051 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
12053 TCGv_i64 fp0
= tcg_temp_new_i64();
12054 TCGv_i64 fp1
= tcg_temp_new_i64();
12055 gen_load_fpr64(ctx
, fp0
, fs
);
12056 gen_load_fpr64(ctx
, fp1
, ft
);
12057 gen_helper_float_min_d(fp1
, cpu_env
, fp0
, fp1
);
12058 gen_store_fpr64(ctx
, fp1
, fd
);
12059 tcg_temp_free_i64(fp1
);
12060 tcg_temp_free_i64(fp0
);
12063 check_cp1_64bitmode(ctx
);
12065 TCGv_i64 fp0
= tcg_temp_new_i64();
12066 TCGv_i64 fp1
= tcg_temp_new_i64();
12068 gen_load_fpr64(ctx
, fp0
, fs
);
12069 gen_load_fpr64(ctx
, fp1
, ft
);
12070 gen_helper_float_recip2_d(fp0
, cpu_env
, fp0
, fp1
);
12071 tcg_temp_free_i64(fp1
);
12072 gen_store_fpr64(ctx
, fp0
, fd
);
12073 tcg_temp_free_i64(fp0
);
12077 case OPC_MINA_D
: /* OPC_RECIP1_D */
12078 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
12080 TCGv_i64 fp0
= tcg_temp_new_i64();
12081 TCGv_i64 fp1
= tcg_temp_new_i64();
12082 gen_load_fpr64(ctx
, fp0
, fs
);
12083 gen_load_fpr64(ctx
, fp1
, ft
);
12084 gen_helper_float_mina_d(fp1
, cpu_env
, fp0
, fp1
);
12085 gen_store_fpr64(ctx
, fp1
, fd
);
12086 tcg_temp_free_i64(fp1
);
12087 tcg_temp_free_i64(fp0
);
12090 check_cp1_64bitmode(ctx
);
12092 TCGv_i64 fp0
= tcg_temp_new_i64();
12094 gen_load_fpr64(ctx
, fp0
, fs
);
12095 gen_helper_float_recip1_d(fp0
, cpu_env
, fp0
);
12096 gen_store_fpr64(ctx
, fp0
, fd
);
12097 tcg_temp_free_i64(fp0
);
12101 case OPC_MAX_D
: /* OPC_RSQRT1_D */
12102 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
12104 TCGv_i64 fp0
= tcg_temp_new_i64();
12105 TCGv_i64 fp1
= tcg_temp_new_i64();
12106 gen_load_fpr64(ctx
, fp0
, fs
);
12107 gen_load_fpr64(ctx
, fp1
, ft
);
12108 gen_helper_float_max_d(fp1
, cpu_env
, fp0
, fp1
);
12109 gen_store_fpr64(ctx
, fp1
, fd
);
12110 tcg_temp_free_i64(fp1
);
12111 tcg_temp_free_i64(fp0
);
12114 check_cp1_64bitmode(ctx
);
12116 TCGv_i64 fp0
= tcg_temp_new_i64();
12118 gen_load_fpr64(ctx
, fp0
, fs
);
12119 gen_helper_float_rsqrt1_d(fp0
, cpu_env
, fp0
);
12120 gen_store_fpr64(ctx
, fp0
, fd
);
12121 tcg_temp_free_i64(fp0
);
12125 case OPC_MAXA_D
: /* OPC_RSQRT2_D */
12126 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
12128 TCGv_i64 fp0
= tcg_temp_new_i64();
12129 TCGv_i64 fp1
= tcg_temp_new_i64();
12130 gen_load_fpr64(ctx
, fp0
, fs
);
12131 gen_load_fpr64(ctx
, fp1
, ft
);
12132 gen_helper_float_maxa_d(fp1
, cpu_env
, fp0
, fp1
);
12133 gen_store_fpr64(ctx
, fp1
, fd
);
12134 tcg_temp_free_i64(fp1
);
12135 tcg_temp_free_i64(fp0
);
12138 check_cp1_64bitmode(ctx
);
12140 TCGv_i64 fp0
= tcg_temp_new_i64();
12141 TCGv_i64 fp1
= tcg_temp_new_i64();
12143 gen_load_fpr64(ctx
, fp0
, fs
);
12144 gen_load_fpr64(ctx
, fp1
, ft
);
12145 gen_helper_float_rsqrt2_d(fp0
, cpu_env
, fp0
, fp1
);
12146 tcg_temp_free_i64(fp1
);
12147 gen_store_fpr64(ctx
, fp0
, fd
);
12148 tcg_temp_free_i64(fp0
);
12155 case OPC_CMP_UEQ_D
:
12156 case OPC_CMP_OLT_D
:
12157 case OPC_CMP_ULT_D
:
12158 case OPC_CMP_OLE_D
:
12159 case OPC_CMP_ULE_D
:
12161 case OPC_CMP_NGLE_D
:
12162 case OPC_CMP_SEQ_D
:
12163 case OPC_CMP_NGL_D
:
12165 case OPC_CMP_NGE_D
:
12167 case OPC_CMP_NGT_D
:
12168 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
12169 if (ctx
->opcode
& (1 << 6)) {
12170 gen_cmpabs_d(ctx
, func
- 48, ft
, fs
, cc
);
12172 gen_cmp_d(ctx
, func
- 48, ft
, fs
, cc
);
12176 check_cp1_registers(ctx
, fs
);
12178 TCGv_i32 fp32
= tcg_temp_new_i32();
12179 TCGv_i64 fp64
= tcg_temp_new_i64();
12181 gen_load_fpr64(ctx
, fp64
, fs
);
12182 gen_helper_float_cvts_d(fp32
, cpu_env
, fp64
);
12183 tcg_temp_free_i64(fp64
);
12184 gen_store_fpr32(ctx
, fp32
, fd
);
12185 tcg_temp_free_i32(fp32
);
12189 check_cp1_registers(ctx
, fs
);
12191 TCGv_i32 fp32
= tcg_temp_new_i32();
12192 TCGv_i64 fp64
= tcg_temp_new_i64();
12194 gen_load_fpr64(ctx
, fp64
, fs
);
12195 if (ctx
->nan2008
) {
12196 gen_helper_float_cvt_2008_w_d(fp32
, cpu_env
, fp64
);
12198 gen_helper_float_cvt_w_d(fp32
, cpu_env
, fp64
);
12200 tcg_temp_free_i64(fp64
);
12201 gen_store_fpr32(ctx
, fp32
, fd
);
12202 tcg_temp_free_i32(fp32
);
12206 check_cp1_64bitmode(ctx
);
12208 TCGv_i64 fp0
= tcg_temp_new_i64();
12210 gen_load_fpr64(ctx
, fp0
, fs
);
12211 if (ctx
->nan2008
) {
12212 gen_helper_float_cvt_2008_l_d(fp0
, cpu_env
, fp0
);
12214 gen_helper_float_cvt_l_d(fp0
, cpu_env
, fp0
);
12216 gen_store_fpr64(ctx
, fp0
, fd
);
12217 tcg_temp_free_i64(fp0
);
12222 TCGv_i32 fp0
= tcg_temp_new_i32();
12224 gen_load_fpr32(ctx
, fp0
, fs
);
12225 gen_helper_float_cvts_w(fp0
, cpu_env
, fp0
);
12226 gen_store_fpr32(ctx
, fp0
, fd
);
12227 tcg_temp_free_i32(fp0
);
12231 check_cp1_registers(ctx
, fd
);
12233 TCGv_i32 fp32
= tcg_temp_new_i32();
12234 TCGv_i64 fp64
= tcg_temp_new_i64();
12236 gen_load_fpr32(ctx
, fp32
, fs
);
12237 gen_helper_float_cvtd_w(fp64
, cpu_env
, fp32
);
12238 tcg_temp_free_i32(fp32
);
12239 gen_store_fpr64(ctx
, fp64
, fd
);
12240 tcg_temp_free_i64(fp64
);
12244 check_cp1_64bitmode(ctx
);
12246 TCGv_i32 fp32
= tcg_temp_new_i32();
12247 TCGv_i64 fp64
= tcg_temp_new_i64();
12249 gen_load_fpr64(ctx
, fp64
, fs
);
12250 gen_helper_float_cvts_l(fp32
, cpu_env
, fp64
);
12251 tcg_temp_free_i64(fp64
);
12252 gen_store_fpr32(ctx
, fp32
, fd
);
12253 tcg_temp_free_i32(fp32
);
12257 check_cp1_64bitmode(ctx
);
12259 TCGv_i64 fp0
= tcg_temp_new_i64();
12261 gen_load_fpr64(ctx
, fp0
, fs
);
12262 gen_helper_float_cvtd_l(fp0
, cpu_env
, fp0
);
12263 gen_store_fpr64(ctx
, fp0
, fd
);
12264 tcg_temp_free_i64(fp0
);
12267 case OPC_CVT_PS_PW
:
12270 TCGv_i64 fp0
= tcg_temp_new_i64();
12272 gen_load_fpr64(ctx
, fp0
, fs
);
12273 gen_helper_float_cvtps_pw(fp0
, cpu_env
, fp0
);
12274 gen_store_fpr64(ctx
, fp0
, fd
);
12275 tcg_temp_free_i64(fp0
);
12281 TCGv_i64 fp0
= tcg_temp_new_i64();
12282 TCGv_i64 fp1
= tcg_temp_new_i64();
12284 gen_load_fpr64(ctx
, fp0
, fs
);
12285 gen_load_fpr64(ctx
, fp1
, ft
);
12286 gen_helper_float_add_ps(fp0
, cpu_env
, fp0
, fp1
);
12287 tcg_temp_free_i64(fp1
);
12288 gen_store_fpr64(ctx
, fp0
, fd
);
12289 tcg_temp_free_i64(fp0
);
12295 TCGv_i64 fp0
= tcg_temp_new_i64();
12296 TCGv_i64 fp1
= tcg_temp_new_i64();
12298 gen_load_fpr64(ctx
, fp0
, fs
);
12299 gen_load_fpr64(ctx
, fp1
, ft
);
12300 gen_helper_float_sub_ps(fp0
, cpu_env
, fp0
, fp1
);
12301 tcg_temp_free_i64(fp1
);
12302 gen_store_fpr64(ctx
, fp0
, fd
);
12303 tcg_temp_free_i64(fp0
);
12309 TCGv_i64 fp0
= tcg_temp_new_i64();
12310 TCGv_i64 fp1
= tcg_temp_new_i64();
12312 gen_load_fpr64(ctx
, fp0
, fs
);
12313 gen_load_fpr64(ctx
, fp1
, ft
);
12314 gen_helper_float_mul_ps(fp0
, cpu_env
, fp0
, fp1
);
12315 tcg_temp_free_i64(fp1
);
12316 gen_store_fpr64(ctx
, fp0
, fd
);
12317 tcg_temp_free_i64(fp0
);
12323 TCGv_i64 fp0
= tcg_temp_new_i64();
12325 gen_load_fpr64(ctx
, fp0
, fs
);
12326 gen_helper_float_abs_ps(fp0
, fp0
);
12327 gen_store_fpr64(ctx
, fp0
, fd
);
12328 tcg_temp_free_i64(fp0
);
12334 TCGv_i64 fp0
= tcg_temp_new_i64();
12336 gen_load_fpr64(ctx
, fp0
, fs
);
12337 gen_store_fpr64(ctx
, fp0
, fd
);
12338 tcg_temp_free_i64(fp0
);
12344 TCGv_i64 fp0
= tcg_temp_new_i64();
12346 gen_load_fpr64(ctx
, fp0
, fs
);
12347 gen_helper_float_chs_ps(fp0
, fp0
);
12348 gen_store_fpr64(ctx
, fp0
, fd
);
12349 tcg_temp_free_i64(fp0
);
12354 gen_movcf_ps(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
12359 TCGLabel
*l1
= gen_new_label();
12363 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
12365 fp0
= tcg_temp_new_i64();
12366 gen_load_fpr64(ctx
, fp0
, fs
);
12367 gen_store_fpr64(ctx
, fp0
, fd
);
12368 tcg_temp_free_i64(fp0
);
12375 TCGLabel
*l1
= gen_new_label();
12379 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
12380 fp0
= tcg_temp_new_i64();
12381 gen_load_fpr64(ctx
, fp0
, fs
);
12382 gen_store_fpr64(ctx
, fp0
, fd
);
12383 tcg_temp_free_i64(fp0
);
12391 TCGv_i64 fp0
= tcg_temp_new_i64();
12392 TCGv_i64 fp1
= tcg_temp_new_i64();
12394 gen_load_fpr64(ctx
, fp0
, ft
);
12395 gen_load_fpr64(ctx
, fp1
, fs
);
12396 gen_helper_float_addr_ps(fp0
, cpu_env
, fp0
, fp1
);
12397 tcg_temp_free_i64(fp1
);
12398 gen_store_fpr64(ctx
, fp0
, fd
);
12399 tcg_temp_free_i64(fp0
);
12405 TCGv_i64 fp0
= tcg_temp_new_i64();
12406 TCGv_i64 fp1
= tcg_temp_new_i64();
12408 gen_load_fpr64(ctx
, fp0
, ft
);
12409 gen_load_fpr64(ctx
, fp1
, fs
);
12410 gen_helper_float_mulr_ps(fp0
, cpu_env
, fp0
, fp1
);
12411 tcg_temp_free_i64(fp1
);
12412 gen_store_fpr64(ctx
, fp0
, fd
);
12413 tcg_temp_free_i64(fp0
);
12416 case OPC_RECIP2_PS
:
12419 TCGv_i64 fp0
= tcg_temp_new_i64();
12420 TCGv_i64 fp1
= tcg_temp_new_i64();
12422 gen_load_fpr64(ctx
, fp0
, fs
);
12423 gen_load_fpr64(ctx
, fp1
, ft
);
12424 gen_helper_float_recip2_ps(fp0
, cpu_env
, fp0
, fp1
);
12425 tcg_temp_free_i64(fp1
);
12426 gen_store_fpr64(ctx
, fp0
, fd
);
12427 tcg_temp_free_i64(fp0
);
12430 case OPC_RECIP1_PS
:
12433 TCGv_i64 fp0
= tcg_temp_new_i64();
12435 gen_load_fpr64(ctx
, fp0
, fs
);
12436 gen_helper_float_recip1_ps(fp0
, cpu_env
, fp0
);
12437 gen_store_fpr64(ctx
, fp0
, fd
);
12438 tcg_temp_free_i64(fp0
);
12441 case OPC_RSQRT1_PS
:
12444 TCGv_i64 fp0
= tcg_temp_new_i64();
12446 gen_load_fpr64(ctx
, fp0
, fs
);
12447 gen_helper_float_rsqrt1_ps(fp0
, cpu_env
, fp0
);
12448 gen_store_fpr64(ctx
, fp0
, fd
);
12449 tcg_temp_free_i64(fp0
);
12452 case OPC_RSQRT2_PS
:
12455 TCGv_i64 fp0
= tcg_temp_new_i64();
12456 TCGv_i64 fp1
= tcg_temp_new_i64();
12458 gen_load_fpr64(ctx
, fp0
, fs
);
12459 gen_load_fpr64(ctx
, fp1
, ft
);
12460 gen_helper_float_rsqrt2_ps(fp0
, cpu_env
, fp0
, fp1
);
12461 tcg_temp_free_i64(fp1
);
12462 gen_store_fpr64(ctx
, fp0
, fd
);
12463 tcg_temp_free_i64(fp0
);
12467 check_cp1_64bitmode(ctx
);
12469 TCGv_i32 fp0
= tcg_temp_new_i32();
12471 gen_load_fpr32h(ctx
, fp0
, fs
);
12472 gen_helper_float_cvts_pu(fp0
, cpu_env
, fp0
);
12473 gen_store_fpr32(ctx
, fp0
, fd
);
12474 tcg_temp_free_i32(fp0
);
12477 case OPC_CVT_PW_PS
:
12480 TCGv_i64 fp0
= tcg_temp_new_i64();
12482 gen_load_fpr64(ctx
, fp0
, fs
);
12483 gen_helper_float_cvtpw_ps(fp0
, cpu_env
, fp0
);
12484 gen_store_fpr64(ctx
, fp0
, fd
);
12485 tcg_temp_free_i64(fp0
);
12489 check_cp1_64bitmode(ctx
);
12491 TCGv_i32 fp0
= tcg_temp_new_i32();
12493 gen_load_fpr32(ctx
, fp0
, fs
);
12494 gen_helper_float_cvts_pl(fp0
, cpu_env
, fp0
);
12495 gen_store_fpr32(ctx
, fp0
, fd
);
12496 tcg_temp_free_i32(fp0
);
12502 TCGv_i32 fp0
= tcg_temp_new_i32();
12503 TCGv_i32 fp1
= tcg_temp_new_i32();
12505 gen_load_fpr32(ctx
, fp0
, fs
);
12506 gen_load_fpr32(ctx
, fp1
, ft
);
12507 gen_store_fpr32h(ctx
, fp0
, fd
);
12508 gen_store_fpr32(ctx
, fp1
, fd
);
12509 tcg_temp_free_i32(fp0
);
12510 tcg_temp_free_i32(fp1
);
12516 TCGv_i32 fp0
= tcg_temp_new_i32();
12517 TCGv_i32 fp1
= tcg_temp_new_i32();
12519 gen_load_fpr32(ctx
, fp0
, fs
);
12520 gen_load_fpr32h(ctx
, fp1
, ft
);
12521 gen_store_fpr32(ctx
, fp1
, fd
);
12522 gen_store_fpr32h(ctx
, fp0
, fd
);
12523 tcg_temp_free_i32(fp0
);
12524 tcg_temp_free_i32(fp1
);
12530 TCGv_i32 fp0
= tcg_temp_new_i32();
12531 TCGv_i32 fp1
= tcg_temp_new_i32();
12533 gen_load_fpr32h(ctx
, fp0
, fs
);
12534 gen_load_fpr32(ctx
, fp1
, ft
);
12535 gen_store_fpr32(ctx
, fp1
, fd
);
12536 gen_store_fpr32h(ctx
, fp0
, fd
);
12537 tcg_temp_free_i32(fp0
);
12538 tcg_temp_free_i32(fp1
);
12544 TCGv_i32 fp0
= tcg_temp_new_i32();
12545 TCGv_i32 fp1
= tcg_temp_new_i32();
12547 gen_load_fpr32h(ctx
, fp0
, fs
);
12548 gen_load_fpr32h(ctx
, fp1
, ft
);
12549 gen_store_fpr32(ctx
, fp1
, fd
);
12550 gen_store_fpr32h(ctx
, fp0
, fd
);
12551 tcg_temp_free_i32(fp0
);
12552 tcg_temp_free_i32(fp1
);
12556 case OPC_CMP_UN_PS
:
12557 case OPC_CMP_EQ_PS
:
12558 case OPC_CMP_UEQ_PS
:
12559 case OPC_CMP_OLT_PS
:
12560 case OPC_CMP_ULT_PS
:
12561 case OPC_CMP_OLE_PS
:
12562 case OPC_CMP_ULE_PS
:
12563 case OPC_CMP_SF_PS
:
12564 case OPC_CMP_NGLE_PS
:
12565 case OPC_CMP_SEQ_PS
:
12566 case OPC_CMP_NGL_PS
:
12567 case OPC_CMP_LT_PS
:
12568 case OPC_CMP_NGE_PS
:
12569 case OPC_CMP_LE_PS
:
12570 case OPC_CMP_NGT_PS
:
12571 if (ctx
->opcode
& (1 << 6)) {
12572 gen_cmpabs_ps(ctx
, func
- 48, ft
, fs
, cc
);
12574 gen_cmp_ps(ctx
, func
- 48, ft
, fs
, cc
);
12578 MIPS_INVAL("farith");
12579 generate_exception_end(ctx
, EXCP_RI
);
12584 /* Coprocessor 3 (FPU) */
12585 static void gen_flt3_ldst(DisasContext
*ctx
, uint32_t opc
,
12586 int fd
, int fs
, int base
, int index
)
12588 TCGv t0
= tcg_temp_new();
12591 gen_load_gpr(t0
, index
);
12592 } else if (index
== 0) {
12593 gen_load_gpr(t0
, base
);
12595 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], cpu_gpr
[index
]);
12598 * Don't do NOP if destination is zero: we must perform the actual
12605 TCGv_i32 fp0
= tcg_temp_new_i32();
12607 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESL
);
12608 tcg_gen_trunc_tl_i32(fp0
, t0
);
12609 gen_store_fpr32(ctx
, fp0
, fd
);
12610 tcg_temp_free_i32(fp0
);
12615 check_cp1_registers(ctx
, fd
);
12617 TCGv_i64 fp0
= tcg_temp_new_i64();
12618 tcg_gen_qemu_ld_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
12619 gen_store_fpr64(ctx
, fp0
, fd
);
12620 tcg_temp_free_i64(fp0
);
12624 check_cp1_64bitmode(ctx
);
12625 tcg_gen_andi_tl(t0
, t0
, ~0x7);
12627 TCGv_i64 fp0
= tcg_temp_new_i64();
12629 tcg_gen_qemu_ld_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
12630 gen_store_fpr64(ctx
, fp0
, fd
);
12631 tcg_temp_free_i64(fp0
);
12637 TCGv_i32 fp0
= tcg_temp_new_i32();
12638 gen_load_fpr32(ctx
, fp0
, fs
);
12639 tcg_gen_qemu_st_i32(fp0
, t0
, ctx
->mem_idx
, MO_TEUL
);
12640 tcg_temp_free_i32(fp0
);
12645 check_cp1_registers(ctx
, fs
);
12647 TCGv_i64 fp0
= tcg_temp_new_i64();
12648 gen_load_fpr64(ctx
, fp0
, fs
);
12649 tcg_gen_qemu_st_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
12650 tcg_temp_free_i64(fp0
);
12654 check_cp1_64bitmode(ctx
);
12655 tcg_gen_andi_tl(t0
, t0
, ~0x7);
12657 TCGv_i64 fp0
= tcg_temp_new_i64();
12658 gen_load_fpr64(ctx
, fp0
, fs
);
12659 tcg_gen_qemu_st_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
12660 tcg_temp_free_i64(fp0
);
12667 static void gen_flt3_arith(DisasContext
*ctx
, uint32_t opc
,
12668 int fd
, int fr
, int fs
, int ft
)
12674 TCGv t0
= tcg_temp_local_new();
12675 TCGv_i32 fp
= tcg_temp_new_i32();
12676 TCGv_i32 fph
= tcg_temp_new_i32();
12677 TCGLabel
*l1
= gen_new_label();
12678 TCGLabel
*l2
= gen_new_label();
12680 gen_load_gpr(t0
, fr
);
12681 tcg_gen_andi_tl(t0
, t0
, 0x7);
12683 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
12684 gen_load_fpr32(ctx
, fp
, fs
);
12685 gen_load_fpr32h(ctx
, fph
, fs
);
12686 gen_store_fpr32(ctx
, fp
, fd
);
12687 gen_store_fpr32h(ctx
, fph
, fd
);
12690 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
12692 #ifdef TARGET_WORDS_BIGENDIAN
12693 gen_load_fpr32(ctx
, fp
, fs
);
12694 gen_load_fpr32h(ctx
, fph
, ft
);
12695 gen_store_fpr32h(ctx
, fp
, fd
);
12696 gen_store_fpr32(ctx
, fph
, fd
);
12698 gen_load_fpr32h(ctx
, fph
, fs
);
12699 gen_load_fpr32(ctx
, fp
, ft
);
12700 gen_store_fpr32(ctx
, fph
, fd
);
12701 gen_store_fpr32h(ctx
, fp
, fd
);
12704 tcg_temp_free_i32(fp
);
12705 tcg_temp_free_i32(fph
);
12711 TCGv_i32 fp0
= tcg_temp_new_i32();
12712 TCGv_i32 fp1
= tcg_temp_new_i32();
12713 TCGv_i32 fp2
= tcg_temp_new_i32();
12715 gen_load_fpr32(ctx
, fp0
, fs
);
12716 gen_load_fpr32(ctx
, fp1
, ft
);
12717 gen_load_fpr32(ctx
, fp2
, fr
);
12718 gen_helper_float_madd_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12719 tcg_temp_free_i32(fp0
);
12720 tcg_temp_free_i32(fp1
);
12721 gen_store_fpr32(ctx
, fp2
, fd
);
12722 tcg_temp_free_i32(fp2
);
12727 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
12729 TCGv_i64 fp0
= tcg_temp_new_i64();
12730 TCGv_i64 fp1
= tcg_temp_new_i64();
12731 TCGv_i64 fp2
= tcg_temp_new_i64();
12733 gen_load_fpr64(ctx
, fp0
, fs
);
12734 gen_load_fpr64(ctx
, fp1
, ft
);
12735 gen_load_fpr64(ctx
, fp2
, fr
);
12736 gen_helper_float_madd_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12737 tcg_temp_free_i64(fp0
);
12738 tcg_temp_free_i64(fp1
);
12739 gen_store_fpr64(ctx
, fp2
, fd
);
12740 tcg_temp_free_i64(fp2
);
12746 TCGv_i64 fp0
= tcg_temp_new_i64();
12747 TCGv_i64 fp1
= tcg_temp_new_i64();
12748 TCGv_i64 fp2
= tcg_temp_new_i64();
12750 gen_load_fpr64(ctx
, fp0
, fs
);
12751 gen_load_fpr64(ctx
, fp1
, ft
);
12752 gen_load_fpr64(ctx
, fp2
, fr
);
12753 gen_helper_float_madd_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12754 tcg_temp_free_i64(fp0
);
12755 tcg_temp_free_i64(fp1
);
12756 gen_store_fpr64(ctx
, fp2
, fd
);
12757 tcg_temp_free_i64(fp2
);
12763 TCGv_i32 fp0
= tcg_temp_new_i32();
12764 TCGv_i32 fp1
= tcg_temp_new_i32();
12765 TCGv_i32 fp2
= tcg_temp_new_i32();
12767 gen_load_fpr32(ctx
, fp0
, fs
);
12768 gen_load_fpr32(ctx
, fp1
, ft
);
12769 gen_load_fpr32(ctx
, fp2
, fr
);
12770 gen_helper_float_msub_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12771 tcg_temp_free_i32(fp0
);
12772 tcg_temp_free_i32(fp1
);
12773 gen_store_fpr32(ctx
, fp2
, fd
);
12774 tcg_temp_free_i32(fp2
);
12779 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
12781 TCGv_i64 fp0
= tcg_temp_new_i64();
12782 TCGv_i64 fp1
= tcg_temp_new_i64();
12783 TCGv_i64 fp2
= tcg_temp_new_i64();
12785 gen_load_fpr64(ctx
, fp0
, fs
);
12786 gen_load_fpr64(ctx
, fp1
, ft
);
12787 gen_load_fpr64(ctx
, fp2
, fr
);
12788 gen_helper_float_msub_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12789 tcg_temp_free_i64(fp0
);
12790 tcg_temp_free_i64(fp1
);
12791 gen_store_fpr64(ctx
, fp2
, fd
);
12792 tcg_temp_free_i64(fp2
);
12798 TCGv_i64 fp0
= tcg_temp_new_i64();
12799 TCGv_i64 fp1
= tcg_temp_new_i64();
12800 TCGv_i64 fp2
= tcg_temp_new_i64();
12802 gen_load_fpr64(ctx
, fp0
, fs
);
12803 gen_load_fpr64(ctx
, fp1
, ft
);
12804 gen_load_fpr64(ctx
, fp2
, fr
);
12805 gen_helper_float_msub_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12806 tcg_temp_free_i64(fp0
);
12807 tcg_temp_free_i64(fp1
);
12808 gen_store_fpr64(ctx
, fp2
, fd
);
12809 tcg_temp_free_i64(fp2
);
12815 TCGv_i32 fp0
= tcg_temp_new_i32();
12816 TCGv_i32 fp1
= tcg_temp_new_i32();
12817 TCGv_i32 fp2
= tcg_temp_new_i32();
12819 gen_load_fpr32(ctx
, fp0
, fs
);
12820 gen_load_fpr32(ctx
, fp1
, ft
);
12821 gen_load_fpr32(ctx
, fp2
, fr
);
12822 gen_helper_float_nmadd_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12823 tcg_temp_free_i32(fp0
);
12824 tcg_temp_free_i32(fp1
);
12825 gen_store_fpr32(ctx
, fp2
, fd
);
12826 tcg_temp_free_i32(fp2
);
12831 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
12833 TCGv_i64 fp0
= tcg_temp_new_i64();
12834 TCGv_i64 fp1
= tcg_temp_new_i64();
12835 TCGv_i64 fp2
= tcg_temp_new_i64();
12837 gen_load_fpr64(ctx
, fp0
, fs
);
12838 gen_load_fpr64(ctx
, fp1
, ft
);
12839 gen_load_fpr64(ctx
, fp2
, fr
);
12840 gen_helper_float_nmadd_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12841 tcg_temp_free_i64(fp0
);
12842 tcg_temp_free_i64(fp1
);
12843 gen_store_fpr64(ctx
, fp2
, fd
);
12844 tcg_temp_free_i64(fp2
);
12850 TCGv_i64 fp0
= tcg_temp_new_i64();
12851 TCGv_i64 fp1
= tcg_temp_new_i64();
12852 TCGv_i64 fp2
= tcg_temp_new_i64();
12854 gen_load_fpr64(ctx
, fp0
, fs
);
12855 gen_load_fpr64(ctx
, fp1
, ft
);
12856 gen_load_fpr64(ctx
, fp2
, fr
);
12857 gen_helper_float_nmadd_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12858 tcg_temp_free_i64(fp0
);
12859 tcg_temp_free_i64(fp1
);
12860 gen_store_fpr64(ctx
, fp2
, fd
);
12861 tcg_temp_free_i64(fp2
);
12867 TCGv_i32 fp0
= tcg_temp_new_i32();
12868 TCGv_i32 fp1
= tcg_temp_new_i32();
12869 TCGv_i32 fp2
= tcg_temp_new_i32();
12871 gen_load_fpr32(ctx
, fp0
, fs
);
12872 gen_load_fpr32(ctx
, fp1
, ft
);
12873 gen_load_fpr32(ctx
, fp2
, fr
);
12874 gen_helper_float_nmsub_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12875 tcg_temp_free_i32(fp0
);
12876 tcg_temp_free_i32(fp1
);
12877 gen_store_fpr32(ctx
, fp2
, fd
);
12878 tcg_temp_free_i32(fp2
);
12883 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
12885 TCGv_i64 fp0
= tcg_temp_new_i64();
12886 TCGv_i64 fp1
= tcg_temp_new_i64();
12887 TCGv_i64 fp2
= tcg_temp_new_i64();
12889 gen_load_fpr64(ctx
, fp0
, fs
);
12890 gen_load_fpr64(ctx
, fp1
, ft
);
12891 gen_load_fpr64(ctx
, fp2
, fr
);
12892 gen_helper_float_nmsub_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12893 tcg_temp_free_i64(fp0
);
12894 tcg_temp_free_i64(fp1
);
12895 gen_store_fpr64(ctx
, fp2
, fd
);
12896 tcg_temp_free_i64(fp2
);
12902 TCGv_i64 fp0
= tcg_temp_new_i64();
12903 TCGv_i64 fp1
= tcg_temp_new_i64();
12904 TCGv_i64 fp2
= tcg_temp_new_i64();
12906 gen_load_fpr64(ctx
, fp0
, fs
);
12907 gen_load_fpr64(ctx
, fp1
, ft
);
12908 gen_load_fpr64(ctx
, fp2
, fr
);
12909 gen_helper_float_nmsub_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
12910 tcg_temp_free_i64(fp0
);
12911 tcg_temp_free_i64(fp1
);
12912 gen_store_fpr64(ctx
, fp2
, fd
);
12913 tcg_temp_free_i64(fp2
);
12917 MIPS_INVAL("flt3_arith");
12918 generate_exception_end(ctx
, EXCP_RI
);
12923 static void gen_rdhwr(DisasContext
*ctx
, int rt
, int rd
, int sel
)
12927 #if !defined(CONFIG_USER_ONLY)
12929 * The Linux kernel will emulate rdhwr if it's not supported natively.
12930 * Therefore only check the ISA in system mode.
12932 check_insn(ctx
, ISA_MIPS32R2
);
12934 t0
= tcg_temp_new();
12938 gen_helper_rdhwr_cpunum(t0
, cpu_env
);
12939 gen_store_gpr(t0
, rt
);
12942 gen_helper_rdhwr_synci_step(t0
, cpu_env
);
12943 gen_store_gpr(t0
, rt
);
12946 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
12949 gen_helper_rdhwr_cc(t0
, cpu_env
);
12950 gen_store_gpr(t0
, rt
);
12952 * Break the TB to be able to take timer interrupts immediately
12953 * after reading count. DISAS_STOP isn't sufficient, we need to ensure
12954 * we break completely out of translated code.
12956 gen_save_pc(ctx
->base
.pc_next
+ 4);
12957 ctx
->base
.is_jmp
= DISAS_EXIT
;
12960 gen_helper_rdhwr_ccres(t0
, cpu_env
);
12961 gen_store_gpr(t0
, rt
);
12964 check_insn(ctx
, ISA_MIPS32R6
);
12967 * Performance counter registers are not implemented other than
12968 * control register 0.
12970 generate_exception(ctx
, EXCP_RI
);
12972 gen_helper_rdhwr_performance(t0
, cpu_env
);
12973 gen_store_gpr(t0
, rt
);
12976 check_insn(ctx
, ISA_MIPS32R6
);
12977 gen_helper_rdhwr_xnp(t0
, cpu_env
);
12978 gen_store_gpr(t0
, rt
);
12981 #if defined(CONFIG_USER_ONLY)
12982 tcg_gen_ld_tl(t0
, cpu_env
,
12983 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
12984 gen_store_gpr(t0
, rt
);
12987 if ((ctx
->hflags
& MIPS_HFLAG_CP0
) ||
12988 (ctx
->hflags
& MIPS_HFLAG_HWRENA_ULR
)) {
12989 tcg_gen_ld_tl(t0
, cpu_env
,
12990 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
12991 gen_store_gpr(t0
, rt
);
12993 generate_exception_end(ctx
, EXCP_RI
);
12997 default: /* Invalid */
12998 MIPS_INVAL("rdhwr");
12999 generate_exception_end(ctx
, EXCP_RI
);
13005 static inline void clear_branch_hflags(DisasContext
*ctx
)
13007 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
13008 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
13009 save_cpu_state(ctx
, 0);
13012 * It is not safe to save ctx->hflags as hflags may be changed
13013 * in execution time by the instruction in delay / forbidden slot.
13015 tcg_gen_andi_i32(hflags
, hflags
, ~MIPS_HFLAG_BMASK
);
13019 static void gen_branch(DisasContext
*ctx
, int insn_bytes
)
13021 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
13022 int proc_hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
13023 /* Branches completion */
13024 clear_branch_hflags(ctx
);
13025 ctx
->base
.is_jmp
= DISAS_NORETURN
;
13026 /* FIXME: Need to clear can_do_io. */
13027 switch (proc_hflags
& MIPS_HFLAG_BMASK_BASE
) {
13028 case MIPS_HFLAG_FBNSLOT
:
13029 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ insn_bytes
);
13032 /* unconditional branch */
13033 if (proc_hflags
& MIPS_HFLAG_BX
) {
13034 tcg_gen_xori_i32(hflags
, hflags
, MIPS_HFLAG_M16
);
13036 gen_goto_tb(ctx
, 0, ctx
->btarget
);
13038 case MIPS_HFLAG_BL
:
13039 /* blikely taken case */
13040 gen_goto_tb(ctx
, 0, ctx
->btarget
);
13042 case MIPS_HFLAG_BC
:
13043 /* Conditional branch */
13045 TCGLabel
*l1
= gen_new_label();
13047 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
13048 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
+ insn_bytes
);
13050 gen_goto_tb(ctx
, 0, ctx
->btarget
);
13053 case MIPS_HFLAG_BR
:
13054 /* unconditional branch to register */
13055 if (ctx
->insn_flags
& (ASE_MIPS16
| ASE_MICROMIPS
)) {
13056 TCGv t0
= tcg_temp_new();
13057 TCGv_i32 t1
= tcg_temp_new_i32();
13059 tcg_gen_andi_tl(t0
, btarget
, 0x1);
13060 tcg_gen_trunc_tl_i32(t1
, t0
);
13062 tcg_gen_andi_i32(hflags
, hflags
, ~(uint32_t)MIPS_HFLAG_M16
);
13063 tcg_gen_shli_i32(t1
, t1
, MIPS_HFLAG_M16_SHIFT
);
13064 tcg_gen_or_i32(hflags
, hflags
, t1
);
13065 tcg_temp_free_i32(t1
);
13067 tcg_gen_andi_tl(cpu_PC
, btarget
, ~(target_ulong
)0x1);
13069 tcg_gen_mov_tl(cpu_PC
, btarget
);
13071 if (ctx
->base
.singlestep_enabled
) {
13072 save_cpu_state(ctx
, 0);
13073 gen_helper_raise_exception_debug(cpu_env
);
13075 tcg_gen_lookup_and_goto_ptr();
13078 fprintf(stderr
, "unknown branch 0x%x\n", proc_hflags
);
13084 /* Compact Branches */
13085 static void gen_compute_compact_branch(DisasContext
*ctx
, uint32_t opc
,
13086 int rs
, int rt
, int32_t offset
)
13088 int bcond_compute
= 0;
13089 TCGv t0
= tcg_temp_new();
13090 TCGv t1
= tcg_temp_new();
13091 int m16_lowbit
= (ctx
->hflags
& MIPS_HFLAG_M16
) != 0;
13093 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
13094 #ifdef MIPS_DEBUG_DISAS
13095 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
13096 "\n", ctx
->base
.pc_next
);
13098 generate_exception_end(ctx
, EXCP_RI
);
13102 /* Load needed operands and calculate btarget */
13104 /* compact branch */
13105 case OPC_BOVC
: /* OPC_BEQZALC, OPC_BEQC */
13106 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC */
13107 gen_load_gpr(t0
, rs
);
13108 gen_load_gpr(t1
, rt
);
13110 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
13111 if (rs
<= rt
&& rs
== 0) {
13112 /* OPC_BEQZALC, OPC_BNEZALC */
13113 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 4 + m16_lowbit
);
13116 case OPC_BLEZC
: /* OPC_BGEZC, OPC_BGEC */
13117 case OPC_BGTZC
: /* OPC_BLTZC, OPC_BLTC */
13118 gen_load_gpr(t0
, rs
);
13119 gen_load_gpr(t1
, rt
);
13121 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
13123 case OPC_BLEZALC
: /* OPC_BGEZALC, OPC_BGEUC */
13124 case OPC_BGTZALC
: /* OPC_BLTZALC, OPC_BLTUC */
13125 if (rs
== 0 || rs
== rt
) {
13126 /* OPC_BLEZALC, OPC_BGEZALC */
13127 /* OPC_BGTZALC, OPC_BLTZALC */
13128 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 4 + m16_lowbit
);
13130 gen_load_gpr(t0
, rs
);
13131 gen_load_gpr(t1
, rt
);
13133 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
13137 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
13142 /* OPC_BEQZC, OPC_BNEZC */
13143 gen_load_gpr(t0
, rs
);
13145 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
13147 /* OPC_JIC, OPC_JIALC */
13148 TCGv tbase
= tcg_temp_new();
13149 TCGv toffset
= tcg_temp_new();
13151 gen_load_gpr(tbase
, rt
);
13152 tcg_gen_movi_tl(toffset
, offset
);
13153 gen_op_addr_add(ctx
, btarget
, tbase
, toffset
);
13154 tcg_temp_free(tbase
);
13155 tcg_temp_free(toffset
);
13159 MIPS_INVAL("Compact branch/jump");
13160 generate_exception_end(ctx
, EXCP_RI
);
13164 if (bcond_compute
== 0) {
13165 /* Uncoditional compact branch */
13168 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 4 + m16_lowbit
);
13171 ctx
->hflags
|= MIPS_HFLAG_BR
;
13174 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 4 + m16_lowbit
);
13177 ctx
->hflags
|= MIPS_HFLAG_B
;
13180 MIPS_INVAL("Compact branch/jump");
13181 generate_exception_end(ctx
, EXCP_RI
);
13185 /* Generating branch here as compact branches don't have delay slot */
13186 gen_branch(ctx
, 4);
13188 /* Conditional compact branch */
13189 TCGLabel
*fs
= gen_new_label();
13190 save_cpu_state(ctx
, 0);
13193 case OPC_BLEZALC
: /* OPC_BGEZALC, OPC_BGEUC */
13194 if (rs
== 0 && rt
!= 0) {
13196 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE
), t1
, 0, fs
);
13197 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
13199 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE
), t1
, 0, fs
);
13202 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU
), t0
, t1
, fs
);
13205 case OPC_BGTZALC
: /* OPC_BLTZALC, OPC_BLTUC */
13206 if (rs
== 0 && rt
!= 0) {
13208 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT
), t1
, 0, fs
);
13209 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
13211 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT
), t1
, 0, fs
);
13214 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU
), t0
, t1
, fs
);
13217 case OPC_BLEZC
: /* OPC_BGEZC, OPC_BGEC */
13218 if (rs
== 0 && rt
!= 0) {
13220 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE
), t1
, 0, fs
);
13221 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
13223 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE
), t1
, 0, fs
);
13226 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE
), t0
, t1
, fs
);
13229 case OPC_BGTZC
: /* OPC_BLTZC, OPC_BLTC */
13230 if (rs
== 0 && rt
!= 0) {
13232 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT
), t1
, 0, fs
);
13233 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
13235 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT
), t1
, 0, fs
);
13238 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT
), t0
, t1
, fs
);
13241 case OPC_BOVC
: /* OPC_BEQZALC, OPC_BEQC */
13242 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC */
13244 /* OPC_BOVC, OPC_BNVC */
13245 TCGv t2
= tcg_temp_new();
13246 TCGv t3
= tcg_temp_new();
13247 TCGv t4
= tcg_temp_new();
13248 TCGv input_overflow
= tcg_temp_new();
13250 gen_load_gpr(t0
, rs
);
13251 gen_load_gpr(t1
, rt
);
13252 tcg_gen_ext32s_tl(t2
, t0
);
13253 tcg_gen_setcond_tl(TCG_COND_NE
, input_overflow
, t2
, t0
);
13254 tcg_gen_ext32s_tl(t3
, t1
);
13255 tcg_gen_setcond_tl(TCG_COND_NE
, t4
, t3
, t1
);
13256 tcg_gen_or_tl(input_overflow
, input_overflow
, t4
);
13258 tcg_gen_add_tl(t4
, t2
, t3
);
13259 tcg_gen_ext32s_tl(t4
, t4
);
13260 tcg_gen_xor_tl(t2
, t2
, t3
);
13261 tcg_gen_xor_tl(t3
, t4
, t3
);
13262 tcg_gen_andc_tl(t2
, t3
, t2
);
13263 tcg_gen_setcondi_tl(TCG_COND_LT
, t4
, t2
, 0);
13264 tcg_gen_or_tl(t4
, t4
, input_overflow
);
13265 if (opc
== OPC_BOVC
) {
13267 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE
), t4
, 0, fs
);
13270 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t4
, 0, fs
);
13272 tcg_temp_free(input_overflow
);
13276 } else if (rs
< rt
&& rs
== 0) {
13277 /* OPC_BEQZALC, OPC_BNEZALC */
13278 if (opc
== OPC_BEQZALC
) {
13280 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t1
, 0, fs
);
13283 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE
), t1
, 0, fs
);
13286 /* OPC_BEQC, OPC_BNEC */
13287 if (opc
== OPC_BEQC
) {
13289 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ
), t0
, t1
, fs
);
13292 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE
), t0
, t1
, fs
);
13297 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t0
, 0, fs
);
13300 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE
), t0
, 0, fs
);
13303 MIPS_INVAL("Compact conditional branch/jump");
13304 generate_exception_end(ctx
, EXCP_RI
);
13308 /* Generating branch here as compact branches don't have delay slot */
13309 gen_goto_tb(ctx
, 1, ctx
->btarget
);
13312 ctx
->hflags
|= MIPS_HFLAG_FBNSLOT
;
13320 /* ISA extensions (ASEs) */
13321 /* MIPS16 extension to MIPS32 */
13323 /* MIPS16 major opcodes */
13325 M16_OPC_ADDIUSP
= 0x00,
13326 M16_OPC_ADDIUPC
= 0x01,
13328 M16_OPC_JAL
= 0x03,
13329 M16_OPC_BEQZ
= 0x04,
13330 M16_OPC_BNEQZ
= 0x05,
13331 M16_OPC_SHIFT
= 0x06,
13333 M16_OPC_RRIA
= 0x08,
13334 M16_OPC_ADDIU8
= 0x09,
13335 M16_OPC_SLTI
= 0x0a,
13336 M16_OPC_SLTIU
= 0x0b,
13339 M16_OPC_CMPI
= 0x0e,
13343 M16_OPC_LWSP
= 0x12,
13345 M16_OPC_LBU
= 0x14,
13346 M16_OPC_LHU
= 0x15,
13347 M16_OPC_LWPC
= 0x16,
13348 M16_OPC_LWU
= 0x17,
13351 M16_OPC_SWSP
= 0x1a,
13353 M16_OPC_RRR
= 0x1c,
13355 M16_OPC_EXTEND
= 0x1e,
13359 /* I8 funct field */
13378 /* RR funct field */
13412 /* I64 funct field */
13420 I64_DADDIUPC
= 0x6,
13424 /* RR ry field for CNVT */
13426 RR_RY_CNVT_ZEB
= 0x0,
13427 RR_RY_CNVT_ZEH
= 0x1,
13428 RR_RY_CNVT_ZEW
= 0x2,
13429 RR_RY_CNVT_SEB
= 0x4,
13430 RR_RY_CNVT_SEH
= 0x5,
13431 RR_RY_CNVT_SEW
= 0x6,
13434 static int xlat(int r
)
13436 static int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
13441 static void gen_mips16_save(DisasContext
*ctx
,
13442 int xsregs
, int aregs
,
13443 int do_ra
, int do_s0
, int do_s1
,
13446 TCGv t0
= tcg_temp_new();
13447 TCGv t1
= tcg_temp_new();
13448 TCGv t2
= tcg_temp_new();
13478 generate_exception_end(ctx
, EXCP_RI
);
13484 gen_base_offset_addr(ctx
, t0
, 29, 12);
13485 gen_load_gpr(t1
, 7);
13486 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
13489 gen_base_offset_addr(ctx
, t0
, 29, 8);
13490 gen_load_gpr(t1
, 6);
13491 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
13494 gen_base_offset_addr(ctx
, t0
, 29, 4);
13495 gen_load_gpr(t1
, 5);
13496 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
13499 gen_base_offset_addr(ctx
, t0
, 29, 0);
13500 gen_load_gpr(t1
, 4);
13501 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
13504 gen_load_gpr(t0
, 29);
13506 #define DECR_AND_STORE(reg) do { \
13507 tcg_gen_movi_tl(t2, -4); \
13508 gen_op_addr_add(ctx, t0, t0, t2); \
13509 gen_load_gpr(t1, reg); \
13510 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
13514 DECR_AND_STORE(31);
13519 DECR_AND_STORE(30);
13522 DECR_AND_STORE(23);
13525 DECR_AND_STORE(22);
13528 DECR_AND_STORE(21);
13531 DECR_AND_STORE(20);
13534 DECR_AND_STORE(19);
13537 DECR_AND_STORE(18);
13541 DECR_AND_STORE(17);
13544 DECR_AND_STORE(16);
13574 generate_exception_end(ctx
, EXCP_RI
);
13590 #undef DECR_AND_STORE
13592 tcg_gen_movi_tl(t2
, -framesize
);
13593 gen_op_addr_add(ctx
, cpu_gpr
[29], cpu_gpr
[29], t2
);
13599 static void gen_mips16_restore(DisasContext
*ctx
,
13600 int xsregs
, int aregs
,
13601 int do_ra
, int do_s0
, int do_s1
,
13605 TCGv t0
= tcg_temp_new();
13606 TCGv t1
= tcg_temp_new();
13607 TCGv t2
= tcg_temp_new();
13609 tcg_gen_movi_tl(t2
, framesize
);
13610 gen_op_addr_add(ctx
, t0
, cpu_gpr
[29], t2
);
13612 #define DECR_AND_LOAD(reg) do { \
13613 tcg_gen_movi_tl(t2, -4); \
13614 gen_op_addr_add(ctx, t0, t0, t2); \
13615 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
13616 gen_store_gpr(t1, reg); \
13680 generate_exception_end(ctx
, EXCP_RI
);
13696 #undef DECR_AND_LOAD
13698 tcg_gen_movi_tl(t2
, framesize
);
13699 gen_op_addr_add(ctx
, cpu_gpr
[29], cpu_gpr
[29], t2
);
13705 static void gen_addiupc(DisasContext
*ctx
, int rx
, int imm
,
13706 int is_64_bit
, int extended
)
13710 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
13711 generate_exception_end(ctx
, EXCP_RI
);
13715 t0
= tcg_temp_new();
13717 tcg_gen_movi_tl(t0
, pc_relative_pc(ctx
));
13718 tcg_gen_addi_tl(cpu_gpr
[rx
], t0
, imm
);
13720 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
13726 static void gen_cache_operation(DisasContext
*ctx
, uint32_t op
, int base
,
13729 TCGv_i32 t0
= tcg_const_i32(op
);
13730 TCGv t1
= tcg_temp_new();
13731 gen_base_offset_addr(ctx
, t1
, base
, offset
);
13732 gen_helper_cache(cpu_env
, t1
, t0
);
13735 #if defined(TARGET_MIPS64)
13736 static void decode_i64_mips16(DisasContext
*ctx
,
13737 int ry
, int funct
, int16_t offset
,
13742 check_insn(ctx
, ISA_MIPS3
);
13743 check_mips_64(ctx
);
13744 offset
= extended
? offset
: offset
<< 3;
13745 gen_ld(ctx
, OPC_LD
, ry
, 29, offset
);
13748 check_insn(ctx
, ISA_MIPS3
);
13749 check_mips_64(ctx
);
13750 offset
= extended
? offset
: offset
<< 3;
13751 gen_st(ctx
, OPC_SD
, ry
, 29, offset
);
13754 check_insn(ctx
, ISA_MIPS3
);
13755 check_mips_64(ctx
);
13756 offset
= extended
? offset
: (ctx
->opcode
& 0xff) << 3;
13757 gen_st(ctx
, OPC_SD
, 31, 29, offset
);
13760 check_insn(ctx
, ISA_MIPS3
);
13761 check_mips_64(ctx
);
13762 offset
= extended
? offset
: ((int8_t)ctx
->opcode
) << 3;
13763 gen_arith_imm(ctx
, OPC_DADDIU
, 29, 29, offset
);
13766 check_insn(ctx
, ISA_MIPS3
);
13767 check_mips_64(ctx
);
13768 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
13769 generate_exception_end(ctx
, EXCP_RI
);
13771 offset
= extended
? offset
: offset
<< 3;
13772 gen_ld(ctx
, OPC_LDPC
, ry
, 0, offset
);
13776 check_insn(ctx
, ISA_MIPS3
);
13777 check_mips_64(ctx
);
13778 offset
= extended
? offset
: ((int8_t)(offset
<< 3)) >> 3;
13779 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, ry
, offset
);
13782 check_insn(ctx
, ISA_MIPS3
);
13783 check_mips_64(ctx
);
13784 offset
= extended
? offset
: offset
<< 2;
13785 gen_addiupc(ctx
, ry
, offset
, 1, extended
);
13788 check_insn(ctx
, ISA_MIPS3
);
13789 check_mips_64(ctx
);
13790 offset
= extended
? offset
: offset
<< 2;
13791 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, 29, offset
);
13797 static int decode_extended_mips16_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
13799 int extend
= cpu_lduw_code(env
, ctx
->base
.pc_next
+ 2);
13800 int op
, rx
, ry
, funct
, sa
;
13801 int16_t imm
, offset
;
13803 ctx
->opcode
= (ctx
->opcode
<< 16) | extend
;
13804 op
= (ctx
->opcode
>> 11) & 0x1f;
13805 sa
= (ctx
->opcode
>> 22) & 0x1f;
13806 funct
= (ctx
->opcode
>> 8) & 0x7;
13807 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
13808 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
13809 offset
= imm
= (int16_t) (((ctx
->opcode
>> 16) & 0x1f) << 11
13810 | ((ctx
->opcode
>> 21) & 0x3f) << 5
13811 | (ctx
->opcode
& 0x1f));
13814 * The extended opcodes cleverly reuse the opcodes from their 16-bit
13818 case M16_OPC_ADDIUSP
:
13819 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, 29, imm
);
13821 case M16_OPC_ADDIUPC
:
13822 gen_addiupc(ctx
, rx
, imm
, 0, 1);
13825 gen_compute_branch(ctx
, OPC_BEQ
, 4, 0, 0, offset
<< 1, 0);
13826 /* No delay slot, so just process as a normal instruction */
13829 gen_compute_branch(ctx
, OPC_BEQ
, 4, rx
, 0, offset
<< 1, 0);
13830 /* No delay slot, so just process as a normal instruction */
13832 case M16_OPC_BNEQZ
:
13833 gen_compute_branch(ctx
, OPC_BNE
, 4, rx
, 0, offset
<< 1, 0);
13834 /* No delay slot, so just process as a normal instruction */
13836 case M16_OPC_SHIFT
:
13837 switch (ctx
->opcode
& 0x3) {
13839 gen_shift_imm(ctx
, OPC_SLL
, rx
, ry
, sa
);
13842 #if defined(TARGET_MIPS64)
13843 check_mips_64(ctx
);
13844 gen_shift_imm(ctx
, OPC_DSLL
, rx
, ry
, sa
);
13846 generate_exception_end(ctx
, EXCP_RI
);
13850 gen_shift_imm(ctx
, OPC_SRL
, rx
, ry
, sa
);
13853 gen_shift_imm(ctx
, OPC_SRA
, rx
, ry
, sa
);
13857 #if defined(TARGET_MIPS64)
13859 check_insn(ctx
, ISA_MIPS3
);
13860 check_mips_64(ctx
);
13861 gen_ld(ctx
, OPC_LD
, ry
, rx
, offset
);
13865 imm
= ctx
->opcode
& 0xf;
13866 imm
= imm
| ((ctx
->opcode
>> 20) & 0x7f) << 4;
13867 imm
= imm
| ((ctx
->opcode
>> 16) & 0xf) << 11;
13868 imm
= (int16_t) (imm
<< 1) >> 1;
13869 if ((ctx
->opcode
>> 4) & 0x1) {
13870 #if defined(TARGET_MIPS64)
13871 check_mips_64(ctx
);
13872 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, rx
, imm
);
13874 generate_exception_end(ctx
, EXCP_RI
);
13877 gen_arith_imm(ctx
, OPC_ADDIU
, ry
, rx
, imm
);
13880 case M16_OPC_ADDIU8
:
13881 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, rx
, imm
);
13884 gen_slt_imm(ctx
, OPC_SLTI
, 24, rx
, imm
);
13886 case M16_OPC_SLTIU
:
13887 gen_slt_imm(ctx
, OPC_SLTIU
, 24, rx
, imm
);
13892 gen_compute_branch(ctx
, OPC_BEQ
, 4, 24, 0, offset
<< 1, 0);
13895 gen_compute_branch(ctx
, OPC_BNE
, 4, 24, 0, offset
<< 1, 0);
13898 gen_st(ctx
, OPC_SW
, 31, 29, imm
);
13901 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, imm
);
13904 check_insn(ctx
, ISA_MIPS32
);
13906 int xsregs
= (ctx
->opcode
>> 24) & 0x7;
13907 int aregs
= (ctx
->opcode
>> 16) & 0xf;
13908 int do_ra
= (ctx
->opcode
>> 6) & 0x1;
13909 int do_s0
= (ctx
->opcode
>> 5) & 0x1;
13910 int do_s1
= (ctx
->opcode
>> 4) & 0x1;
13911 int framesize
= (((ctx
->opcode
>> 20) & 0xf) << 4
13912 | (ctx
->opcode
& 0xf)) << 3;
13914 if (ctx
->opcode
& (1 << 7)) {
13915 gen_mips16_save(ctx
, xsregs
, aregs
,
13916 do_ra
, do_s0
, do_s1
,
13919 gen_mips16_restore(ctx
, xsregs
, aregs
,
13920 do_ra
, do_s0
, do_s1
,
13926 generate_exception_end(ctx
, EXCP_RI
);
13931 tcg_gen_movi_tl(cpu_gpr
[rx
], (uint16_t) imm
);
13934 tcg_gen_xori_tl(cpu_gpr
[24], cpu_gpr
[rx
], (uint16_t) imm
);
13936 #if defined(TARGET_MIPS64)
13938 check_insn(ctx
, ISA_MIPS3
);
13939 check_mips_64(ctx
);
13940 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
);
13944 gen_ld(ctx
, OPC_LB
, ry
, rx
, offset
);
13947 gen_ld(ctx
, OPC_LH
, ry
, rx
, offset
);
13950 gen_ld(ctx
, OPC_LW
, rx
, 29, offset
);
13953 gen_ld(ctx
, OPC_LW
, ry
, rx
, offset
);
13956 gen_ld(ctx
, OPC_LBU
, ry
, rx
, offset
);
13959 gen_ld(ctx
, OPC_LHU
, ry
, rx
, offset
);
13962 gen_ld(ctx
, OPC_LWPC
, rx
, 0, offset
);
13964 #if defined(TARGET_MIPS64)
13966 check_insn(ctx
, ISA_MIPS3
);
13967 check_mips_64(ctx
);
13968 gen_ld(ctx
, OPC_LWU
, ry
, rx
, offset
);
13972 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
13975 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
);
13978 gen_st(ctx
, OPC_SW
, rx
, 29, offset
);
13981 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
);
13983 #if defined(TARGET_MIPS64)
13985 decode_i64_mips16(ctx
, ry
, funct
, offset
, 1);
13989 generate_exception_end(ctx
, EXCP_RI
);
13996 static inline bool is_uhi(int sdbbp_code
)
13998 #ifdef CONFIG_USER_ONLY
14001 return semihosting_enabled() && sdbbp_code
== 1;
14005 #ifdef CONFIG_USER_ONLY
14006 /* The above should dead-code away any calls to this..*/
14007 static inline void gen_helper_do_semihosting(void *env
)
14009 g_assert_not_reached();
14013 static int decode_mips16_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
14017 int op
, cnvt_op
, op1
, offset
;
14021 op
= (ctx
->opcode
>> 11) & 0x1f;
14022 sa
= (ctx
->opcode
>> 2) & 0x7;
14023 sa
= sa
== 0 ? 8 : sa
;
14024 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
14025 cnvt_op
= (ctx
->opcode
>> 5) & 0x7;
14026 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
14027 op1
= offset
= ctx
->opcode
& 0x1f;
14032 case M16_OPC_ADDIUSP
:
14034 int16_t imm
= ((uint8_t) ctx
->opcode
) << 2;
14036 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, 29, imm
);
14039 case M16_OPC_ADDIUPC
:
14040 gen_addiupc(ctx
, rx
, ((uint8_t) ctx
->opcode
) << 2, 0, 0);
14043 offset
= (ctx
->opcode
& 0x7ff) << 1;
14044 offset
= (int16_t)(offset
<< 4) >> 4;
14045 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0, offset
, 0);
14046 /* No delay slot, so just process as a normal instruction */
14049 offset
= cpu_lduw_code(env
, ctx
->base
.pc_next
+ 2);
14050 offset
= (((ctx
->opcode
& 0x1f) << 21)
14051 | ((ctx
->opcode
>> 5) & 0x1f) << 16
14053 op
= ((ctx
->opcode
>> 10) & 0x1) ? OPC_JALX
: OPC_JAL
;
14054 gen_compute_branch(ctx
, op
, 4, rx
, ry
, offset
, 2);
14058 gen_compute_branch(ctx
, OPC_BEQ
, 2, rx
, 0,
14059 ((int8_t)ctx
->opcode
) << 1, 0);
14060 /* No delay slot, so just process as a normal instruction */
14062 case M16_OPC_BNEQZ
:
14063 gen_compute_branch(ctx
, OPC_BNE
, 2, rx
, 0,
14064 ((int8_t)ctx
->opcode
) << 1, 0);
14065 /* No delay slot, so just process as a normal instruction */
14067 case M16_OPC_SHIFT
:
14068 switch (ctx
->opcode
& 0x3) {
14070 gen_shift_imm(ctx
, OPC_SLL
, rx
, ry
, sa
);
14073 #if defined(TARGET_MIPS64)
14074 check_insn(ctx
, ISA_MIPS3
);
14075 check_mips_64(ctx
);
14076 gen_shift_imm(ctx
, OPC_DSLL
, rx
, ry
, sa
);
14078 generate_exception_end(ctx
, EXCP_RI
);
14082 gen_shift_imm(ctx
, OPC_SRL
, rx
, ry
, sa
);
14085 gen_shift_imm(ctx
, OPC_SRA
, rx
, ry
, sa
);
14089 #if defined(TARGET_MIPS64)
14091 check_insn(ctx
, ISA_MIPS3
);
14092 check_mips_64(ctx
);
14093 gen_ld(ctx
, OPC_LD
, ry
, rx
, offset
<< 3);
14098 int16_t imm
= (int8_t)((ctx
->opcode
& 0xf) << 4) >> 4;
14100 if ((ctx
->opcode
>> 4) & 1) {
14101 #if defined(TARGET_MIPS64)
14102 check_insn(ctx
, ISA_MIPS3
);
14103 check_mips_64(ctx
);
14104 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, rx
, imm
);
14106 generate_exception_end(ctx
, EXCP_RI
);
14109 gen_arith_imm(ctx
, OPC_ADDIU
, ry
, rx
, imm
);
14113 case M16_OPC_ADDIU8
:
14115 int16_t imm
= (int8_t) ctx
->opcode
;
14117 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, rx
, imm
);
14122 int16_t imm
= (uint8_t) ctx
->opcode
;
14123 gen_slt_imm(ctx
, OPC_SLTI
, 24, rx
, imm
);
14126 case M16_OPC_SLTIU
:
14128 int16_t imm
= (uint8_t) ctx
->opcode
;
14129 gen_slt_imm(ctx
, OPC_SLTIU
, 24, rx
, imm
);
14136 funct
= (ctx
->opcode
>> 8) & 0x7;
14139 gen_compute_branch(ctx
, OPC_BEQ
, 2, 24, 0,
14140 ((int8_t)ctx
->opcode
) << 1, 0);
14143 gen_compute_branch(ctx
, OPC_BNE
, 2, 24, 0,
14144 ((int8_t)ctx
->opcode
) << 1, 0);
14147 gen_st(ctx
, OPC_SW
, 31, 29, (ctx
->opcode
& 0xff) << 2);
14150 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29,
14151 ((int8_t)ctx
->opcode
) << 3);
14154 check_insn(ctx
, ISA_MIPS32
);
14156 int do_ra
= ctx
->opcode
& (1 << 6);
14157 int do_s0
= ctx
->opcode
& (1 << 5);
14158 int do_s1
= ctx
->opcode
& (1 << 4);
14159 int framesize
= ctx
->opcode
& 0xf;
14161 if (framesize
== 0) {
14164 framesize
= framesize
<< 3;
14167 if (ctx
->opcode
& (1 << 7)) {
14168 gen_mips16_save(ctx
, 0, 0,
14169 do_ra
, do_s0
, do_s1
, framesize
);
14171 gen_mips16_restore(ctx
, 0, 0,
14172 do_ra
, do_s0
, do_s1
, framesize
);
14178 int rz
= xlat(ctx
->opcode
& 0x7);
14180 reg32
= (((ctx
->opcode
>> 3) & 0x3) << 3) |
14181 ((ctx
->opcode
>> 5) & 0x7);
14182 gen_arith(ctx
, OPC_ADDU
, reg32
, rz
, 0);
14186 reg32
= ctx
->opcode
& 0x1f;
14187 gen_arith(ctx
, OPC_ADDU
, ry
, reg32
, 0);
14190 generate_exception_end(ctx
, EXCP_RI
);
14197 int16_t imm
= (uint8_t) ctx
->opcode
;
14199 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, 0, imm
);
14204 int16_t imm
= (uint8_t) ctx
->opcode
;
14205 gen_logic_imm(ctx
, OPC_XORI
, 24, rx
, imm
);
14208 #if defined(TARGET_MIPS64)
14210 check_insn(ctx
, ISA_MIPS3
);
14211 check_mips_64(ctx
);
14212 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
<< 3);
14216 gen_ld(ctx
, OPC_LB
, ry
, rx
, offset
);
14219 gen_ld(ctx
, OPC_LH
, ry
, rx
, offset
<< 1);
14222 gen_ld(ctx
, OPC_LW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
14225 gen_ld(ctx
, OPC_LW
, ry
, rx
, offset
<< 2);
14228 gen_ld(ctx
, OPC_LBU
, ry
, rx
, offset
);
14231 gen_ld(ctx
, OPC_LHU
, ry
, rx
, offset
<< 1);
14234 gen_ld(ctx
, OPC_LWPC
, rx
, 0, ((uint8_t)ctx
->opcode
) << 2);
14236 #if defined(TARGET_MIPS64)
14238 check_insn(ctx
, ISA_MIPS3
);
14239 check_mips_64(ctx
);
14240 gen_ld(ctx
, OPC_LWU
, ry
, rx
, offset
<< 2);
14244 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
14247 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
<< 1);
14250 gen_st(ctx
, OPC_SW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
14253 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
<< 2);
14257 int rz
= xlat((ctx
->opcode
>> 2) & 0x7);
14260 switch (ctx
->opcode
& 0x3) {
14262 mips32_op
= OPC_ADDU
;
14265 mips32_op
= OPC_SUBU
;
14267 #if defined(TARGET_MIPS64)
14269 mips32_op
= OPC_DADDU
;
14270 check_insn(ctx
, ISA_MIPS3
);
14271 check_mips_64(ctx
);
14274 mips32_op
= OPC_DSUBU
;
14275 check_insn(ctx
, ISA_MIPS3
);
14276 check_mips_64(ctx
);
14280 generate_exception_end(ctx
, EXCP_RI
);
14284 gen_arith(ctx
, mips32_op
, rz
, rx
, ry
);
14293 int nd
= (ctx
->opcode
>> 7) & 0x1;
14294 int link
= (ctx
->opcode
>> 6) & 0x1;
14295 int ra
= (ctx
->opcode
>> 5) & 0x1;
14298 check_insn(ctx
, ISA_MIPS32
);
14307 gen_compute_branch(ctx
, op
, 2, ra
? 31 : rx
, 31, 0,
14312 if (is_uhi(extract32(ctx
->opcode
, 5, 6))) {
14313 gen_helper_do_semihosting(cpu_env
);
14316 * XXX: not clear which exception should be raised
14317 * when in debug mode...
14319 check_insn(ctx
, ISA_MIPS32
);
14320 generate_exception_end(ctx
, EXCP_DBp
);
14324 gen_slt(ctx
, OPC_SLT
, 24, rx
, ry
);
14327 gen_slt(ctx
, OPC_SLTU
, 24, rx
, ry
);
14330 generate_exception_end(ctx
, EXCP_BREAK
);
14333 gen_shift(ctx
, OPC_SLLV
, ry
, rx
, ry
);
14336 gen_shift(ctx
, OPC_SRLV
, ry
, rx
, ry
);
14339 gen_shift(ctx
, OPC_SRAV
, ry
, rx
, ry
);
14341 #if defined(TARGET_MIPS64)
14343 check_insn(ctx
, ISA_MIPS3
);
14344 check_mips_64(ctx
);
14345 gen_shift_imm(ctx
, OPC_DSRL
, ry
, ry
, sa
);
14349 gen_logic(ctx
, OPC_XOR
, 24, rx
, ry
);
14352 gen_arith(ctx
, OPC_SUBU
, rx
, 0, ry
);
14355 gen_logic(ctx
, OPC_AND
, rx
, rx
, ry
);
14358 gen_logic(ctx
, OPC_OR
, rx
, rx
, ry
);
14361 gen_logic(ctx
, OPC_XOR
, rx
, rx
, ry
);
14364 gen_logic(ctx
, OPC_NOR
, rx
, ry
, 0);
14367 gen_HILO(ctx
, OPC_MFHI
, 0, rx
);
14370 check_insn(ctx
, ISA_MIPS32
);
14372 case RR_RY_CNVT_ZEB
:
14373 tcg_gen_ext8u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
14375 case RR_RY_CNVT_ZEH
:
14376 tcg_gen_ext16u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
14378 case RR_RY_CNVT_SEB
:
14379 tcg_gen_ext8s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
14381 case RR_RY_CNVT_SEH
:
14382 tcg_gen_ext16s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
14384 #if defined(TARGET_MIPS64)
14385 case RR_RY_CNVT_ZEW
:
14386 check_insn(ctx
, ISA_MIPS64
);
14387 check_mips_64(ctx
);
14388 tcg_gen_ext32u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
14390 case RR_RY_CNVT_SEW
:
14391 check_insn(ctx
, ISA_MIPS64
);
14392 check_mips_64(ctx
);
14393 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
14397 generate_exception_end(ctx
, EXCP_RI
);
14402 gen_HILO(ctx
, OPC_MFLO
, 0, rx
);
14404 #if defined(TARGET_MIPS64)
14406 check_insn(ctx
, ISA_MIPS3
);
14407 check_mips_64(ctx
);
14408 gen_shift_imm(ctx
, OPC_DSRA
, ry
, ry
, sa
);
14411 check_insn(ctx
, ISA_MIPS3
);
14412 check_mips_64(ctx
);
14413 gen_shift(ctx
, OPC_DSLLV
, ry
, rx
, ry
);
14416 check_insn(ctx
, ISA_MIPS3
);
14417 check_mips_64(ctx
);
14418 gen_shift(ctx
, OPC_DSRLV
, ry
, rx
, ry
);
14421 check_insn(ctx
, ISA_MIPS3
);
14422 check_mips_64(ctx
);
14423 gen_shift(ctx
, OPC_DSRAV
, ry
, rx
, ry
);
14427 gen_muldiv(ctx
, OPC_MULT
, 0, rx
, ry
);
14430 gen_muldiv(ctx
, OPC_MULTU
, 0, rx
, ry
);
14433 gen_muldiv(ctx
, OPC_DIV
, 0, rx
, ry
);
14436 gen_muldiv(ctx
, OPC_DIVU
, 0, rx
, ry
);
14438 #if defined(TARGET_MIPS64)
14440 check_insn(ctx
, ISA_MIPS3
);
14441 check_mips_64(ctx
);
14442 gen_muldiv(ctx
, OPC_DMULT
, 0, rx
, ry
);
14445 check_insn(ctx
, ISA_MIPS3
);
14446 check_mips_64(ctx
);
14447 gen_muldiv(ctx
, OPC_DMULTU
, 0, rx
, ry
);
14450 check_insn(ctx
, ISA_MIPS3
);
14451 check_mips_64(ctx
);
14452 gen_muldiv(ctx
, OPC_DDIV
, 0, rx
, ry
);
14455 check_insn(ctx
, ISA_MIPS3
);
14456 check_mips_64(ctx
);
14457 gen_muldiv(ctx
, OPC_DDIVU
, 0, rx
, ry
);
14461 generate_exception_end(ctx
, EXCP_RI
);
14465 case M16_OPC_EXTEND
:
14466 decode_extended_mips16_opc(env
, ctx
);
14469 #if defined(TARGET_MIPS64)
14471 funct
= (ctx
->opcode
>> 8) & 0x7;
14472 decode_i64_mips16(ctx
, ry
, funct
, offset
, 0);
14476 generate_exception_end(ctx
, EXCP_RI
);
14483 /* microMIPS extension to MIPS32/MIPS64 */
14486 * microMIPS32/microMIPS64 major opcodes
14488 * 1. MIPS Architecture for Programmers Volume II-B:
14489 * The microMIPS32 Instruction Set (Revision 3.05)
14491 * Table 6.2 microMIPS32 Encoding of Major Opcode Field
14493 * 2. MIPS Architecture For Programmers Volume II-A:
14494 * The MIPS64 Instruction Set (Revision 3.51)
14524 POOL32S
= 0x16, /* MIPS64 */
14525 DADDIU32
= 0x17, /* MIPS64 */
14554 /* 0x29 is reserved */
14567 /* 0x31 is reserved */
14580 SD32
= 0x36, /* MIPS64 */
14581 LD32
= 0x37, /* MIPS64 */
14583 /* 0x39 is reserved */
14599 /* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */
14621 /* POOL32A encoding of minor opcode field */
14625 * These opcodes are distinguished only by bits 9..6; those bits are
14626 * what are recorded below.
14664 /* The following can be distinguished by their lower 6 bits. */
14674 /* POOL32AXF encoding of minor opcode field extension */
14677 * 1. MIPS Architecture for Programmers Volume II-B:
14678 * The microMIPS32 Instruction Set (Revision 3.05)
14680 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
14682 * 2. MIPS Architecture for Programmers VolumeIV-e:
14683 * The MIPS DSP Application-Specific Extension
14684 * to the microMIPS32 Architecture (Revision 2.34)
14686 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
14701 /* begin of microMIPS32 DSP */
14703 /* bits 13..12 for 0x01 */
14709 /* bits 13..12 for 0x2a */
14715 /* bits 13..12 for 0x32 */
14719 /* end of microMIPS32 DSP */
14721 /* bits 15..12 for 0x2c */
14738 /* bits 15..12 for 0x34 */
14746 /* bits 15..12 for 0x3c */
14748 JR
= 0x0, /* alias */
14756 /* bits 15..12 for 0x05 */
14760 /* bits 15..12 for 0x0d */
14772 /* bits 15..12 for 0x15 */
14778 /* bits 15..12 for 0x1d */
14782 /* bits 15..12 for 0x2d */
14787 /* bits 15..12 for 0x35 */
14794 /* POOL32B encoding of minor opcode field (bits 15..12) */
14810 /* POOL32C encoding of minor opcode field (bits 15..12) */
14831 /* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */
14844 /* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */
14857 /* POOL32F encoding of minor opcode field (bits 5..0) */
14860 /* These are the bit 7..6 values */
14869 /* These are the bit 8..6 values */
14894 MOVZ_FMT_05
= 0x05,
14928 CABS_COND_FMT
= 0x1c, /* MIPS3D */
14935 /* POOL32Fxf encoding of minor opcode extension field */
14973 /* POOL32I encoding of minor opcode field (bits 25..21) */
15003 /* These overlap and are distinguished by bit16 of the instruction */
15012 /* POOL16A encoding of minor opcode field */
15019 /* POOL16B encoding of minor opcode field */
15026 /* POOL16C encoding of minor opcode field */
15046 /* R6 POOL16C encoding of minor opcode field (bits 0..5) */
15070 /* POOL16D encoding of minor opcode field */
15077 /* POOL16E encoding of minor opcode field */
15084 static int mmreg(int r
)
15086 static const int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
15091 /* Used for 16-bit store instructions. */
15092 static int mmreg2(int r
)
15094 static const int map
[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
15099 #define uMIPS_RD(op) ((op >> 7) & 0x7)
15100 #define uMIPS_RS(op) ((op >> 4) & 0x7)
15101 #define uMIPS_RS2(op) uMIPS_RS(op)
15102 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
15103 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
15104 #define uMIPS_RS5(op) (op & 0x1f)
15106 /* Signed immediate */
15107 #define SIMM(op, start, width) \
15108 ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \
15111 /* Zero-extended immediate */
15112 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width)))
15114 static void gen_addiur1sp(DisasContext
*ctx
)
15116 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
15118 gen_arith_imm(ctx
, OPC_ADDIU
, rd
, 29, ((ctx
->opcode
>> 1) & 0x3f) << 2);
15121 static void gen_addiur2(DisasContext
*ctx
)
15123 static const int decoded_imm
[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
15124 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
15125 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
15127 gen_arith_imm(ctx
, OPC_ADDIU
, rd
, rs
, decoded_imm
[ZIMM(ctx
->opcode
, 1, 3)]);
15130 static void gen_addiusp(DisasContext
*ctx
)
15132 int encoded
= ZIMM(ctx
->opcode
, 1, 9);
15135 if (encoded
<= 1) {
15136 decoded
= 256 + encoded
;
15137 } else if (encoded
<= 255) {
15139 } else if (encoded
<= 509) {
15140 decoded
= encoded
- 512;
15142 decoded
= encoded
- 768;
15145 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, decoded
<< 2);
15148 static void gen_addius5(DisasContext
*ctx
)
15150 int imm
= SIMM(ctx
->opcode
, 1, 4);
15151 int rd
= (ctx
->opcode
>> 5) & 0x1f;
15153 gen_arith_imm(ctx
, OPC_ADDIU
, rd
, rd
, imm
);
15156 static void gen_andi16(DisasContext
*ctx
)
15158 static const int decoded_imm
[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
15159 31, 32, 63, 64, 255, 32768, 65535 };
15160 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
15161 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
15162 int encoded
= ZIMM(ctx
->opcode
, 0, 4);
15164 gen_logic_imm(ctx
, OPC_ANDI
, rd
, rs
, decoded_imm
[encoded
]);
15167 static void gen_ldst_multiple(DisasContext
*ctx
, uint32_t opc
, int reglist
,
15168 int base
, int16_t offset
)
15173 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
15174 generate_exception_end(ctx
, EXCP_RI
);
15178 t0
= tcg_temp_new();
15180 gen_base_offset_addr(ctx
, t0
, base
, offset
);
15182 t1
= tcg_const_tl(reglist
);
15183 t2
= tcg_const_i32(ctx
->mem_idx
);
15185 save_cpu_state(ctx
, 1);
15188 gen_helper_lwm(cpu_env
, t0
, t1
, t2
);
15191 gen_helper_swm(cpu_env
, t0
, t1
, t2
);
15193 #ifdef TARGET_MIPS64
15195 gen_helper_ldm(cpu_env
, t0
, t1
, t2
);
15198 gen_helper_sdm(cpu_env
, t0
, t1
, t2
);
15204 tcg_temp_free_i32(t2
);
15208 static void gen_pool16c_insn(DisasContext
*ctx
)
15210 int rd
= mmreg((ctx
->opcode
>> 3) & 0x7);
15211 int rs
= mmreg(ctx
->opcode
& 0x7);
15213 switch (((ctx
->opcode
) >> 4) & 0x3f) {
15218 gen_logic(ctx
, OPC_NOR
, rd
, rs
, 0);
15224 gen_logic(ctx
, OPC_XOR
, rd
, rd
, rs
);
15230 gen_logic(ctx
, OPC_AND
, rd
, rd
, rs
);
15236 gen_logic(ctx
, OPC_OR
, rd
, rd
, rs
);
15243 static const int lwm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
15244 int offset
= ZIMM(ctx
->opcode
, 0, 4);
15246 gen_ldst_multiple(ctx
, LWM32
, lwm_convert
[(ctx
->opcode
>> 4) & 0x3],
15255 static const int swm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
15256 int offset
= ZIMM(ctx
->opcode
, 0, 4);
15258 gen_ldst_multiple(ctx
, SWM32
, swm_convert
[(ctx
->opcode
>> 4) & 0x3],
15265 int reg
= ctx
->opcode
& 0x1f;
15267 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0, 4);
15273 int reg
= ctx
->opcode
& 0x1f;
15274 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0, 0);
15276 * Let normal delay slot handling in our caller take us
15277 * to the branch target.
15283 gen_compute_branch(ctx
, OPC_JALR
, 2, ctx
->opcode
& 0x1f, 31, 0, 4);
15284 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
15288 gen_compute_branch(ctx
, OPC_JALR
, 2, ctx
->opcode
& 0x1f, 31, 0, 2);
15289 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
15293 gen_HILO(ctx
, OPC_MFHI
, 0, uMIPS_RS5(ctx
->opcode
));
15297 gen_HILO(ctx
, OPC_MFLO
, 0, uMIPS_RS5(ctx
->opcode
));
15300 generate_exception_end(ctx
, EXCP_BREAK
);
15303 if (is_uhi(extract32(ctx
->opcode
, 0, 4))) {
15304 gen_helper_do_semihosting(cpu_env
);
15307 * XXX: not clear which exception should be raised
15308 * when in debug mode...
15310 check_insn(ctx
, ISA_MIPS32
);
15311 generate_exception_end(ctx
, EXCP_DBp
);
15314 case JRADDIUSP
+ 0:
15315 case JRADDIUSP
+ 1:
15317 int imm
= ZIMM(ctx
->opcode
, 0, 5);
15318 gen_compute_branch(ctx
, OPC_JR
, 2, 31, 0, 0, 0);
15319 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, imm
<< 2);
15321 * Let normal delay slot handling in our caller take us
15322 * to the branch target.
15327 generate_exception_end(ctx
, EXCP_RI
);
15332 static inline void gen_movep(DisasContext
*ctx
, int enc_dest
, int enc_rt
,
15335 int rd
, rs
, re
, rt
;
15336 static const int rd_enc
[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
15337 static const int re_enc
[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
15338 static const int rs_rt_enc
[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
15339 rd
= rd_enc
[enc_dest
];
15340 re
= re_enc
[enc_dest
];
15341 rs
= rs_rt_enc
[enc_rs
];
15342 rt
= rs_rt_enc
[enc_rt
];
15344 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
15346 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
15349 tcg_gen_mov_tl(cpu_gpr
[re
], cpu_gpr
[rt
]);
15351 tcg_gen_movi_tl(cpu_gpr
[re
], 0);
15355 static void gen_pool16c_r6_insn(DisasContext
*ctx
)
15357 int rt
= mmreg((ctx
->opcode
>> 7) & 0x7);
15358 int rs
= mmreg((ctx
->opcode
>> 4) & 0x7);
15360 switch (ctx
->opcode
& 0xf) {
15362 gen_logic(ctx
, OPC_NOR
, rt
, rs
, 0);
15365 gen_logic(ctx
, OPC_AND
, rt
, rt
, rs
);
15369 int lwm_converted
= 0x11 + extract32(ctx
->opcode
, 8, 2);
15370 int offset
= extract32(ctx
->opcode
, 4, 4);
15371 gen_ldst_multiple(ctx
, LWM32
, lwm_converted
, 29, offset
<< 2);
15374 case R6_JRC16
: /* JRCADDIUSP */
15375 if ((ctx
->opcode
>> 4) & 1) {
15377 int imm
= extract32(ctx
->opcode
, 5, 5);
15378 gen_compute_branch(ctx
, OPC_JR
, 2, 31, 0, 0, 0);
15379 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, imm
<< 2);
15382 rs
= extract32(ctx
->opcode
, 5, 5);
15383 gen_compute_branch(ctx
, OPC_JR
, 2, rs
, 0, 0, 0);
15395 int enc_dest
= uMIPS_RD(ctx
->opcode
);
15396 int enc_rt
= uMIPS_RS2(ctx
->opcode
);
15397 int enc_rs
= (ctx
->opcode
& 3) | ((ctx
->opcode
>> 1) & 4);
15398 gen_movep(ctx
, enc_dest
, enc_rt
, enc_rs
);
15402 gen_logic(ctx
, OPC_XOR
, rt
, rt
, rs
);
15405 gen_logic(ctx
, OPC_OR
, rt
, rt
, rs
);
15409 int swm_converted
= 0x11 + extract32(ctx
->opcode
, 8, 2);
15410 int offset
= extract32(ctx
->opcode
, 4, 4);
15411 gen_ldst_multiple(ctx
, SWM32
, swm_converted
, 29, offset
<< 2);
15414 case JALRC16
: /* BREAK16, SDBBP16 */
15415 switch (ctx
->opcode
& 0x3f) {
15417 case JALRC16
+ 0x20:
15419 gen_compute_branch(ctx
, OPC_JALR
, 2, (ctx
->opcode
>> 5) & 0x1f,
15424 generate_exception(ctx
, EXCP_BREAK
);
15428 if (is_uhi(extract32(ctx
->opcode
, 6, 4))) {
15429 gen_helper_do_semihosting(cpu_env
);
15431 if (ctx
->hflags
& MIPS_HFLAG_SBRI
) {
15432 generate_exception(ctx
, EXCP_RI
);
15434 generate_exception(ctx
, EXCP_DBp
);
15441 generate_exception(ctx
, EXCP_RI
);
15446 static void gen_ldxs(DisasContext
*ctx
, int base
, int index
, int rd
)
15448 TCGv t0
= tcg_temp_new();
15449 TCGv t1
= tcg_temp_new();
15451 gen_load_gpr(t0
, base
);
15454 gen_load_gpr(t1
, index
);
15455 tcg_gen_shli_tl(t1
, t1
, 2);
15456 gen_op_addr_add(ctx
, t0
, t1
, t0
);
15459 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TESL
);
15460 gen_store_gpr(t1
, rd
);
15466 static void gen_ldst_pair(DisasContext
*ctx
, uint32_t opc
, int rd
,
15467 int base
, int16_t offset
)
15471 if (ctx
->hflags
& MIPS_HFLAG_BMASK
|| rd
== 31) {
15472 generate_exception_end(ctx
, EXCP_RI
);
15476 t0
= tcg_temp_new();
15477 t1
= tcg_temp_new();
15479 gen_base_offset_addr(ctx
, t0
, base
, offset
);
15484 generate_exception_end(ctx
, EXCP_RI
);
15487 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TESL
);
15488 gen_store_gpr(t1
, rd
);
15489 tcg_gen_movi_tl(t1
, 4);
15490 gen_op_addr_add(ctx
, t0
, t0
, t1
);
15491 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TESL
);
15492 gen_store_gpr(t1
, rd
+ 1);
15495 gen_load_gpr(t1
, rd
);
15496 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
15497 tcg_gen_movi_tl(t1
, 4);
15498 gen_op_addr_add(ctx
, t0
, t0
, t1
);
15499 gen_load_gpr(t1
, rd
+ 1);
15500 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
15502 #ifdef TARGET_MIPS64
15505 generate_exception_end(ctx
, EXCP_RI
);
15508 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
15509 gen_store_gpr(t1
, rd
);
15510 tcg_gen_movi_tl(t1
, 8);
15511 gen_op_addr_add(ctx
, t0
, t0
, t1
);
15512 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
15513 gen_store_gpr(t1
, rd
+ 1);
15516 gen_load_gpr(t1
, rd
);
15517 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
15518 tcg_gen_movi_tl(t1
, 8);
15519 gen_op_addr_add(ctx
, t0
, t0
, t1
);
15520 gen_load_gpr(t1
, rd
+ 1);
15521 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
15529 static void gen_sync(int stype
)
15531 TCGBar tcg_mo
= TCG_BAR_SC
;
15534 case 0x4: /* SYNC_WMB */
15535 tcg_mo
|= TCG_MO_ST_ST
;
15537 case 0x10: /* SYNC_MB */
15538 tcg_mo
|= TCG_MO_ALL
;
15540 case 0x11: /* SYNC_ACQUIRE */
15541 tcg_mo
|= TCG_MO_LD_LD
| TCG_MO_LD_ST
;
15543 case 0x12: /* SYNC_RELEASE */
15544 tcg_mo
|= TCG_MO_ST_ST
| TCG_MO_LD_ST
;
15546 case 0x13: /* SYNC_RMB */
15547 tcg_mo
|= TCG_MO_LD_LD
;
15550 tcg_mo
|= TCG_MO_ALL
;
15554 tcg_gen_mb(tcg_mo
);
15557 static void gen_pool32axf(CPUMIPSState
*env
, DisasContext
*ctx
, int rt
, int rs
)
15559 int extension
= (ctx
->opcode
>> 6) & 0x3f;
15560 int minor
= (ctx
->opcode
>> 12) & 0xf;
15561 uint32_t mips32_op
;
15563 switch (extension
) {
15565 mips32_op
= OPC_TEQ
;
15568 mips32_op
= OPC_TGE
;
15571 mips32_op
= OPC_TGEU
;
15574 mips32_op
= OPC_TLT
;
15577 mips32_op
= OPC_TLTU
;
15580 mips32_op
= OPC_TNE
;
15582 gen_trap(ctx
, mips32_op
, rs
, rt
, -1);
15584 #ifndef CONFIG_USER_ONLY
15587 check_cp0_enabled(ctx
);
15589 /* Treat as NOP. */
15592 gen_mfc0(ctx
, cpu_gpr
[rt
], rs
, (ctx
->opcode
>> 11) & 0x7);
15596 check_cp0_enabled(ctx
);
15598 TCGv t0
= tcg_temp_new();
15600 gen_load_gpr(t0
, rt
);
15601 gen_mtc0(ctx
, t0
, rs
, (ctx
->opcode
>> 11) & 0x7);
15607 switch (minor
& 3) {
15609 gen_muldiv(ctx
, OPC_MADD
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
15612 gen_muldiv(ctx
, OPC_MADDU
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
15615 gen_muldiv(ctx
, OPC_MSUB
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
15618 gen_muldiv(ctx
, OPC_MSUBU
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
15621 goto pool32axf_invalid
;
15625 switch (minor
& 3) {
15627 gen_muldiv(ctx
, OPC_MULT
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
15630 gen_muldiv(ctx
, OPC_MULTU
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
15633 goto pool32axf_invalid
;
15639 check_insn(ctx
, ISA_MIPS32R6
);
15640 gen_bitswap(ctx
, OPC_BITSWAP
, rs
, rt
);
15643 gen_bshfl(ctx
, OPC_SEB
, rs
, rt
);
15646 gen_bshfl(ctx
, OPC_SEH
, rs
, rt
);
15649 mips32_op
= OPC_CLO
;
15652 mips32_op
= OPC_CLZ
;
15654 check_insn(ctx
, ISA_MIPS32
);
15655 gen_cl(ctx
, mips32_op
, rt
, rs
);
15658 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15659 gen_rdhwr(ctx
, rt
, rs
, 0);
15662 gen_bshfl(ctx
, OPC_WSBH
, rs
, rt
);
15665 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15666 mips32_op
= OPC_MULT
;
15669 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15670 mips32_op
= OPC_MULTU
;
15673 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15674 mips32_op
= OPC_DIV
;
15677 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15678 mips32_op
= OPC_DIVU
;
15681 check_insn(ctx
, ISA_MIPS32
);
15682 gen_muldiv(ctx
, mips32_op
, 0, rs
, rt
);
15685 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15686 mips32_op
= OPC_MADD
;
15689 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15690 mips32_op
= OPC_MADDU
;
15693 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15694 mips32_op
= OPC_MSUB
;
15697 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15698 mips32_op
= OPC_MSUBU
;
15700 check_insn(ctx
, ISA_MIPS32
);
15701 gen_muldiv(ctx
, mips32_op
, 0, rs
, rt
);
15704 goto pool32axf_invalid
;
15715 generate_exception_err(ctx
, EXCP_CpU
, 2);
15718 goto pool32axf_invalid
;
15723 case JALR
: /* JALRC */
15724 case JALR_HB
: /* JALRC_HB */
15725 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
15726 /* JALRC, JALRC_HB */
15727 gen_compute_branch(ctx
, OPC_JALR
, 4, rs
, rt
, 0, 0);
15729 /* JALR, JALR_HB */
15730 gen_compute_branch(ctx
, OPC_JALR
, 4, rs
, rt
, 0, 4);
15731 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
15736 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15737 gen_compute_branch(ctx
, OPC_JALR
, 4, rs
, rt
, 0, 2);
15738 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
15741 goto pool32axf_invalid
;
15747 check_cp0_enabled(ctx
);
15748 check_insn(ctx
, ISA_MIPS32R2
);
15749 gen_load_srsgpr(rs
, rt
);
15752 check_cp0_enabled(ctx
);
15753 check_insn(ctx
, ISA_MIPS32R2
);
15754 gen_store_srsgpr(rs
, rt
);
15757 goto pool32axf_invalid
;
15760 #ifndef CONFIG_USER_ONLY
15764 mips32_op
= OPC_TLBP
;
15767 mips32_op
= OPC_TLBR
;
15770 mips32_op
= OPC_TLBWI
;
15773 mips32_op
= OPC_TLBWR
;
15776 mips32_op
= OPC_TLBINV
;
15779 mips32_op
= OPC_TLBINVF
;
15782 mips32_op
= OPC_WAIT
;
15785 mips32_op
= OPC_DERET
;
15788 mips32_op
= OPC_ERET
;
15790 gen_cp0(env
, ctx
, mips32_op
, rt
, rs
);
15793 goto pool32axf_invalid
;
15799 check_cp0_enabled(ctx
);
15801 TCGv t0
= tcg_temp_new();
15803 save_cpu_state(ctx
, 1);
15804 gen_helper_di(t0
, cpu_env
);
15805 gen_store_gpr(t0
, rs
);
15807 * Stop translation as we may have switched the execution
15810 ctx
->base
.is_jmp
= DISAS_STOP
;
15815 check_cp0_enabled(ctx
);
15817 TCGv t0
= tcg_temp_new();
15819 save_cpu_state(ctx
, 1);
15820 gen_helper_ei(t0
, cpu_env
);
15821 gen_store_gpr(t0
, rs
);
15823 * DISAS_STOP isn't sufficient, we need to ensure we break out
15824 * of translated code to check for pending interrupts.
15826 gen_save_pc(ctx
->base
.pc_next
+ 4);
15827 ctx
->base
.is_jmp
= DISAS_EXIT
;
15832 goto pool32axf_invalid
;
15839 gen_sync(extract32(ctx
->opcode
, 16, 5));
15842 generate_exception_end(ctx
, EXCP_SYSCALL
);
15845 if (is_uhi(extract32(ctx
->opcode
, 16, 10))) {
15846 gen_helper_do_semihosting(cpu_env
);
15848 check_insn(ctx
, ISA_MIPS32
);
15849 if (ctx
->hflags
& MIPS_HFLAG_SBRI
) {
15850 generate_exception_end(ctx
, EXCP_RI
);
15852 generate_exception_end(ctx
, EXCP_DBp
);
15857 goto pool32axf_invalid
;
15861 switch (minor
& 3) {
15863 gen_HILO(ctx
, OPC_MFHI
, minor
>> 2, rs
);
15866 gen_HILO(ctx
, OPC_MFLO
, minor
>> 2, rs
);
15869 gen_HILO(ctx
, OPC_MTHI
, minor
>> 2, rs
);
15872 gen_HILO(ctx
, OPC_MTLO
, minor
>> 2, rs
);
15875 goto pool32axf_invalid
;
15879 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
15882 gen_HILO(ctx
, OPC_MFHI
, 0, rs
);
15885 gen_HILO(ctx
, OPC_MFLO
, 0, rs
);
15888 gen_HILO(ctx
, OPC_MTHI
, 0, rs
);
15891 gen_HILO(ctx
, OPC_MTLO
, 0, rs
);
15894 goto pool32axf_invalid
;
15899 MIPS_INVAL("pool32axf");
15900 generate_exception_end(ctx
, EXCP_RI
);
15906 * Values for microMIPS fmt field. Variable-width, depending on which
15907 * formats the instruction supports.
15926 static void gen_pool32fxf(DisasContext
*ctx
, int rt
, int rs
)
15928 int extension
= (ctx
->opcode
>> 6) & 0x3ff;
15929 uint32_t mips32_op
;
15931 #define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc)
15932 #define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc)
15933 #define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc)
15935 switch (extension
) {
15936 case FLOAT_1BIT_FMT(CFC1
, 0):
15937 mips32_op
= OPC_CFC1
;
15939 case FLOAT_1BIT_FMT(CTC1
, 0):
15940 mips32_op
= OPC_CTC1
;
15942 case FLOAT_1BIT_FMT(MFC1
, 0):
15943 mips32_op
= OPC_MFC1
;
15945 case FLOAT_1BIT_FMT(MTC1
, 0):
15946 mips32_op
= OPC_MTC1
;
15948 case FLOAT_1BIT_FMT(MFHC1
, 0):
15949 mips32_op
= OPC_MFHC1
;
15951 case FLOAT_1BIT_FMT(MTHC1
, 0):
15952 mips32_op
= OPC_MTHC1
;
15954 gen_cp1(ctx
, mips32_op
, rt
, rs
);
15957 /* Reciprocal square root */
15958 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_S
):
15959 mips32_op
= OPC_RSQRT_S
;
15961 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_D
):
15962 mips32_op
= OPC_RSQRT_D
;
15966 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_S
):
15967 mips32_op
= OPC_SQRT_S
;
15969 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_D
):
15970 mips32_op
= OPC_SQRT_D
;
15974 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_S
):
15975 mips32_op
= OPC_RECIP_S
;
15977 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_D
):
15978 mips32_op
= OPC_RECIP_D
;
15982 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_S
):
15983 mips32_op
= OPC_FLOOR_L_S
;
15985 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_D
):
15986 mips32_op
= OPC_FLOOR_L_D
;
15988 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_S
):
15989 mips32_op
= OPC_FLOOR_W_S
;
15991 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_D
):
15992 mips32_op
= OPC_FLOOR_W_D
;
15996 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_S
):
15997 mips32_op
= OPC_CEIL_L_S
;
15999 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_D
):
16000 mips32_op
= OPC_CEIL_L_D
;
16002 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_S
):
16003 mips32_op
= OPC_CEIL_W_S
;
16005 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_D
):
16006 mips32_op
= OPC_CEIL_W_D
;
16010 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_S
):
16011 mips32_op
= OPC_TRUNC_L_S
;
16013 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_D
):
16014 mips32_op
= OPC_TRUNC_L_D
;
16016 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_S
):
16017 mips32_op
= OPC_TRUNC_W_S
;
16019 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_D
):
16020 mips32_op
= OPC_TRUNC_W_D
;
16024 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_S
):
16025 mips32_op
= OPC_ROUND_L_S
;
16027 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_D
):
16028 mips32_op
= OPC_ROUND_L_D
;
16030 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_S
):
16031 mips32_op
= OPC_ROUND_W_S
;
16033 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_D
):
16034 mips32_op
= OPC_ROUND_W_D
;
16037 /* Integer to floating-point conversion */
16038 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_S
):
16039 mips32_op
= OPC_CVT_L_S
;
16041 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_D
):
16042 mips32_op
= OPC_CVT_L_D
;
16044 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_S
):
16045 mips32_op
= OPC_CVT_W_S
;
16047 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_D
):
16048 mips32_op
= OPC_CVT_W_D
;
16051 /* Paired-foo conversions */
16052 case FLOAT_1BIT_FMT(CVT_S_PL
, 0):
16053 mips32_op
= OPC_CVT_S_PL
;
16055 case FLOAT_1BIT_FMT(CVT_S_PU
, 0):
16056 mips32_op
= OPC_CVT_S_PU
;
16058 case FLOAT_1BIT_FMT(CVT_PW_PS
, 0):
16059 mips32_op
= OPC_CVT_PW_PS
;
16061 case FLOAT_1BIT_FMT(CVT_PS_PW
, 0):
16062 mips32_op
= OPC_CVT_PS_PW
;
16065 /* Floating-point moves */
16066 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_S
):
16067 mips32_op
= OPC_MOV_S
;
16069 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_D
):
16070 mips32_op
= OPC_MOV_D
;
16072 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_PS
):
16073 mips32_op
= OPC_MOV_PS
;
16076 /* Absolute value */
16077 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_S
):
16078 mips32_op
= OPC_ABS_S
;
16080 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_D
):
16081 mips32_op
= OPC_ABS_D
;
16083 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_PS
):
16084 mips32_op
= OPC_ABS_PS
;
16088 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_S
):
16089 mips32_op
= OPC_NEG_S
;
16091 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_D
):
16092 mips32_op
= OPC_NEG_D
;
16094 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_PS
):
16095 mips32_op
= OPC_NEG_PS
;
16098 /* Reciprocal square root step */
16099 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_S
):
16100 mips32_op
= OPC_RSQRT1_S
;
16102 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_D
):
16103 mips32_op
= OPC_RSQRT1_D
;
16105 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_PS
):
16106 mips32_op
= OPC_RSQRT1_PS
;
16109 /* Reciprocal step */
16110 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_S
):
16111 mips32_op
= OPC_RECIP1_S
;
16113 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_D
):
16114 mips32_op
= OPC_RECIP1_S
;
16116 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_PS
):
16117 mips32_op
= OPC_RECIP1_PS
;
16120 /* Conversions from double */
16121 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_S
):
16122 mips32_op
= OPC_CVT_D_S
;
16124 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_W
):
16125 mips32_op
= OPC_CVT_D_W
;
16127 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_L
):
16128 mips32_op
= OPC_CVT_D_L
;
16131 /* Conversions from single */
16132 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_D
):
16133 mips32_op
= OPC_CVT_S_D
;
16135 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_W
):
16136 mips32_op
= OPC_CVT_S_W
;
16138 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_L
):
16139 mips32_op
= OPC_CVT_S_L
;
16141 gen_farith(ctx
, mips32_op
, -1, rs
, rt
, 0);
16144 /* Conditional moves on floating-point codes */
16145 case COND_FLOAT_MOV(MOVT
, 0):
16146 case COND_FLOAT_MOV(MOVT
, 1):
16147 case COND_FLOAT_MOV(MOVT
, 2):
16148 case COND_FLOAT_MOV(MOVT
, 3):
16149 case COND_FLOAT_MOV(MOVT
, 4):
16150 case COND_FLOAT_MOV(MOVT
, 5):
16151 case COND_FLOAT_MOV(MOVT
, 6):
16152 case COND_FLOAT_MOV(MOVT
, 7):
16153 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16154 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 1);
16156 case COND_FLOAT_MOV(MOVF
, 0):
16157 case COND_FLOAT_MOV(MOVF
, 1):
16158 case COND_FLOAT_MOV(MOVF
, 2):
16159 case COND_FLOAT_MOV(MOVF
, 3):
16160 case COND_FLOAT_MOV(MOVF
, 4):
16161 case COND_FLOAT_MOV(MOVF
, 5):
16162 case COND_FLOAT_MOV(MOVF
, 6):
16163 case COND_FLOAT_MOV(MOVF
, 7):
16164 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16165 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 0);
16168 MIPS_INVAL("pool32fxf");
16169 generate_exception_end(ctx
, EXCP_RI
);
16174 static void decode_micromips32_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
16178 int rt
, rs
, rd
, rr
;
16180 uint32_t op
, minor
, minor2
, mips32_op
;
16181 uint32_t cond
, fmt
, cc
;
16183 insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
+ 2);
16184 ctx
->opcode
= (ctx
->opcode
<< 16) | insn
;
16186 rt
= (ctx
->opcode
>> 21) & 0x1f;
16187 rs
= (ctx
->opcode
>> 16) & 0x1f;
16188 rd
= (ctx
->opcode
>> 11) & 0x1f;
16189 rr
= (ctx
->opcode
>> 6) & 0x1f;
16190 imm
= (int16_t) ctx
->opcode
;
16192 op
= (ctx
->opcode
>> 26) & 0x3f;
16195 minor
= ctx
->opcode
& 0x3f;
16198 minor
= (ctx
->opcode
>> 6) & 0xf;
16201 mips32_op
= OPC_SLL
;
16204 mips32_op
= OPC_SRA
;
16207 mips32_op
= OPC_SRL
;
16210 mips32_op
= OPC_ROTR
;
16212 gen_shift_imm(ctx
, mips32_op
, rt
, rs
, rd
);
16215 check_insn(ctx
, ISA_MIPS32R6
);
16216 gen_cond_move(ctx
, OPC_SELEQZ
, rd
, rs
, rt
);
16219 check_insn(ctx
, ISA_MIPS32R6
);
16220 gen_cond_move(ctx
, OPC_SELNEZ
, rd
, rs
, rt
);
16223 check_insn(ctx
, ISA_MIPS32R6
);
16224 gen_rdhwr(ctx
, rt
, rs
, extract32(ctx
->opcode
, 11, 3));
16227 goto pool32a_invalid
;
16231 minor
= (ctx
->opcode
>> 6) & 0xf;
16235 mips32_op
= OPC_ADD
;
16238 mips32_op
= OPC_ADDU
;
16241 mips32_op
= OPC_SUB
;
16244 mips32_op
= OPC_SUBU
;
16247 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16248 mips32_op
= OPC_MUL
;
16250 gen_arith(ctx
, mips32_op
, rd
, rs
, rt
);
16254 mips32_op
= OPC_SLLV
;
16257 mips32_op
= OPC_SRLV
;
16260 mips32_op
= OPC_SRAV
;
16263 mips32_op
= OPC_ROTRV
;
16265 gen_shift(ctx
, mips32_op
, rd
, rs
, rt
);
16267 /* Logical operations */
16269 mips32_op
= OPC_AND
;
16272 mips32_op
= OPC_OR
;
16275 mips32_op
= OPC_NOR
;
16278 mips32_op
= OPC_XOR
;
16280 gen_logic(ctx
, mips32_op
, rd
, rs
, rt
);
16282 /* Set less than */
16284 mips32_op
= OPC_SLT
;
16287 mips32_op
= OPC_SLTU
;
16289 gen_slt(ctx
, mips32_op
, rd
, rs
, rt
);
16292 goto pool32a_invalid
;
16296 minor
= (ctx
->opcode
>> 6) & 0xf;
16298 /* Conditional moves */
16299 case MOVN
: /* MUL */
16300 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16302 gen_r6_muldiv(ctx
, R6_OPC_MUL
, rd
, rs
, rt
);
16305 gen_cond_move(ctx
, OPC_MOVN
, rd
, rs
, rt
);
16308 case MOVZ
: /* MUH */
16309 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16311 gen_r6_muldiv(ctx
, R6_OPC_MUH
, rd
, rs
, rt
);
16314 gen_cond_move(ctx
, OPC_MOVZ
, rd
, rs
, rt
);
16318 check_insn(ctx
, ISA_MIPS32R6
);
16319 gen_r6_muldiv(ctx
, R6_OPC_MULU
, rd
, rs
, rt
);
16322 check_insn(ctx
, ISA_MIPS32R6
);
16323 gen_r6_muldiv(ctx
, R6_OPC_MUHU
, rd
, rs
, rt
);
16325 case LWXS
: /* DIV */
16326 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16328 gen_r6_muldiv(ctx
, R6_OPC_DIV
, rd
, rs
, rt
);
16331 gen_ldxs(ctx
, rs
, rt
, rd
);
16335 check_insn(ctx
, ISA_MIPS32R6
);
16336 gen_r6_muldiv(ctx
, R6_OPC_MOD
, rd
, rs
, rt
);
16339 check_insn(ctx
, ISA_MIPS32R6
);
16340 gen_r6_muldiv(ctx
, R6_OPC_DIVU
, rd
, rs
, rt
);
16343 check_insn(ctx
, ISA_MIPS32R6
);
16344 gen_r6_muldiv(ctx
, R6_OPC_MODU
, rd
, rs
, rt
);
16347 goto pool32a_invalid
;
16351 gen_bitops(ctx
, OPC_INS
, rt
, rs
, rr
, rd
);
16354 check_insn(ctx
, ISA_MIPS32R6
);
16355 gen_lsa(ctx
, OPC_LSA
, rd
, rs
, rt
,
16356 extract32(ctx
->opcode
, 9, 2));
16359 check_insn(ctx
, ISA_MIPS32R6
);
16360 gen_align(ctx
, 32, rd
, rs
, rt
, extract32(ctx
->opcode
, 9, 2));
16363 gen_bitops(ctx
, OPC_EXT
, rt
, rs
, rr
, rd
);
16366 gen_pool32axf(env
, ctx
, rt
, rs
);
16369 generate_exception_end(ctx
, EXCP_BREAK
);
16372 check_insn(ctx
, ISA_MIPS32R6
);
16373 generate_exception_end(ctx
, EXCP_RI
);
16377 MIPS_INVAL("pool32a");
16378 generate_exception_end(ctx
, EXCP_RI
);
16383 minor
= (ctx
->opcode
>> 12) & 0xf;
16386 check_cp0_enabled(ctx
);
16387 if (ctx
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
16388 gen_cache_operation(ctx
, rt
, rs
, imm
);
16393 /* COP2: Not implemented. */
16394 generate_exception_err(ctx
, EXCP_CpU
, 2);
16396 #ifdef TARGET_MIPS64
16399 check_insn(ctx
, ISA_MIPS3
);
16400 check_mips_64(ctx
);
16405 gen_ldst_pair(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
16407 #ifdef TARGET_MIPS64
16410 check_insn(ctx
, ISA_MIPS3
);
16411 check_mips_64(ctx
);
16416 gen_ldst_multiple(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
16419 MIPS_INVAL("pool32b");
16420 generate_exception_end(ctx
, EXCP_RI
);
16425 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
16426 minor
= ctx
->opcode
& 0x3f;
16427 check_cp1_enabled(ctx
);
16430 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16431 mips32_op
= OPC_ALNV_PS
;
16434 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16435 mips32_op
= OPC_MADD_S
;
16438 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16439 mips32_op
= OPC_MADD_D
;
16442 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16443 mips32_op
= OPC_MADD_PS
;
16446 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16447 mips32_op
= OPC_MSUB_S
;
16450 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16451 mips32_op
= OPC_MSUB_D
;
16454 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16455 mips32_op
= OPC_MSUB_PS
;
16458 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16459 mips32_op
= OPC_NMADD_S
;
16462 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16463 mips32_op
= OPC_NMADD_D
;
16466 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16467 mips32_op
= OPC_NMADD_PS
;
16470 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16471 mips32_op
= OPC_NMSUB_S
;
16474 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16475 mips32_op
= OPC_NMSUB_D
;
16478 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16479 mips32_op
= OPC_NMSUB_PS
;
16481 gen_flt3_arith(ctx
, mips32_op
, rd
, rr
, rs
, rt
);
16483 case CABS_COND_FMT
:
16484 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16485 cond
= (ctx
->opcode
>> 6) & 0xf;
16486 cc
= (ctx
->opcode
>> 13) & 0x7;
16487 fmt
= (ctx
->opcode
>> 10) & 0x3;
16490 gen_cmpabs_s(ctx
, cond
, rt
, rs
, cc
);
16493 gen_cmpabs_d(ctx
, cond
, rt
, rs
, cc
);
16496 gen_cmpabs_ps(ctx
, cond
, rt
, rs
, cc
);
16499 goto pool32f_invalid
;
16503 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16504 cond
= (ctx
->opcode
>> 6) & 0xf;
16505 cc
= (ctx
->opcode
>> 13) & 0x7;
16506 fmt
= (ctx
->opcode
>> 10) & 0x3;
16509 gen_cmp_s(ctx
, cond
, rt
, rs
, cc
);
16512 gen_cmp_d(ctx
, cond
, rt
, rs
, cc
);
16515 gen_cmp_ps(ctx
, cond
, rt
, rs
, cc
);
16518 goto pool32f_invalid
;
16522 check_insn(ctx
, ISA_MIPS32R6
);
16523 gen_r6_cmp_s(ctx
, (ctx
->opcode
>> 6) & 0x1f, rt
, rs
, rd
);
16526 check_insn(ctx
, ISA_MIPS32R6
);
16527 gen_r6_cmp_d(ctx
, (ctx
->opcode
>> 6) & 0x1f, rt
, rs
, rd
);
16530 gen_pool32fxf(ctx
, rt
, rs
);
16534 switch ((ctx
->opcode
>> 6) & 0x7) {
16536 mips32_op
= OPC_PLL_PS
;
16539 mips32_op
= OPC_PLU_PS
;
16542 mips32_op
= OPC_PUL_PS
;
16545 mips32_op
= OPC_PUU_PS
;
16548 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16549 mips32_op
= OPC_CVT_PS_S
;
16551 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
16554 goto pool32f_invalid
;
16558 check_insn(ctx
, ISA_MIPS32R6
);
16559 switch ((ctx
->opcode
>> 9) & 0x3) {
16561 gen_farith(ctx
, OPC_MIN_S
, rt
, rs
, rd
, 0);
16564 gen_farith(ctx
, OPC_MIN_D
, rt
, rs
, rd
, 0);
16567 goto pool32f_invalid
;
16572 switch ((ctx
->opcode
>> 6) & 0x7) {
16574 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16575 mips32_op
= OPC_LWXC1
;
16578 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16579 mips32_op
= OPC_SWXC1
;
16582 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16583 mips32_op
= OPC_LDXC1
;
16586 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16587 mips32_op
= OPC_SDXC1
;
16590 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16591 mips32_op
= OPC_LUXC1
;
16594 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16595 mips32_op
= OPC_SUXC1
;
16597 gen_flt3_ldst(ctx
, mips32_op
, rd
, rd
, rt
, rs
);
16600 goto pool32f_invalid
;
16604 check_insn(ctx
, ISA_MIPS32R6
);
16605 switch ((ctx
->opcode
>> 9) & 0x3) {
16607 gen_farith(ctx
, OPC_MAX_S
, rt
, rs
, rd
, 0);
16610 gen_farith(ctx
, OPC_MAX_D
, rt
, rs
, rd
, 0);
16613 goto pool32f_invalid
;
16618 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16619 fmt
= (ctx
->opcode
>> 9) & 0x3;
16620 switch ((ctx
->opcode
>> 6) & 0x7) {
16624 mips32_op
= OPC_RSQRT2_S
;
16627 mips32_op
= OPC_RSQRT2_D
;
16630 mips32_op
= OPC_RSQRT2_PS
;
16633 goto pool32f_invalid
;
16639 mips32_op
= OPC_RECIP2_S
;
16642 mips32_op
= OPC_RECIP2_D
;
16645 mips32_op
= OPC_RECIP2_PS
;
16648 goto pool32f_invalid
;
16652 mips32_op
= OPC_ADDR_PS
;
16655 mips32_op
= OPC_MULR_PS
;
16657 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
16660 goto pool32f_invalid
;
16664 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
16665 cc
= (ctx
->opcode
>> 13) & 0x7;
16666 fmt
= (ctx
->opcode
>> 9) & 0x3;
16667 switch ((ctx
->opcode
>> 6) & 0x7) {
16668 case MOVF_FMT
: /* RINT_FMT */
16669 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16673 gen_farith(ctx
, OPC_RINT_S
, 0, rt
, rs
, 0);
16676 gen_farith(ctx
, OPC_RINT_D
, 0, rt
, rs
, 0);
16679 goto pool32f_invalid
;
16685 gen_movcf_s(ctx
, rs
, rt
, cc
, 0);
16688 gen_movcf_d(ctx
, rs
, rt
, cc
, 0);
16692 gen_movcf_ps(ctx
, rs
, rt
, cc
, 0);
16695 goto pool32f_invalid
;
16699 case MOVT_FMT
: /* CLASS_FMT */
16700 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16704 gen_farith(ctx
, OPC_CLASS_S
, 0, rt
, rs
, 0);
16707 gen_farith(ctx
, OPC_CLASS_D
, 0, rt
, rs
, 0);
16710 goto pool32f_invalid
;
16716 gen_movcf_s(ctx
, rs
, rt
, cc
, 1);
16719 gen_movcf_d(ctx
, rs
, rt
, cc
, 1);
16723 gen_movcf_ps(ctx
, rs
, rt
, cc
, 1);
16726 goto pool32f_invalid
;
16731 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16734 goto pool32f_invalid
;
16737 #define FINSN_3ARG_SDPS(prfx) \
16738 switch ((ctx->opcode >> 8) & 0x3) { \
16740 mips32_op = OPC_##prfx##_S; \
16743 mips32_op = OPC_##prfx##_D; \
16745 case FMT_SDPS_PS: \
16747 mips32_op = OPC_##prfx##_PS; \
16750 goto pool32f_invalid; \
16753 check_insn(ctx
, ISA_MIPS32R6
);
16754 switch ((ctx
->opcode
>> 9) & 0x3) {
16756 gen_farith(ctx
, OPC_MINA_S
, rt
, rs
, rd
, 0);
16759 gen_farith(ctx
, OPC_MINA_D
, rt
, rs
, rd
, 0);
16762 goto pool32f_invalid
;
16766 check_insn(ctx
, ISA_MIPS32R6
);
16767 switch ((ctx
->opcode
>> 9) & 0x3) {
16769 gen_farith(ctx
, OPC_MAXA_S
, rt
, rs
, rd
, 0);
16772 gen_farith(ctx
, OPC_MAXA_D
, rt
, rs
, rd
, 0);
16775 goto pool32f_invalid
;
16779 /* regular FP ops */
16780 switch ((ctx
->opcode
>> 6) & 0x3) {
16782 FINSN_3ARG_SDPS(ADD
);
16785 FINSN_3ARG_SDPS(SUB
);
16788 FINSN_3ARG_SDPS(MUL
);
16791 fmt
= (ctx
->opcode
>> 8) & 0x3;
16793 mips32_op
= OPC_DIV_D
;
16794 } else if (fmt
== 0) {
16795 mips32_op
= OPC_DIV_S
;
16797 goto pool32f_invalid
;
16801 goto pool32f_invalid
;
16806 switch ((ctx
->opcode
>> 6) & 0x7) {
16807 case MOVN_FMT
: /* SELEQZ_FMT */
16808 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16810 switch ((ctx
->opcode
>> 9) & 0x3) {
16812 gen_sel_s(ctx
, OPC_SELEQZ_S
, rd
, rt
, rs
);
16815 gen_sel_d(ctx
, OPC_SELEQZ_D
, rd
, rt
, rs
);
16818 goto pool32f_invalid
;
16822 FINSN_3ARG_SDPS(MOVN
);
16826 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16827 FINSN_3ARG_SDPS(MOVN
);
16829 case MOVZ_FMT
: /* SELNEZ_FMT */
16830 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16832 switch ((ctx
->opcode
>> 9) & 0x3) {
16834 gen_sel_s(ctx
, OPC_SELNEZ_S
, rd
, rt
, rs
);
16837 gen_sel_d(ctx
, OPC_SELNEZ_D
, rd
, rt
, rs
);
16840 goto pool32f_invalid
;
16844 FINSN_3ARG_SDPS(MOVZ
);
16848 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16849 FINSN_3ARG_SDPS(MOVZ
);
16852 check_insn(ctx
, ISA_MIPS32R6
);
16853 switch ((ctx
->opcode
>> 9) & 0x3) {
16855 gen_sel_s(ctx
, OPC_SEL_S
, rd
, rt
, rs
);
16858 gen_sel_d(ctx
, OPC_SEL_D
, rd
, rt
, rs
);
16861 goto pool32f_invalid
;
16865 check_insn(ctx
, ISA_MIPS32R6
);
16866 switch ((ctx
->opcode
>> 9) & 0x3) {
16868 mips32_op
= OPC_MADDF_S
;
16871 mips32_op
= OPC_MADDF_D
;
16874 goto pool32f_invalid
;
16878 check_insn(ctx
, ISA_MIPS32R6
);
16879 switch ((ctx
->opcode
>> 9) & 0x3) {
16881 mips32_op
= OPC_MSUBF_S
;
16884 mips32_op
= OPC_MSUBF_D
;
16887 goto pool32f_invalid
;
16891 goto pool32f_invalid
;
16895 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
16899 MIPS_INVAL("pool32f");
16900 generate_exception_end(ctx
, EXCP_RI
);
16904 generate_exception_err(ctx
, EXCP_CpU
, 1);
16908 minor
= (ctx
->opcode
>> 21) & 0x1f;
16911 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16912 gen_compute_branch(ctx
, OPC_BLTZ
, 4, rs
, -1, imm
<< 1, 4);
16915 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16916 gen_compute_branch(ctx
, OPC_BLTZAL
, 4, rs
, -1, imm
<< 1, 4);
16917 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
16920 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16921 gen_compute_branch(ctx
, OPC_BLTZAL
, 4, rs
, -1, imm
<< 1, 2);
16922 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
16925 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16926 gen_compute_branch(ctx
, OPC_BGEZ
, 4, rs
, -1, imm
<< 1, 4);
16929 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16930 gen_compute_branch(ctx
, OPC_BGEZAL
, 4, rs
, -1, imm
<< 1, 4);
16931 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
16934 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16935 gen_compute_branch(ctx
, OPC_BGEZAL
, 4, rs
, -1, imm
<< 1, 2);
16936 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
16939 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16940 gen_compute_branch(ctx
, OPC_BLEZ
, 4, rs
, -1, imm
<< 1, 4);
16943 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16944 gen_compute_branch(ctx
, OPC_BGTZ
, 4, rs
, -1, imm
<< 1, 4);
16948 case TLTI
: /* BC1EQZC */
16949 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16951 check_cp1_enabled(ctx
);
16952 gen_compute_branch1_r6(ctx
, OPC_BC1EQZ
, rs
, imm
<< 1, 0);
16955 mips32_op
= OPC_TLTI
;
16959 case TGEI
: /* BC1NEZC */
16960 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16962 check_cp1_enabled(ctx
);
16963 gen_compute_branch1_r6(ctx
, OPC_BC1NEZ
, rs
, imm
<< 1, 0);
16966 mips32_op
= OPC_TGEI
;
16971 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16972 mips32_op
= OPC_TLTIU
;
16975 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16976 mips32_op
= OPC_TGEIU
;
16978 case TNEI
: /* SYNCI */
16979 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16982 * Break the TB to be able to sync copied instructions
16985 ctx
->base
.is_jmp
= DISAS_STOP
;
16988 mips32_op
= OPC_TNEI
;
16993 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16994 mips32_op
= OPC_TEQI
;
16996 gen_trap(ctx
, mips32_op
, rs
, -1, imm
);
17001 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17002 gen_compute_branch(ctx
, minor
== BNEZC
? OPC_BNE
: OPC_BEQ
,
17003 4, rs
, 0, imm
<< 1, 0);
17005 * Compact branches don't have a delay slot, so just let
17006 * the normal delay slot handling take us to the branch
17011 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17012 gen_logic_imm(ctx
, OPC_LUI
, rs
, 0, imm
);
17015 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17017 * Break the TB to be able to sync copied instructions
17020 ctx
->base
.is_jmp
= DISAS_STOP
;
17024 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17025 /* COP2: Not implemented. */
17026 generate_exception_err(ctx
, EXCP_CpU
, 2);
17029 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17030 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1FANY2
: OPC_BC1F
;
17033 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17034 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1TANY2
: OPC_BC1T
;
17037 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17038 mips32_op
= OPC_BC1FANY4
;
17041 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17042 mips32_op
= OPC_BC1TANY4
;
17045 check_insn(ctx
, ASE_MIPS3D
);
17048 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
17049 check_cp1_enabled(ctx
);
17050 gen_compute_branch1(ctx
, mips32_op
,
17051 (ctx
->opcode
>> 18) & 0x7, imm
<< 1);
17053 generate_exception_err(ctx
, EXCP_CpU
, 1);
17058 /* MIPS DSP: not implemented */
17061 MIPS_INVAL("pool32i");
17062 generate_exception_end(ctx
, EXCP_RI
);
17067 minor
= (ctx
->opcode
>> 12) & 0xf;
17068 offset
= sextract32(ctx
->opcode
, 0,
17069 (ctx
->insn_flags
& ISA_MIPS32R6
) ? 9 : 12);
17072 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17073 mips32_op
= OPC_LWL
;
17076 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17077 mips32_op
= OPC_SWL
;
17080 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17081 mips32_op
= OPC_LWR
;
17084 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17085 mips32_op
= OPC_SWR
;
17087 #if defined(TARGET_MIPS64)
17089 check_insn(ctx
, ISA_MIPS3
);
17090 check_mips_64(ctx
);
17091 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17092 mips32_op
= OPC_LDL
;
17095 check_insn(ctx
, ISA_MIPS3
);
17096 check_mips_64(ctx
);
17097 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17098 mips32_op
= OPC_SDL
;
17101 check_insn(ctx
, ISA_MIPS3
);
17102 check_mips_64(ctx
);
17103 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17104 mips32_op
= OPC_LDR
;
17107 check_insn(ctx
, ISA_MIPS3
);
17108 check_mips_64(ctx
);
17109 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17110 mips32_op
= OPC_SDR
;
17113 check_insn(ctx
, ISA_MIPS3
);
17114 check_mips_64(ctx
);
17115 mips32_op
= OPC_LWU
;
17118 check_insn(ctx
, ISA_MIPS3
);
17119 check_mips_64(ctx
);
17120 mips32_op
= OPC_LLD
;
17124 mips32_op
= OPC_LL
;
17127 gen_ld(ctx
, mips32_op
, rt
, rs
, offset
);
17130 gen_st(ctx
, mips32_op
, rt
, rs
, offset
);
17133 gen_st_cond(ctx
, rt
, rs
, offset
, MO_TESL
, false);
17135 #if defined(TARGET_MIPS64)
17137 check_insn(ctx
, ISA_MIPS3
);
17138 check_mips_64(ctx
);
17139 gen_st_cond(ctx
, rt
, rs
, offset
, MO_TEQ
, false);
17144 MIPS_INVAL("pool32c ld-eva");
17145 generate_exception_end(ctx
, EXCP_RI
);
17148 check_cp0_enabled(ctx
);
17150 minor2
= (ctx
->opcode
>> 9) & 0x7;
17151 offset
= sextract32(ctx
->opcode
, 0, 9);
17154 mips32_op
= OPC_LBUE
;
17157 mips32_op
= OPC_LHUE
;
17160 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17161 mips32_op
= OPC_LWLE
;
17164 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17165 mips32_op
= OPC_LWRE
;
17168 mips32_op
= OPC_LBE
;
17171 mips32_op
= OPC_LHE
;
17174 mips32_op
= OPC_LLE
;
17177 mips32_op
= OPC_LWE
;
17183 MIPS_INVAL("pool32c st-eva");
17184 generate_exception_end(ctx
, EXCP_RI
);
17187 check_cp0_enabled(ctx
);
17189 minor2
= (ctx
->opcode
>> 9) & 0x7;
17190 offset
= sextract32(ctx
->opcode
, 0, 9);
17193 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17194 mips32_op
= OPC_SWLE
;
17197 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17198 mips32_op
= OPC_SWRE
;
17201 /* Treat as no-op */
17202 if ((ctx
->insn_flags
& ISA_MIPS32R6
) && (rt
>= 24)) {
17203 /* hint codes 24-31 are reserved and signal RI */
17204 generate_exception(ctx
, EXCP_RI
);
17208 /* Treat as no-op */
17209 if (ctx
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
17210 gen_cache_operation(ctx
, rt
, rs
, offset
);
17214 mips32_op
= OPC_SBE
;
17217 mips32_op
= OPC_SHE
;
17220 gen_st_cond(ctx
, rt
, rs
, offset
, MO_TESL
, true);
17223 mips32_op
= OPC_SWE
;
17228 /* Treat as no-op */
17229 if ((ctx
->insn_flags
& ISA_MIPS32R6
) && (rt
>= 24)) {
17230 /* hint codes 24-31 are reserved and signal RI */
17231 generate_exception(ctx
, EXCP_RI
);
17235 MIPS_INVAL("pool32c");
17236 generate_exception_end(ctx
, EXCP_RI
);
17240 case ADDI32
: /* AUI, LUI */
17241 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17243 gen_logic_imm(ctx
, OPC_LUI
, rt
, rs
, imm
);
17246 mips32_op
= OPC_ADDI
;
17251 mips32_op
= OPC_ADDIU
;
17253 gen_arith_imm(ctx
, mips32_op
, rt
, rs
, imm
);
17256 /* Logical operations */
17258 mips32_op
= OPC_ORI
;
17261 mips32_op
= OPC_XORI
;
17264 mips32_op
= OPC_ANDI
;
17266 gen_logic_imm(ctx
, mips32_op
, rt
, rs
, imm
);
17269 /* Set less than immediate */
17271 mips32_op
= OPC_SLTI
;
17274 mips32_op
= OPC_SLTIU
;
17276 gen_slt_imm(ctx
, mips32_op
, rt
, rs
, imm
);
17279 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17280 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
17281 gen_compute_branch(ctx
, OPC_JALX
, 4, rt
, rs
, offset
, 4);
17282 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
17284 case JALS32
: /* BOVC, BEQC, BEQZALC */
17285 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17288 mips32_op
= OPC_BOVC
;
17289 } else if (rs
< rt
&& rs
== 0) {
17291 mips32_op
= OPC_BEQZALC
;
17294 mips32_op
= OPC_BEQC
;
17296 gen_compute_compact_branch(ctx
, mips32_op
, rs
, rt
, imm
<< 1);
17299 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1;
17300 gen_compute_branch(ctx
, OPC_JAL
, 4, rt
, rs
, offset
, 2);
17301 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
17304 case BEQ32
: /* BC */
17305 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17307 gen_compute_compact_branch(ctx
, OPC_BC
, 0, 0,
17308 sextract32(ctx
->opcode
<< 1, 0, 27));
17311 gen_compute_branch(ctx
, OPC_BEQ
, 4, rt
, rs
, imm
<< 1, 4);
17314 case BNE32
: /* BALC */
17315 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17317 gen_compute_compact_branch(ctx
, OPC_BALC
, 0, 0,
17318 sextract32(ctx
->opcode
<< 1, 0, 27));
17321 gen_compute_branch(ctx
, OPC_BNE
, 4, rt
, rs
, imm
<< 1, 4);
17324 case J32
: /* BGTZC, BLTZC, BLTC */
17325 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17326 if (rs
== 0 && rt
!= 0) {
17328 mips32_op
= OPC_BGTZC
;
17329 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
17331 mips32_op
= OPC_BLTZC
;
17334 mips32_op
= OPC_BLTC
;
17336 gen_compute_compact_branch(ctx
, mips32_op
, rs
, rt
, imm
<< 1);
17339 gen_compute_branch(ctx
, OPC_J
, 4, rt
, rs
,
17340 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1, 4);
17343 case JAL32
: /* BLEZC, BGEZC, BGEC */
17344 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17345 if (rs
== 0 && rt
!= 0) {
17347 mips32_op
= OPC_BLEZC
;
17348 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
17350 mips32_op
= OPC_BGEZC
;
17353 mips32_op
= OPC_BGEC
;
17355 gen_compute_compact_branch(ctx
, mips32_op
, rs
, rt
, imm
<< 1);
17358 gen_compute_branch(ctx
, OPC_JAL
, 4, rt
, rs
,
17359 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1, 4);
17360 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
17363 /* Floating point (COP1) */
17365 mips32_op
= OPC_LWC1
;
17368 mips32_op
= OPC_LDC1
;
17371 mips32_op
= OPC_SWC1
;
17374 mips32_op
= OPC_SDC1
;
17376 gen_cop1_ldst(ctx
, mips32_op
, rt
, rs
, imm
);
17378 case ADDIUPC
: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
17379 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17380 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
17381 switch ((ctx
->opcode
>> 16) & 0x1f) {
17390 gen_pcrel(ctx
, OPC_ADDIUPC
, ctx
->base
.pc_next
& ~0x3, rt
);
17393 gen_pcrel(ctx
, OPC_AUIPC
, ctx
->base
.pc_next
, rt
);
17396 gen_pcrel(ctx
, OPC_ALUIPC
, ctx
->base
.pc_next
, rt
);
17406 gen_pcrel(ctx
, R6_OPC_LWPC
, ctx
->base
.pc_next
& ~0x3, rt
);
17409 generate_exception(ctx
, EXCP_RI
);
17414 int reg
= mmreg(ZIMM(ctx
->opcode
, 23, 3));
17415 offset
= SIMM(ctx
->opcode
, 0, 23) << 2;
17417 gen_addiupc(ctx
, reg
, offset
, 0, 0);
17420 case BNVC
: /* BNEC, BNEZALC */
17421 check_insn(ctx
, ISA_MIPS32R6
);
17424 mips32_op
= OPC_BNVC
;
17425 } else if (rs
< rt
&& rs
== 0) {
17427 mips32_op
= OPC_BNEZALC
;
17430 mips32_op
= OPC_BNEC
;
17432 gen_compute_compact_branch(ctx
, mips32_op
, rs
, rt
, imm
<< 1);
17434 case R6_BNEZC
: /* JIALC */
17435 check_insn(ctx
, ISA_MIPS32R6
);
17438 gen_compute_compact_branch(ctx
, OPC_BNEZC
, rt
, 0,
17439 sextract32(ctx
->opcode
<< 1, 0, 22));
17442 gen_compute_compact_branch(ctx
, OPC_JIALC
, 0, rs
, imm
);
17445 case R6_BEQZC
: /* JIC */
17446 check_insn(ctx
, ISA_MIPS32R6
);
17449 gen_compute_compact_branch(ctx
, OPC_BEQZC
, rt
, 0,
17450 sextract32(ctx
->opcode
<< 1, 0, 22));
17453 gen_compute_compact_branch(ctx
, OPC_JIC
, 0, rs
, imm
);
17456 case BLEZALC
: /* BGEZALC, BGEUC */
17457 check_insn(ctx
, ISA_MIPS32R6
);
17458 if (rs
== 0 && rt
!= 0) {
17460 mips32_op
= OPC_BLEZALC
;
17461 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
17463 mips32_op
= OPC_BGEZALC
;
17466 mips32_op
= OPC_BGEUC
;
17468 gen_compute_compact_branch(ctx
, mips32_op
, rs
, rt
, imm
<< 1);
17470 case BGTZALC
: /* BLTZALC, BLTUC */
17471 check_insn(ctx
, ISA_MIPS32R6
);
17472 if (rs
== 0 && rt
!= 0) {
17474 mips32_op
= OPC_BGTZALC
;
17475 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
17477 mips32_op
= OPC_BLTZALC
;
17480 mips32_op
= OPC_BLTUC
;
17482 gen_compute_compact_branch(ctx
, mips32_op
, rs
, rt
, imm
<< 1);
17484 /* Loads and stores */
17486 mips32_op
= OPC_LB
;
17489 mips32_op
= OPC_LBU
;
17492 mips32_op
= OPC_LH
;
17495 mips32_op
= OPC_LHU
;
17498 mips32_op
= OPC_LW
;
17500 #ifdef TARGET_MIPS64
17502 check_insn(ctx
, ISA_MIPS3
);
17503 check_mips_64(ctx
);
17504 mips32_op
= OPC_LD
;
17507 check_insn(ctx
, ISA_MIPS3
);
17508 check_mips_64(ctx
);
17509 mips32_op
= OPC_SD
;
17513 mips32_op
= OPC_SB
;
17516 mips32_op
= OPC_SH
;
17519 mips32_op
= OPC_SW
;
17522 gen_ld(ctx
, mips32_op
, rt
, rs
, imm
);
17525 gen_st(ctx
, mips32_op
, rt
, rs
, imm
);
17528 generate_exception_end(ctx
, EXCP_RI
);
17533 static int decode_micromips_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
17537 /* make sure instructions are on a halfword boundary */
17538 if (ctx
->base
.pc_next
& 0x1) {
17539 env
->CP0_BadVAddr
= ctx
->base
.pc_next
;
17540 generate_exception_end(ctx
, EXCP_AdEL
);
17544 op
= (ctx
->opcode
>> 10) & 0x3f;
17545 /* Enforce properly-sized instructions in a delay slot */
17546 if (ctx
->hflags
& MIPS_HFLAG_BDS_STRICT
) {
17547 switch (op
& 0x7) { /* MSB-3..MSB-5 */
17549 /* POOL32A, POOL32B, POOL32I, POOL32C */
17551 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */
17553 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */
17555 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */
17557 /* LB32, LH32, LWC132, LDC132, LW32 */
17558 if (ctx
->hflags
& MIPS_HFLAG_BDS16
) {
17559 generate_exception_end(ctx
, EXCP_RI
);
17564 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */
17566 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */
17568 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
17569 if (ctx
->hflags
& MIPS_HFLAG_BDS32
) {
17570 generate_exception_end(ctx
, EXCP_RI
);
17580 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
17581 int rs1
= mmreg(uMIPS_RS1(ctx
->opcode
));
17582 int rs2
= mmreg(uMIPS_RS2(ctx
->opcode
));
17585 switch (ctx
->opcode
& 0x1) {
17593 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17595 * In the Release 6, the register number location in
17596 * the instruction encoding has changed.
17598 gen_arith(ctx
, opc
, rs1
, rd
, rs2
);
17600 gen_arith(ctx
, opc
, rd
, rs1
, rs2
);
17606 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
17607 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
17608 int amount
= (ctx
->opcode
>> 1) & 0x7;
17610 amount
= amount
== 0 ? 8 : amount
;
17612 switch (ctx
->opcode
& 0x1) {
17621 gen_shift_imm(ctx
, opc
, rd
, rs
, amount
);
17625 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17626 gen_pool16c_r6_insn(ctx
);
17628 gen_pool16c_insn(ctx
);
17633 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
17634 int rb
= 28; /* GP */
17635 int16_t offset
= SIMM(ctx
->opcode
, 0, 7) << 2;
17637 gen_ld(ctx
, OPC_LW
, rd
, rb
, offset
);
17641 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
17642 if (ctx
->opcode
& 1) {
17643 generate_exception_end(ctx
, EXCP_RI
);
17646 int enc_dest
= uMIPS_RD(ctx
->opcode
);
17647 int enc_rt
= uMIPS_RS2(ctx
->opcode
);
17648 int enc_rs
= uMIPS_RS1(ctx
->opcode
);
17649 gen_movep(ctx
, enc_dest
, enc_rt
, enc_rs
);
17654 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
17655 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
17656 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
17657 offset
= (offset
== 0xf ? -1 : offset
);
17659 gen_ld(ctx
, OPC_LBU
, rd
, rb
, offset
);
17664 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
17665 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
17666 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
17668 gen_ld(ctx
, OPC_LHU
, rd
, rb
, offset
);
17673 int rd
= (ctx
->opcode
>> 5) & 0x1f;
17674 int rb
= 29; /* SP */
17675 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
17677 gen_ld(ctx
, OPC_LW
, rd
, rb
, offset
);
17682 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
17683 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
17684 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
17686 gen_ld(ctx
, OPC_LW
, rd
, rb
, offset
);
17691 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
17692 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
17693 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
17695 gen_st(ctx
, OPC_SB
, rd
, rb
, offset
);
17700 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
17701 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
17702 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
17704 gen_st(ctx
, OPC_SH
, rd
, rb
, offset
);
17709 int rd
= (ctx
->opcode
>> 5) & 0x1f;
17710 int rb
= 29; /* SP */
17711 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
17713 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
17718 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
17719 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
17720 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
17722 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
17727 int rd
= uMIPS_RD5(ctx
->opcode
);
17728 int rs
= uMIPS_RS5(ctx
->opcode
);
17730 gen_arith(ctx
, OPC_ADDU
, rd
, rs
, 0);
17737 switch (ctx
->opcode
& 0x1) {
17747 switch (ctx
->opcode
& 0x1) {
17752 gen_addiur1sp(ctx
);
17756 case B16
: /* BC16 */
17757 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0,
17758 sextract32(ctx
->opcode
, 0, 10) << 1,
17759 (ctx
->insn_flags
& ISA_MIPS32R6
) ? 0 : 4);
17761 case BNEZ16
: /* BNEZC16 */
17762 case BEQZ16
: /* BEQZC16 */
17763 gen_compute_branch(ctx
, op
== BNEZ16
? OPC_BNE
: OPC_BEQ
, 2,
17764 mmreg(uMIPS_RD(ctx
->opcode
)),
17765 0, sextract32(ctx
->opcode
, 0, 7) << 1,
17766 (ctx
->insn_flags
& ISA_MIPS32R6
) ? 0 : 4);
17771 int reg
= mmreg(uMIPS_RD(ctx
->opcode
));
17772 int imm
= ZIMM(ctx
->opcode
, 0, 7);
17774 imm
= (imm
== 0x7f ? -1 : imm
);
17775 tcg_gen_movi_tl(cpu_gpr
[reg
], imm
);
17781 generate_exception_end(ctx
, EXCP_RI
);
17784 decode_micromips32_opc(env
, ctx
);
17797 /* MAJOR, P16, and P32 pools opcodes */
17801 NM_MOVE_BALC
= 0x02,
17809 NM_P16_SHIFT
= 0x0c,
17827 NM_P_LS_U12
= 0x21,
17837 NM_P16_ADDU
= 0x2c,
17851 NM_MOVEPREV
= 0x3f,
17854 /* POOL32A instruction pool */
17856 NM_POOL32A0
= 0x00,
17857 NM_SPECIAL2
= 0x01,
17860 NM_POOL32A5
= 0x05,
17861 NM_POOL32A7
= 0x07,
17864 /* P.GP.W instruction pool */
17866 NM_ADDIUGP_W
= 0x00,
17871 /* P48I instruction pool */
17875 NM_ADDIUGP48
= 0x02,
17876 NM_ADDIUPC48
= 0x03,
17881 /* P.U12 instruction pool */
17890 NM_ADDIUNEG
= 0x08,
17897 /* POOL32F instruction pool */
17899 NM_POOL32F_0
= 0x00,
17900 NM_POOL32F_3
= 0x03,
17901 NM_POOL32F_5
= 0x05,
17904 /* POOL32S instruction pool */
17906 NM_POOL32S_0
= 0x00,
17907 NM_POOL32S_4
= 0x04,
17910 /* P.LUI instruction pool */
17916 /* P.GP.BH instruction pool */
17921 NM_ADDIUGP_B
= 0x03,
17924 NM_P_GP_CP1
= 0x06,
17927 /* P.LS.U12 instruction pool */
17932 NM_P_PREFU12
= 0x03,
17945 /* P.LS.S9 instruction pool */
17951 NM_P_LS_UAWM
= 0x05,
17954 /* P.BAL instruction pool */
17960 /* P.J instruction pool */
17963 NM_JALRC_HB
= 0x01,
17964 NM_P_BALRSC
= 0x08,
17967 /* P.BR1 instruction pool */
17975 /* P.BR2 instruction pool */
17982 /* P.BRI instruction pool */
17994 /* P16.SHIFT instruction pool */
18000 /* POOL16C instruction pool */
18002 NM_POOL16C_0
= 0x00,
18006 /* P16.A1 instruction pool */
18008 NM_ADDIUR1SP
= 0x01,
18011 /* P16.A2 instruction pool */
18014 NM_P_ADDIURS5
= 0x01,
18017 /* P16.ADDU instruction pool */
18023 /* P16.SR instruction pool */
18026 NM_RESTORE_JRC16
= 0x01,
18029 /* P16.4X4 instruction pool */
18035 /* P16.LB instruction pool */
18042 /* P16.LH instruction pool */
18049 /* P.RI instruction pool */
18052 NM_P_SYSCALL
= 0x01,
18057 /* POOL32A0 instruction pool */
18092 NM_D_E_MT_VPE
= 0x56,
18100 /* CRC32 instruction pool */
18110 /* POOL32A5 instruction pool */
18112 NM_CMP_EQ_PH
= 0x00,
18113 NM_CMP_LT_PH
= 0x08,
18114 NM_CMP_LE_PH
= 0x10,
18115 NM_CMPGU_EQ_QB
= 0x18,
18116 NM_CMPGU_LT_QB
= 0x20,
18117 NM_CMPGU_LE_QB
= 0x28,
18118 NM_CMPGDU_EQ_QB
= 0x30,
18119 NM_CMPGDU_LT_QB
= 0x38,
18120 NM_CMPGDU_LE_QB
= 0x40,
18121 NM_CMPU_EQ_QB
= 0x48,
18122 NM_CMPU_LT_QB
= 0x50,
18123 NM_CMPU_LE_QB
= 0x58,
18124 NM_ADDQ_S_W
= 0x60,
18125 NM_SUBQ_S_W
= 0x68,
18129 NM_ADDQ_S_PH
= 0x01,
18130 NM_ADDQH_R_PH
= 0x09,
18131 NM_ADDQH_R_W
= 0x11,
18132 NM_ADDU_S_QB
= 0x19,
18133 NM_ADDU_S_PH
= 0x21,
18134 NM_ADDUH_R_QB
= 0x29,
18135 NM_SHRAV_R_PH
= 0x31,
18136 NM_SHRAV_R_QB
= 0x39,
18137 NM_SUBQ_S_PH
= 0x41,
18138 NM_SUBQH_R_PH
= 0x49,
18139 NM_SUBQH_R_W
= 0x51,
18140 NM_SUBU_S_QB
= 0x59,
18141 NM_SUBU_S_PH
= 0x61,
18142 NM_SUBUH_R_QB
= 0x69,
18143 NM_SHLLV_S_PH
= 0x71,
18144 NM_PRECR_SRA_R_PH_W
= 0x79,
18146 NM_MULEU_S_PH_QBL
= 0x12,
18147 NM_MULEU_S_PH_QBR
= 0x1a,
18148 NM_MULQ_RS_PH
= 0x22,
18149 NM_MULQ_S_PH
= 0x2a,
18150 NM_MULQ_RS_W
= 0x32,
18151 NM_MULQ_S_W
= 0x3a,
18154 NM_SHRAV_R_W
= 0x5a,
18155 NM_SHRLV_PH
= 0x62,
18156 NM_SHRLV_QB
= 0x6a,
18157 NM_SHLLV_QB
= 0x72,
18158 NM_SHLLV_S_W
= 0x7a,
18162 NM_MULEQ_S_W_PHL
= 0x04,
18163 NM_MULEQ_S_W_PHR
= 0x0c,
18165 NM_MUL_S_PH
= 0x05,
18166 NM_PRECR_QB_PH
= 0x0d,
18167 NM_PRECRQ_QB_PH
= 0x15,
18168 NM_PRECRQ_PH_W
= 0x1d,
18169 NM_PRECRQ_RS_PH_W
= 0x25,
18170 NM_PRECRQU_S_QB_PH
= 0x2d,
18171 NM_PACKRL_PH
= 0x35,
18175 NM_SHRA_R_W
= 0x5e,
18176 NM_SHRA_R_PH
= 0x66,
18177 NM_SHLL_S_PH
= 0x76,
18178 NM_SHLL_S_W
= 0x7e,
18183 /* POOL32A7 instruction pool */
18188 NM_POOL32AXF
= 0x07,
18191 /* P.SR instruction pool */
18197 /* P.SHIFT instruction pool */
18205 /* P.ROTX instruction pool */
18210 /* P.INS instruction pool */
18215 /* P.EXT instruction pool */
18220 /* POOL32F_0 (fmt) instruction pool */
18225 NM_SELEQZ_S
= 0x07,
18226 NM_SELEQZ_D
= 0x47,
18230 NM_SELNEZ_S
= 0x0f,
18231 NM_SELNEZ_D
= 0x4f,
18246 /* POOL32F_3 instruction pool */
18250 NM_MINA_FMT
= 0x04,
18251 NM_MAXA_FMT
= 0x05,
18252 NM_POOL32FXF
= 0x07,
18255 /* POOL32F_5 instruction pool */
18257 NM_CMP_CONDN_S
= 0x00,
18258 NM_CMP_CONDN_D
= 0x02,
18261 /* P.GP.LH instruction pool */
18267 /* P.GP.SH instruction pool */
18272 /* P.GP.CP1 instruction pool */
18280 /* P.LS.S0 instruction pool */
18297 NM_P_PREFS9
= 0x03,
18303 /* P.LS.S1 instruction pool */
18305 NM_ASET_ACLR
= 0x02,
18313 /* P.LS.E0 instruction pool */
18329 /* P.PREFE instruction pool */
18335 /* P.LLE instruction pool */
18341 /* P.SCE instruction pool */
18347 /* P.LS.WM instruction pool */
18353 /* P.LS.UAWM instruction pool */
18359 /* P.BR3A instruction pool */
18365 NM_BPOSGE32C
= 0x04,
18368 /* P16.RI instruction pool */
18370 NM_P16_SYSCALL
= 0x01,
18375 /* POOL16C_0 instruction pool */
18377 NM_POOL16C_00
= 0x00,
18380 /* P16.JRC instruction pool */
18386 /* P.SYSCALL instruction pool */
18392 /* P.TRAP instruction pool */
18398 /* P.CMOVE instruction pool */
18404 /* POOL32Axf instruction pool */
18406 NM_POOL32AXF_1
= 0x01,
18407 NM_POOL32AXF_2
= 0x02,
18408 NM_POOL32AXF_4
= 0x04,
18409 NM_POOL32AXF_5
= 0x05,
18410 NM_POOL32AXF_7
= 0x07,
18413 /* POOL32Axf_1 instruction pool */
18415 NM_POOL32AXF_1_0
= 0x00,
18416 NM_POOL32AXF_1_1
= 0x01,
18417 NM_POOL32AXF_1_3
= 0x03,
18418 NM_POOL32AXF_1_4
= 0x04,
18419 NM_POOL32AXF_1_5
= 0x05,
18420 NM_POOL32AXF_1_7
= 0x07,
18423 /* POOL32Axf_2 instruction pool */
18425 NM_POOL32AXF_2_0_7
= 0x00,
18426 NM_POOL32AXF_2_8_15
= 0x01,
18427 NM_POOL32AXF_2_16_23
= 0x02,
18428 NM_POOL32AXF_2_24_31
= 0x03,
18431 /* POOL32Axf_7 instruction pool */
18433 NM_SHRA_R_QB
= 0x0,
18438 /* POOL32Axf_1_0 instruction pool */
18446 /* POOL32Axf_1_1 instruction pool */
18452 /* POOL32Axf_1_3 instruction pool */
18460 /* POOL32Axf_1_4 instruction pool */
18466 /* POOL32Axf_1_5 instruction pool */
18468 NM_MAQ_S_W_PHR
= 0x0,
18469 NM_MAQ_S_W_PHL
= 0x1,
18470 NM_MAQ_SA_W_PHR
= 0x2,
18471 NM_MAQ_SA_W_PHL
= 0x3,
18474 /* POOL32Axf_1_7 instruction pool */
18478 NM_EXTR_RS_W
= 0x2,
18482 /* POOL32Axf_2_0_7 instruction pool */
18485 NM_DPAQ_S_W_PH
= 0x1,
18487 NM_DPSQ_S_W_PH
= 0x3,
18494 /* POOL32Axf_2_8_15 instruction pool */
18496 NM_DPAX_W_PH
= 0x0,
18497 NM_DPAQ_SA_L_W
= 0x1,
18498 NM_DPSX_W_PH
= 0x2,
18499 NM_DPSQ_SA_L_W
= 0x3,
18502 NM_EXTRV_R_W
= 0x7,
18505 /* POOL32Axf_2_16_23 instruction pool */
18507 NM_DPAU_H_QBL
= 0x0,
18508 NM_DPAQX_S_W_PH
= 0x1,
18509 NM_DPSU_H_QBL
= 0x2,
18510 NM_DPSQX_S_W_PH
= 0x3,
18513 NM_MULSA_W_PH
= 0x6,
18514 NM_EXTRV_RS_W
= 0x7,
18517 /* POOL32Axf_2_24_31 instruction pool */
18519 NM_DPAU_H_QBR
= 0x0,
18520 NM_DPAQX_SA_W_PH
= 0x1,
18521 NM_DPSU_H_QBR
= 0x2,
18522 NM_DPSQX_SA_W_PH
= 0x3,
18525 NM_MULSAQ_S_W_PH
= 0x6,
18526 NM_EXTRV_S_H
= 0x7,
18529 /* POOL32Axf_{4, 5} instruction pool */
18548 /* nanoMIPS DSP instructions */
18549 NM_ABSQ_S_QB
= 0x00,
18550 NM_ABSQ_S_PH
= 0x08,
18551 NM_ABSQ_S_W
= 0x10,
18552 NM_PRECEQ_W_PHL
= 0x28,
18553 NM_PRECEQ_W_PHR
= 0x30,
18554 NM_PRECEQU_PH_QBL
= 0x38,
18555 NM_PRECEQU_PH_QBR
= 0x48,
18556 NM_PRECEU_PH_QBL
= 0x58,
18557 NM_PRECEU_PH_QBR
= 0x68,
18558 NM_PRECEQU_PH_QBLA
= 0x39,
18559 NM_PRECEQU_PH_QBRA
= 0x49,
18560 NM_PRECEU_PH_QBLA
= 0x59,
18561 NM_PRECEU_PH_QBRA
= 0x69,
18562 NM_REPLV_PH
= 0x01,
18563 NM_REPLV_QB
= 0x09,
18566 NM_RADDU_W_QB
= 0x78,
18572 /* PP.SR instruction pool */
18576 NM_RESTORE_JRC
= 0x03,
18579 /* P.SR.F instruction pool */
18582 NM_RESTOREF
= 0x01,
18585 /* P16.SYSCALL instruction pool */
18587 NM_SYSCALL16
= 0x00,
18588 NM_HYPCALL16
= 0x01,
18591 /* POOL16C_00 instruction pool */
18599 /* PP.LSX and PP.LSXS instruction pool */
18637 /* ERETx instruction pool */
18643 /* POOL32FxF_{0, 1} insturction pool */
18652 NM_CVT_S_PL
= 0x84,
18653 NM_CVT_S_PU
= 0xa4,
18655 NM_CVT_L_S
= 0x004,
18656 NM_CVT_L_D
= 0x104,
18657 NM_CVT_W_S
= 0x024,
18658 NM_CVT_W_D
= 0x124,
18660 NM_RSQRT_S
= 0x008,
18661 NM_RSQRT_D
= 0x108,
18666 NM_RECIP_S
= 0x048,
18667 NM_RECIP_D
= 0x148,
18669 NM_FLOOR_L_S
= 0x00c,
18670 NM_FLOOR_L_D
= 0x10c,
18672 NM_FLOOR_W_S
= 0x02c,
18673 NM_FLOOR_W_D
= 0x12c,
18675 NM_CEIL_L_S
= 0x04c,
18676 NM_CEIL_L_D
= 0x14c,
18677 NM_CEIL_W_S
= 0x06c,
18678 NM_CEIL_W_D
= 0x16c,
18679 NM_TRUNC_L_S
= 0x08c,
18680 NM_TRUNC_L_D
= 0x18c,
18681 NM_TRUNC_W_S
= 0x0ac,
18682 NM_TRUNC_W_D
= 0x1ac,
18683 NM_ROUND_L_S
= 0x0cc,
18684 NM_ROUND_L_D
= 0x1cc,
18685 NM_ROUND_W_S
= 0x0ec,
18686 NM_ROUND_W_D
= 0x1ec,
18694 NM_CVT_D_S
= 0x04d,
18695 NM_CVT_D_W
= 0x0cd,
18696 NM_CVT_D_L
= 0x14d,
18697 NM_CVT_S_D
= 0x06d,
18698 NM_CVT_S_W
= 0x0ed,
18699 NM_CVT_S_L
= 0x16d,
18702 /* P.LL instruction pool */
18708 /* P.SC instruction pool */
18714 /* P.DVP instruction pool */
18723 * nanoMIPS decoding engine
18728 /* extraction utilities */
18730 #define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
18731 #define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
18732 #define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
18733 #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
18734 #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
18736 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3'). */
18737 static inline int decode_gpr_gpr3(int r
)
18739 static const int map
[] = { 16, 17, 18, 19, 4, 5, 6, 7 };
18741 return map
[r
& 0x7];
18744 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3.src.store'). */
18745 static inline int decode_gpr_gpr3_src_store(int r
)
18747 static const int map
[] = { 0, 17, 18, 19, 4, 5, 6, 7 };
18749 return map
[r
& 0x7];
18752 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4'). */
18753 static inline int decode_gpr_gpr4(int r
)
18755 static const int map
[] = { 8, 9, 10, 11, 4, 5, 6, 7,
18756 16, 17, 18, 19, 20, 21, 22, 23 };
18758 return map
[r
& 0xf];
18761 /* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4.zero'). */
18762 static inline int decode_gpr_gpr4_zero(int r
)
18764 static const int map
[] = { 8, 9, 10, 0, 4, 5, 6, 7,
18765 16, 17, 18, 19, 20, 21, 22, 23 };
18767 return map
[r
& 0xf];
18771 static void gen_adjust_sp(DisasContext
*ctx
, int u
)
18773 gen_op_addr_addi(ctx
, cpu_gpr
[29], cpu_gpr
[29], u
);
18776 static void gen_save(DisasContext
*ctx
, uint8_t rt
, uint8_t count
,
18777 uint8_t gp
, uint16_t u
)
18780 TCGv va
= tcg_temp_new();
18781 TCGv t0
= tcg_temp_new();
18783 while (counter
!= count
) {
18784 bool use_gp
= gp
&& (counter
== count
- 1);
18785 int this_rt
= use_gp
? 28 : (rt
& 0x10) | ((rt
+ counter
) & 0x1f);
18786 int this_offset
= -((counter
+ 1) << 2);
18787 gen_base_offset_addr(ctx
, va
, 29, this_offset
);
18788 gen_load_gpr(t0
, this_rt
);
18789 tcg_gen_qemu_st_tl(t0
, va
, ctx
->mem_idx
,
18790 (MO_TEUL
| ctx
->default_tcg_memop_mask
));
18794 /* adjust stack pointer */
18795 gen_adjust_sp(ctx
, -u
);
18801 static void gen_restore(DisasContext
*ctx
, uint8_t rt
, uint8_t count
,
18802 uint8_t gp
, uint16_t u
)
18805 TCGv va
= tcg_temp_new();
18806 TCGv t0
= tcg_temp_new();
18808 while (counter
!= count
) {
18809 bool use_gp
= gp
&& (counter
== count
- 1);
18810 int this_rt
= use_gp
? 28 : (rt
& 0x10) | ((rt
+ counter
) & 0x1f);
18811 int this_offset
= u
- ((counter
+ 1) << 2);
18812 gen_base_offset_addr(ctx
, va
, 29, this_offset
);
18813 tcg_gen_qemu_ld_tl(t0
, va
, ctx
->mem_idx
, MO_TESL
|
18814 ctx
->default_tcg_memop_mask
);
18815 tcg_gen_ext32s_tl(t0
, t0
);
18816 gen_store_gpr(t0
, this_rt
);
18820 /* adjust stack pointer */
18821 gen_adjust_sp(ctx
, u
);
18827 static void gen_pool16c_nanomips_insn(DisasContext
*ctx
)
18829 int rt
= decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx
->opcode
));
18830 int rs
= decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx
->opcode
));
18832 switch (extract32(ctx
->opcode
, 2, 2)) {
18834 gen_logic(ctx
, OPC_NOR
, rt
, rs
, 0);
18837 gen_logic(ctx
, OPC_AND
, rt
, rt
, rs
);
18840 gen_logic(ctx
, OPC_XOR
, rt
, rt
, rs
);
18843 gen_logic(ctx
, OPC_OR
, rt
, rt
, rs
);
18848 static void gen_pool32a0_nanomips_insn(CPUMIPSState
*env
, DisasContext
*ctx
)
18850 int rt
= extract32(ctx
->opcode
, 21, 5);
18851 int rs
= extract32(ctx
->opcode
, 16, 5);
18852 int rd
= extract32(ctx
->opcode
, 11, 5);
18854 switch (extract32(ctx
->opcode
, 3, 7)) {
18856 switch (extract32(ctx
->opcode
, 10, 1)) {
18859 gen_trap(ctx
, OPC_TEQ
, rs
, rt
, -1);
18863 gen_trap(ctx
, OPC_TNE
, rs
, rt
, -1);
18869 gen_rdhwr(ctx
, rt
, rs
, extract32(ctx
->opcode
, 11, 3));
18873 gen_bshfl(ctx
, OPC_SEB
, rs
, rt
);
18876 gen_bshfl(ctx
, OPC_SEH
, rs
, rt
);
18879 gen_shift(ctx
, OPC_SLLV
, rd
, rt
, rs
);
18882 gen_shift(ctx
, OPC_SRLV
, rd
, rt
, rs
);
18885 gen_shift(ctx
, OPC_SRAV
, rd
, rt
, rs
);
18888 gen_shift(ctx
, OPC_ROTRV
, rd
, rt
, rs
);
18891 gen_arith(ctx
, OPC_ADD
, rd
, rs
, rt
);
18894 gen_arith(ctx
, OPC_ADDU
, rd
, rs
, rt
);
18898 gen_arith(ctx
, OPC_SUB
, rd
, rs
, rt
);
18901 gen_arith(ctx
, OPC_SUBU
, rd
, rs
, rt
);
18904 switch (extract32(ctx
->opcode
, 10, 1)) {
18906 gen_cond_move(ctx
, OPC_MOVZ
, rd
, rs
, rt
);
18909 gen_cond_move(ctx
, OPC_MOVN
, rd
, rs
, rt
);
18914 gen_logic(ctx
, OPC_AND
, rd
, rs
, rt
);
18917 gen_logic(ctx
, OPC_OR
, rd
, rs
, rt
);
18920 gen_logic(ctx
, OPC_NOR
, rd
, rs
, rt
);
18923 gen_logic(ctx
, OPC_XOR
, rd
, rs
, rt
);
18926 gen_slt(ctx
, OPC_SLT
, rd
, rs
, rt
);
18931 #ifndef CONFIG_USER_ONLY
18932 TCGv t0
= tcg_temp_new();
18933 switch (extract32(ctx
->opcode
, 10, 1)) {
18936 check_cp0_enabled(ctx
);
18937 gen_helper_dvp(t0
, cpu_env
);
18938 gen_store_gpr(t0
, rt
);
18943 check_cp0_enabled(ctx
);
18944 gen_helper_evp(t0
, cpu_env
);
18945 gen_store_gpr(t0
, rt
);
18952 gen_slt(ctx
, OPC_SLTU
, rd
, rs
, rt
);
18957 TCGv t0
= tcg_temp_new();
18958 TCGv t1
= tcg_temp_new();
18959 TCGv t2
= tcg_temp_new();
18961 gen_load_gpr(t1
, rs
);
18962 gen_load_gpr(t2
, rt
);
18963 tcg_gen_add_tl(t0
, t1
, t2
);
18964 tcg_gen_ext32s_tl(t0
, t0
);
18965 tcg_gen_xor_tl(t1
, t1
, t2
);
18966 tcg_gen_xor_tl(t2
, t0
, t2
);
18967 tcg_gen_andc_tl(t1
, t2
, t1
);
18969 /* operands of same sign, result different sign */
18970 tcg_gen_setcondi_tl(TCG_COND_LT
, t0
, t1
, 0);
18971 gen_store_gpr(t0
, rd
);
18979 gen_r6_muldiv(ctx
, R6_OPC_MUL
, rd
, rs
, rt
);
18982 gen_r6_muldiv(ctx
, R6_OPC_MUH
, rd
, rs
, rt
);
18985 gen_r6_muldiv(ctx
, R6_OPC_MULU
, rd
, rs
, rt
);
18988 gen_r6_muldiv(ctx
, R6_OPC_MUHU
, rd
, rs
, rt
);
18991 gen_r6_muldiv(ctx
, R6_OPC_DIV
, rd
, rs
, rt
);
18994 gen_r6_muldiv(ctx
, R6_OPC_MOD
, rd
, rs
, rt
);
18997 gen_r6_muldiv(ctx
, R6_OPC_DIVU
, rd
, rs
, rt
);
19000 gen_r6_muldiv(ctx
, R6_OPC_MODU
, rd
, rs
, rt
);
19002 #ifndef CONFIG_USER_ONLY
19004 check_cp0_enabled(ctx
);
19006 /* Treat as NOP. */
19009 gen_mfc0(ctx
, cpu_gpr
[rt
], rs
, extract32(ctx
->opcode
, 11, 3));
19012 check_cp0_enabled(ctx
);
19014 TCGv t0
= tcg_temp_new();
19016 gen_load_gpr(t0
, rt
);
19017 gen_mtc0(ctx
, t0
, rs
, extract32(ctx
->opcode
, 11, 3));
19021 case NM_D_E_MT_VPE
:
19023 uint8_t sc
= extract32(ctx
->opcode
, 10, 1);
19024 TCGv t0
= tcg_temp_new();
19031 gen_helper_dmt(t0
);
19032 gen_store_gpr(t0
, rt
);
19033 } else if (rs
== 0) {
19036 gen_helper_dvpe(t0
, cpu_env
);
19037 gen_store_gpr(t0
, rt
);
19039 generate_exception_end(ctx
, EXCP_RI
);
19046 gen_helper_emt(t0
);
19047 gen_store_gpr(t0
, rt
);
19048 } else if (rs
== 0) {
19051 gen_helper_evpe(t0
, cpu_env
);
19052 gen_store_gpr(t0
, rt
);
19054 generate_exception_end(ctx
, EXCP_RI
);
19065 TCGv t0
= tcg_temp_new();
19066 TCGv t1
= tcg_temp_new();
19068 gen_load_gpr(t0
, rt
);
19069 gen_load_gpr(t1
, rs
);
19070 gen_helper_fork(t0
, t1
);
19077 check_cp0_enabled(ctx
);
19079 /* Treat as NOP. */
19082 gen_mftr(env
, ctx
, rs
, rt
, extract32(ctx
->opcode
, 10, 1),
19083 extract32(ctx
->opcode
, 11, 5), extract32(ctx
->opcode
, 3, 1));
19087 check_cp0_enabled(ctx
);
19088 gen_mttr(env
, ctx
, rs
, rt
, extract32(ctx
->opcode
, 10, 1),
19089 extract32(ctx
->opcode
, 11, 5), extract32(ctx
->opcode
, 3, 1));
19094 TCGv t0
= tcg_temp_new();
19096 gen_load_gpr(t0
, rs
);
19097 gen_helper_yield(t0
, cpu_env
, t0
);
19098 gen_store_gpr(t0
, rt
);
19104 generate_exception_end(ctx
, EXCP_RI
);
19110 static void gen_pool32axf_1_5_nanomips_insn(DisasContext
*ctx
, uint32_t opc
,
19111 int ret
, int v1
, int v2
)
19117 t0
= tcg_temp_new_i32();
19119 v0_t
= tcg_temp_new();
19120 v1_t
= tcg_temp_new();
19122 tcg_gen_movi_i32(t0
, v2
>> 3);
19124 gen_load_gpr(v0_t
, ret
);
19125 gen_load_gpr(v1_t
, v1
);
19128 case NM_MAQ_S_W_PHR
:
19130 gen_helper_maq_s_w_phr(t0
, v1_t
, v0_t
, cpu_env
);
19132 case NM_MAQ_S_W_PHL
:
19134 gen_helper_maq_s_w_phl(t0
, v1_t
, v0_t
, cpu_env
);
19136 case NM_MAQ_SA_W_PHR
:
19138 gen_helper_maq_sa_w_phr(t0
, v1_t
, v0_t
, cpu_env
);
19140 case NM_MAQ_SA_W_PHL
:
19142 gen_helper_maq_sa_w_phl(t0
, v1_t
, v0_t
, cpu_env
);
19145 generate_exception_end(ctx
, EXCP_RI
);
19149 tcg_temp_free_i32(t0
);
19151 tcg_temp_free(v0_t
);
19152 tcg_temp_free(v1_t
);
19156 static void gen_pool32axf_1_nanomips_insn(DisasContext
*ctx
, uint32_t opc
,
19157 int ret
, int v1
, int v2
)
19160 TCGv t0
= tcg_temp_new();
19161 TCGv t1
= tcg_temp_new();
19162 TCGv v0_t
= tcg_temp_new();
19164 gen_load_gpr(v0_t
, v1
);
19167 case NM_POOL32AXF_1_0
:
19169 switch (extract32(ctx
->opcode
, 12, 2)) {
19171 gen_HILO(ctx
, OPC_MFHI
, v2
>> 3, ret
);
19174 gen_HILO(ctx
, OPC_MFLO
, v2
>> 3, ret
);
19177 gen_HILO(ctx
, OPC_MTHI
, v2
>> 3, v1
);
19180 gen_HILO(ctx
, OPC_MTLO
, v2
>> 3, v1
);
19184 case NM_POOL32AXF_1_1
:
19186 switch (extract32(ctx
->opcode
, 12, 2)) {
19188 tcg_gen_movi_tl(t0
, v2
);
19189 gen_helper_mthlip(t0
, v0_t
, cpu_env
);
19192 tcg_gen_movi_tl(t0
, v2
>> 3);
19193 gen_helper_shilo(t0
, v0_t
, cpu_env
);
19196 generate_exception_end(ctx
, EXCP_RI
);
19200 case NM_POOL32AXF_1_3
:
19202 imm
= extract32(ctx
->opcode
, 14, 7);
19203 switch (extract32(ctx
->opcode
, 12, 2)) {
19205 tcg_gen_movi_tl(t0
, imm
);
19206 gen_helper_rddsp(t0
, t0
, cpu_env
);
19207 gen_store_gpr(t0
, ret
);
19210 gen_load_gpr(t0
, ret
);
19211 tcg_gen_movi_tl(t1
, imm
);
19212 gen_helper_wrdsp(t0
, t1
, cpu_env
);
19215 tcg_gen_movi_tl(t0
, v2
>> 3);
19216 tcg_gen_movi_tl(t1
, v1
);
19217 gen_helper_extp(t0
, t0
, t1
, cpu_env
);
19218 gen_store_gpr(t0
, ret
);
19221 tcg_gen_movi_tl(t0
, v2
>> 3);
19222 tcg_gen_movi_tl(t1
, v1
);
19223 gen_helper_extpdp(t0
, t0
, t1
, cpu_env
);
19224 gen_store_gpr(t0
, ret
);
19228 case NM_POOL32AXF_1_4
:
19230 tcg_gen_movi_tl(t0
, v2
>> 2);
19231 switch (extract32(ctx
->opcode
, 12, 1)) {
19233 gen_helper_shll_qb(t0
, t0
, v0_t
, cpu_env
);
19234 gen_store_gpr(t0
, ret
);
19237 gen_helper_shrl_qb(t0
, t0
, v0_t
);
19238 gen_store_gpr(t0
, ret
);
19242 case NM_POOL32AXF_1_5
:
19243 opc
= extract32(ctx
->opcode
, 12, 2);
19244 gen_pool32axf_1_5_nanomips_insn(ctx
, opc
, ret
, v1
, v2
);
19246 case NM_POOL32AXF_1_7
:
19248 tcg_gen_movi_tl(t0
, v2
>> 3);
19249 tcg_gen_movi_tl(t1
, v1
);
19250 switch (extract32(ctx
->opcode
, 12, 2)) {
19252 gen_helper_extr_w(t0
, t0
, t1
, cpu_env
);
19253 gen_store_gpr(t0
, ret
);
19256 gen_helper_extr_r_w(t0
, t0
, t1
, cpu_env
);
19257 gen_store_gpr(t0
, ret
);
19260 gen_helper_extr_rs_w(t0
, t0
, t1
, cpu_env
);
19261 gen_store_gpr(t0
, ret
);
19264 gen_helper_extr_s_h(t0
, t0
, t1
, cpu_env
);
19265 gen_store_gpr(t0
, ret
);
19270 generate_exception_end(ctx
, EXCP_RI
);
19276 tcg_temp_free(v0_t
);
19279 static void gen_pool32axf_2_multiply(DisasContext
*ctx
, uint32_t opc
,
19280 TCGv v0
, TCGv v1
, int rd
)
19284 t0
= tcg_temp_new_i32();
19286 tcg_gen_movi_i32(t0
, rd
>> 3);
19289 case NM_POOL32AXF_2_0_7
:
19290 switch (extract32(ctx
->opcode
, 9, 3)) {
19293 gen_helper_dpa_w_ph(t0
, v1
, v0
, cpu_env
);
19295 case NM_DPAQ_S_W_PH
:
19297 gen_helper_dpaq_s_w_ph(t0
, v1
, v0
, cpu_env
);
19301 gen_helper_dps_w_ph(t0
, v1
, v0
, cpu_env
);
19303 case NM_DPSQ_S_W_PH
:
19305 gen_helper_dpsq_s_w_ph(t0
, v1
, v0
, cpu_env
);
19308 generate_exception_end(ctx
, EXCP_RI
);
19312 case NM_POOL32AXF_2_8_15
:
19313 switch (extract32(ctx
->opcode
, 9, 3)) {
19316 gen_helper_dpax_w_ph(t0
, v0
, v1
, cpu_env
);
19318 case NM_DPAQ_SA_L_W
:
19320 gen_helper_dpaq_sa_l_w(t0
, v0
, v1
, cpu_env
);
19324 gen_helper_dpsx_w_ph(t0
, v0
, v1
, cpu_env
);
19326 case NM_DPSQ_SA_L_W
:
19328 gen_helper_dpsq_sa_l_w(t0
, v0
, v1
, cpu_env
);
19331 generate_exception_end(ctx
, EXCP_RI
);
19335 case NM_POOL32AXF_2_16_23
:
19336 switch (extract32(ctx
->opcode
, 9, 3)) {
19337 case NM_DPAU_H_QBL
:
19339 gen_helper_dpau_h_qbl(t0
, v0
, v1
, cpu_env
);
19341 case NM_DPAQX_S_W_PH
:
19343 gen_helper_dpaqx_s_w_ph(t0
, v0
, v1
, cpu_env
);
19345 case NM_DPSU_H_QBL
:
19347 gen_helper_dpsu_h_qbl(t0
, v0
, v1
, cpu_env
);
19349 case NM_DPSQX_S_W_PH
:
19351 gen_helper_dpsqx_s_w_ph(t0
, v0
, v1
, cpu_env
);
19353 case NM_MULSA_W_PH
:
19355 gen_helper_mulsa_w_ph(t0
, v0
, v1
, cpu_env
);
19358 generate_exception_end(ctx
, EXCP_RI
);
19362 case NM_POOL32AXF_2_24_31
:
19363 switch (extract32(ctx
->opcode
, 9, 3)) {
19364 case NM_DPAU_H_QBR
:
19366 gen_helper_dpau_h_qbr(t0
, v1
, v0
, cpu_env
);
19368 case NM_DPAQX_SA_W_PH
:
19370 gen_helper_dpaqx_sa_w_ph(t0
, v1
, v0
, cpu_env
);
19372 case NM_DPSU_H_QBR
:
19374 gen_helper_dpsu_h_qbr(t0
, v1
, v0
, cpu_env
);
19376 case NM_DPSQX_SA_W_PH
:
19378 gen_helper_dpsqx_sa_w_ph(t0
, v1
, v0
, cpu_env
);
19380 case NM_MULSAQ_S_W_PH
:
19382 gen_helper_mulsaq_s_w_ph(t0
, v1
, v0
, cpu_env
);
19385 generate_exception_end(ctx
, EXCP_RI
);
19390 generate_exception_end(ctx
, EXCP_RI
);
19394 tcg_temp_free_i32(t0
);
19397 static void gen_pool32axf_2_nanomips_insn(DisasContext
*ctx
, uint32_t opc
,
19398 int rt
, int rs
, int rd
)
19401 TCGv t0
= tcg_temp_new();
19402 TCGv t1
= tcg_temp_new();
19403 TCGv v0_t
= tcg_temp_new();
19404 TCGv v1_t
= tcg_temp_new();
19406 gen_load_gpr(v0_t
, rt
);
19407 gen_load_gpr(v1_t
, rs
);
19410 case NM_POOL32AXF_2_0_7
:
19411 switch (extract32(ctx
->opcode
, 9, 3)) {
19413 case NM_DPAQ_S_W_PH
:
19415 case NM_DPSQ_S_W_PH
:
19416 gen_pool32axf_2_multiply(ctx
, opc
, v0_t
, v1_t
, rd
);
19421 gen_load_gpr(t0
, rs
);
19423 if (rd
!= 0 && rd
!= 2) {
19424 tcg_gen_shli_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], 8 * rd
);
19425 tcg_gen_ext32u_tl(t0
, t0
);
19426 tcg_gen_shri_tl(t0
, t0
, 8 * (4 - rd
));
19427 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
19429 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
19435 int acc
= extract32(ctx
->opcode
, 14, 2);
19436 TCGv_i64 t2
= tcg_temp_new_i64();
19437 TCGv_i64 t3
= tcg_temp_new_i64();
19439 gen_load_gpr(t0
, rt
);
19440 gen_load_gpr(t1
, rs
);
19441 tcg_gen_ext_tl_i64(t2
, t0
);
19442 tcg_gen_ext_tl_i64(t3
, t1
);
19443 tcg_gen_mul_i64(t2
, t2
, t3
);
19444 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
19445 tcg_gen_add_i64(t2
, t2
, t3
);
19446 tcg_temp_free_i64(t3
);
19447 gen_move_low32(cpu_LO
[acc
], t2
);
19448 gen_move_high32(cpu_HI
[acc
], t2
);
19449 tcg_temp_free_i64(t2
);
19455 int acc
= extract32(ctx
->opcode
, 14, 2);
19456 TCGv_i32 t2
= tcg_temp_new_i32();
19457 TCGv_i32 t3
= tcg_temp_new_i32();
19459 gen_load_gpr(t0
, rs
);
19460 gen_load_gpr(t1
, rt
);
19461 tcg_gen_trunc_tl_i32(t2
, t0
);
19462 tcg_gen_trunc_tl_i32(t3
, t1
);
19463 tcg_gen_muls2_i32(t2
, t3
, t2
, t3
);
19464 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
19465 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
19466 tcg_temp_free_i32(t2
);
19467 tcg_temp_free_i32(t3
);
19472 gen_load_gpr(v1_t
, rs
);
19473 tcg_gen_movi_tl(t0
, rd
>> 3);
19474 gen_helper_extr_w(t0
, t0
, v1_t
, cpu_env
);
19475 gen_store_gpr(t0
, ret
);
19479 case NM_POOL32AXF_2_8_15
:
19480 switch (extract32(ctx
->opcode
, 9, 3)) {
19482 case NM_DPAQ_SA_L_W
:
19484 case NM_DPSQ_SA_L_W
:
19485 gen_pool32axf_2_multiply(ctx
, opc
, v0_t
, v1_t
, rd
);
19490 int acc
= extract32(ctx
->opcode
, 14, 2);
19491 TCGv_i64 t2
= tcg_temp_new_i64();
19492 TCGv_i64 t3
= tcg_temp_new_i64();
19494 gen_load_gpr(t0
, rs
);
19495 gen_load_gpr(t1
, rt
);
19496 tcg_gen_ext32u_tl(t0
, t0
);
19497 tcg_gen_ext32u_tl(t1
, t1
);
19498 tcg_gen_extu_tl_i64(t2
, t0
);
19499 tcg_gen_extu_tl_i64(t3
, t1
);
19500 tcg_gen_mul_i64(t2
, t2
, t3
);
19501 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
19502 tcg_gen_add_i64(t2
, t2
, t3
);
19503 tcg_temp_free_i64(t3
);
19504 gen_move_low32(cpu_LO
[acc
], t2
);
19505 gen_move_high32(cpu_HI
[acc
], t2
);
19506 tcg_temp_free_i64(t2
);
19512 int acc
= extract32(ctx
->opcode
, 14, 2);
19513 TCGv_i32 t2
= tcg_temp_new_i32();
19514 TCGv_i32 t3
= tcg_temp_new_i32();
19516 gen_load_gpr(t0
, rs
);
19517 gen_load_gpr(t1
, rt
);
19518 tcg_gen_trunc_tl_i32(t2
, t0
);
19519 tcg_gen_trunc_tl_i32(t3
, t1
);
19520 tcg_gen_mulu2_i32(t2
, t3
, t2
, t3
);
19521 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
19522 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
19523 tcg_temp_free_i32(t2
);
19524 tcg_temp_free_i32(t3
);
19529 tcg_gen_movi_tl(t0
, rd
>> 3);
19530 gen_helper_extr_r_w(t0
, t0
, v1_t
, cpu_env
);
19531 gen_store_gpr(t0
, ret
);
19534 generate_exception_end(ctx
, EXCP_RI
);
19538 case NM_POOL32AXF_2_16_23
:
19539 switch (extract32(ctx
->opcode
, 9, 3)) {
19540 case NM_DPAU_H_QBL
:
19541 case NM_DPAQX_S_W_PH
:
19542 case NM_DPSU_H_QBL
:
19543 case NM_DPSQX_S_W_PH
:
19544 case NM_MULSA_W_PH
:
19545 gen_pool32axf_2_multiply(ctx
, opc
, v0_t
, v1_t
, rd
);
19549 tcg_gen_movi_tl(t0
, rd
>> 3);
19550 gen_helper_extp(t0
, t0
, v1_t
, cpu_env
);
19551 gen_store_gpr(t0
, ret
);
19556 int acc
= extract32(ctx
->opcode
, 14, 2);
19557 TCGv_i64 t2
= tcg_temp_new_i64();
19558 TCGv_i64 t3
= tcg_temp_new_i64();
19560 gen_load_gpr(t0
, rs
);
19561 gen_load_gpr(t1
, rt
);
19562 tcg_gen_ext_tl_i64(t2
, t0
);
19563 tcg_gen_ext_tl_i64(t3
, t1
);
19564 tcg_gen_mul_i64(t2
, t2
, t3
);
19565 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
19566 tcg_gen_sub_i64(t2
, t3
, t2
);
19567 tcg_temp_free_i64(t3
);
19568 gen_move_low32(cpu_LO
[acc
], t2
);
19569 gen_move_high32(cpu_HI
[acc
], t2
);
19570 tcg_temp_free_i64(t2
);
19573 case NM_EXTRV_RS_W
:
19575 tcg_gen_movi_tl(t0
, rd
>> 3);
19576 gen_helper_extr_rs_w(t0
, t0
, v1_t
, cpu_env
);
19577 gen_store_gpr(t0
, ret
);
19581 case NM_POOL32AXF_2_24_31
:
19582 switch (extract32(ctx
->opcode
, 9, 3)) {
19583 case NM_DPAU_H_QBR
:
19584 case NM_DPAQX_SA_W_PH
:
19585 case NM_DPSU_H_QBR
:
19586 case NM_DPSQX_SA_W_PH
:
19587 case NM_MULSAQ_S_W_PH
:
19588 gen_pool32axf_2_multiply(ctx
, opc
, v0_t
, v1_t
, rd
);
19592 tcg_gen_movi_tl(t0
, rd
>> 3);
19593 gen_helper_extpdp(t0
, t0
, v1_t
, cpu_env
);
19594 gen_store_gpr(t0
, ret
);
19599 int acc
= extract32(ctx
->opcode
, 14, 2);
19600 TCGv_i64 t2
= tcg_temp_new_i64();
19601 TCGv_i64 t3
= tcg_temp_new_i64();
19603 gen_load_gpr(t0
, rs
);
19604 gen_load_gpr(t1
, rt
);
19605 tcg_gen_ext32u_tl(t0
, t0
);
19606 tcg_gen_ext32u_tl(t1
, t1
);
19607 tcg_gen_extu_tl_i64(t2
, t0
);
19608 tcg_gen_extu_tl_i64(t3
, t1
);
19609 tcg_gen_mul_i64(t2
, t2
, t3
);
19610 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
19611 tcg_gen_sub_i64(t2
, t3
, t2
);
19612 tcg_temp_free_i64(t3
);
19613 gen_move_low32(cpu_LO
[acc
], t2
);
19614 gen_move_high32(cpu_HI
[acc
], t2
);
19615 tcg_temp_free_i64(t2
);
19620 tcg_gen_movi_tl(t0
, rd
>> 3);
19621 gen_helper_extr_s_h(t0
, t0
, v0_t
, cpu_env
);
19622 gen_store_gpr(t0
, ret
);
19627 generate_exception_end(ctx
, EXCP_RI
);
19634 tcg_temp_free(v0_t
);
19635 tcg_temp_free(v1_t
);
19638 static void gen_pool32axf_4_nanomips_insn(DisasContext
*ctx
, uint32_t opc
,
19642 TCGv t0
= tcg_temp_new();
19643 TCGv v0_t
= tcg_temp_new();
19645 gen_load_gpr(v0_t
, rs
);
19650 gen_helper_absq_s_qb(v0_t
, v0_t
, cpu_env
);
19651 gen_store_gpr(v0_t
, ret
);
19655 gen_helper_absq_s_ph(v0_t
, v0_t
, cpu_env
);
19656 gen_store_gpr(v0_t
, ret
);
19660 gen_helper_absq_s_w(v0_t
, v0_t
, cpu_env
);
19661 gen_store_gpr(v0_t
, ret
);
19663 case NM_PRECEQ_W_PHL
:
19665 tcg_gen_andi_tl(v0_t
, v0_t
, 0xFFFF0000);
19666 tcg_gen_ext32s_tl(v0_t
, v0_t
);
19667 gen_store_gpr(v0_t
, ret
);
19669 case NM_PRECEQ_W_PHR
:
19671 tcg_gen_andi_tl(v0_t
, v0_t
, 0x0000FFFF);
19672 tcg_gen_shli_tl(v0_t
, v0_t
, 16);
19673 tcg_gen_ext32s_tl(v0_t
, v0_t
);
19674 gen_store_gpr(v0_t
, ret
);
19676 case NM_PRECEQU_PH_QBL
:
19678 gen_helper_precequ_ph_qbl(v0_t
, v0_t
);
19679 gen_store_gpr(v0_t
, ret
);
19681 case NM_PRECEQU_PH_QBR
:
19683 gen_helper_precequ_ph_qbr(v0_t
, v0_t
);
19684 gen_store_gpr(v0_t
, ret
);
19686 case NM_PRECEQU_PH_QBLA
:
19688 gen_helper_precequ_ph_qbla(v0_t
, v0_t
);
19689 gen_store_gpr(v0_t
, ret
);
19691 case NM_PRECEQU_PH_QBRA
:
19693 gen_helper_precequ_ph_qbra(v0_t
, v0_t
);
19694 gen_store_gpr(v0_t
, ret
);
19696 case NM_PRECEU_PH_QBL
:
19698 gen_helper_preceu_ph_qbl(v0_t
, v0_t
);
19699 gen_store_gpr(v0_t
, ret
);
19701 case NM_PRECEU_PH_QBR
:
19703 gen_helper_preceu_ph_qbr(v0_t
, v0_t
);
19704 gen_store_gpr(v0_t
, ret
);
19706 case NM_PRECEU_PH_QBLA
:
19708 gen_helper_preceu_ph_qbla(v0_t
, v0_t
);
19709 gen_store_gpr(v0_t
, ret
);
19711 case NM_PRECEU_PH_QBRA
:
19713 gen_helper_preceu_ph_qbra(v0_t
, v0_t
);
19714 gen_store_gpr(v0_t
, ret
);
19718 tcg_gen_ext16u_tl(v0_t
, v0_t
);
19719 tcg_gen_shli_tl(t0
, v0_t
, 16);
19720 tcg_gen_or_tl(v0_t
, v0_t
, t0
);
19721 tcg_gen_ext32s_tl(v0_t
, v0_t
);
19722 gen_store_gpr(v0_t
, ret
);
19726 tcg_gen_ext8u_tl(v0_t
, v0_t
);
19727 tcg_gen_shli_tl(t0
, v0_t
, 8);
19728 tcg_gen_or_tl(v0_t
, v0_t
, t0
);
19729 tcg_gen_shli_tl(t0
, v0_t
, 16);
19730 tcg_gen_or_tl(v0_t
, v0_t
, t0
);
19731 tcg_gen_ext32s_tl(v0_t
, v0_t
);
19732 gen_store_gpr(v0_t
, ret
);
19736 gen_helper_bitrev(v0_t
, v0_t
);
19737 gen_store_gpr(v0_t
, ret
);
19742 TCGv tv0
= tcg_temp_new();
19744 gen_load_gpr(tv0
, rt
);
19745 gen_helper_insv(v0_t
, cpu_env
, v0_t
, tv0
);
19746 gen_store_gpr(v0_t
, ret
);
19747 tcg_temp_free(tv0
);
19750 case NM_RADDU_W_QB
:
19752 gen_helper_raddu_w_qb(v0_t
, v0_t
);
19753 gen_store_gpr(v0_t
, ret
);
19756 gen_bitswap(ctx
, OPC_BITSWAP
, ret
, rs
);
19760 gen_cl(ctx
, OPC_CLO
, ret
, rs
);
19764 gen_cl(ctx
, OPC_CLZ
, ret
, rs
);
19767 gen_bshfl(ctx
, OPC_WSBH
, ret
, rs
);
19770 generate_exception_end(ctx
, EXCP_RI
);
19774 tcg_temp_free(v0_t
);
19778 static void gen_pool32axf_7_nanomips_insn(DisasContext
*ctx
, uint32_t opc
,
19779 int rt
, int rs
, int rd
)
19781 TCGv t0
= tcg_temp_new();
19782 TCGv rs_t
= tcg_temp_new();
19784 gen_load_gpr(rs_t
, rs
);
19789 tcg_gen_movi_tl(t0
, rd
>> 2);
19790 switch (extract32(ctx
->opcode
, 12, 1)) {
19793 gen_helper_shra_qb(t0
, t0
, rs_t
);
19794 gen_store_gpr(t0
, rt
);
19798 gen_helper_shra_r_qb(t0
, t0
, rs_t
);
19799 gen_store_gpr(t0
, rt
);
19805 tcg_gen_movi_tl(t0
, rd
>> 1);
19806 gen_helper_shrl_ph(t0
, t0
, rs_t
);
19807 gen_store_gpr(t0
, rt
);
19813 target_long result
;
19814 imm
= extract32(ctx
->opcode
, 13, 8);
19815 result
= (uint32_t)imm
<< 24 |
19816 (uint32_t)imm
<< 16 |
19817 (uint32_t)imm
<< 8 |
19819 result
= (int32_t)result
;
19820 tcg_gen_movi_tl(t0
, result
);
19821 gen_store_gpr(t0
, rt
);
19825 generate_exception_end(ctx
, EXCP_RI
);
19829 tcg_temp_free(rs_t
);
19833 static void gen_pool32axf_nanomips_insn(CPUMIPSState
*env
, DisasContext
*ctx
)
19835 int rt
= extract32(ctx
->opcode
, 21, 5);
19836 int rs
= extract32(ctx
->opcode
, 16, 5);
19837 int rd
= extract32(ctx
->opcode
, 11, 5);
19839 switch (extract32(ctx
->opcode
, 6, 3)) {
19840 case NM_POOL32AXF_1
:
19842 int32_t op1
= extract32(ctx
->opcode
, 9, 3);
19843 gen_pool32axf_1_nanomips_insn(ctx
, op1
, rt
, rs
, rd
);
19846 case NM_POOL32AXF_2
:
19848 int32_t op1
= extract32(ctx
->opcode
, 12, 2);
19849 gen_pool32axf_2_nanomips_insn(ctx
, op1
, rt
, rs
, rd
);
19852 case NM_POOL32AXF_4
:
19854 int32_t op1
= extract32(ctx
->opcode
, 9, 7);
19855 gen_pool32axf_4_nanomips_insn(ctx
, op1
, rt
, rs
);
19858 case NM_POOL32AXF_5
:
19859 switch (extract32(ctx
->opcode
, 9, 7)) {
19860 #ifndef CONFIG_USER_ONLY
19862 gen_cp0(env
, ctx
, OPC_TLBP
, 0, 0);
19865 gen_cp0(env
, ctx
, OPC_TLBR
, 0, 0);
19868 gen_cp0(env
, ctx
, OPC_TLBWI
, 0, 0);
19871 gen_cp0(env
, ctx
, OPC_TLBWR
, 0, 0);
19874 gen_cp0(env
, ctx
, OPC_TLBINV
, 0, 0);
19877 gen_cp0(env
, ctx
, OPC_TLBINVF
, 0, 0);
19880 check_cp0_enabled(ctx
);
19882 TCGv t0
= tcg_temp_new();
19884 save_cpu_state(ctx
, 1);
19885 gen_helper_di(t0
, cpu_env
);
19886 gen_store_gpr(t0
, rt
);
19887 /* Stop translation as we may have switched the execution mode */
19888 ctx
->base
.is_jmp
= DISAS_STOP
;
19893 check_cp0_enabled(ctx
);
19895 TCGv t0
= tcg_temp_new();
19897 save_cpu_state(ctx
, 1);
19898 gen_helper_ei(t0
, cpu_env
);
19899 gen_store_gpr(t0
, rt
);
19900 /* Stop translation as we may have switched the execution mode */
19901 ctx
->base
.is_jmp
= DISAS_STOP
;
19906 gen_load_srsgpr(rs
, rt
);
19909 gen_store_srsgpr(rs
, rt
);
19912 gen_cp0(env
, ctx
, OPC_WAIT
, 0, 0);
19915 gen_cp0(env
, ctx
, OPC_DERET
, 0, 0);
19918 gen_cp0(env
, ctx
, OPC_ERET
, 0, 0);
19922 generate_exception_end(ctx
, EXCP_RI
);
19926 case NM_POOL32AXF_7
:
19928 int32_t op1
= extract32(ctx
->opcode
, 9, 3);
19929 gen_pool32axf_7_nanomips_insn(ctx
, op1
, rt
, rs
, rd
);
19933 generate_exception_end(ctx
, EXCP_RI
);
19938 /* Immediate Value Compact Branches */
19939 static void gen_compute_imm_branch(DisasContext
*ctx
, uint32_t opc
,
19940 int rt
, int32_t imm
, int32_t offset
)
19943 int bcond_compute
= 0;
19944 TCGv t0
= tcg_temp_new();
19945 TCGv t1
= tcg_temp_new();
19947 gen_load_gpr(t0
, rt
);
19948 tcg_gen_movi_tl(t1
, imm
);
19949 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
19951 /* Load needed operands and calculate btarget */
19954 if (rt
== 0 && imm
== 0) {
19955 /* Unconditional branch */
19956 } else if (rt
== 0 && imm
!= 0) {
19961 cond
= TCG_COND_EQ
;
19967 if (imm
>= 32 && !(ctx
->hflags
& MIPS_HFLAG_64
)) {
19968 generate_exception_end(ctx
, EXCP_RI
);
19970 } else if (rt
== 0 && opc
== NM_BBEQZC
) {
19971 /* Unconditional branch */
19972 } else if (rt
== 0 && opc
== NM_BBNEZC
) {
19976 tcg_gen_shri_tl(t0
, t0
, imm
);
19977 tcg_gen_andi_tl(t0
, t0
, 1);
19978 tcg_gen_movi_tl(t1
, 0);
19980 if (opc
== NM_BBEQZC
) {
19981 cond
= TCG_COND_EQ
;
19983 cond
= TCG_COND_NE
;
19988 if (rt
== 0 && imm
== 0) {
19991 } else if (rt
== 0 && imm
!= 0) {
19992 /* Unconditional branch */
19995 cond
= TCG_COND_NE
;
19999 if (rt
== 0 && imm
== 0) {
20000 /* Unconditional branch */
20003 cond
= TCG_COND_GE
;
20008 cond
= TCG_COND_LT
;
20011 if (rt
== 0 && imm
== 0) {
20012 /* Unconditional branch */
20015 cond
= TCG_COND_GEU
;
20020 cond
= TCG_COND_LTU
;
20023 MIPS_INVAL("Immediate Value Compact branch");
20024 generate_exception_end(ctx
, EXCP_RI
);
20028 /* branch completion */
20029 clear_branch_hflags(ctx
);
20030 ctx
->base
.is_jmp
= DISAS_NORETURN
;
20032 if (bcond_compute
== 0) {
20033 /* Uncoditional compact branch */
20034 gen_goto_tb(ctx
, 0, ctx
->btarget
);
20036 /* Conditional compact branch */
20037 TCGLabel
*fs
= gen_new_label();
20039 tcg_gen_brcond_tl(tcg_invert_cond(cond
), t0
, t1
, fs
);
20041 gen_goto_tb(ctx
, 1, ctx
->btarget
);
20044 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ 4);
20052 /* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
20053 static void gen_compute_nanomips_pbalrsc_branch(DisasContext
*ctx
, int rs
,
20056 TCGv t0
= tcg_temp_new();
20057 TCGv t1
= tcg_temp_new();
20060 gen_load_gpr(t0
, rs
);
20064 tcg_gen_movi_tl(cpu_gpr
[rt
], ctx
->base
.pc_next
+ 4);
20067 /* calculate btarget */
20068 tcg_gen_shli_tl(t0
, t0
, 1);
20069 tcg_gen_movi_tl(t1
, ctx
->base
.pc_next
+ 4);
20070 gen_op_addr_add(ctx
, btarget
, t1
, t0
);
20072 /* branch completion */
20073 clear_branch_hflags(ctx
);
20074 ctx
->base
.is_jmp
= DISAS_NORETURN
;
20076 /* unconditional branch to register */
20077 tcg_gen_mov_tl(cpu_PC
, btarget
);
20078 tcg_gen_lookup_and_goto_ptr();
20084 /* nanoMIPS Branches */
20085 static void gen_compute_compact_branch_nm(DisasContext
*ctx
, uint32_t opc
,
20086 int rs
, int rt
, int32_t offset
)
20088 int bcond_compute
= 0;
20089 TCGv t0
= tcg_temp_new();
20090 TCGv t1
= tcg_temp_new();
20092 /* Load needed operands and calculate btarget */
20094 /* compact branch */
20097 gen_load_gpr(t0
, rs
);
20098 gen_load_gpr(t1
, rt
);
20100 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
20104 if (rs
== 0 || rs
== rt
) {
20105 /* OPC_BLEZALC, OPC_BGEZALC */
20106 /* OPC_BGTZALC, OPC_BLTZALC */
20107 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->base
.pc_next
+ 4);
20109 gen_load_gpr(t0
, rs
);
20110 gen_load_gpr(t1
, rt
);
20112 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
20115 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
20119 /* OPC_BEQZC, OPC_BNEZC */
20120 gen_load_gpr(t0
, rs
);
20122 ctx
->btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
20124 /* OPC_JIC, OPC_JIALC */
20125 TCGv tbase
= tcg_temp_new();
20126 TCGv toffset
= tcg_temp_new();
20128 gen_load_gpr(tbase
, rt
);
20129 tcg_gen_movi_tl(toffset
, offset
);
20130 gen_op_addr_add(ctx
, btarget
, tbase
, toffset
);
20131 tcg_temp_free(tbase
);
20132 tcg_temp_free(toffset
);
20136 MIPS_INVAL("Compact branch/jump");
20137 generate_exception_end(ctx
, EXCP_RI
);
20141 if (bcond_compute
== 0) {
20142 /* Uncoditional compact branch */
20145 gen_goto_tb(ctx
, 0, ctx
->btarget
);
20148 MIPS_INVAL("Compact branch/jump");
20149 generate_exception_end(ctx
, EXCP_RI
);
20153 /* Conditional compact branch */
20154 TCGLabel
*fs
= gen_new_label();
20158 if (rs
== 0 && rt
!= 0) {
20160 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE
), t1
, 0, fs
);
20161 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
20163 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE
), t1
, 0, fs
);
20166 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU
), t0
, t1
, fs
);
20170 if (rs
== 0 && rt
!= 0) {
20172 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT
), t1
, 0, fs
);
20173 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
20175 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT
), t1
, 0, fs
);
20178 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU
), t0
, t1
, fs
);
20182 if (rs
== 0 && rt
!= 0) {
20184 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE
), t1
, 0, fs
);
20185 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
20187 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE
), t1
, 0, fs
);
20190 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE
), t0
, t1
, fs
);
20194 if (rs
== 0 && rt
!= 0) {
20196 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT
), t1
, 0, fs
);
20197 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
20199 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT
), t1
, 0, fs
);
20202 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT
), t0
, t1
, fs
);
20206 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t0
, 0, fs
);
20209 MIPS_INVAL("Compact conditional branch/jump");
20210 generate_exception_end(ctx
, EXCP_RI
);
20214 /* branch completion */
20215 clear_branch_hflags(ctx
);
20216 ctx
->base
.is_jmp
= DISAS_NORETURN
;
20218 /* Generating branch here as compact branches don't have delay slot */
20219 gen_goto_tb(ctx
, 1, ctx
->btarget
);
20222 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ 4);
20231 /* nanoMIPS CP1 Branches */
20232 static void gen_compute_branch_cp1_nm(DisasContext
*ctx
, uint32_t op
,
20233 int32_t ft
, int32_t offset
)
20235 target_ulong btarget
;
20236 TCGv_i64 t0
= tcg_temp_new_i64();
20238 gen_load_fpr64(ctx
, t0
, ft
);
20239 tcg_gen_andi_i64(t0
, t0
, 1);
20241 btarget
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
20245 tcg_gen_xori_i64(t0
, t0
, 1);
20246 ctx
->hflags
|= MIPS_HFLAG_BC
;
20249 /* t0 already set */
20250 ctx
->hflags
|= MIPS_HFLAG_BC
;
20253 MIPS_INVAL("cp1 cond branch");
20254 generate_exception_end(ctx
, EXCP_RI
);
20258 tcg_gen_trunc_i64_tl(bcond
, t0
);
20260 ctx
->btarget
= btarget
;
20263 tcg_temp_free_i64(t0
);
20267 static void gen_p_lsx(DisasContext
*ctx
, int rd
, int rs
, int rt
)
20270 t0
= tcg_temp_new();
20271 t1
= tcg_temp_new();
20273 gen_load_gpr(t0
, rs
);
20274 gen_load_gpr(t1
, rt
);
20276 if ((extract32(ctx
->opcode
, 6, 1)) == 1) {
20277 /* PP.LSXS instructions require shifting */
20278 switch (extract32(ctx
->opcode
, 7, 4)) {
20284 tcg_gen_shli_tl(t0
, t0
, 1);
20292 tcg_gen_shli_tl(t0
, t0
, 2);
20296 tcg_gen_shli_tl(t0
, t0
, 3);
20300 gen_op_addr_add(ctx
, t0
, t0
, t1
);
20302 switch (extract32(ctx
->opcode
, 7, 4)) {
20304 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
,
20306 gen_store_gpr(t0
, rd
);
20310 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
,
20312 gen_store_gpr(t0
, rd
);
20316 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
,
20318 gen_store_gpr(t0
, rd
);
20321 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
,
20323 gen_store_gpr(t0
, rd
);
20327 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
,
20329 gen_store_gpr(t0
, rd
);
20333 gen_load_gpr(t1
, rd
);
20334 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
,
20340 gen_load_gpr(t1
, rd
);
20341 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
,
20347 gen_load_gpr(t1
, rd
);
20348 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
,
20352 /*case NM_LWC1XS:*/
20354 /*case NM_LDC1XS:*/
20356 /*case NM_SWC1XS:*/
20358 /*case NM_SDC1XS:*/
20359 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
20360 check_cp1_enabled(ctx
);
20361 switch (extract32(ctx
->opcode
, 7, 4)) {
20363 /*case NM_LWC1XS:*/
20364 gen_flt_ldst(ctx
, OPC_LWC1
, rd
, t0
);
20367 /*case NM_LDC1XS:*/
20368 gen_flt_ldst(ctx
, OPC_LDC1
, rd
, t0
);
20371 /*case NM_SWC1XS:*/
20372 gen_flt_ldst(ctx
, OPC_SWC1
, rd
, t0
);
20375 /*case NM_SDC1XS:*/
20376 gen_flt_ldst(ctx
, OPC_SDC1
, rd
, t0
);
20380 generate_exception_err(ctx
, EXCP_CpU
, 1);
20384 generate_exception_end(ctx
, EXCP_RI
);
20392 static void gen_pool32f_nanomips_insn(DisasContext
*ctx
)
20396 rt
= extract32(ctx
->opcode
, 21, 5);
20397 rs
= extract32(ctx
->opcode
, 16, 5);
20398 rd
= extract32(ctx
->opcode
, 11, 5);
20400 if (!(ctx
->CP0_Config1
& (1 << CP0C1_FP
))) {
20401 generate_exception_end(ctx
, EXCP_RI
);
20404 check_cp1_enabled(ctx
);
20405 switch (extract32(ctx
->opcode
, 0, 3)) {
20407 switch (extract32(ctx
->opcode
, 3, 7)) {
20409 gen_farith(ctx
, OPC_RINT_S
, 0, rt
, rs
, 0);
20412 gen_farith(ctx
, OPC_RINT_D
, 0, rt
, rs
, 0);
20415 gen_farith(ctx
, OPC_CLASS_S
, 0, rt
, rs
, 0);
20418 gen_farith(ctx
, OPC_CLASS_D
, 0, rt
, rs
, 0);
20421 gen_farith(ctx
, OPC_ADD_S
, rt
, rs
, rd
, 0);
20424 gen_farith(ctx
, OPC_ADD_D
, rt
, rs
, rd
, 0);
20427 gen_farith(ctx
, OPC_SUB_S
, rt
, rs
, rd
, 0);
20430 gen_farith(ctx
, OPC_SUB_D
, rt
, rs
, rd
, 0);
20433 gen_farith(ctx
, OPC_MUL_S
, rt
, rs
, rd
, 0);
20436 gen_farith(ctx
, OPC_MUL_D
, rt
, rs
, rd
, 0);
20439 gen_farith(ctx
, OPC_DIV_S
, rt
, rs
, rd
, 0);
20442 gen_farith(ctx
, OPC_DIV_D
, rt
, rs
, rd
, 0);
20445 gen_sel_s(ctx
, OPC_SELEQZ_S
, rd
, rt
, rs
);
20448 gen_sel_d(ctx
, OPC_SELEQZ_D
, rd
, rt
, rs
);
20451 gen_sel_s(ctx
, OPC_SELNEZ_S
, rd
, rt
, rs
);
20454 gen_sel_d(ctx
, OPC_SELNEZ_D
, rd
, rt
, rs
);
20457 gen_sel_s(ctx
, OPC_SEL_S
, rd
, rt
, rs
);
20460 gen_sel_d(ctx
, OPC_SEL_D
, rd
, rt
, rs
);
20463 gen_farith(ctx
, OPC_MADDF_S
, rt
, rs
, rd
, 0);
20466 gen_farith(ctx
, OPC_MADDF_D
, rt
, rs
, rd
, 0);
20469 gen_farith(ctx
, OPC_MSUBF_S
, rt
, rs
, rd
, 0);
20472 gen_farith(ctx
, OPC_MSUBF_D
, rt
, rs
, rd
, 0);
20475 generate_exception_end(ctx
, EXCP_RI
);
20480 switch (extract32(ctx
->opcode
, 3, 3)) {
20482 switch (extract32(ctx
->opcode
, 9, 1)) {
20484 gen_farith(ctx
, OPC_MIN_S
, rt
, rs
, rd
, 0);
20487 gen_farith(ctx
, OPC_MIN_D
, rt
, rs
, rd
, 0);
20492 switch (extract32(ctx
->opcode
, 9, 1)) {
20494 gen_farith(ctx
, OPC_MAX_S
, rt
, rs
, rd
, 0);
20497 gen_farith(ctx
, OPC_MAX_D
, rt
, rs
, rd
, 0);
20502 switch (extract32(ctx
->opcode
, 9, 1)) {
20504 gen_farith(ctx
, OPC_MINA_S
, rt
, rs
, rd
, 0);
20507 gen_farith(ctx
, OPC_MINA_D
, rt
, rs
, rd
, 0);
20512 switch (extract32(ctx
->opcode
, 9, 1)) {
20514 gen_farith(ctx
, OPC_MAXA_S
, rt
, rs
, rd
, 0);
20517 gen_farith(ctx
, OPC_MAXA_D
, rt
, rs
, rd
, 0);
20522 switch (extract32(ctx
->opcode
, 6, 8)) {
20524 gen_cp1(ctx
, OPC_CFC1
, rt
, rs
);
20527 gen_cp1(ctx
, OPC_CTC1
, rt
, rs
);
20530 gen_cp1(ctx
, OPC_MFC1
, rt
, rs
);
20533 gen_cp1(ctx
, OPC_MTC1
, rt
, rs
);
20536 gen_cp1(ctx
, OPC_MFHC1
, rt
, rs
);
20539 gen_cp1(ctx
, OPC_MTHC1
, rt
, rs
);
20542 gen_farith(ctx
, OPC_CVT_S_PL
, -1, rs
, rt
, 0);
20545 gen_farith(ctx
, OPC_CVT_S_PU
, -1, rs
, rt
, 0);
20548 switch (extract32(ctx
->opcode
, 6, 9)) {
20550 gen_farith(ctx
, OPC_CVT_L_S
, -1, rs
, rt
, 0);
20553 gen_farith(ctx
, OPC_CVT_L_D
, -1, rs
, rt
, 0);
20556 gen_farith(ctx
, OPC_CVT_W_S
, -1, rs
, rt
, 0);
20559 gen_farith(ctx
, OPC_CVT_W_D
, -1, rs
, rt
, 0);
20562 gen_farith(ctx
, OPC_RSQRT_S
, -1, rs
, rt
, 0);
20565 gen_farith(ctx
, OPC_RSQRT_D
, -1, rs
, rt
, 0);
20568 gen_farith(ctx
, OPC_SQRT_S
, -1, rs
, rt
, 0);
20571 gen_farith(ctx
, OPC_SQRT_D
, -1, rs
, rt
, 0);
20574 gen_farith(ctx
, OPC_RECIP_S
, -1, rs
, rt
, 0);
20577 gen_farith(ctx
, OPC_RECIP_D
, -1, rs
, rt
, 0);
20580 gen_farith(ctx
, OPC_FLOOR_L_S
, -1, rs
, rt
, 0);
20583 gen_farith(ctx
, OPC_FLOOR_L_D
, -1, rs
, rt
, 0);
20586 gen_farith(ctx
, OPC_FLOOR_W_S
, -1, rs
, rt
, 0);
20589 gen_farith(ctx
, OPC_FLOOR_W_D
, -1, rs
, rt
, 0);
20592 gen_farith(ctx
, OPC_CEIL_L_S
, -1, rs
, rt
, 0);
20595 gen_farith(ctx
, OPC_CEIL_L_D
, -1, rs
, rt
, 0);
20598 gen_farith(ctx
, OPC_CEIL_W_S
, -1, rs
, rt
, 0);
20601 gen_farith(ctx
, OPC_CEIL_W_D
, -1, rs
, rt
, 0);
20604 gen_farith(ctx
, OPC_TRUNC_L_S
, -1, rs
, rt
, 0);
20607 gen_farith(ctx
, OPC_TRUNC_L_D
, -1, rs
, rt
, 0);
20610 gen_farith(ctx
, OPC_TRUNC_W_S
, -1, rs
, rt
, 0);
20613 gen_farith(ctx
, OPC_TRUNC_W_D
, -1, rs
, rt
, 0);
20616 gen_farith(ctx
, OPC_ROUND_L_S
, -1, rs
, rt
, 0);
20619 gen_farith(ctx
, OPC_ROUND_L_D
, -1, rs
, rt
, 0);
20622 gen_farith(ctx
, OPC_ROUND_W_S
, -1, rs
, rt
, 0);
20625 gen_farith(ctx
, OPC_ROUND_W_D
, -1, rs
, rt
, 0);
20628 gen_farith(ctx
, OPC_MOV_S
, -1, rs
, rt
, 0);
20631 gen_farith(ctx
, OPC_MOV_D
, -1, rs
, rt
, 0);
20634 gen_farith(ctx
, OPC_ABS_S
, -1, rs
, rt
, 0);
20637 gen_farith(ctx
, OPC_ABS_D
, -1, rs
, rt
, 0);
20640 gen_farith(ctx
, OPC_NEG_S
, -1, rs
, rt
, 0);
20643 gen_farith(ctx
, OPC_NEG_D
, -1, rs
, rt
, 0);
20646 gen_farith(ctx
, OPC_CVT_D_S
, -1, rs
, rt
, 0);
20649 gen_farith(ctx
, OPC_CVT_D_W
, -1, rs
, rt
, 0);
20652 gen_farith(ctx
, OPC_CVT_D_L
, -1, rs
, rt
, 0);
20655 gen_farith(ctx
, OPC_CVT_S_D
, -1, rs
, rt
, 0);
20658 gen_farith(ctx
, OPC_CVT_S_W
, -1, rs
, rt
, 0);
20661 gen_farith(ctx
, OPC_CVT_S_L
, -1, rs
, rt
, 0);
20664 generate_exception_end(ctx
, EXCP_RI
);
20673 switch (extract32(ctx
->opcode
, 3, 3)) {
20674 case NM_CMP_CONDN_S
:
20675 gen_r6_cmp_s(ctx
, extract32(ctx
->opcode
, 6, 5), rt
, rs
, rd
);
20677 case NM_CMP_CONDN_D
:
20678 gen_r6_cmp_d(ctx
, extract32(ctx
->opcode
, 6, 5), rt
, rs
, rd
);
20681 generate_exception_end(ctx
, EXCP_RI
);
20686 generate_exception_end(ctx
, EXCP_RI
);
20691 static void gen_pool32a5_nanomips_insn(DisasContext
*ctx
, int opc
,
20692 int rd
, int rs
, int rt
)
20695 TCGv t0
= tcg_temp_new();
20696 TCGv v1_t
= tcg_temp_new();
20697 TCGv v2_t
= tcg_temp_new();
20699 gen_load_gpr(v1_t
, rs
);
20700 gen_load_gpr(v2_t
, rt
);
20705 gen_helper_cmp_eq_ph(v1_t
, v2_t
, cpu_env
);
20709 gen_helper_cmp_lt_ph(v1_t
, v2_t
, cpu_env
);
20713 gen_helper_cmp_le_ph(v1_t
, v2_t
, cpu_env
);
20715 case NM_CMPU_EQ_QB
:
20717 gen_helper_cmpu_eq_qb(v1_t
, v2_t
, cpu_env
);
20719 case NM_CMPU_LT_QB
:
20721 gen_helper_cmpu_lt_qb(v1_t
, v2_t
, cpu_env
);
20723 case NM_CMPU_LE_QB
:
20725 gen_helper_cmpu_le_qb(v1_t
, v2_t
, cpu_env
);
20727 case NM_CMPGU_EQ_QB
:
20729 gen_helper_cmpgu_eq_qb(v1_t
, v1_t
, v2_t
);
20730 gen_store_gpr(v1_t
, ret
);
20732 case NM_CMPGU_LT_QB
:
20734 gen_helper_cmpgu_lt_qb(v1_t
, v1_t
, v2_t
);
20735 gen_store_gpr(v1_t
, ret
);
20737 case NM_CMPGU_LE_QB
:
20739 gen_helper_cmpgu_le_qb(v1_t
, v1_t
, v2_t
);
20740 gen_store_gpr(v1_t
, ret
);
20742 case NM_CMPGDU_EQ_QB
:
20744 gen_helper_cmpgu_eq_qb(v1_t
, v1_t
, v2_t
);
20745 tcg_gen_deposit_tl(cpu_dspctrl
, cpu_dspctrl
, v1_t
, 24, 4);
20746 gen_store_gpr(v1_t
, ret
);
20748 case NM_CMPGDU_LT_QB
:
20750 gen_helper_cmpgu_lt_qb(v1_t
, v1_t
, v2_t
);
20751 tcg_gen_deposit_tl(cpu_dspctrl
, cpu_dspctrl
, v1_t
, 24, 4);
20752 gen_store_gpr(v1_t
, ret
);
20754 case NM_CMPGDU_LE_QB
:
20756 gen_helper_cmpgu_le_qb(v1_t
, v1_t
, v2_t
);
20757 tcg_gen_deposit_tl(cpu_dspctrl
, cpu_dspctrl
, v1_t
, 24, 4);
20758 gen_store_gpr(v1_t
, ret
);
20762 gen_helper_packrl_ph(v1_t
, v1_t
, v2_t
);
20763 gen_store_gpr(v1_t
, ret
);
20767 gen_helper_pick_qb(v1_t
, v1_t
, v2_t
, cpu_env
);
20768 gen_store_gpr(v1_t
, ret
);
20772 gen_helper_pick_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20773 gen_store_gpr(v1_t
, ret
);
20777 gen_helper_addq_s_w(v1_t
, v1_t
, v2_t
, cpu_env
);
20778 gen_store_gpr(v1_t
, ret
);
20782 gen_helper_subq_s_w(v1_t
, v1_t
, v2_t
, cpu_env
);
20783 gen_store_gpr(v1_t
, ret
);
20787 gen_helper_addsc(v1_t
, v1_t
, v2_t
, cpu_env
);
20788 gen_store_gpr(v1_t
, ret
);
20792 gen_helper_addwc(v1_t
, v1_t
, v2_t
, cpu_env
);
20793 gen_store_gpr(v1_t
, ret
);
20797 switch (extract32(ctx
->opcode
, 10, 1)) {
20800 gen_helper_addq_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20801 gen_store_gpr(v1_t
, ret
);
20805 gen_helper_addq_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20806 gen_store_gpr(v1_t
, ret
);
20810 case NM_ADDQH_R_PH
:
20812 switch (extract32(ctx
->opcode
, 10, 1)) {
20815 gen_helper_addqh_ph(v1_t
, v1_t
, v2_t
);
20816 gen_store_gpr(v1_t
, ret
);
20820 gen_helper_addqh_r_ph(v1_t
, v1_t
, v2_t
);
20821 gen_store_gpr(v1_t
, ret
);
20827 switch (extract32(ctx
->opcode
, 10, 1)) {
20830 gen_helper_addqh_w(v1_t
, v1_t
, v2_t
);
20831 gen_store_gpr(v1_t
, ret
);
20835 gen_helper_addqh_r_w(v1_t
, v1_t
, v2_t
);
20836 gen_store_gpr(v1_t
, ret
);
20842 switch (extract32(ctx
->opcode
, 10, 1)) {
20845 gen_helper_addu_qb(v1_t
, v1_t
, v2_t
, cpu_env
);
20846 gen_store_gpr(v1_t
, ret
);
20850 gen_helper_addu_s_qb(v1_t
, v1_t
, v2_t
, cpu_env
);
20851 gen_store_gpr(v1_t
, ret
);
20857 switch (extract32(ctx
->opcode
, 10, 1)) {
20860 gen_helper_addu_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20861 gen_store_gpr(v1_t
, ret
);
20865 gen_helper_addu_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20866 gen_store_gpr(v1_t
, ret
);
20870 case NM_ADDUH_R_QB
:
20872 switch (extract32(ctx
->opcode
, 10, 1)) {
20875 gen_helper_adduh_qb(v1_t
, v1_t
, v2_t
);
20876 gen_store_gpr(v1_t
, ret
);
20880 gen_helper_adduh_r_qb(v1_t
, v1_t
, v2_t
);
20881 gen_store_gpr(v1_t
, ret
);
20885 case NM_SHRAV_R_PH
:
20887 switch (extract32(ctx
->opcode
, 10, 1)) {
20890 gen_helper_shra_ph(v1_t
, v1_t
, v2_t
);
20891 gen_store_gpr(v1_t
, ret
);
20895 gen_helper_shra_r_ph(v1_t
, v1_t
, v2_t
);
20896 gen_store_gpr(v1_t
, ret
);
20900 case NM_SHRAV_R_QB
:
20902 switch (extract32(ctx
->opcode
, 10, 1)) {
20905 gen_helper_shra_qb(v1_t
, v1_t
, v2_t
);
20906 gen_store_gpr(v1_t
, ret
);
20910 gen_helper_shra_r_qb(v1_t
, v1_t
, v2_t
);
20911 gen_store_gpr(v1_t
, ret
);
20917 switch (extract32(ctx
->opcode
, 10, 1)) {
20920 gen_helper_subq_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20921 gen_store_gpr(v1_t
, ret
);
20925 gen_helper_subq_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20926 gen_store_gpr(v1_t
, ret
);
20930 case NM_SUBQH_R_PH
:
20932 switch (extract32(ctx
->opcode
, 10, 1)) {
20935 gen_helper_subqh_ph(v1_t
, v1_t
, v2_t
);
20936 gen_store_gpr(v1_t
, ret
);
20940 gen_helper_subqh_r_ph(v1_t
, v1_t
, v2_t
);
20941 gen_store_gpr(v1_t
, ret
);
20947 switch (extract32(ctx
->opcode
, 10, 1)) {
20950 gen_helper_subqh_w(v1_t
, v1_t
, v2_t
);
20951 gen_store_gpr(v1_t
, ret
);
20955 gen_helper_subqh_r_w(v1_t
, v1_t
, v2_t
);
20956 gen_store_gpr(v1_t
, ret
);
20962 switch (extract32(ctx
->opcode
, 10, 1)) {
20965 gen_helper_subu_qb(v1_t
, v1_t
, v2_t
, cpu_env
);
20966 gen_store_gpr(v1_t
, ret
);
20970 gen_helper_subu_s_qb(v1_t
, v1_t
, v2_t
, cpu_env
);
20971 gen_store_gpr(v1_t
, ret
);
20977 switch (extract32(ctx
->opcode
, 10, 1)) {
20980 gen_helper_subu_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20981 gen_store_gpr(v1_t
, ret
);
20985 gen_helper_subu_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
20986 gen_store_gpr(v1_t
, ret
);
20990 case NM_SUBUH_R_QB
:
20992 switch (extract32(ctx
->opcode
, 10, 1)) {
20995 gen_helper_subuh_qb(v1_t
, v1_t
, v2_t
);
20996 gen_store_gpr(v1_t
, ret
);
21000 gen_helper_subuh_r_qb(v1_t
, v1_t
, v2_t
);
21001 gen_store_gpr(v1_t
, ret
);
21005 case NM_SHLLV_S_PH
:
21007 switch (extract32(ctx
->opcode
, 10, 1)) {
21010 gen_helper_shll_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21011 gen_store_gpr(v1_t
, ret
);
21015 gen_helper_shll_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21016 gen_store_gpr(v1_t
, ret
);
21020 case NM_PRECR_SRA_R_PH_W
:
21022 switch (extract32(ctx
->opcode
, 10, 1)) {
21024 /* PRECR_SRA_PH_W */
21026 TCGv_i32 sa_t
= tcg_const_i32(rd
);
21027 gen_helper_precr_sra_ph_w(v1_t
, sa_t
, v1_t
,
21029 gen_store_gpr(v1_t
, rt
);
21030 tcg_temp_free_i32(sa_t
);
21034 /* PRECR_SRA_R_PH_W */
21036 TCGv_i32 sa_t
= tcg_const_i32(rd
);
21037 gen_helper_precr_sra_r_ph_w(v1_t
, sa_t
, v1_t
,
21039 gen_store_gpr(v1_t
, rt
);
21040 tcg_temp_free_i32(sa_t
);
21045 case NM_MULEU_S_PH_QBL
:
21047 gen_helper_muleu_s_ph_qbl(v1_t
, v1_t
, v2_t
, cpu_env
);
21048 gen_store_gpr(v1_t
, ret
);
21050 case NM_MULEU_S_PH_QBR
:
21052 gen_helper_muleu_s_ph_qbr(v1_t
, v1_t
, v2_t
, cpu_env
);
21053 gen_store_gpr(v1_t
, ret
);
21055 case NM_MULQ_RS_PH
:
21057 gen_helper_mulq_rs_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21058 gen_store_gpr(v1_t
, ret
);
21062 gen_helper_mulq_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21063 gen_store_gpr(v1_t
, ret
);
21067 gen_helper_mulq_rs_w(v1_t
, v1_t
, v2_t
, cpu_env
);
21068 gen_store_gpr(v1_t
, ret
);
21072 gen_helper_mulq_s_w(v1_t
, v1_t
, v2_t
, cpu_env
);
21073 gen_store_gpr(v1_t
, ret
);
21077 gen_load_gpr(t0
, rs
);
21079 tcg_gen_deposit_tl(cpu_gpr
[rt
], t0
, cpu_gpr
[rt
], rd
, 32 - rd
);
21081 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
21085 gen_helper_modsub(v1_t
, v1_t
, v2_t
);
21086 gen_store_gpr(v1_t
, ret
);
21090 gen_helper_shra_r_w(v1_t
, v1_t
, v2_t
);
21091 gen_store_gpr(v1_t
, ret
);
21095 gen_helper_shrl_ph(v1_t
, v1_t
, v2_t
);
21096 gen_store_gpr(v1_t
, ret
);
21100 gen_helper_shrl_qb(v1_t
, v1_t
, v2_t
);
21101 gen_store_gpr(v1_t
, ret
);
21105 gen_helper_shll_qb(v1_t
, v1_t
, v2_t
, cpu_env
);
21106 gen_store_gpr(v1_t
, ret
);
21110 gen_helper_shll_s_w(v1_t
, v1_t
, v2_t
, cpu_env
);
21111 gen_store_gpr(v1_t
, ret
);
21116 TCGv tv0
= tcg_temp_new();
21117 TCGv tv1
= tcg_temp_new();
21118 int16_t imm
= extract32(ctx
->opcode
, 16, 7);
21120 tcg_gen_movi_tl(tv0
, rd
>> 3);
21121 tcg_gen_movi_tl(tv1
, imm
);
21122 gen_helper_shilo(tv0
, tv1
, cpu_env
);
21125 case NM_MULEQ_S_W_PHL
:
21127 gen_helper_muleq_s_w_phl(v1_t
, v1_t
, v2_t
, cpu_env
);
21128 gen_store_gpr(v1_t
, ret
);
21130 case NM_MULEQ_S_W_PHR
:
21132 gen_helper_muleq_s_w_phr(v1_t
, v1_t
, v2_t
, cpu_env
);
21133 gen_store_gpr(v1_t
, ret
);
21137 switch (extract32(ctx
->opcode
, 10, 1)) {
21140 gen_helper_mul_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21141 gen_store_gpr(v1_t
, ret
);
21145 gen_helper_mul_s_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21146 gen_store_gpr(v1_t
, ret
);
21150 case NM_PRECR_QB_PH
:
21152 gen_helper_precr_qb_ph(v1_t
, v1_t
, v2_t
);
21153 gen_store_gpr(v1_t
, ret
);
21155 case NM_PRECRQ_QB_PH
:
21157 gen_helper_precrq_qb_ph(v1_t
, v1_t
, v2_t
);
21158 gen_store_gpr(v1_t
, ret
);
21160 case NM_PRECRQ_PH_W
:
21162 gen_helper_precrq_ph_w(v1_t
, v1_t
, v2_t
);
21163 gen_store_gpr(v1_t
, ret
);
21165 case NM_PRECRQ_RS_PH_W
:
21167 gen_helper_precrq_rs_ph_w(v1_t
, v1_t
, v2_t
, cpu_env
);
21168 gen_store_gpr(v1_t
, ret
);
21170 case NM_PRECRQU_S_QB_PH
:
21172 gen_helper_precrqu_s_qb_ph(v1_t
, v1_t
, v2_t
, cpu_env
);
21173 gen_store_gpr(v1_t
, ret
);
21177 tcg_gen_movi_tl(t0
, rd
);
21178 gen_helper_shra_r_w(v1_t
, t0
, v1_t
);
21179 gen_store_gpr(v1_t
, rt
);
21183 tcg_gen_movi_tl(t0
, rd
>> 1);
21184 switch (extract32(ctx
->opcode
, 10, 1)) {
21187 gen_helper_shra_ph(v1_t
, t0
, v1_t
);
21188 gen_store_gpr(v1_t
, rt
);
21192 gen_helper_shra_r_ph(v1_t
, t0
, v1_t
);
21193 gen_store_gpr(v1_t
, rt
);
21199 tcg_gen_movi_tl(t0
, rd
>> 1);
21200 switch (extract32(ctx
->opcode
, 10, 2)) {
21203 gen_helper_shll_ph(v1_t
, t0
, v1_t
, cpu_env
);
21204 gen_store_gpr(v1_t
, rt
);
21208 gen_helper_shll_s_ph(v1_t
, t0
, v1_t
, cpu_env
);
21209 gen_store_gpr(v1_t
, rt
);
21212 generate_exception_end(ctx
, EXCP_RI
);
21218 tcg_gen_movi_tl(t0
, rd
);
21219 gen_helper_shll_s_w(v1_t
, t0
, v1_t
, cpu_env
);
21220 gen_store_gpr(v1_t
, rt
);
21226 imm
= sextract32(ctx
->opcode
, 11, 11);
21227 imm
= (int16_t)(imm
<< 6) >> 6;
21229 tcg_gen_movi_tl(cpu_gpr
[rt
], dup_const(MO_16
, imm
));
21234 generate_exception_end(ctx
, EXCP_RI
);
21239 static int decode_nanomips_32_48_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
21247 insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
+ 2);
21248 ctx
->opcode
= (ctx
->opcode
<< 16) | insn
;
21250 rt
= extract32(ctx
->opcode
, 21, 5);
21251 rs
= extract32(ctx
->opcode
, 16, 5);
21252 rd
= extract32(ctx
->opcode
, 11, 5);
21254 op
= extract32(ctx
->opcode
, 26, 6);
21259 switch (extract32(ctx
->opcode
, 19, 2)) {
21262 generate_exception_end(ctx
, EXCP_RI
);
21265 if ((extract32(ctx
->opcode
, 18, 1)) == NM_SYSCALL
) {
21266 generate_exception_end(ctx
, EXCP_SYSCALL
);
21268 generate_exception_end(ctx
, EXCP_RI
);
21272 generate_exception_end(ctx
, EXCP_BREAK
);
21275 if (is_uhi(extract32(ctx
->opcode
, 0, 19))) {
21276 gen_helper_do_semihosting(cpu_env
);
21278 if (ctx
->hflags
& MIPS_HFLAG_SBRI
) {
21279 generate_exception_end(ctx
, EXCP_RI
);
21281 generate_exception_end(ctx
, EXCP_DBp
);
21288 imm
= extract32(ctx
->opcode
, 0, 16);
21290 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], imm
);
21292 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
);
21294 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
21299 offset
= sextract32(ctx
->opcode
, 0, 1) << 21 |
21300 extract32(ctx
->opcode
, 1, 20) << 1;
21301 target_long addr
= addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
21302 tcg_gen_movi_tl(cpu_gpr
[rt
], addr
);
21306 switch (ctx
->opcode
& 0x07) {
21308 gen_pool32a0_nanomips_insn(env
, ctx
);
21312 int32_t op1
= extract32(ctx
->opcode
, 3, 7);
21313 gen_pool32a5_nanomips_insn(ctx
, op1
, rd
, rs
, rt
);
21317 switch (extract32(ctx
->opcode
, 3, 3)) {
21319 gen_p_lsx(ctx
, rd
, rs
, rt
);
21323 * In nanoMIPS, the shift field directly encodes the shift
21324 * amount, meaning that the supported shift values are in
21325 * the range 0 to 3 (instead of 1 to 4 in MIPSR6).
21327 gen_lsa(ctx
, OPC_LSA
, rd
, rs
, rt
,
21328 extract32(ctx
->opcode
, 9, 2) - 1);
21331 gen_ext(ctx
, 32, rd
, rs
, rt
, extract32(ctx
->opcode
, 6, 5));
21334 gen_pool32axf_nanomips_insn(env
, ctx
);
21337 generate_exception_end(ctx
, EXCP_RI
);
21342 generate_exception_end(ctx
, EXCP_RI
);
21347 switch (ctx
->opcode
& 0x03) {
21350 offset
= extract32(ctx
->opcode
, 0, 21);
21351 gen_op_addr_addi(ctx
, cpu_gpr
[rt
], cpu_gpr
[28], offset
);
21355 gen_ld(ctx
, OPC_LW
, rt
, 28, extract32(ctx
->opcode
, 2, 19) << 2);
21358 gen_st(ctx
, OPC_SW
, rt
, 28, extract32(ctx
->opcode
, 2, 19) << 2);
21361 generate_exception_end(ctx
, EXCP_RI
);
21367 insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
+ 4);
21368 target_long addr_off
= extract32(ctx
->opcode
, 0, 16) | insn
<< 16;
21369 switch (extract32(ctx
->opcode
, 16, 5)) {
21373 tcg_gen_movi_tl(cpu_gpr
[rt
], addr_off
);
21379 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], addr_off
);
21380 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
21386 gen_op_addr_addi(ctx
, cpu_gpr
[rt
], cpu_gpr
[28], addr_off
);
21392 target_long addr
= addr_add(ctx
, ctx
->base
.pc_next
+ 6,
21395 tcg_gen_movi_tl(cpu_gpr
[rt
], addr
);
21402 t0
= tcg_temp_new();
21404 target_long addr
= addr_add(ctx
, ctx
->base
.pc_next
+ 6,
21407 tcg_gen_movi_tl(t0
, addr
);
21408 tcg_gen_qemu_ld_tl(cpu_gpr
[rt
], t0
, ctx
->mem_idx
, MO_TESL
);
21416 t0
= tcg_temp_new();
21417 t1
= tcg_temp_new();
21419 target_long addr
= addr_add(ctx
, ctx
->base
.pc_next
+ 6,
21422 tcg_gen_movi_tl(t0
, addr
);
21423 gen_load_gpr(t1
, rt
);
21425 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
21432 generate_exception_end(ctx
, EXCP_RI
);
21438 switch (extract32(ctx
->opcode
, 12, 4)) {
21440 gen_logic_imm(ctx
, OPC_ORI
, rt
, rs
, extract32(ctx
->opcode
, 0, 12));
21443 gen_logic_imm(ctx
, OPC_XORI
, rt
, rs
, extract32(ctx
->opcode
, 0, 12));
21446 gen_logic_imm(ctx
, OPC_ANDI
, rt
, rs
, extract32(ctx
->opcode
, 0, 12));
21449 switch (extract32(ctx
->opcode
, 20, 1)) {
21451 switch (ctx
->opcode
& 3) {
21453 gen_save(ctx
, rt
, extract32(ctx
->opcode
, 16, 4),
21454 extract32(ctx
->opcode
, 2, 1),
21455 extract32(ctx
->opcode
, 3, 9) << 3);
21458 case NM_RESTORE_JRC
:
21459 gen_restore(ctx
, rt
, extract32(ctx
->opcode
, 16, 4),
21460 extract32(ctx
->opcode
, 2, 1),
21461 extract32(ctx
->opcode
, 3, 9) << 3);
21462 if ((ctx
->opcode
& 3) == NM_RESTORE_JRC
) {
21463 gen_compute_branch_nm(ctx
, OPC_JR
, 2, 31, 0, 0);
21467 generate_exception_end(ctx
, EXCP_RI
);
21472 generate_exception_end(ctx
, EXCP_RI
);
21477 gen_slt_imm(ctx
, OPC_SLTI
, rt
, rs
, extract32(ctx
->opcode
, 0, 12));
21480 gen_slt_imm(ctx
, OPC_SLTIU
, rt
, rs
, extract32(ctx
->opcode
, 0, 12));
21484 TCGv t0
= tcg_temp_new();
21486 imm
= extract32(ctx
->opcode
, 0, 12);
21487 gen_load_gpr(t0
, rs
);
21488 tcg_gen_setcondi_tl(TCG_COND_EQ
, t0
, t0
, imm
);
21489 gen_store_gpr(t0
, rt
);
21495 imm
= (int16_t) extract32(ctx
->opcode
, 0, 12);
21496 gen_arith_imm(ctx
, OPC_ADDIU
, rt
, rs
, -imm
);
21500 int shift
= extract32(ctx
->opcode
, 0, 5);
21501 switch (extract32(ctx
->opcode
, 5, 4)) {
21503 if (rt
== 0 && shift
== 0) {
21505 } else if (rt
== 0 && shift
== 3) {
21506 /* EHB - treat as NOP */
21507 } else if (rt
== 0 && shift
== 5) {
21508 /* PAUSE - treat as NOP */
21509 } else if (rt
== 0 && shift
== 6) {
21511 gen_sync(extract32(ctx
->opcode
, 16, 5));
21514 gen_shift_imm(ctx
, OPC_SLL
, rt
, rs
,
21515 extract32(ctx
->opcode
, 0, 5));
21519 gen_shift_imm(ctx
, OPC_SRL
, rt
, rs
,
21520 extract32(ctx
->opcode
, 0, 5));
21523 gen_shift_imm(ctx
, OPC_SRA
, rt
, rs
,
21524 extract32(ctx
->opcode
, 0, 5));
21527 gen_shift_imm(ctx
, OPC_ROTR
, rt
, rs
,
21528 extract32(ctx
->opcode
, 0, 5));
21536 TCGv t0
= tcg_temp_new();
21537 TCGv_i32 shift
= tcg_const_i32(extract32(ctx
->opcode
, 0, 5));
21538 TCGv_i32 shiftx
= tcg_const_i32(extract32(ctx
->opcode
, 7, 4)
21540 TCGv_i32 stripe
= tcg_const_i32(extract32(ctx
->opcode
, 6, 1));
21542 gen_load_gpr(t0
, rs
);
21543 gen_helper_rotx(cpu_gpr
[rt
], t0
, shift
, shiftx
, stripe
);
21546 tcg_temp_free_i32(shift
);
21547 tcg_temp_free_i32(shiftx
);
21548 tcg_temp_free_i32(stripe
);
21552 switch (((ctx
->opcode
>> 10) & 2) |
21553 (extract32(ctx
->opcode
, 5, 1))) {
21556 gen_bitops(ctx
, OPC_INS
, rt
, rs
, extract32(ctx
->opcode
, 0, 5),
21557 extract32(ctx
->opcode
, 6, 5));
21560 generate_exception_end(ctx
, EXCP_RI
);
21565 switch (((ctx
->opcode
>> 10) & 2) |
21566 (extract32(ctx
->opcode
, 5, 1))) {
21569 gen_bitops(ctx
, OPC_EXT
, rt
, rs
, extract32(ctx
->opcode
, 0, 5),
21570 extract32(ctx
->opcode
, 6, 5));
21573 generate_exception_end(ctx
, EXCP_RI
);
21578 generate_exception_end(ctx
, EXCP_RI
);
21583 gen_pool32f_nanomips_insn(ctx
);
21588 switch (extract32(ctx
->opcode
, 1, 1)) {
21591 tcg_gen_movi_tl(cpu_gpr
[rt
],
21592 sextract32(ctx
->opcode
, 0, 1) << 31 |
21593 extract32(ctx
->opcode
, 2, 10) << 21 |
21594 extract32(ctx
->opcode
, 12, 9) << 12);
21599 offset
= sextract32(ctx
->opcode
, 0, 1) << 31 |
21600 extract32(ctx
->opcode
, 2, 10) << 21 |
21601 extract32(ctx
->opcode
, 12, 9) << 12;
21603 addr
= ~0xFFF & addr_add(ctx
, ctx
->base
.pc_next
+ 4, offset
);
21604 tcg_gen_movi_tl(cpu_gpr
[rt
], addr
);
21611 uint32_t u
= extract32(ctx
->opcode
, 0, 18);
21613 switch (extract32(ctx
->opcode
, 18, 3)) {
21615 gen_ld(ctx
, OPC_LB
, rt
, 28, u
);
21618 gen_st(ctx
, OPC_SB
, rt
, 28, u
);
21621 gen_ld(ctx
, OPC_LBU
, rt
, 28, u
);
21625 gen_op_addr_addi(ctx
, cpu_gpr
[rt
], cpu_gpr
[28], u
);
21630 switch (ctx
->opcode
& 1) {
21632 gen_ld(ctx
, OPC_LH
, rt
, 28, u
);
21635 gen_ld(ctx
, OPC_LHU
, rt
, 28, u
);
21641 switch (ctx
->opcode
& 1) {
21643 gen_st(ctx
, OPC_SH
, rt
, 28, u
);
21646 generate_exception_end(ctx
, EXCP_RI
);
21652 switch (ctx
->opcode
& 0x3) {
21654 gen_cop1_ldst(ctx
, OPC_LWC1
, rt
, 28, u
);
21657 gen_cop1_ldst(ctx
, OPC_LDC1
, rt
, 28, u
);
21660 gen_cop1_ldst(ctx
, OPC_SWC1
, rt
, 28, u
);
21663 gen_cop1_ldst(ctx
, OPC_SDC1
, rt
, 28, u
);
21668 generate_exception_end(ctx
, EXCP_RI
);
21675 uint32_t u
= extract32(ctx
->opcode
, 0, 12);
21677 switch (extract32(ctx
->opcode
, 12, 4)) {
21682 * Break the TB to be able to sync copied instructions
21685 ctx
->base
.is_jmp
= DISAS_STOP
;
21688 /* Treat as NOP. */
21692 gen_ld(ctx
, OPC_LB
, rt
, rs
, u
);
21695 gen_ld(ctx
, OPC_LH
, rt
, rs
, u
);
21698 gen_ld(ctx
, OPC_LW
, rt
, rs
, u
);
21701 gen_ld(ctx
, OPC_LBU
, rt
, rs
, u
);
21704 gen_ld(ctx
, OPC_LHU
, rt
, rs
, u
);
21707 gen_st(ctx
, OPC_SB
, rt
, rs
, u
);
21710 gen_st(ctx
, OPC_SH
, rt
, rs
, u
);
21713 gen_st(ctx
, OPC_SW
, rt
, rs
, u
);
21716 gen_cop1_ldst(ctx
, OPC_LWC1
, rt
, rs
, u
);
21719 gen_cop1_ldst(ctx
, OPC_LDC1
, rt
, rs
, u
);
21722 gen_cop1_ldst(ctx
, OPC_SWC1
, rt
, rs
, u
);
21725 gen_cop1_ldst(ctx
, OPC_SDC1
, rt
, rs
, u
);
21728 generate_exception_end(ctx
, EXCP_RI
);
21735 int32_t s
= (sextract32(ctx
->opcode
, 15, 1) << 8) |
21736 extract32(ctx
->opcode
, 0, 8);
21738 switch (extract32(ctx
->opcode
, 8, 3)) {
21740 switch (extract32(ctx
->opcode
, 11, 4)) {
21742 gen_ld(ctx
, OPC_LB
, rt
, rs
, s
);
21745 gen_ld(ctx
, OPC_LH
, rt
, rs
, s
);
21748 gen_ld(ctx
, OPC_LW
, rt
, rs
, s
);
21751 gen_ld(ctx
, OPC_LBU
, rt
, rs
, s
);
21754 gen_ld(ctx
, OPC_LHU
, rt
, rs
, s
);
21757 gen_st(ctx
, OPC_SB
, rt
, rs
, s
);
21760 gen_st(ctx
, OPC_SH
, rt
, rs
, s
);
21763 gen_st(ctx
, OPC_SW
, rt
, rs
, s
);
21766 gen_cop1_ldst(ctx
, OPC_LWC1
, rt
, rs
, s
);
21769 gen_cop1_ldst(ctx
, OPC_LDC1
, rt
, rs
, s
);
21772 gen_cop1_ldst(ctx
, OPC_SWC1
, rt
, rs
, s
);
21775 gen_cop1_ldst(ctx
, OPC_SDC1
, rt
, rs
, s
);
21781 * Break the TB to be able to sync copied instructions
21784 ctx
->base
.is_jmp
= DISAS_STOP
;
21787 /* Treat as NOP. */
21791 generate_exception_end(ctx
, EXCP_RI
);
21796 switch (extract32(ctx
->opcode
, 11, 4)) {
21801 TCGv t0
= tcg_temp_new();
21802 TCGv t1
= tcg_temp_new();
21804 gen_base_offset_addr(ctx
, t0
, rs
, s
);
21806 switch (extract32(ctx
->opcode
, 11, 4)) {
21808 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESW
|
21810 gen_store_gpr(t0
, rt
);
21813 gen_load_gpr(t1
, rt
);
21814 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUW
|
21823 switch (ctx
->opcode
& 0x03) {
21825 gen_ld(ctx
, OPC_LL
, rt
, rs
, s
);
21829 gen_llwp(ctx
, rs
, 0, rt
, extract32(ctx
->opcode
, 3, 5));
21834 switch (ctx
->opcode
& 0x03) {
21836 gen_st_cond(ctx
, rt
, rs
, s
, MO_TESL
, false);
21840 gen_scwp(ctx
, rs
, 0, rt
, extract32(ctx
->opcode
, 3, 5),
21846 check_cp0_enabled(ctx
);
21847 if (ctx
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
21848 gen_cache_operation(ctx
, rt
, rs
, s
);
21854 switch (extract32(ctx
->opcode
, 11, 4)) {
21857 check_cp0_enabled(ctx
);
21858 gen_ld(ctx
, OPC_LBE
, rt
, rs
, s
);
21862 check_cp0_enabled(ctx
);
21863 gen_st(ctx
, OPC_SBE
, rt
, rs
, s
);
21867 check_cp0_enabled(ctx
);
21868 gen_ld(ctx
, OPC_LBUE
, rt
, rs
, s
);
21872 /* case NM_SYNCIE */
21874 check_cp0_enabled(ctx
);
21876 * Break the TB to be able to sync copied instructions
21879 ctx
->base
.is_jmp
= DISAS_STOP
;
21881 /* case NM_PREFE */
21883 check_cp0_enabled(ctx
);
21884 /* Treat as NOP. */
21889 check_cp0_enabled(ctx
);
21890 gen_ld(ctx
, OPC_LHE
, rt
, rs
, s
);
21894 check_cp0_enabled(ctx
);
21895 gen_st(ctx
, OPC_SHE
, rt
, rs
, s
);
21899 check_cp0_enabled(ctx
);
21900 gen_ld(ctx
, OPC_LHUE
, rt
, rs
, s
);
21903 check_nms_dl_il_sl_tl_l2c(ctx
);
21904 gen_cache_operation(ctx
, rt
, rs
, s
);
21908 check_cp0_enabled(ctx
);
21909 gen_ld(ctx
, OPC_LWE
, rt
, rs
, s
);
21913 check_cp0_enabled(ctx
);
21914 gen_st(ctx
, OPC_SWE
, rt
, rs
, s
);
21917 switch (extract32(ctx
->opcode
, 2, 2)) {
21921 check_cp0_enabled(ctx
);
21922 gen_ld(ctx
, OPC_LLE
, rt
, rs
, s
);
21927 check_cp0_enabled(ctx
);
21928 gen_llwp(ctx
, rs
, 0, rt
, extract32(ctx
->opcode
, 3, 5));
21931 generate_exception_end(ctx
, EXCP_RI
);
21936 switch (extract32(ctx
->opcode
, 2, 2)) {
21940 check_cp0_enabled(ctx
);
21941 gen_st_cond(ctx
, rt
, rs
, s
, MO_TESL
, true);
21946 check_cp0_enabled(ctx
);
21947 gen_scwp(ctx
, rs
, 0, rt
, extract32(ctx
->opcode
, 3, 5),
21951 generate_exception_end(ctx
, EXCP_RI
);
21961 int count
= extract32(ctx
->opcode
, 12, 3);
21964 offset
= sextract32(ctx
->opcode
, 15, 1) << 8 |
21965 extract32(ctx
->opcode
, 0, 8);
21966 TCGv va
= tcg_temp_new();
21967 TCGv t1
= tcg_temp_new();
21968 MemOp memop
= (extract32(ctx
->opcode
, 8, 3)) ==
21969 NM_P_LS_UAWM
? MO_UNALN
: 0;
21971 count
= (count
== 0) ? 8 : count
;
21972 while (counter
!= count
) {
21973 int this_rt
= ((rt
+ counter
) & 0x1f) | (rt
& 0x10);
21974 int this_offset
= offset
+ (counter
<< 2);
21976 gen_base_offset_addr(ctx
, va
, rs
, this_offset
);
21978 switch (extract32(ctx
->opcode
, 11, 1)) {
21980 tcg_gen_qemu_ld_tl(t1
, va
, ctx
->mem_idx
,
21982 gen_store_gpr(t1
, this_rt
);
21983 if ((this_rt
== rs
) &&
21984 (counter
!= (count
- 1))) {
21985 /* UNPREDICTABLE */
21989 this_rt
= (rt
== 0) ? 0 : this_rt
;
21990 gen_load_gpr(t1
, this_rt
);
21991 tcg_gen_qemu_st_tl(t1
, va
, ctx
->mem_idx
,
22002 generate_exception_end(ctx
, EXCP_RI
);
22010 TCGv t0
= tcg_temp_new();
22011 int32_t s
= sextract32(ctx
->opcode
, 0, 1) << 21 |
22012 extract32(ctx
->opcode
, 1, 20) << 1;
22013 rd
= (extract32(ctx
->opcode
, 24, 1)) == 0 ? 4 : 5;
22014 rt
= decode_gpr_gpr4_zero(extract32(ctx
->opcode
, 25, 1) << 3 |
22015 extract32(ctx
->opcode
, 21, 3));
22016 gen_load_gpr(t0
, rt
);
22017 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
22018 gen_compute_branch_nm(ctx
, OPC_BGEZAL
, 4, 0, 0, s
);
22024 int32_t s
= sextract32(ctx
->opcode
, 0, 1) << 25 |
22025 extract32(ctx
->opcode
, 1, 24) << 1;
22027 if ((extract32(ctx
->opcode
, 25, 1)) == 0) {
22029 gen_compute_branch_nm(ctx
, OPC_BEQ
, 4, 0, 0, s
);
22032 gen_compute_branch_nm(ctx
, OPC_BGEZAL
, 4, 0, 0, s
);
22037 switch (extract32(ctx
->opcode
, 12, 4)) {
22040 gen_compute_branch_nm(ctx
, OPC_JALR
, 4, rs
, rt
, 0);
22043 gen_compute_nanomips_pbalrsc_branch(ctx
, rs
, rt
);
22046 generate_exception_end(ctx
, EXCP_RI
);
22052 int32_t s
= sextract32(ctx
->opcode
, 0, 1) << 14 |
22053 extract32(ctx
->opcode
, 1, 13) << 1;
22054 switch (extract32(ctx
->opcode
, 14, 2)) {
22057 gen_compute_branch_nm(ctx
, OPC_BEQ
, 4, rs
, rt
, s
);
22060 s
= sextract32(ctx
->opcode
, 0, 1) << 14 |
22061 extract32(ctx
->opcode
, 1, 13) << 1;
22062 check_cp1_enabled(ctx
);
22063 switch (extract32(ctx
->opcode
, 16, 5)) {
22065 gen_compute_branch_cp1_nm(ctx
, OPC_BC1EQZ
, rt
, s
);
22068 gen_compute_branch_cp1_nm(ctx
, OPC_BC1NEZ
, rt
, s
);
22073 int32_t imm
= extract32(ctx
->opcode
, 1, 13) |
22074 extract32(ctx
->opcode
, 0, 1) << 13;
22076 gen_compute_branch_nm(ctx
, OPC_BPOSGE32
, 4, -1, -2,
22081 generate_exception_end(ctx
, EXCP_RI
);
22087 gen_compute_compact_branch_nm(ctx
, OPC_BC
, rs
, rt
, s
);
22089 gen_compute_compact_branch_nm(ctx
, OPC_BGEC
, rs
, rt
, s
);
22093 if (rs
== rt
|| rt
== 0) {
22094 gen_compute_compact_branch_nm(ctx
, OPC_BC
, 0, 0, s
);
22095 } else if (rs
== 0) {
22096 gen_compute_compact_branch_nm(ctx
, OPC_BEQZC
, rt
, 0, s
);
22098 gen_compute_compact_branch_nm(ctx
, OPC_BGEUC
, rs
, rt
, s
);
22106 int32_t s
= sextract32(ctx
->opcode
, 0, 1) << 14 |
22107 extract32(ctx
->opcode
, 1, 13) << 1;
22108 switch (extract32(ctx
->opcode
, 14, 2)) {
22111 gen_compute_branch_nm(ctx
, OPC_BNE
, 4, rs
, rt
, s
);
22114 if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
22116 ctx
->hflags
|= MIPS_HFLAG_FBNSLOT
;
22118 gen_compute_compact_branch_nm(ctx
, OPC_BLTC
, rs
, rt
, s
);
22122 if (rs
== 0 || rs
== rt
) {
22124 ctx
->hflags
|= MIPS_HFLAG_FBNSLOT
;
22126 gen_compute_compact_branch_nm(ctx
, OPC_BLTUC
, rs
, rt
, s
);
22130 generate_exception_end(ctx
, EXCP_RI
);
22137 int32_t s
= sextract32(ctx
->opcode
, 0, 1) << 11 |
22138 extract32(ctx
->opcode
, 1, 10) << 1;
22139 uint32_t u
= extract32(ctx
->opcode
, 11, 7);
22141 gen_compute_imm_branch(ctx
, extract32(ctx
->opcode
, 18, 3),
22146 generate_exception_end(ctx
, EXCP_RI
);
22152 static int decode_nanomips_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
22155 int rt
= decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx
->opcode
));
22156 int rs
= decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx
->opcode
));
22157 int rd
= decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx
->opcode
));
22161 /* make sure instructions are on a halfword boundary */
22162 if (ctx
->base
.pc_next
& 0x1) {
22163 TCGv tmp
= tcg_const_tl(ctx
->base
.pc_next
);
22164 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPUMIPSState
, CP0_BadVAddr
));
22165 tcg_temp_free(tmp
);
22166 generate_exception_end(ctx
, EXCP_AdEL
);
22170 op
= extract32(ctx
->opcode
, 10, 6);
22173 rt
= NANOMIPS_EXTRACT_RD5(ctx
->opcode
);
22176 rs
= NANOMIPS_EXTRACT_RS5(ctx
->opcode
);
22177 gen_arith(ctx
, OPC_ADDU
, rt
, rs
, 0);
22180 switch (extract32(ctx
->opcode
, 3, 2)) {
22181 case NM_P16_SYSCALL
:
22182 if (extract32(ctx
->opcode
, 2, 1) == 0) {
22183 generate_exception_end(ctx
, EXCP_SYSCALL
);
22185 generate_exception_end(ctx
, EXCP_RI
);
22189 generate_exception_end(ctx
, EXCP_BREAK
);
22192 if (is_uhi(extract32(ctx
->opcode
, 0, 3))) {
22193 gen_helper_do_semihosting(cpu_env
);
22195 if (ctx
->hflags
& MIPS_HFLAG_SBRI
) {
22196 generate_exception_end(ctx
, EXCP_RI
);
22198 generate_exception_end(ctx
, EXCP_DBp
);
22203 generate_exception_end(ctx
, EXCP_RI
);
22210 int shift
= extract32(ctx
->opcode
, 0, 3);
22212 shift
= (shift
== 0) ? 8 : shift
;
22214 switch (extract32(ctx
->opcode
, 3, 1)) {
22222 gen_shift_imm(ctx
, opc
, rt
, rs
, shift
);
22226 switch (ctx
->opcode
& 1) {
22228 gen_pool16c_nanomips_insn(ctx
);
22231 gen_ldxs(ctx
, rt
, rs
, rd
);
22236 switch (extract32(ctx
->opcode
, 6, 1)) {
22238 imm
= extract32(ctx
->opcode
, 0, 6) << 2;
22239 gen_arith_imm(ctx
, OPC_ADDIU
, rt
, 29, imm
);
22242 generate_exception_end(ctx
, EXCP_RI
);
22247 switch (extract32(ctx
->opcode
, 3, 1)) {
22249 imm
= extract32(ctx
->opcode
, 0, 3) << 2;
22250 gen_arith_imm(ctx
, OPC_ADDIU
, rt
, rs
, imm
);
22252 case NM_P_ADDIURS5
:
22253 rt
= extract32(ctx
->opcode
, 5, 5);
22255 /* imm = sign_extend(s[3] . s[2:0] , from_nbits = 4) */
22256 imm
= (sextract32(ctx
->opcode
, 4, 1) << 3) |
22257 (extract32(ctx
->opcode
, 0, 3));
22258 gen_arith_imm(ctx
, OPC_ADDIU
, rt
, rt
, imm
);
22264 switch (ctx
->opcode
& 0x1) {
22266 gen_arith(ctx
, OPC_ADDU
, rd
, rs
, rt
);
22269 gen_arith(ctx
, OPC_SUBU
, rd
, rs
, rt
);
22274 rt
= (extract32(ctx
->opcode
, 9, 1) << 3) |
22275 extract32(ctx
->opcode
, 5, 3);
22276 rs
= (extract32(ctx
->opcode
, 4, 1) << 3) |
22277 extract32(ctx
->opcode
, 0, 3);
22278 rt
= decode_gpr_gpr4(rt
);
22279 rs
= decode_gpr_gpr4(rs
);
22280 switch ((extract32(ctx
->opcode
, 7, 2) & 0x2) |
22281 (extract32(ctx
->opcode
, 3, 1))) {
22284 gen_arith(ctx
, OPC_ADDU
, rt
, rs
, rt
);
22288 gen_r6_muldiv(ctx
, R6_OPC_MUL
, rt
, rs
, rt
);
22291 generate_exception_end(ctx
, EXCP_RI
);
22297 int imm
= extract32(ctx
->opcode
, 0, 7);
22298 imm
= (imm
== 0x7f ? -1 : imm
);
22300 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
);
22306 uint32_t u
= extract32(ctx
->opcode
, 0, 4);
22307 u
= (u
== 12) ? 0xff :
22308 (u
== 13) ? 0xffff : u
;
22309 gen_logic_imm(ctx
, OPC_ANDI
, rt
, rs
, u
);
22313 offset
= extract32(ctx
->opcode
, 0, 2);
22314 switch (extract32(ctx
->opcode
, 2, 2)) {
22316 gen_ld(ctx
, OPC_LB
, rt
, rs
, offset
);
22319 rt
= decode_gpr_gpr3_src_store(
22320 NANOMIPS_EXTRACT_RT3(ctx
->opcode
));
22321 gen_st(ctx
, OPC_SB
, rt
, rs
, offset
);
22324 gen_ld(ctx
, OPC_LBU
, rt
, rs
, offset
);
22327 generate_exception_end(ctx
, EXCP_RI
);
22332 offset
= extract32(ctx
->opcode
, 1, 2) << 1;
22333 switch ((extract32(ctx
->opcode
, 3, 1) << 1) | (ctx
->opcode
& 1)) {
22335 gen_ld(ctx
, OPC_LH
, rt
, rs
, offset
);
22338 rt
= decode_gpr_gpr3_src_store(
22339 NANOMIPS_EXTRACT_RT3(ctx
->opcode
));
22340 gen_st(ctx
, OPC_SH
, rt
, rs
, offset
);
22343 gen_ld(ctx
, OPC_LHU
, rt
, rs
, offset
);
22346 generate_exception_end(ctx
, EXCP_RI
);
22351 offset
= extract32(ctx
->opcode
, 0, 4) << 2;
22352 gen_ld(ctx
, OPC_LW
, rt
, rs
, offset
);
22355 rt
= NANOMIPS_EXTRACT_RD5(ctx
->opcode
);
22356 offset
= extract32(ctx
->opcode
, 0, 5) << 2;
22357 gen_ld(ctx
, OPC_LW
, rt
, 29, offset
);
22361 rt
= (extract32(ctx
->opcode
, 9, 1) << 3) |
22362 extract32(ctx
->opcode
, 5, 3);
22363 rs
= (extract32(ctx
->opcode
, 4, 1) << 3) |
22364 extract32(ctx
->opcode
, 0, 3);
22365 offset
= (extract32(ctx
->opcode
, 3, 1) << 3) |
22366 (extract32(ctx
->opcode
, 8, 1) << 2);
22367 rt
= decode_gpr_gpr4(rt
);
22368 rs
= decode_gpr_gpr4(rs
);
22369 gen_ld(ctx
, OPC_LW
, rt
, rs
, offset
);
22373 rt
= (extract32(ctx
->opcode
, 9, 1) << 3) |
22374 extract32(ctx
->opcode
, 5, 3);
22375 rs
= (extract32(ctx
->opcode
, 4, 1) << 3) |
22376 extract32(ctx
->opcode
, 0, 3);
22377 offset
= (extract32(ctx
->opcode
, 3, 1) << 3) |
22378 (extract32(ctx
->opcode
, 8, 1) << 2);
22379 rt
= decode_gpr_gpr4_zero(rt
);
22380 rs
= decode_gpr_gpr4(rs
);
22381 gen_st(ctx
, OPC_SW
, rt
, rs
, offset
);
22384 offset
= extract32(ctx
->opcode
, 0, 7) << 2;
22385 gen_ld(ctx
, OPC_LW
, rt
, 28, offset
);
22388 rt
= NANOMIPS_EXTRACT_RD5(ctx
->opcode
);
22389 offset
= extract32(ctx
->opcode
, 0, 5) << 2;
22390 gen_st(ctx
, OPC_SW
, rt
, 29, offset
);
22393 rt
= decode_gpr_gpr3_src_store(
22394 NANOMIPS_EXTRACT_RT3(ctx
->opcode
));
22395 rs
= decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx
->opcode
));
22396 offset
= extract32(ctx
->opcode
, 0, 4) << 2;
22397 gen_st(ctx
, OPC_SW
, rt
, rs
, offset
);
22400 rt
= decode_gpr_gpr3_src_store(
22401 NANOMIPS_EXTRACT_RT3(ctx
->opcode
));
22402 offset
= extract32(ctx
->opcode
, 0, 7) << 2;
22403 gen_st(ctx
, OPC_SW
, rt
, 28, offset
);
22406 gen_compute_branch_nm(ctx
, OPC_BEQ
, 2, 0, 0,
22407 (sextract32(ctx
->opcode
, 0, 1) << 10) |
22408 (extract32(ctx
->opcode
, 1, 9) << 1));
22411 gen_compute_branch_nm(ctx
, OPC_BGEZAL
, 2, 0, 0,
22412 (sextract32(ctx
->opcode
, 0, 1) << 10) |
22413 (extract32(ctx
->opcode
, 1, 9) << 1));
22416 gen_compute_branch_nm(ctx
, OPC_BEQ
, 2, rt
, 0,
22417 (sextract32(ctx
->opcode
, 0, 1) << 7) |
22418 (extract32(ctx
->opcode
, 1, 6) << 1));
22421 gen_compute_branch_nm(ctx
, OPC_BNE
, 2, rt
, 0,
22422 (sextract32(ctx
->opcode
, 0, 1) << 7) |
22423 (extract32(ctx
->opcode
, 1, 6) << 1));
22426 switch (ctx
->opcode
& 0xf) {
22429 switch (extract32(ctx
->opcode
, 4, 1)) {
22431 gen_compute_branch_nm(ctx
, OPC_JR
, 2,
22432 extract32(ctx
->opcode
, 5, 5), 0, 0);
22435 gen_compute_branch_nm(ctx
, OPC_JALR
, 2,
22436 extract32(ctx
->opcode
, 5, 5), 31, 0);
22443 uint32_t opc
= extract32(ctx
->opcode
, 4, 3) <
22444 extract32(ctx
->opcode
, 7, 3) ? OPC_BEQ
: OPC_BNE
;
22445 gen_compute_branch_nm(ctx
, opc
, 2, rs
, rt
,
22446 extract32(ctx
->opcode
, 0, 4) << 1);
22453 int count
= extract32(ctx
->opcode
, 0, 4);
22454 int u
= extract32(ctx
->opcode
, 4, 4) << 4;
22456 rt
= 30 + extract32(ctx
->opcode
, 9, 1);
22457 switch (extract32(ctx
->opcode
, 8, 1)) {
22459 gen_save(ctx
, rt
, count
, 0, u
);
22461 case NM_RESTORE_JRC16
:
22462 gen_restore(ctx
, rt
, count
, 0, u
);
22463 gen_compute_branch_nm(ctx
, OPC_JR
, 2, 31, 0, 0);
22472 static const int gpr2reg1
[] = {4, 5, 6, 7};
22473 static const int gpr2reg2
[] = {5, 6, 7, 8};
22475 int rd2
= extract32(ctx
->opcode
, 3, 1) << 1 |
22476 extract32(ctx
->opcode
, 8, 1);
22477 int r1
= gpr2reg1
[rd2
];
22478 int r2
= gpr2reg2
[rd2
];
22479 int r3
= extract32(ctx
->opcode
, 4, 1) << 3 |
22480 extract32(ctx
->opcode
, 0, 3);
22481 int r4
= extract32(ctx
->opcode
, 9, 1) << 3 |
22482 extract32(ctx
->opcode
, 5, 3);
22483 TCGv t0
= tcg_temp_new();
22484 TCGv t1
= tcg_temp_new();
22485 if (op
== NM_MOVEP
) {
22488 rs
= decode_gpr_gpr4_zero(r3
);
22489 rt
= decode_gpr_gpr4_zero(r4
);
22491 rd
= decode_gpr_gpr4(r3
);
22492 re
= decode_gpr_gpr4(r4
);
22496 gen_load_gpr(t0
, rs
);
22497 gen_load_gpr(t1
, rt
);
22498 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
22499 tcg_gen_mov_tl(cpu_gpr
[re
], t1
);
22505 return decode_nanomips_32_48_opc(env
, ctx
);
22512 /* SmartMIPS extension to MIPS32 */
22514 #if defined(TARGET_MIPS64)
22516 /* MDMX extension to MIPS64 */
22520 /* MIPSDSP functions. */
22521 static void gen_mipsdsp_ld(DisasContext
*ctx
, uint32_t opc
,
22522 int rd
, int base
, int offset
)
22527 t0
= tcg_temp_new();
22530 gen_load_gpr(t0
, offset
);
22531 } else if (offset
== 0) {
22532 gen_load_gpr(t0
, base
);
22534 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], cpu_gpr
[offset
]);
22539 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_UB
);
22540 gen_store_gpr(t0
, rd
);
22543 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESW
);
22544 gen_store_gpr(t0
, rd
);
22547 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESL
);
22548 gen_store_gpr(t0
, rd
);
22550 #if defined(TARGET_MIPS64)
22552 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEQ
);
22553 gen_store_gpr(t0
, rd
);
22560 static void gen_mipsdsp_arith(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
22561 int ret
, int v1
, int v2
)
22567 /* Treat as NOP. */
22571 v1_t
= tcg_temp_new();
22572 v2_t
= tcg_temp_new();
22574 gen_load_gpr(v1_t
, v1
);
22575 gen_load_gpr(v2_t
, v2
);
22578 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
22579 case OPC_MULT_G_2E
:
22583 gen_helper_adduh_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
22585 case OPC_ADDUH_R_QB
:
22586 gen_helper_adduh_r_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
22589 gen_helper_addqh_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
22591 case OPC_ADDQH_R_PH
:
22592 gen_helper_addqh_r_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
22595 gen_helper_addqh_w(cpu_gpr
[ret
], v1_t
, v2_t
);
22597 case OPC_ADDQH_R_W
:
22598 gen_helper_addqh_r_w(cpu_gpr
[ret
], v1_t
, v2_t
);
22601 gen_helper_subuh_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
22603 case OPC_SUBUH_R_QB
:
22604 gen_helper_subuh_r_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
22607 gen_helper_subqh_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
22609 case OPC_SUBQH_R_PH
:
22610 gen_helper_subqh_r_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
22613 gen_helper_subqh_w(cpu_gpr
[ret
], v1_t
, v2_t
);
22615 case OPC_SUBQH_R_W
:
22616 gen_helper_subqh_r_w(cpu_gpr
[ret
], v1_t
, v2_t
);
22620 case OPC_ABSQ_S_PH_DSP
:
22622 case OPC_ABSQ_S_QB
:
22624 gen_helper_absq_s_qb(cpu_gpr
[ret
], v2_t
, cpu_env
);
22626 case OPC_ABSQ_S_PH
:
22628 gen_helper_absq_s_ph(cpu_gpr
[ret
], v2_t
, cpu_env
);
22632 gen_helper_absq_s_w(cpu_gpr
[ret
], v2_t
, cpu_env
);
22634 case OPC_PRECEQ_W_PHL
:
22636 tcg_gen_andi_tl(cpu_gpr
[ret
], v2_t
, 0xFFFF0000);
22637 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
22639 case OPC_PRECEQ_W_PHR
:
22641 tcg_gen_andi_tl(cpu_gpr
[ret
], v2_t
, 0x0000FFFF);
22642 tcg_gen_shli_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], 16);
22643 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
22645 case OPC_PRECEQU_PH_QBL
:
22647 gen_helper_precequ_ph_qbl(cpu_gpr
[ret
], v2_t
);
22649 case OPC_PRECEQU_PH_QBR
:
22651 gen_helper_precequ_ph_qbr(cpu_gpr
[ret
], v2_t
);
22653 case OPC_PRECEQU_PH_QBLA
:
22655 gen_helper_precequ_ph_qbla(cpu_gpr
[ret
], v2_t
);
22657 case OPC_PRECEQU_PH_QBRA
:
22659 gen_helper_precequ_ph_qbra(cpu_gpr
[ret
], v2_t
);
22661 case OPC_PRECEU_PH_QBL
:
22663 gen_helper_preceu_ph_qbl(cpu_gpr
[ret
], v2_t
);
22665 case OPC_PRECEU_PH_QBR
:
22667 gen_helper_preceu_ph_qbr(cpu_gpr
[ret
], v2_t
);
22669 case OPC_PRECEU_PH_QBLA
:
22671 gen_helper_preceu_ph_qbla(cpu_gpr
[ret
], v2_t
);
22673 case OPC_PRECEU_PH_QBRA
:
22675 gen_helper_preceu_ph_qbra(cpu_gpr
[ret
], v2_t
);
22679 case OPC_ADDU_QB_DSP
:
22683 gen_helper_addq_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22685 case OPC_ADDQ_S_PH
:
22687 gen_helper_addq_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22691 gen_helper_addq_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22695 gen_helper_addu_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22697 case OPC_ADDU_S_QB
:
22699 gen_helper_addu_s_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22703 gen_helper_addu_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22705 case OPC_ADDU_S_PH
:
22707 gen_helper_addu_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22711 gen_helper_subq_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22713 case OPC_SUBQ_S_PH
:
22715 gen_helper_subq_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22719 gen_helper_subq_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22723 gen_helper_subu_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22725 case OPC_SUBU_S_QB
:
22727 gen_helper_subu_s_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22731 gen_helper_subu_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22733 case OPC_SUBU_S_PH
:
22735 gen_helper_subu_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22739 gen_helper_addsc(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22743 gen_helper_addwc(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22747 gen_helper_modsub(cpu_gpr
[ret
], v1_t
, v2_t
);
22749 case OPC_RADDU_W_QB
:
22751 gen_helper_raddu_w_qb(cpu_gpr
[ret
], v1_t
);
22755 case OPC_CMPU_EQ_QB_DSP
:
22757 case OPC_PRECR_QB_PH
:
22759 gen_helper_precr_qb_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
22761 case OPC_PRECRQ_QB_PH
:
22763 gen_helper_precrq_qb_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
22765 case OPC_PRECR_SRA_PH_W
:
22768 TCGv_i32 sa_t
= tcg_const_i32(v2
);
22769 gen_helper_precr_sra_ph_w(cpu_gpr
[ret
], sa_t
, v1_t
,
22771 tcg_temp_free_i32(sa_t
);
22774 case OPC_PRECR_SRA_R_PH_W
:
22777 TCGv_i32 sa_t
= tcg_const_i32(v2
);
22778 gen_helper_precr_sra_r_ph_w(cpu_gpr
[ret
], sa_t
, v1_t
,
22780 tcg_temp_free_i32(sa_t
);
22783 case OPC_PRECRQ_PH_W
:
22785 gen_helper_precrq_ph_w(cpu_gpr
[ret
], v1_t
, v2_t
);
22787 case OPC_PRECRQ_RS_PH_W
:
22789 gen_helper_precrq_rs_ph_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22791 case OPC_PRECRQU_S_QB_PH
:
22793 gen_helper_precrqu_s_qb_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22797 #ifdef TARGET_MIPS64
22798 case OPC_ABSQ_S_QH_DSP
:
22800 case OPC_PRECEQ_L_PWL
:
22802 tcg_gen_andi_tl(cpu_gpr
[ret
], v2_t
, 0xFFFFFFFF00000000ull
);
22804 case OPC_PRECEQ_L_PWR
:
22806 tcg_gen_shli_tl(cpu_gpr
[ret
], v2_t
, 32);
22808 case OPC_PRECEQ_PW_QHL
:
22810 gen_helper_preceq_pw_qhl(cpu_gpr
[ret
], v2_t
);
22812 case OPC_PRECEQ_PW_QHR
:
22814 gen_helper_preceq_pw_qhr(cpu_gpr
[ret
], v2_t
);
22816 case OPC_PRECEQ_PW_QHLA
:
22818 gen_helper_preceq_pw_qhla(cpu_gpr
[ret
], v2_t
);
22820 case OPC_PRECEQ_PW_QHRA
:
22822 gen_helper_preceq_pw_qhra(cpu_gpr
[ret
], v2_t
);
22824 case OPC_PRECEQU_QH_OBL
:
22826 gen_helper_precequ_qh_obl(cpu_gpr
[ret
], v2_t
);
22828 case OPC_PRECEQU_QH_OBR
:
22830 gen_helper_precequ_qh_obr(cpu_gpr
[ret
], v2_t
);
22832 case OPC_PRECEQU_QH_OBLA
:
22834 gen_helper_precequ_qh_obla(cpu_gpr
[ret
], v2_t
);
22836 case OPC_PRECEQU_QH_OBRA
:
22838 gen_helper_precequ_qh_obra(cpu_gpr
[ret
], v2_t
);
22840 case OPC_PRECEU_QH_OBL
:
22842 gen_helper_preceu_qh_obl(cpu_gpr
[ret
], v2_t
);
22844 case OPC_PRECEU_QH_OBR
:
22846 gen_helper_preceu_qh_obr(cpu_gpr
[ret
], v2_t
);
22848 case OPC_PRECEU_QH_OBLA
:
22850 gen_helper_preceu_qh_obla(cpu_gpr
[ret
], v2_t
);
22852 case OPC_PRECEU_QH_OBRA
:
22854 gen_helper_preceu_qh_obra(cpu_gpr
[ret
], v2_t
);
22856 case OPC_ABSQ_S_OB
:
22858 gen_helper_absq_s_ob(cpu_gpr
[ret
], v2_t
, cpu_env
);
22860 case OPC_ABSQ_S_PW
:
22862 gen_helper_absq_s_pw(cpu_gpr
[ret
], v2_t
, cpu_env
);
22864 case OPC_ABSQ_S_QH
:
22866 gen_helper_absq_s_qh(cpu_gpr
[ret
], v2_t
, cpu_env
);
22870 case OPC_ADDU_OB_DSP
:
22872 case OPC_RADDU_L_OB
:
22874 gen_helper_raddu_l_ob(cpu_gpr
[ret
], v1_t
);
22878 gen_helper_subq_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22880 case OPC_SUBQ_S_PW
:
22882 gen_helper_subq_s_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22886 gen_helper_subq_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22888 case OPC_SUBQ_S_QH
:
22890 gen_helper_subq_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22894 gen_helper_subu_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22896 case OPC_SUBU_S_OB
:
22898 gen_helper_subu_s_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22902 gen_helper_subu_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22904 case OPC_SUBU_S_QH
:
22906 gen_helper_subu_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22910 gen_helper_subuh_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
22912 case OPC_SUBUH_R_OB
:
22914 gen_helper_subuh_r_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
22918 gen_helper_addq_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22920 case OPC_ADDQ_S_PW
:
22922 gen_helper_addq_s_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22926 gen_helper_addq_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22928 case OPC_ADDQ_S_QH
:
22930 gen_helper_addq_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22934 gen_helper_addu_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22936 case OPC_ADDU_S_OB
:
22938 gen_helper_addu_s_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22942 gen_helper_addu_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22944 case OPC_ADDU_S_QH
:
22946 gen_helper_addu_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22950 gen_helper_adduh_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
22952 case OPC_ADDUH_R_OB
:
22954 gen_helper_adduh_r_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
22958 case OPC_CMPU_EQ_OB_DSP
:
22960 case OPC_PRECR_OB_QH
:
22962 gen_helper_precr_ob_qh(cpu_gpr
[ret
], v1_t
, v2_t
);
22964 case OPC_PRECR_SRA_QH_PW
:
22967 TCGv_i32 ret_t
= tcg_const_i32(ret
);
22968 gen_helper_precr_sra_qh_pw(v2_t
, v1_t
, v2_t
, ret_t
);
22969 tcg_temp_free_i32(ret_t
);
22972 case OPC_PRECR_SRA_R_QH_PW
:
22975 TCGv_i32 sa_v
= tcg_const_i32(ret
);
22976 gen_helper_precr_sra_r_qh_pw(v2_t
, v1_t
, v2_t
, sa_v
);
22977 tcg_temp_free_i32(sa_v
);
22980 case OPC_PRECRQ_OB_QH
:
22982 gen_helper_precrq_ob_qh(cpu_gpr
[ret
], v1_t
, v2_t
);
22984 case OPC_PRECRQ_PW_L
:
22986 gen_helper_precrq_pw_l(cpu_gpr
[ret
], v1_t
, v2_t
);
22988 case OPC_PRECRQ_QH_PW
:
22990 gen_helper_precrq_qh_pw(cpu_gpr
[ret
], v1_t
, v2_t
);
22992 case OPC_PRECRQ_RS_QH_PW
:
22994 gen_helper_precrq_rs_qh_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
22996 case OPC_PRECRQU_S_OB_QH
:
22998 gen_helper_precrqu_s_ob_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23005 tcg_temp_free(v1_t
);
23006 tcg_temp_free(v2_t
);
23009 static void gen_mipsdsp_shift(DisasContext
*ctx
, uint32_t opc
,
23010 int ret
, int v1
, int v2
)
23018 /* Treat as NOP. */
23022 t0
= tcg_temp_new();
23023 v1_t
= tcg_temp_new();
23024 v2_t
= tcg_temp_new();
23026 tcg_gen_movi_tl(t0
, v1
);
23027 gen_load_gpr(v1_t
, v1
);
23028 gen_load_gpr(v2_t
, v2
);
23031 case OPC_SHLL_QB_DSP
:
23033 op2
= MASK_SHLL_QB(ctx
->opcode
);
23037 gen_helper_shll_qb(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
23041 gen_helper_shll_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23045 gen_helper_shll_ph(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
23049 gen_helper_shll_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23051 case OPC_SHLL_S_PH
:
23053 gen_helper_shll_s_ph(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
23055 case OPC_SHLLV_S_PH
:
23057 gen_helper_shll_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23061 gen_helper_shll_s_w(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
23063 case OPC_SHLLV_S_W
:
23065 gen_helper_shll_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23069 gen_helper_shrl_qb(cpu_gpr
[ret
], t0
, v2_t
);
23073 gen_helper_shrl_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
23077 gen_helper_shrl_ph(cpu_gpr
[ret
], t0
, v2_t
);
23081 gen_helper_shrl_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
23085 gen_helper_shra_qb(cpu_gpr
[ret
], t0
, v2_t
);
23087 case OPC_SHRA_R_QB
:
23089 gen_helper_shra_r_qb(cpu_gpr
[ret
], t0
, v2_t
);
23093 gen_helper_shra_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
23095 case OPC_SHRAV_R_QB
:
23097 gen_helper_shra_r_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
23101 gen_helper_shra_ph(cpu_gpr
[ret
], t0
, v2_t
);
23103 case OPC_SHRA_R_PH
:
23105 gen_helper_shra_r_ph(cpu_gpr
[ret
], t0
, v2_t
);
23109 gen_helper_shra_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
23111 case OPC_SHRAV_R_PH
:
23113 gen_helper_shra_r_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
23117 gen_helper_shra_r_w(cpu_gpr
[ret
], t0
, v2_t
);
23119 case OPC_SHRAV_R_W
:
23121 gen_helper_shra_r_w(cpu_gpr
[ret
], v1_t
, v2_t
);
23123 default: /* Invalid */
23124 MIPS_INVAL("MASK SHLL.QB");
23125 generate_exception_end(ctx
, EXCP_RI
);
23130 #ifdef TARGET_MIPS64
23131 case OPC_SHLL_OB_DSP
:
23132 op2
= MASK_SHLL_OB(ctx
->opcode
);
23136 gen_helper_shll_pw(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
23140 gen_helper_shll_pw(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
23142 case OPC_SHLL_S_PW
:
23144 gen_helper_shll_s_pw(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
23146 case OPC_SHLLV_S_PW
:
23148 gen_helper_shll_s_pw(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
23152 gen_helper_shll_ob(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
23156 gen_helper_shll_ob(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
23160 gen_helper_shll_qh(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
23164 gen_helper_shll_qh(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
23166 case OPC_SHLL_S_QH
:
23168 gen_helper_shll_s_qh(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
23170 case OPC_SHLLV_S_QH
:
23172 gen_helper_shll_s_qh(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
23176 gen_helper_shra_ob(cpu_gpr
[ret
], v2_t
, t0
);
23180 gen_helper_shra_ob(cpu_gpr
[ret
], v2_t
, v1_t
);
23182 case OPC_SHRA_R_OB
:
23184 gen_helper_shra_r_ob(cpu_gpr
[ret
], v2_t
, t0
);
23186 case OPC_SHRAV_R_OB
:
23188 gen_helper_shra_r_ob(cpu_gpr
[ret
], v2_t
, v1_t
);
23192 gen_helper_shra_pw(cpu_gpr
[ret
], v2_t
, t0
);
23196 gen_helper_shra_pw(cpu_gpr
[ret
], v2_t
, v1_t
);
23198 case OPC_SHRA_R_PW
:
23200 gen_helper_shra_r_pw(cpu_gpr
[ret
], v2_t
, t0
);
23202 case OPC_SHRAV_R_PW
:
23204 gen_helper_shra_r_pw(cpu_gpr
[ret
], v2_t
, v1_t
);
23208 gen_helper_shra_qh(cpu_gpr
[ret
], v2_t
, t0
);
23212 gen_helper_shra_qh(cpu_gpr
[ret
], v2_t
, v1_t
);
23214 case OPC_SHRA_R_QH
:
23216 gen_helper_shra_r_qh(cpu_gpr
[ret
], v2_t
, t0
);
23218 case OPC_SHRAV_R_QH
:
23220 gen_helper_shra_r_qh(cpu_gpr
[ret
], v2_t
, v1_t
);
23224 gen_helper_shrl_ob(cpu_gpr
[ret
], v2_t
, t0
);
23228 gen_helper_shrl_ob(cpu_gpr
[ret
], v2_t
, v1_t
);
23232 gen_helper_shrl_qh(cpu_gpr
[ret
], v2_t
, t0
);
23236 gen_helper_shrl_qh(cpu_gpr
[ret
], v2_t
, v1_t
);
23238 default: /* Invalid */
23239 MIPS_INVAL("MASK SHLL.OB");
23240 generate_exception_end(ctx
, EXCP_RI
);
23248 tcg_temp_free(v1_t
);
23249 tcg_temp_free(v2_t
);
23252 static void gen_mipsdsp_multiply(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
23253 int ret
, int v1
, int v2
, int check_ret
)
23259 if ((ret
== 0) && (check_ret
== 1)) {
23260 /* Treat as NOP. */
23264 t0
= tcg_temp_new_i32();
23265 v1_t
= tcg_temp_new();
23266 v2_t
= tcg_temp_new();
23268 tcg_gen_movi_i32(t0
, ret
);
23269 gen_load_gpr(v1_t
, v1
);
23270 gen_load_gpr(v2_t
, v2
);
23274 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
23275 * the same mask and op1.
23277 case OPC_MULT_G_2E
:
23281 gen_helper_mul_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23284 gen_helper_mul_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23287 gen_helper_mulq_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23289 case OPC_MULQ_RS_W
:
23290 gen_helper_mulq_rs_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23294 case OPC_DPA_W_PH_DSP
:
23296 case OPC_DPAU_H_QBL
:
23298 gen_helper_dpau_h_qbl(t0
, v1_t
, v2_t
, cpu_env
);
23300 case OPC_DPAU_H_QBR
:
23302 gen_helper_dpau_h_qbr(t0
, v1_t
, v2_t
, cpu_env
);
23304 case OPC_DPSU_H_QBL
:
23306 gen_helper_dpsu_h_qbl(t0
, v1_t
, v2_t
, cpu_env
);
23308 case OPC_DPSU_H_QBR
:
23310 gen_helper_dpsu_h_qbr(t0
, v1_t
, v2_t
, cpu_env
);
23314 gen_helper_dpa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23316 case OPC_DPAX_W_PH
:
23318 gen_helper_dpax_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23320 case OPC_DPAQ_S_W_PH
:
23322 gen_helper_dpaq_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23324 case OPC_DPAQX_S_W_PH
:
23326 gen_helper_dpaqx_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23328 case OPC_DPAQX_SA_W_PH
:
23330 gen_helper_dpaqx_sa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23334 gen_helper_dps_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23336 case OPC_DPSX_W_PH
:
23338 gen_helper_dpsx_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23340 case OPC_DPSQ_S_W_PH
:
23342 gen_helper_dpsq_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23344 case OPC_DPSQX_S_W_PH
:
23346 gen_helper_dpsqx_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23348 case OPC_DPSQX_SA_W_PH
:
23350 gen_helper_dpsqx_sa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23352 case OPC_MULSAQ_S_W_PH
:
23354 gen_helper_mulsaq_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23356 case OPC_DPAQ_SA_L_W
:
23358 gen_helper_dpaq_sa_l_w(t0
, v1_t
, v2_t
, cpu_env
);
23360 case OPC_DPSQ_SA_L_W
:
23362 gen_helper_dpsq_sa_l_w(t0
, v1_t
, v2_t
, cpu_env
);
23364 case OPC_MAQ_S_W_PHL
:
23366 gen_helper_maq_s_w_phl(t0
, v1_t
, v2_t
, cpu_env
);
23368 case OPC_MAQ_S_W_PHR
:
23370 gen_helper_maq_s_w_phr(t0
, v1_t
, v2_t
, cpu_env
);
23372 case OPC_MAQ_SA_W_PHL
:
23374 gen_helper_maq_sa_w_phl(t0
, v1_t
, v2_t
, cpu_env
);
23376 case OPC_MAQ_SA_W_PHR
:
23378 gen_helper_maq_sa_w_phr(t0
, v1_t
, v2_t
, cpu_env
);
23380 case OPC_MULSA_W_PH
:
23382 gen_helper_mulsa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
23386 #ifdef TARGET_MIPS64
23387 case OPC_DPAQ_W_QH_DSP
:
23389 int ac
= ret
& 0x03;
23390 tcg_gen_movi_i32(t0
, ac
);
23395 gen_helper_dmadd(v1_t
, v2_t
, t0
, cpu_env
);
23399 gen_helper_dmaddu(v1_t
, v2_t
, t0
, cpu_env
);
23403 gen_helper_dmsub(v1_t
, v2_t
, t0
, cpu_env
);
23407 gen_helper_dmsubu(v1_t
, v2_t
, t0
, cpu_env
);
23411 gen_helper_dpa_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
23413 case OPC_DPAQ_S_W_QH
:
23415 gen_helper_dpaq_s_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
23417 case OPC_DPAQ_SA_L_PW
:
23419 gen_helper_dpaq_sa_l_pw(v1_t
, v2_t
, t0
, cpu_env
);
23421 case OPC_DPAU_H_OBL
:
23423 gen_helper_dpau_h_obl(v1_t
, v2_t
, t0
, cpu_env
);
23425 case OPC_DPAU_H_OBR
:
23427 gen_helper_dpau_h_obr(v1_t
, v2_t
, t0
, cpu_env
);
23431 gen_helper_dps_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
23433 case OPC_DPSQ_S_W_QH
:
23435 gen_helper_dpsq_s_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
23437 case OPC_DPSQ_SA_L_PW
:
23439 gen_helper_dpsq_sa_l_pw(v1_t
, v2_t
, t0
, cpu_env
);
23441 case OPC_DPSU_H_OBL
:
23443 gen_helper_dpsu_h_obl(v1_t
, v2_t
, t0
, cpu_env
);
23445 case OPC_DPSU_H_OBR
:
23447 gen_helper_dpsu_h_obr(v1_t
, v2_t
, t0
, cpu_env
);
23449 case OPC_MAQ_S_L_PWL
:
23451 gen_helper_maq_s_l_pwl(v1_t
, v2_t
, t0
, cpu_env
);
23453 case OPC_MAQ_S_L_PWR
:
23455 gen_helper_maq_s_l_pwr(v1_t
, v2_t
, t0
, cpu_env
);
23457 case OPC_MAQ_S_W_QHLL
:
23459 gen_helper_maq_s_w_qhll(v1_t
, v2_t
, t0
, cpu_env
);
23461 case OPC_MAQ_SA_W_QHLL
:
23463 gen_helper_maq_sa_w_qhll(v1_t
, v2_t
, t0
, cpu_env
);
23465 case OPC_MAQ_S_W_QHLR
:
23467 gen_helper_maq_s_w_qhlr(v1_t
, v2_t
, t0
, cpu_env
);
23469 case OPC_MAQ_SA_W_QHLR
:
23471 gen_helper_maq_sa_w_qhlr(v1_t
, v2_t
, t0
, cpu_env
);
23473 case OPC_MAQ_S_W_QHRL
:
23475 gen_helper_maq_s_w_qhrl(v1_t
, v2_t
, t0
, cpu_env
);
23477 case OPC_MAQ_SA_W_QHRL
:
23479 gen_helper_maq_sa_w_qhrl(v1_t
, v2_t
, t0
, cpu_env
);
23481 case OPC_MAQ_S_W_QHRR
:
23483 gen_helper_maq_s_w_qhrr(v1_t
, v2_t
, t0
, cpu_env
);
23485 case OPC_MAQ_SA_W_QHRR
:
23487 gen_helper_maq_sa_w_qhrr(v1_t
, v2_t
, t0
, cpu_env
);
23489 case OPC_MULSAQ_S_L_PW
:
23491 gen_helper_mulsaq_s_l_pw(v1_t
, v2_t
, t0
, cpu_env
);
23493 case OPC_MULSAQ_S_W_QH
:
23495 gen_helper_mulsaq_s_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
23501 case OPC_ADDU_QB_DSP
:
23503 case OPC_MULEU_S_PH_QBL
:
23505 gen_helper_muleu_s_ph_qbl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23507 case OPC_MULEU_S_PH_QBR
:
23509 gen_helper_muleu_s_ph_qbr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23511 case OPC_MULQ_RS_PH
:
23513 gen_helper_mulq_rs_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23515 case OPC_MULEQ_S_W_PHL
:
23517 gen_helper_muleq_s_w_phl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23519 case OPC_MULEQ_S_W_PHR
:
23521 gen_helper_muleq_s_w_phr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23523 case OPC_MULQ_S_PH
:
23525 gen_helper_mulq_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23529 #ifdef TARGET_MIPS64
23530 case OPC_ADDU_OB_DSP
:
23532 case OPC_MULEQ_S_PW_QHL
:
23534 gen_helper_muleq_s_pw_qhl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23536 case OPC_MULEQ_S_PW_QHR
:
23538 gen_helper_muleq_s_pw_qhr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23540 case OPC_MULEU_S_QH_OBL
:
23542 gen_helper_muleu_s_qh_obl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23544 case OPC_MULEU_S_QH_OBR
:
23546 gen_helper_muleu_s_qh_obr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23548 case OPC_MULQ_RS_QH
:
23550 gen_helper_mulq_rs_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23557 tcg_temp_free_i32(t0
);
23558 tcg_temp_free(v1_t
);
23559 tcg_temp_free(v2_t
);
23562 static void gen_mipsdsp_bitinsn(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
23570 /* Treat as NOP. */
23574 t0
= tcg_temp_new();
23575 val_t
= tcg_temp_new();
23576 gen_load_gpr(val_t
, val
);
23579 case OPC_ABSQ_S_PH_DSP
:
23583 gen_helper_bitrev(cpu_gpr
[ret
], val_t
);
23588 target_long result
;
23589 imm
= (ctx
->opcode
>> 16) & 0xFF;
23590 result
= (uint32_t)imm
<< 24 |
23591 (uint32_t)imm
<< 16 |
23592 (uint32_t)imm
<< 8 |
23594 result
= (int32_t)result
;
23595 tcg_gen_movi_tl(cpu_gpr
[ret
], result
);
23600 tcg_gen_ext8u_tl(cpu_gpr
[ret
], val_t
);
23601 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 8);
23602 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23603 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
23604 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23605 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
23610 imm
= (ctx
->opcode
>> 16) & 0x03FF;
23611 imm
= (int16_t)(imm
<< 6) >> 6;
23612 tcg_gen_movi_tl(cpu_gpr
[ret
], \
23613 (target_long
)((int32_t)imm
<< 16 | \
23619 tcg_gen_ext16u_tl(cpu_gpr
[ret
], val_t
);
23620 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
23621 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23622 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
23626 #ifdef TARGET_MIPS64
23627 case OPC_ABSQ_S_QH_DSP
:
23634 imm
= (ctx
->opcode
>> 16) & 0xFF;
23635 temp
= ((uint64_t)imm
<< 8) | (uint64_t)imm
;
23636 temp
= (temp
<< 16) | temp
;
23637 temp
= (temp
<< 32) | temp
;
23638 tcg_gen_movi_tl(cpu_gpr
[ret
], temp
);
23646 imm
= (ctx
->opcode
>> 16) & 0x03FF;
23647 imm
= (int16_t)(imm
<< 6) >> 6;
23648 temp
= ((target_long
)imm
<< 32) \
23649 | ((target_long
)imm
& 0xFFFFFFFF);
23650 tcg_gen_movi_tl(cpu_gpr
[ret
], temp
);
23658 imm
= (ctx
->opcode
>> 16) & 0x03FF;
23659 imm
= (int16_t)(imm
<< 6) >> 6;
23661 temp
= ((uint64_t)(uint16_t)imm
<< 48) |
23662 ((uint64_t)(uint16_t)imm
<< 32) |
23663 ((uint64_t)(uint16_t)imm
<< 16) |
23664 (uint64_t)(uint16_t)imm
;
23665 tcg_gen_movi_tl(cpu_gpr
[ret
], temp
);
23670 tcg_gen_ext8u_tl(cpu_gpr
[ret
], val_t
);
23671 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 8);
23672 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23673 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
23674 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23675 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 32);
23676 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23680 tcg_gen_ext32u_i64(cpu_gpr
[ret
], val_t
);
23681 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 32);
23682 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23686 tcg_gen_ext16u_tl(cpu_gpr
[ret
], val_t
);
23687 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
23688 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23689 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 32);
23690 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
23697 tcg_temp_free(val_t
);
23700 static void gen_mipsdsp_add_cmp_pick(DisasContext
*ctx
,
23701 uint32_t op1
, uint32_t op2
,
23702 int ret
, int v1
, int v2
, int check_ret
)
23708 if ((ret
== 0) && (check_ret
== 1)) {
23709 /* Treat as NOP. */
23713 t1
= tcg_temp_new();
23714 v1_t
= tcg_temp_new();
23715 v2_t
= tcg_temp_new();
23717 gen_load_gpr(v1_t
, v1
);
23718 gen_load_gpr(v2_t
, v2
);
23721 case OPC_CMPU_EQ_QB_DSP
:
23723 case OPC_CMPU_EQ_QB
:
23725 gen_helper_cmpu_eq_qb(v1_t
, v2_t
, cpu_env
);
23727 case OPC_CMPU_LT_QB
:
23729 gen_helper_cmpu_lt_qb(v1_t
, v2_t
, cpu_env
);
23731 case OPC_CMPU_LE_QB
:
23733 gen_helper_cmpu_le_qb(v1_t
, v2_t
, cpu_env
);
23735 case OPC_CMPGU_EQ_QB
:
23737 gen_helper_cmpgu_eq_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
23739 case OPC_CMPGU_LT_QB
:
23741 gen_helper_cmpgu_lt_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
23743 case OPC_CMPGU_LE_QB
:
23745 gen_helper_cmpgu_le_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
23747 case OPC_CMPGDU_EQ_QB
:
23749 gen_helper_cmpgu_eq_qb(t1
, v1_t
, v2_t
);
23750 tcg_gen_mov_tl(cpu_gpr
[ret
], t1
);
23751 tcg_gen_andi_tl(cpu_dspctrl
, cpu_dspctrl
, 0xF0FFFFFF);
23752 tcg_gen_shli_tl(t1
, t1
, 24);
23753 tcg_gen_or_tl(cpu_dspctrl
, cpu_dspctrl
, t1
);
23755 case OPC_CMPGDU_LT_QB
:
23757 gen_helper_cmpgu_lt_qb(t1
, v1_t
, v2_t
);
23758 tcg_gen_mov_tl(cpu_gpr
[ret
], t1
);
23759 tcg_gen_andi_tl(cpu_dspctrl
, cpu_dspctrl
, 0xF0FFFFFF);
23760 tcg_gen_shli_tl(t1
, t1
, 24);
23761 tcg_gen_or_tl(cpu_dspctrl
, cpu_dspctrl
, t1
);
23763 case OPC_CMPGDU_LE_QB
:
23765 gen_helper_cmpgu_le_qb(t1
, v1_t
, v2_t
);
23766 tcg_gen_mov_tl(cpu_gpr
[ret
], t1
);
23767 tcg_gen_andi_tl(cpu_dspctrl
, cpu_dspctrl
, 0xF0FFFFFF);
23768 tcg_gen_shli_tl(t1
, t1
, 24);
23769 tcg_gen_or_tl(cpu_dspctrl
, cpu_dspctrl
, t1
);
23771 case OPC_CMP_EQ_PH
:
23773 gen_helper_cmp_eq_ph(v1_t
, v2_t
, cpu_env
);
23775 case OPC_CMP_LT_PH
:
23777 gen_helper_cmp_lt_ph(v1_t
, v2_t
, cpu_env
);
23779 case OPC_CMP_LE_PH
:
23781 gen_helper_cmp_le_ph(v1_t
, v2_t
, cpu_env
);
23785 gen_helper_pick_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23789 gen_helper_pick_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23791 case OPC_PACKRL_PH
:
23793 gen_helper_packrl_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
23797 #ifdef TARGET_MIPS64
23798 case OPC_CMPU_EQ_OB_DSP
:
23800 case OPC_CMP_EQ_PW
:
23802 gen_helper_cmp_eq_pw(v1_t
, v2_t
, cpu_env
);
23804 case OPC_CMP_LT_PW
:
23806 gen_helper_cmp_lt_pw(v1_t
, v2_t
, cpu_env
);
23808 case OPC_CMP_LE_PW
:
23810 gen_helper_cmp_le_pw(v1_t
, v2_t
, cpu_env
);
23812 case OPC_CMP_EQ_QH
:
23814 gen_helper_cmp_eq_qh(v1_t
, v2_t
, cpu_env
);
23816 case OPC_CMP_LT_QH
:
23818 gen_helper_cmp_lt_qh(v1_t
, v2_t
, cpu_env
);
23820 case OPC_CMP_LE_QH
:
23822 gen_helper_cmp_le_qh(v1_t
, v2_t
, cpu_env
);
23824 case OPC_CMPGDU_EQ_OB
:
23826 gen_helper_cmpgdu_eq_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23828 case OPC_CMPGDU_LT_OB
:
23830 gen_helper_cmpgdu_lt_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23832 case OPC_CMPGDU_LE_OB
:
23834 gen_helper_cmpgdu_le_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23836 case OPC_CMPGU_EQ_OB
:
23838 gen_helper_cmpgu_eq_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
23840 case OPC_CMPGU_LT_OB
:
23842 gen_helper_cmpgu_lt_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
23844 case OPC_CMPGU_LE_OB
:
23846 gen_helper_cmpgu_le_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
23848 case OPC_CMPU_EQ_OB
:
23850 gen_helper_cmpu_eq_ob(v1_t
, v2_t
, cpu_env
);
23852 case OPC_CMPU_LT_OB
:
23854 gen_helper_cmpu_lt_ob(v1_t
, v2_t
, cpu_env
);
23856 case OPC_CMPU_LE_OB
:
23858 gen_helper_cmpu_le_ob(v1_t
, v2_t
, cpu_env
);
23860 case OPC_PACKRL_PW
:
23862 gen_helper_packrl_pw(cpu_gpr
[ret
], v1_t
, v2_t
);
23866 gen_helper_pick_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23870 gen_helper_pick_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23874 gen_helper_pick_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
23882 tcg_temp_free(v1_t
);
23883 tcg_temp_free(v2_t
);
23886 static void gen_mipsdsp_append(CPUMIPSState
*env
, DisasContext
*ctx
,
23887 uint32_t op1
, int rt
, int rs
, int sa
)
23894 /* Treat as NOP. */
23898 t0
= tcg_temp_new();
23899 gen_load_gpr(t0
, rs
);
23902 case OPC_APPEND_DSP
:
23903 switch (MASK_APPEND(ctx
->opcode
)) {
23906 tcg_gen_deposit_tl(cpu_gpr
[rt
], t0
, cpu_gpr
[rt
], sa
, 32 - sa
);
23908 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
23912 tcg_gen_ext32u_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
23913 tcg_gen_shri_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], sa
);
23914 tcg_gen_shli_tl(t0
, t0
, 32 - sa
);
23915 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
23917 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
23921 if (sa
!= 0 && sa
!= 2) {
23922 tcg_gen_shli_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], 8 * sa
);
23923 tcg_gen_ext32u_tl(t0
, t0
);
23924 tcg_gen_shri_tl(t0
, t0
, 8 * (4 - sa
));
23925 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
23927 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
23929 default: /* Invalid */
23930 MIPS_INVAL("MASK APPEND");
23931 generate_exception_end(ctx
, EXCP_RI
);
23935 #ifdef TARGET_MIPS64
23936 case OPC_DAPPEND_DSP
:
23937 switch (MASK_DAPPEND(ctx
->opcode
)) {
23940 tcg_gen_deposit_tl(cpu_gpr
[rt
], t0
, cpu_gpr
[rt
], sa
, 64 - sa
);
23944 tcg_gen_shri_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], 0x20 | sa
);
23945 tcg_gen_shli_tl(t0
, t0
, 64 - (0x20 | sa
));
23946 tcg_gen_or_tl(cpu_gpr
[rt
], t0
, t0
);
23950 tcg_gen_shri_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], sa
);
23951 tcg_gen_shli_tl(t0
, t0
, 64 - sa
);
23952 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
23957 if (sa
!= 0 && sa
!= 2 && sa
!= 4) {
23958 tcg_gen_shli_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], 8 * sa
);
23959 tcg_gen_shri_tl(t0
, t0
, 8 * (8 - sa
));
23960 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
23963 default: /* Invalid */
23964 MIPS_INVAL("MASK DAPPEND");
23965 generate_exception_end(ctx
, EXCP_RI
);
23974 static void gen_mipsdsp_accinsn(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
23975 int ret
, int v1
, int v2
, int check_ret
)
23984 if ((ret
== 0) && (check_ret
== 1)) {
23985 /* Treat as NOP. */
23989 t0
= tcg_temp_new();
23990 t1
= tcg_temp_new();
23991 v1_t
= tcg_temp_new();
23992 v2_t
= tcg_temp_new();
23994 gen_load_gpr(v1_t
, v1
);
23995 gen_load_gpr(v2_t
, v2
);
23998 case OPC_EXTR_W_DSP
:
24002 tcg_gen_movi_tl(t0
, v2
);
24003 tcg_gen_movi_tl(t1
, v1
);
24004 gen_helper_extr_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24007 tcg_gen_movi_tl(t0
, v2
);
24008 tcg_gen_movi_tl(t1
, v1
);
24009 gen_helper_extr_r_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24011 case OPC_EXTR_RS_W
:
24012 tcg_gen_movi_tl(t0
, v2
);
24013 tcg_gen_movi_tl(t1
, v1
);
24014 gen_helper_extr_rs_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24017 tcg_gen_movi_tl(t0
, v2
);
24018 tcg_gen_movi_tl(t1
, v1
);
24019 gen_helper_extr_s_h(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24021 case OPC_EXTRV_S_H
:
24022 tcg_gen_movi_tl(t0
, v2
);
24023 gen_helper_extr_s_h(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24026 tcg_gen_movi_tl(t0
, v2
);
24027 gen_helper_extr_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24029 case OPC_EXTRV_R_W
:
24030 tcg_gen_movi_tl(t0
, v2
);
24031 gen_helper_extr_r_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24033 case OPC_EXTRV_RS_W
:
24034 tcg_gen_movi_tl(t0
, v2
);
24035 gen_helper_extr_rs_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24038 tcg_gen_movi_tl(t0
, v2
);
24039 tcg_gen_movi_tl(t1
, v1
);
24040 gen_helper_extp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24043 tcg_gen_movi_tl(t0
, v2
);
24044 gen_helper_extp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24047 tcg_gen_movi_tl(t0
, v2
);
24048 tcg_gen_movi_tl(t1
, v1
);
24049 gen_helper_extpdp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24052 tcg_gen_movi_tl(t0
, v2
);
24053 gen_helper_extpdp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24056 imm
= (ctx
->opcode
>> 20) & 0x3F;
24057 tcg_gen_movi_tl(t0
, ret
);
24058 tcg_gen_movi_tl(t1
, imm
);
24059 gen_helper_shilo(t0
, t1
, cpu_env
);
24062 tcg_gen_movi_tl(t0
, ret
);
24063 gen_helper_shilo(t0
, v1_t
, cpu_env
);
24066 tcg_gen_movi_tl(t0
, ret
);
24067 gen_helper_mthlip(t0
, v1_t
, cpu_env
);
24070 imm
= (ctx
->opcode
>> 11) & 0x3FF;
24071 tcg_gen_movi_tl(t0
, imm
);
24072 gen_helper_wrdsp(v1_t
, t0
, cpu_env
);
24075 imm
= (ctx
->opcode
>> 16) & 0x03FF;
24076 tcg_gen_movi_tl(t0
, imm
);
24077 gen_helper_rddsp(cpu_gpr
[ret
], t0
, cpu_env
);
24081 #ifdef TARGET_MIPS64
24082 case OPC_DEXTR_W_DSP
:
24086 tcg_gen_movi_tl(t0
, ret
);
24087 gen_helper_dmthlip(v1_t
, t0
, cpu_env
);
24091 int shift
= (ctx
->opcode
>> 19) & 0x7F;
24092 int ac
= (ctx
->opcode
>> 11) & 0x03;
24093 tcg_gen_movi_tl(t0
, shift
);
24094 tcg_gen_movi_tl(t1
, ac
);
24095 gen_helper_dshilo(t0
, t1
, cpu_env
);
24100 int ac
= (ctx
->opcode
>> 11) & 0x03;
24101 tcg_gen_movi_tl(t0
, ac
);
24102 gen_helper_dshilo(v1_t
, t0
, cpu_env
);
24106 tcg_gen_movi_tl(t0
, v2
);
24107 tcg_gen_movi_tl(t1
, v1
);
24109 gen_helper_dextp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24112 tcg_gen_movi_tl(t0
, v2
);
24113 gen_helper_dextp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24116 tcg_gen_movi_tl(t0
, v2
);
24117 tcg_gen_movi_tl(t1
, v1
);
24118 gen_helper_dextpdp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24121 tcg_gen_movi_tl(t0
, v2
);
24122 gen_helper_dextpdp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24125 tcg_gen_movi_tl(t0
, v2
);
24126 tcg_gen_movi_tl(t1
, v1
);
24127 gen_helper_dextr_l(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24129 case OPC_DEXTR_R_L
:
24130 tcg_gen_movi_tl(t0
, v2
);
24131 tcg_gen_movi_tl(t1
, v1
);
24132 gen_helper_dextr_r_l(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24134 case OPC_DEXTR_RS_L
:
24135 tcg_gen_movi_tl(t0
, v2
);
24136 tcg_gen_movi_tl(t1
, v1
);
24137 gen_helper_dextr_rs_l(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24140 tcg_gen_movi_tl(t0
, v2
);
24141 tcg_gen_movi_tl(t1
, v1
);
24142 gen_helper_dextr_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24144 case OPC_DEXTR_R_W
:
24145 tcg_gen_movi_tl(t0
, v2
);
24146 tcg_gen_movi_tl(t1
, v1
);
24147 gen_helper_dextr_r_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24149 case OPC_DEXTR_RS_W
:
24150 tcg_gen_movi_tl(t0
, v2
);
24151 tcg_gen_movi_tl(t1
, v1
);
24152 gen_helper_dextr_rs_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24154 case OPC_DEXTR_S_H
:
24155 tcg_gen_movi_tl(t0
, v2
);
24156 tcg_gen_movi_tl(t1
, v1
);
24157 gen_helper_dextr_s_h(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24159 case OPC_DEXTRV_S_H
:
24160 tcg_gen_movi_tl(t0
, v2
);
24161 tcg_gen_movi_tl(t1
, v1
);
24162 gen_helper_dextr_s_h(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
24165 tcg_gen_movi_tl(t0
, v2
);
24166 gen_helper_dextr_l(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24168 case OPC_DEXTRV_R_L
:
24169 tcg_gen_movi_tl(t0
, v2
);
24170 gen_helper_dextr_r_l(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24172 case OPC_DEXTRV_RS_L
:
24173 tcg_gen_movi_tl(t0
, v2
);
24174 gen_helper_dextr_rs_l(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24177 tcg_gen_movi_tl(t0
, v2
);
24178 gen_helper_dextr_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24180 case OPC_DEXTRV_R_W
:
24181 tcg_gen_movi_tl(t0
, v2
);
24182 gen_helper_dextr_r_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24184 case OPC_DEXTRV_RS_W
:
24185 tcg_gen_movi_tl(t0
, v2
);
24186 gen_helper_dextr_rs_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
24195 tcg_temp_free(v1_t
);
24196 tcg_temp_free(v2_t
);
24199 /* End MIPSDSP functions. */
24201 static void decode_opc_special_r6(CPUMIPSState
*env
, DisasContext
*ctx
)
24203 int rs
, rt
, rd
, sa
;
24206 rs
= (ctx
->opcode
>> 21) & 0x1f;
24207 rt
= (ctx
->opcode
>> 16) & 0x1f;
24208 rd
= (ctx
->opcode
>> 11) & 0x1f;
24209 sa
= (ctx
->opcode
>> 6) & 0x1f;
24211 op1
= MASK_SPECIAL(ctx
->opcode
);
24214 gen_lsa(ctx
, op1
, rd
, rs
, rt
, extract32(ctx
->opcode
, 6, 2));
24220 op2
= MASK_R6_MULDIV(ctx
->opcode
);
24230 gen_r6_muldiv(ctx
, op2
, rd
, rs
, rt
);
24233 MIPS_INVAL("special_r6 muldiv");
24234 generate_exception_end(ctx
, EXCP_RI
);
24240 gen_cond_move(ctx
, op1
, rd
, rs
, rt
);
24244 if (rt
== 0 && sa
== 1) {
24246 * Major opcode and function field is shared with preR6 MFHI/MTHI.
24247 * We need additionally to check other fields.
24249 gen_cl(ctx
, op1
, rd
, rs
);
24251 generate_exception_end(ctx
, EXCP_RI
);
24255 if (is_uhi(extract32(ctx
->opcode
, 6, 20))) {
24256 gen_helper_do_semihosting(cpu_env
);
24258 if (ctx
->hflags
& MIPS_HFLAG_SBRI
) {
24259 generate_exception_end(ctx
, EXCP_RI
);
24261 generate_exception_end(ctx
, EXCP_DBp
);
24265 #if defined(TARGET_MIPS64)
24267 check_mips_64(ctx
);
24268 gen_lsa(ctx
, op1
, rd
, rs
, rt
, extract32(ctx
->opcode
, 6, 2));
24272 if (rt
== 0 && sa
== 1) {
24274 * Major opcode and function field is shared with preR6 MFHI/MTHI.
24275 * We need additionally to check other fields.
24277 check_mips_64(ctx
);
24278 gen_cl(ctx
, op1
, rd
, rs
);
24280 generate_exception_end(ctx
, EXCP_RI
);
24288 op2
= MASK_R6_MULDIV(ctx
->opcode
);
24298 check_mips_64(ctx
);
24299 gen_r6_muldiv(ctx
, op2
, rd
, rs
, rt
);
24302 MIPS_INVAL("special_r6 muldiv");
24303 generate_exception_end(ctx
, EXCP_RI
);
24308 default: /* Invalid */
24309 MIPS_INVAL("special_r6");
24310 generate_exception_end(ctx
, EXCP_RI
);
24315 static void decode_opc_special_tx79(CPUMIPSState
*env
, DisasContext
*ctx
)
24317 int rs
= extract32(ctx
->opcode
, 21, 5);
24318 int rt
= extract32(ctx
->opcode
, 16, 5);
24319 int rd
= extract32(ctx
->opcode
, 11, 5);
24320 uint32_t op1
= MASK_SPECIAL(ctx
->opcode
);
24323 case OPC_MOVN
: /* Conditional move */
24325 gen_cond_move(ctx
, op1
, rd
, rs
, rt
);
24327 case OPC_MFHI
: /* Move from HI/LO */
24329 gen_HILO(ctx
, op1
, 0, rd
);
24332 case OPC_MTLO
: /* Move to HI/LO */
24333 gen_HILO(ctx
, op1
, 0, rs
);
24337 gen_mul_txx9(ctx
, op1
, rd
, rs
, rt
);
24341 gen_muldiv(ctx
, op1
, 0, rs
, rt
);
24343 #if defined(TARGET_MIPS64)
24348 check_insn_opc_user_only(ctx
, INSN_R5900
);
24349 gen_muldiv(ctx
, op1
, 0, rs
, rt
);
24353 gen_compute_branch(ctx
, op1
, 4, rs
, 0, 0, 4);
24355 default: /* Invalid */
24356 MIPS_INVAL("special_tx79");
24357 generate_exception_end(ctx
, EXCP_RI
);
24362 static void decode_opc_special_legacy(CPUMIPSState
*env
, DisasContext
*ctx
)
24364 int rs
, rt
, rd
, sa
;
24367 rs
= (ctx
->opcode
>> 21) & 0x1f;
24368 rt
= (ctx
->opcode
>> 16) & 0x1f;
24369 rd
= (ctx
->opcode
>> 11) & 0x1f;
24370 sa
= (ctx
->opcode
>> 6) & 0x1f;
24372 op1
= MASK_SPECIAL(ctx
->opcode
);
24374 case OPC_MOVN
: /* Conditional move */
24376 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
|
24377 INSN_LOONGSON2E
| INSN_LOONGSON2F
);
24378 gen_cond_move(ctx
, op1
, rd
, rs
, rt
);
24380 case OPC_MFHI
: /* Move from HI/LO */
24382 gen_HILO(ctx
, op1
, rs
& 3, rd
);
24385 case OPC_MTLO
: /* Move to HI/LO */
24386 gen_HILO(ctx
, op1
, rd
& 3, rs
);
24389 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
);
24390 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
24391 check_cp1_enabled(ctx
);
24392 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
24393 (ctx
->opcode
>> 16) & 1);
24395 generate_exception_err(ctx
, EXCP_CpU
, 1);
24401 check_insn(ctx
, INSN_VR54XX
);
24402 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
24403 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
24405 gen_muldiv(ctx
, op1
, rd
& 3, rs
, rt
);
24410 gen_muldiv(ctx
, op1
, 0, rs
, rt
);
24412 #if defined(TARGET_MIPS64)
24417 check_insn(ctx
, ISA_MIPS3
);
24418 check_mips_64(ctx
);
24419 gen_muldiv(ctx
, op1
, 0, rs
, rt
);
24423 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
, 4);
24426 #ifdef MIPS_STRICT_STANDARD
24427 MIPS_INVAL("SPIM");
24428 generate_exception_end(ctx
, EXCP_RI
);
24430 /* Implemented as RI exception for now. */
24431 MIPS_INVAL("spim (unofficial)");
24432 generate_exception_end(ctx
, EXCP_RI
);
24435 default: /* Invalid */
24436 MIPS_INVAL("special_legacy");
24437 generate_exception_end(ctx
, EXCP_RI
);
24442 static void decode_opc_special(CPUMIPSState
*env
, DisasContext
*ctx
)
24444 int rs
, rt
, rd
, sa
;
24447 rs
= (ctx
->opcode
>> 21) & 0x1f;
24448 rt
= (ctx
->opcode
>> 16) & 0x1f;
24449 rd
= (ctx
->opcode
>> 11) & 0x1f;
24450 sa
= (ctx
->opcode
>> 6) & 0x1f;
24452 op1
= MASK_SPECIAL(ctx
->opcode
);
24454 case OPC_SLL
: /* Shift with immediate */
24455 if (sa
== 5 && rd
== 0 &&
24456 rs
== 0 && rt
== 0) { /* PAUSE */
24457 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
24458 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
24459 generate_exception_end(ctx
, EXCP_RI
);
24465 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
24468 switch ((ctx
->opcode
>> 21) & 0x1f) {
24470 /* rotr is decoded as srl on non-R2 CPUs */
24471 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
24476 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
24479 generate_exception_end(ctx
, EXCP_RI
);
24487 gen_arith(ctx
, op1
, rd
, rs
, rt
);
24489 case OPC_SLLV
: /* Shifts */
24491 gen_shift(ctx
, op1
, rd
, rs
, rt
);
24494 switch ((ctx
->opcode
>> 6) & 0x1f) {
24496 /* rotrv is decoded as srlv on non-R2 CPUs */
24497 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
24502 gen_shift(ctx
, op1
, rd
, rs
, rt
);
24505 generate_exception_end(ctx
, EXCP_RI
);
24509 case OPC_SLT
: /* Set on less than */
24511 gen_slt(ctx
, op1
, rd
, rs
, rt
);
24513 case OPC_AND
: /* Logic*/
24517 gen_logic(ctx
, op1
, rd
, rs
, rt
);
24520 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
, 4);
24522 case OPC_TGE
: /* Traps */
24528 check_insn(ctx
, ISA_MIPS2
);
24529 gen_trap(ctx
, op1
, rs
, rt
, -1);
24531 case OPC_LSA
: /* OPC_PMON */
24532 if ((ctx
->insn_flags
& ISA_MIPS32R6
) ||
24533 (env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
24534 decode_opc_special_r6(env
, ctx
);
24536 /* Pmon entry point, also R4010 selsl */
24537 #ifdef MIPS_STRICT_STANDARD
24538 MIPS_INVAL("PMON / selsl");
24539 generate_exception_end(ctx
, EXCP_RI
);
24541 gen_helper_0e0i(pmon
, sa
);
24546 generate_exception_end(ctx
, EXCP_SYSCALL
);
24549 generate_exception_end(ctx
, EXCP_BREAK
);
24552 check_insn(ctx
, ISA_MIPS2
);
24553 gen_sync(extract32(ctx
->opcode
, 6, 5));
24556 #if defined(TARGET_MIPS64)
24557 /* MIPS64 specific opcodes */
24562 check_insn(ctx
, ISA_MIPS3
);
24563 check_mips_64(ctx
);
24564 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
24567 switch ((ctx
->opcode
>> 21) & 0x1f) {
24569 /* drotr is decoded as dsrl on non-R2 CPUs */
24570 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
24575 check_insn(ctx
, ISA_MIPS3
);
24576 check_mips_64(ctx
);
24577 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
24580 generate_exception_end(ctx
, EXCP_RI
);
24585 switch ((ctx
->opcode
>> 21) & 0x1f) {
24587 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
24588 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
24593 check_insn(ctx
, ISA_MIPS3
);
24594 check_mips_64(ctx
);
24595 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
24598 generate_exception_end(ctx
, EXCP_RI
);
24606 check_insn(ctx
, ISA_MIPS3
);
24607 check_mips_64(ctx
);
24608 gen_arith(ctx
, op1
, rd
, rs
, rt
);
24612 check_insn(ctx
, ISA_MIPS3
);
24613 check_mips_64(ctx
);
24614 gen_shift(ctx
, op1
, rd
, rs
, rt
);
24617 switch ((ctx
->opcode
>> 6) & 0x1f) {
24619 /* drotrv is decoded as dsrlv on non-R2 CPUs */
24620 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
24625 check_insn(ctx
, ISA_MIPS3
);
24626 check_mips_64(ctx
);
24627 gen_shift(ctx
, op1
, rd
, rs
, rt
);
24630 generate_exception_end(ctx
, EXCP_RI
);
24635 if ((ctx
->insn_flags
& ISA_MIPS32R6
) ||
24636 (env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
24637 decode_opc_special_r6(env
, ctx
);
24642 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
24643 decode_opc_special_r6(env
, ctx
);
24644 } else if (ctx
->insn_flags
& INSN_R5900
) {
24645 decode_opc_special_tx79(env
, ctx
);
24647 decode_opc_special_legacy(env
, ctx
);
24653 #if defined(TARGET_MIPS64)
24657 * MMI (MultiMedia Interface) ASE instructions
24658 * ===========================================
24662 * MMI instructions category: data communication
24663 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24665 * PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH
24666 * PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W
24667 * PCPYUD PEXEH PEXTLW PPACW
24676 * Parallel Copy Halfword
24678 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
24679 * +-----------+---------+---------+---------+---------+-----------+
24680 * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
24681 * +-----------+---------+---------+---------+---------+-----------+
24683 static void gen_mmi_pcpyh(DisasContext
*ctx
)
24685 uint32_t pd
, rt
, rd
;
24688 opcode
= ctx
->opcode
;
24690 pd
= extract32(opcode
, 21, 5);
24691 rt
= extract32(opcode
, 16, 5);
24692 rd
= extract32(opcode
, 11, 5);
24694 if (unlikely(pd
!= 0)) {
24695 generate_exception_end(ctx
, EXCP_RI
);
24696 } else if (rd
== 0) {
24698 } else if (rt
== 0) {
24699 tcg_gen_movi_i64(cpu_gpr
[rd
], 0);
24700 tcg_gen_movi_i64(cpu_mmr
[rd
], 0);
24702 TCGv_i64 t0
= tcg_temp_new();
24703 TCGv_i64 t1
= tcg_temp_new();
24704 uint64_t mask
= (1ULL << 16) - 1;
24706 tcg_gen_andi_i64(t0
, cpu_gpr
[rt
], mask
);
24707 tcg_gen_movi_i64(t1
, 0);
24708 tcg_gen_or_i64(t1
, t0
, t1
);
24709 tcg_gen_shli_i64(t0
, t0
, 16);
24710 tcg_gen_or_i64(t1
, t0
, t1
);
24711 tcg_gen_shli_i64(t0
, t0
, 16);
24712 tcg_gen_or_i64(t1
, t0
, t1
);
24713 tcg_gen_shli_i64(t0
, t0
, 16);
24714 tcg_gen_or_i64(t1
, t0
, t1
);
24716 tcg_gen_mov_i64(cpu_gpr
[rd
], t1
);
24718 tcg_gen_andi_i64(t0
, cpu_mmr
[rt
], mask
);
24719 tcg_gen_movi_i64(t1
, 0);
24720 tcg_gen_or_i64(t1
, t0
, t1
);
24721 tcg_gen_shli_i64(t0
, t0
, 16);
24722 tcg_gen_or_i64(t1
, t0
, t1
);
24723 tcg_gen_shli_i64(t0
, t0
, 16);
24724 tcg_gen_or_i64(t1
, t0
, t1
);
24725 tcg_gen_shli_i64(t0
, t0
, 16);
24726 tcg_gen_or_i64(t1
, t0
, t1
);
24728 tcg_gen_mov_i64(cpu_mmr
[rd
], t1
);
24736 * PCPYLD rd, rs, rt
24738 * Parallel Copy Lower Doubleword
24740 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
24741 * +-----------+---------+---------+---------+---------+-----------+
24742 * | MMI | rs | rt | rd | PCPYLD | MMI2 |
24743 * +-----------+---------+---------+---------+---------+-----------+
24745 static void gen_mmi_pcpyld(DisasContext
*ctx
)
24747 uint32_t rs
, rt
, rd
;
24750 opcode
= ctx
->opcode
;
24752 rs
= extract32(opcode
, 21, 5);
24753 rt
= extract32(opcode
, 16, 5);
24754 rd
= extract32(opcode
, 11, 5);
24760 tcg_gen_movi_i64(cpu_mmr
[rd
], 0);
24762 tcg_gen_mov_i64(cpu_mmr
[rd
], cpu_gpr
[rs
]);
24765 tcg_gen_movi_i64(cpu_gpr
[rd
], 0);
24768 tcg_gen_mov_i64(cpu_gpr
[rd
], cpu_gpr
[rt
]);
24775 * PCPYUD rd, rs, rt
24777 * Parallel Copy Upper Doubleword
24779 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
24780 * +-----------+---------+---------+---------+---------+-----------+
24781 * | MMI | rs | rt | rd | PCPYUD | MMI3 |
24782 * +-----------+---------+---------+---------+---------+-----------+
24784 static void gen_mmi_pcpyud(DisasContext
*ctx
)
24786 uint32_t rs
, rt
, rd
;
24789 opcode
= ctx
->opcode
;
24791 rs
= extract32(opcode
, 21, 5);
24792 rt
= extract32(opcode
, 16, 5);
24793 rd
= extract32(opcode
, 11, 5);
24799 tcg_gen_movi_i64(cpu_gpr
[rd
], 0);
24801 tcg_gen_mov_i64(cpu_gpr
[rd
], cpu_mmr
[rs
]);
24804 tcg_gen_movi_i64(cpu_mmr
[rd
], 0);
24807 tcg_gen_mov_i64(cpu_mmr
[rd
], cpu_mmr
[rt
]);
24816 #if !defined(TARGET_MIPS64)
24818 /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
24819 #define MXU_APTN1_A 0
24820 #define MXU_APTN1_S 1
24822 /* MXU accumulate add/subtract 2-bit pattern 'aptn2' */
24823 #define MXU_APTN2_AA 0
24824 #define MXU_APTN2_AS 1
24825 #define MXU_APTN2_SA 2
24826 #define MXU_APTN2_SS 3
24828 /* MXU execute add/subtract 2-bit pattern 'eptn2' */
24829 #define MXU_EPTN2_AA 0
24830 #define MXU_EPTN2_AS 1
24831 #define MXU_EPTN2_SA 2
24832 #define MXU_EPTN2_SS 3
24834 /* MXU operand getting pattern 'optn2' */
24835 #define MXU_OPTN2_PTN0 0
24836 #define MXU_OPTN2_PTN1 1
24837 #define MXU_OPTN2_PTN2 2
24838 #define MXU_OPTN2_PTN3 3
24839 /* alternative naming scheme for 'optn2' */
24840 #define MXU_OPTN2_WW 0
24841 #define MXU_OPTN2_LW 1
24842 #define MXU_OPTN2_HW 2
24843 #define MXU_OPTN2_XW 3
24845 /* MXU operand getting pattern 'optn3' */
24846 #define MXU_OPTN3_PTN0 0
24847 #define MXU_OPTN3_PTN1 1
24848 #define MXU_OPTN3_PTN2 2
24849 #define MXU_OPTN3_PTN3 3
24850 #define MXU_OPTN3_PTN4 4
24851 #define MXU_OPTN3_PTN5 5
24852 #define MXU_OPTN3_PTN6 6
24853 #define MXU_OPTN3_PTN7 7
24857 * S32I2M XRa, rb - Register move from GRF to XRF
24859 static void gen_mxu_s32i2m(DisasContext
*ctx
)
24864 t0
= tcg_temp_new();
24866 XRa
= extract32(ctx
->opcode
, 6, 5);
24867 Rb
= extract32(ctx
->opcode
, 16, 5);
24869 gen_load_gpr(t0
, Rb
);
24871 gen_store_mxu_gpr(t0
, XRa
);
24872 } else if (XRa
== 16) {
24873 gen_store_mxu_cr(t0
);
24880 * S32M2I XRa, rb - Register move from XRF to GRF
24882 static void gen_mxu_s32m2i(DisasContext
*ctx
)
24887 t0
= tcg_temp_new();
24889 XRa
= extract32(ctx
->opcode
, 6, 5);
24890 Rb
= extract32(ctx
->opcode
, 16, 5);
24893 gen_load_mxu_gpr(t0
, XRa
);
24894 } else if (XRa
== 16) {
24895 gen_load_mxu_cr(t0
);
24898 gen_store_gpr(t0
, Rb
);
24904 * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF
24906 static void gen_mxu_s8ldd(DisasContext
*ctx
)
24909 uint32_t XRa
, Rb
, s8
, optn3
;
24911 t0
= tcg_temp_new();
24912 t1
= tcg_temp_new();
24914 XRa
= extract32(ctx
->opcode
, 6, 4);
24915 s8
= extract32(ctx
->opcode
, 10, 8);
24916 optn3
= extract32(ctx
->opcode
, 18, 3);
24917 Rb
= extract32(ctx
->opcode
, 21, 5);
24919 gen_load_gpr(t0
, Rb
);
24920 tcg_gen_addi_tl(t0
, t0
, (int8_t)s8
);
24923 /* XRa[7:0] = tmp8 */
24924 case MXU_OPTN3_PTN0
:
24925 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24926 gen_load_mxu_gpr(t0
, XRa
);
24927 tcg_gen_deposit_tl(t0
, t0
, t1
, 0, 8);
24929 /* XRa[15:8] = tmp8 */
24930 case MXU_OPTN3_PTN1
:
24931 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24932 gen_load_mxu_gpr(t0
, XRa
);
24933 tcg_gen_deposit_tl(t0
, t0
, t1
, 8, 8);
24935 /* XRa[23:16] = tmp8 */
24936 case MXU_OPTN3_PTN2
:
24937 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24938 gen_load_mxu_gpr(t0
, XRa
);
24939 tcg_gen_deposit_tl(t0
, t0
, t1
, 16, 8);
24941 /* XRa[31:24] = tmp8 */
24942 case MXU_OPTN3_PTN3
:
24943 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24944 gen_load_mxu_gpr(t0
, XRa
);
24945 tcg_gen_deposit_tl(t0
, t0
, t1
, 24, 8);
24947 /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
24948 case MXU_OPTN3_PTN4
:
24949 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24950 tcg_gen_deposit_tl(t0
, t1
, t1
, 16, 16);
24952 /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
24953 case MXU_OPTN3_PTN5
:
24954 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24955 tcg_gen_shli_tl(t1
, t1
, 8);
24956 tcg_gen_deposit_tl(t0
, t1
, t1
, 16, 16);
24958 /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
24959 case MXU_OPTN3_PTN6
:
24960 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_SB
);
24961 tcg_gen_mov_tl(t0
, t1
);
24962 tcg_gen_andi_tl(t0
, t0
, 0xFF00FFFF);
24963 tcg_gen_shli_tl(t1
, t1
, 16);
24964 tcg_gen_or_tl(t0
, t0
, t1
);
24966 /* XRa = {tmp8, tmp8, tmp8, tmp8} */
24967 case MXU_OPTN3_PTN7
:
24968 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_UB
);
24969 tcg_gen_deposit_tl(t1
, t1
, t1
, 8, 8);
24970 tcg_gen_deposit_tl(t0
, t1
, t1
, 16, 16);
24974 gen_store_mxu_gpr(t0
, XRa
);
24981 * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication
24983 static void gen_mxu_d16mul(DisasContext
*ctx
)
24985 TCGv t0
, t1
, t2
, t3
;
24986 uint32_t XRa
, XRb
, XRc
, XRd
, optn2
;
24988 t0
= tcg_temp_new();
24989 t1
= tcg_temp_new();
24990 t2
= tcg_temp_new();
24991 t3
= tcg_temp_new();
24993 XRa
= extract32(ctx
->opcode
, 6, 4);
24994 XRb
= extract32(ctx
->opcode
, 10, 4);
24995 XRc
= extract32(ctx
->opcode
, 14, 4);
24996 XRd
= extract32(ctx
->opcode
, 18, 4);
24997 optn2
= extract32(ctx
->opcode
, 22, 2);
24999 gen_load_mxu_gpr(t1
, XRb
);
25000 tcg_gen_sextract_tl(t0
, t1
, 0, 16);
25001 tcg_gen_sextract_tl(t1
, t1
, 16, 16);
25002 gen_load_mxu_gpr(t3
, XRc
);
25003 tcg_gen_sextract_tl(t2
, t3
, 0, 16);
25004 tcg_gen_sextract_tl(t3
, t3
, 16, 16);
25007 case MXU_OPTN2_WW
: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
25008 tcg_gen_mul_tl(t3
, t1
, t3
);
25009 tcg_gen_mul_tl(t2
, t0
, t2
);
25011 case MXU_OPTN2_LW
: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
25012 tcg_gen_mul_tl(t3
, t0
, t3
);
25013 tcg_gen_mul_tl(t2
, t0
, t2
);
25015 case MXU_OPTN2_HW
: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
25016 tcg_gen_mul_tl(t3
, t1
, t3
);
25017 tcg_gen_mul_tl(t2
, t1
, t2
);
25019 case MXU_OPTN2_XW
: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
25020 tcg_gen_mul_tl(t3
, t0
, t3
);
25021 tcg_gen_mul_tl(t2
, t1
, t2
);
25024 gen_store_mxu_gpr(t3
, XRa
);
25025 gen_store_mxu_gpr(t2
, XRd
);
25034 * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply
25037 static void gen_mxu_d16mac(DisasContext
*ctx
)
25039 TCGv t0
, t1
, t2
, t3
;
25040 uint32_t XRa
, XRb
, XRc
, XRd
, optn2
, aptn2
;
25042 t0
= tcg_temp_new();
25043 t1
= tcg_temp_new();
25044 t2
= tcg_temp_new();
25045 t3
= tcg_temp_new();
25047 XRa
= extract32(ctx
->opcode
, 6, 4);
25048 XRb
= extract32(ctx
->opcode
, 10, 4);
25049 XRc
= extract32(ctx
->opcode
, 14, 4);
25050 XRd
= extract32(ctx
->opcode
, 18, 4);
25051 optn2
= extract32(ctx
->opcode
, 22, 2);
25052 aptn2
= extract32(ctx
->opcode
, 24, 2);
25054 gen_load_mxu_gpr(t1
, XRb
);
25055 tcg_gen_sextract_tl(t0
, t1
, 0, 16);
25056 tcg_gen_sextract_tl(t1
, t1
, 16, 16);
25058 gen_load_mxu_gpr(t3
, XRc
);
25059 tcg_gen_sextract_tl(t2
, t3
, 0, 16);
25060 tcg_gen_sextract_tl(t3
, t3
, 16, 16);
25063 case MXU_OPTN2_WW
: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
25064 tcg_gen_mul_tl(t3
, t1
, t3
);
25065 tcg_gen_mul_tl(t2
, t0
, t2
);
25067 case MXU_OPTN2_LW
: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
25068 tcg_gen_mul_tl(t3
, t0
, t3
);
25069 tcg_gen_mul_tl(t2
, t0
, t2
);
25071 case MXU_OPTN2_HW
: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
25072 tcg_gen_mul_tl(t3
, t1
, t3
);
25073 tcg_gen_mul_tl(t2
, t1
, t2
);
25075 case MXU_OPTN2_XW
: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
25076 tcg_gen_mul_tl(t3
, t0
, t3
);
25077 tcg_gen_mul_tl(t2
, t1
, t2
);
25080 gen_load_mxu_gpr(t0
, XRa
);
25081 gen_load_mxu_gpr(t1
, XRd
);
25085 tcg_gen_add_tl(t3
, t0
, t3
);
25086 tcg_gen_add_tl(t2
, t1
, t2
);
25089 tcg_gen_add_tl(t3
, t0
, t3
);
25090 tcg_gen_sub_tl(t2
, t1
, t2
);
25093 tcg_gen_sub_tl(t3
, t0
, t3
);
25094 tcg_gen_add_tl(t2
, t1
, t2
);
25097 tcg_gen_sub_tl(t3
, t0
, t3
);
25098 tcg_gen_sub_tl(t2
, t1
, t2
);
25101 gen_store_mxu_gpr(t3
, XRa
);
25102 gen_store_mxu_gpr(t2
, XRd
);
25111 * Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply
25112 * Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply
25114 static void gen_mxu_q8mul_q8mulsu(DisasContext
*ctx
)
25116 TCGv t0
, t1
, t2
, t3
, t4
, t5
, t6
, t7
;
25117 uint32_t XRa
, XRb
, XRc
, XRd
, sel
;
25119 t0
= tcg_temp_new();
25120 t1
= tcg_temp_new();
25121 t2
= tcg_temp_new();
25122 t3
= tcg_temp_new();
25123 t4
= tcg_temp_new();
25124 t5
= tcg_temp_new();
25125 t6
= tcg_temp_new();
25126 t7
= tcg_temp_new();
25128 XRa
= extract32(ctx
->opcode
, 6, 4);
25129 XRb
= extract32(ctx
->opcode
, 10, 4);
25130 XRc
= extract32(ctx
->opcode
, 14, 4);
25131 XRd
= extract32(ctx
->opcode
, 18, 4);
25132 sel
= extract32(ctx
->opcode
, 22, 2);
25134 gen_load_mxu_gpr(t3
, XRb
);
25135 gen_load_mxu_gpr(t7
, XRc
);
25139 tcg_gen_ext8s_tl(t0
, t3
);
25140 tcg_gen_shri_tl(t3
, t3
, 8);
25141 tcg_gen_ext8s_tl(t1
, t3
);
25142 tcg_gen_shri_tl(t3
, t3
, 8);
25143 tcg_gen_ext8s_tl(t2
, t3
);
25144 tcg_gen_shri_tl(t3
, t3
, 8);
25145 tcg_gen_ext8s_tl(t3
, t3
);
25148 tcg_gen_ext8u_tl(t0
, t3
);
25149 tcg_gen_shri_tl(t3
, t3
, 8);
25150 tcg_gen_ext8u_tl(t1
, t3
);
25151 tcg_gen_shri_tl(t3
, t3
, 8);
25152 tcg_gen_ext8u_tl(t2
, t3
);
25153 tcg_gen_shri_tl(t3
, t3
, 8);
25154 tcg_gen_ext8u_tl(t3
, t3
);
25157 tcg_gen_ext8u_tl(t4
, t7
);
25158 tcg_gen_shri_tl(t7
, t7
, 8);
25159 tcg_gen_ext8u_tl(t5
, t7
);
25160 tcg_gen_shri_tl(t7
, t7
, 8);
25161 tcg_gen_ext8u_tl(t6
, t7
);
25162 tcg_gen_shri_tl(t7
, t7
, 8);
25163 tcg_gen_ext8u_tl(t7
, t7
);
25165 tcg_gen_mul_tl(t0
, t0
, t4
);
25166 tcg_gen_mul_tl(t1
, t1
, t5
);
25167 tcg_gen_mul_tl(t2
, t2
, t6
);
25168 tcg_gen_mul_tl(t3
, t3
, t7
);
25170 tcg_gen_andi_tl(t0
, t0
, 0xFFFF);
25171 tcg_gen_andi_tl(t1
, t1
, 0xFFFF);
25172 tcg_gen_andi_tl(t2
, t2
, 0xFFFF);
25173 tcg_gen_andi_tl(t3
, t3
, 0xFFFF);
25175 tcg_gen_shli_tl(t1
, t1
, 16);
25176 tcg_gen_shli_tl(t3
, t3
, 16);
25178 tcg_gen_or_tl(t0
, t0
, t1
);
25179 tcg_gen_or_tl(t1
, t2
, t3
);
25181 gen_store_mxu_gpr(t0
, XRd
);
25182 gen_store_mxu_gpr(t1
, XRa
);
25195 * S32LDD XRa, Rb, S12 - Load a word from memory to XRF
25196 * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte seq.
25198 static void gen_mxu_s32ldd_s32lddr(DisasContext
*ctx
)
25201 uint32_t XRa
, Rb
, s12
, sel
;
25203 t0
= tcg_temp_new();
25204 t1
= tcg_temp_new();
25206 XRa
= extract32(ctx
->opcode
, 6, 4);
25207 s12
= extract32(ctx
->opcode
, 10, 10);
25208 sel
= extract32(ctx
->opcode
, 20, 1);
25209 Rb
= extract32(ctx
->opcode
, 21, 5);
25211 gen_load_gpr(t0
, Rb
);
25213 tcg_gen_movi_tl(t1
, s12
);
25214 tcg_gen_shli_tl(t1
, t1
, 2);
25216 tcg_gen_ori_tl(t1
, t1
, 0xFFFFF000);
25218 tcg_gen_add_tl(t1
, t0
, t1
);
25219 tcg_gen_qemu_ld_tl(t1
, t1
, ctx
->mem_idx
, MO_SL
);
25223 tcg_gen_bswap32_tl(t1
, t1
);
25225 gen_store_mxu_gpr(t1
, XRa
);
25233 * MXU instruction category: logic
25234 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25236 * S32NOR S32AND S32OR S32XOR
25240 * S32NOR XRa, XRb, XRc
25241 * Update XRa with the result of logical bitwise 'nor' operation
25242 * applied to the content of XRb and XRc.
25244 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25245 * +-----------+---------+-----+-------+-------+-------+-----------+
25246 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
25247 * +-----------+---------+-----+-------+-------+-------+-----------+
25249 static void gen_mxu_S32NOR(DisasContext
*ctx
)
25251 uint32_t pad
, XRc
, XRb
, XRa
;
25253 pad
= extract32(ctx
->opcode
, 21, 5);
25254 XRc
= extract32(ctx
->opcode
, 14, 4);
25255 XRb
= extract32(ctx
->opcode
, 10, 4);
25256 XRa
= extract32(ctx
->opcode
, 6, 4);
25258 if (unlikely(pad
!= 0)) {
25259 /* opcode padding incorrect -> do nothing */
25260 } else if (unlikely(XRa
== 0)) {
25261 /* destination is zero register -> do nothing */
25262 } else if (unlikely((XRb
== 0) && (XRc
== 0))) {
25263 /* both operands zero registers -> just set destination to all 1s */
25264 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0xFFFFFFFF);
25265 } else if (unlikely(XRb
== 0)) {
25266 /* XRb zero register -> just set destination to the negation of XRc */
25267 tcg_gen_not_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRc
- 1]);
25268 } else if (unlikely(XRc
== 0)) {
25269 /* XRa zero register -> just set destination to the negation of XRb */
25270 tcg_gen_not_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25271 } else if (unlikely(XRb
== XRc
)) {
25272 /* both operands same -> just set destination to the negation of XRb */
25273 tcg_gen_not_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25275 /* the most general case */
25276 tcg_gen_nor_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1], mxu_gpr
[XRc
- 1]);
25281 * S32AND XRa, XRb, XRc
25282 * Update XRa with the result of logical bitwise 'and' operation
25283 * applied to the content of XRb and XRc.
25285 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25286 * +-----------+---------+-----+-------+-------+-------+-----------+
25287 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
25288 * +-----------+---------+-----+-------+-------+-------+-----------+
25290 static void gen_mxu_S32AND(DisasContext
*ctx
)
25292 uint32_t pad
, XRc
, XRb
, XRa
;
25294 pad
= extract32(ctx
->opcode
, 21, 5);
25295 XRc
= extract32(ctx
->opcode
, 14, 4);
25296 XRb
= extract32(ctx
->opcode
, 10, 4);
25297 XRa
= extract32(ctx
->opcode
, 6, 4);
25299 if (unlikely(pad
!= 0)) {
25300 /* opcode padding incorrect -> do nothing */
25301 } else if (unlikely(XRa
== 0)) {
25302 /* destination is zero register -> do nothing */
25303 } else if (unlikely((XRb
== 0) || (XRc
== 0))) {
25304 /* one of operands zero register -> just set destination to all 0s */
25305 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25306 } else if (unlikely(XRb
== XRc
)) {
25307 /* both operands same -> just set destination to one of them */
25308 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25310 /* the most general case */
25311 tcg_gen_and_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1], mxu_gpr
[XRc
- 1]);
25316 * S32OR XRa, XRb, XRc
25317 * Update XRa with the result of logical bitwise 'or' operation
25318 * applied to the content of XRb and XRc.
25320 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25321 * +-----------+---------+-----+-------+-------+-------+-----------+
25322 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
25323 * +-----------+---------+-----+-------+-------+-------+-----------+
25325 static void gen_mxu_S32OR(DisasContext
*ctx
)
25327 uint32_t pad
, XRc
, XRb
, XRa
;
25329 pad
= extract32(ctx
->opcode
, 21, 5);
25330 XRc
= extract32(ctx
->opcode
, 14, 4);
25331 XRb
= extract32(ctx
->opcode
, 10, 4);
25332 XRa
= extract32(ctx
->opcode
, 6, 4);
25334 if (unlikely(pad
!= 0)) {
25335 /* opcode padding incorrect -> do nothing */
25336 } else if (unlikely(XRa
== 0)) {
25337 /* destination is zero register -> do nothing */
25338 } else if (unlikely((XRb
== 0) && (XRc
== 0))) {
25339 /* both operands zero registers -> just set destination to all 0s */
25340 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25341 } else if (unlikely(XRb
== 0)) {
25342 /* XRb zero register -> just set destination to the content of XRc */
25343 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRc
- 1]);
25344 } else if (unlikely(XRc
== 0)) {
25345 /* XRc zero register -> just set destination to the content of XRb */
25346 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25347 } else if (unlikely(XRb
== XRc
)) {
25348 /* both operands same -> just set destination to one of them */
25349 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25351 /* the most general case */
25352 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1], mxu_gpr
[XRc
- 1]);
25357 * S32XOR XRa, XRb, XRc
25358 * Update XRa with the result of logical bitwise 'xor' operation
25359 * applied to the content of XRb and XRc.
25361 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25362 * +-----------+---------+-----+-------+-------+-------+-----------+
25363 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
25364 * +-----------+---------+-----+-------+-------+-------+-----------+
25366 static void gen_mxu_S32XOR(DisasContext
*ctx
)
25368 uint32_t pad
, XRc
, XRb
, XRa
;
25370 pad
= extract32(ctx
->opcode
, 21, 5);
25371 XRc
= extract32(ctx
->opcode
, 14, 4);
25372 XRb
= extract32(ctx
->opcode
, 10, 4);
25373 XRa
= extract32(ctx
->opcode
, 6, 4);
25375 if (unlikely(pad
!= 0)) {
25376 /* opcode padding incorrect -> do nothing */
25377 } else if (unlikely(XRa
== 0)) {
25378 /* destination is zero register -> do nothing */
25379 } else if (unlikely((XRb
== 0) && (XRc
== 0))) {
25380 /* both operands zero registers -> just set destination to all 0s */
25381 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25382 } else if (unlikely(XRb
== 0)) {
25383 /* XRb zero register -> just set destination to the content of XRc */
25384 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRc
- 1]);
25385 } else if (unlikely(XRc
== 0)) {
25386 /* XRc zero register -> just set destination to the content of XRb */
25387 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25388 } else if (unlikely(XRb
== XRc
)) {
25389 /* both operands same -> just set destination to all 0s */
25390 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25392 /* the most general case */
25393 tcg_gen_xor_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1], mxu_gpr
[XRc
- 1]);
25399 * MXU instruction category max/min
25400 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25402 * S32MAX D16MAX Q8MAX
25403 * S32MIN D16MIN Q8MIN
25407 * S32MAX XRa, XRb, XRc
25408 * Update XRa with the maximum of signed 32-bit integers contained
25411 * S32MIN XRa, XRb, XRc
25412 * Update XRa with the minimum of signed 32-bit integers contained
25415 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25416 * +-----------+---------+-----+-------+-------+-------+-----------+
25417 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
25418 * +-----------+---------+-----+-------+-------+-------+-----------+
25420 static void gen_mxu_S32MAX_S32MIN(DisasContext
*ctx
)
25422 uint32_t pad
, opc
, XRc
, XRb
, XRa
;
25424 pad
= extract32(ctx
->opcode
, 21, 5);
25425 opc
= extract32(ctx
->opcode
, 18, 3);
25426 XRc
= extract32(ctx
->opcode
, 14, 4);
25427 XRb
= extract32(ctx
->opcode
, 10, 4);
25428 XRa
= extract32(ctx
->opcode
, 6, 4);
25430 if (unlikely(pad
!= 0)) {
25431 /* opcode padding incorrect -> do nothing */
25432 } else if (unlikely(XRa
== 0)) {
25433 /* destination is zero register -> do nothing */
25434 } else if (unlikely((XRb
== 0) && (XRc
== 0))) {
25435 /* both operands zero registers -> just set destination to zero */
25436 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25437 } else if (unlikely((XRb
== 0) || (XRc
== 0))) {
25438 /* exactly one operand is zero register - find which one is not...*/
25439 uint32_t XRx
= XRb
? XRb
: XRc
;
25440 /* ...and do max/min operation with one operand 0 */
25441 if (opc
== OPC_MXU_S32MAX
) {
25442 tcg_gen_smax_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRx
- 1], 0);
25444 tcg_gen_smin_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRx
- 1], 0);
25446 } else if (unlikely(XRb
== XRc
)) {
25447 /* both operands same -> just set destination to one of them */
25448 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25450 /* the most general case */
25451 if (opc
== OPC_MXU_S32MAX
) {
25452 tcg_gen_smax_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1],
25455 tcg_gen_smin_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1],
25463 * Update XRa with the 16-bit-wise maximums of signed integers
25464 * contained in XRb and XRc.
25467 * Update XRa with the 16-bit-wise minimums of signed integers
25468 * contained in XRb and XRc.
25470 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25471 * +-----------+---------+-----+-------+-------+-------+-----------+
25472 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
25473 * +-----------+---------+-----+-------+-------+-------+-----------+
25475 static void gen_mxu_D16MAX_D16MIN(DisasContext
*ctx
)
25477 uint32_t pad
, opc
, XRc
, XRb
, XRa
;
25479 pad
= extract32(ctx
->opcode
, 21, 5);
25480 opc
= extract32(ctx
->opcode
, 18, 3);
25481 XRc
= extract32(ctx
->opcode
, 14, 4);
25482 XRb
= extract32(ctx
->opcode
, 10, 4);
25483 XRa
= extract32(ctx
->opcode
, 6, 4);
25485 if (unlikely(pad
!= 0)) {
25486 /* opcode padding incorrect -> do nothing */
25487 } else if (unlikely(XRc
== 0)) {
25488 /* destination is zero register -> do nothing */
25489 } else if (unlikely((XRb
== 0) && (XRa
== 0))) {
25490 /* both operands zero registers -> just set destination to zero */
25491 tcg_gen_movi_i32(mxu_gpr
[XRc
- 1], 0);
25492 } else if (unlikely((XRb
== 0) || (XRa
== 0))) {
25493 /* exactly one operand is zero register - find which one is not...*/
25494 uint32_t XRx
= XRb
? XRb
: XRc
;
25495 /* ...and do half-word-wise max/min with one operand 0 */
25496 TCGv_i32 t0
= tcg_temp_new();
25497 TCGv_i32 t1
= tcg_const_i32(0);
25499 /* the left half-word first */
25500 tcg_gen_andi_i32(t0
, mxu_gpr
[XRx
- 1], 0xFFFF0000);
25501 if (opc
== OPC_MXU_D16MAX
) {
25502 tcg_gen_smax_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25504 tcg_gen_smin_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25507 /* the right half-word */
25508 tcg_gen_andi_i32(t0
, mxu_gpr
[XRx
- 1], 0x0000FFFF);
25509 /* move half-words to the leftmost position */
25510 tcg_gen_shli_i32(t0
, t0
, 16);
25511 /* t0 will be max/min of t0 and t1 */
25512 if (opc
== OPC_MXU_D16MAX
) {
25513 tcg_gen_smax_i32(t0
, t0
, t1
);
25515 tcg_gen_smin_i32(t0
, t0
, t1
);
25517 /* return resulting half-words to its original position */
25518 tcg_gen_shri_i32(t0
, t0
, 16);
25519 /* finaly update the destination */
25520 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRa
- 1], t0
);
25524 } else if (unlikely(XRb
== XRc
)) {
25525 /* both operands same -> just set destination to one of them */
25526 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25528 /* the most general case */
25529 TCGv_i32 t0
= tcg_temp_new();
25530 TCGv_i32 t1
= tcg_temp_new();
25532 /* the left half-word first */
25533 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0xFFFF0000);
25534 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0xFFFF0000);
25535 if (opc
== OPC_MXU_D16MAX
) {
25536 tcg_gen_smax_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25538 tcg_gen_smin_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25541 /* the right half-word */
25542 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0x0000FFFF);
25543 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0x0000FFFF);
25544 /* move half-words to the leftmost position */
25545 tcg_gen_shli_i32(t0
, t0
, 16);
25546 tcg_gen_shli_i32(t1
, t1
, 16);
25547 /* t0 will be max/min of t0 and t1 */
25548 if (opc
== OPC_MXU_D16MAX
) {
25549 tcg_gen_smax_i32(t0
, t0
, t1
);
25551 tcg_gen_smin_i32(t0
, t0
, t1
);
25553 /* return resulting half-words to its original position */
25554 tcg_gen_shri_i32(t0
, t0
, 16);
25555 /* finaly update the destination */
25556 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRa
- 1], t0
);
25565 * Update XRa with the 8-bit-wise maximums of signed integers
25566 * contained in XRb and XRc.
25569 * Update XRa with the 8-bit-wise minimums of signed integers
25570 * contained in XRb and XRc.
25572 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25573 * +-----------+---------+-----+-------+-------+-------+-----------+
25574 * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
25575 * +-----------+---------+-----+-------+-------+-------+-----------+
25577 static void gen_mxu_Q8MAX_Q8MIN(DisasContext
*ctx
)
25579 uint32_t pad
, opc
, XRc
, XRb
, XRa
;
25581 pad
= extract32(ctx
->opcode
, 21, 5);
25582 opc
= extract32(ctx
->opcode
, 18, 3);
25583 XRc
= extract32(ctx
->opcode
, 14, 4);
25584 XRb
= extract32(ctx
->opcode
, 10, 4);
25585 XRa
= extract32(ctx
->opcode
, 6, 4);
25587 if (unlikely(pad
!= 0)) {
25588 /* opcode padding incorrect -> do nothing */
25589 } else if (unlikely(XRa
== 0)) {
25590 /* destination is zero register -> do nothing */
25591 } else if (unlikely((XRb
== 0) && (XRc
== 0))) {
25592 /* both operands zero registers -> just set destination to zero */
25593 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25594 } else if (unlikely((XRb
== 0) || (XRc
== 0))) {
25595 /* exactly one operand is zero register - make it be the first...*/
25596 uint32_t XRx
= XRb
? XRb
: XRc
;
25597 /* ...and do byte-wise max/min with one operand 0 */
25598 TCGv_i32 t0
= tcg_temp_new();
25599 TCGv_i32 t1
= tcg_const_i32(0);
25602 /* the leftmost byte (byte 3) first */
25603 tcg_gen_andi_i32(t0
, mxu_gpr
[XRx
- 1], 0xFF000000);
25604 if (opc
== OPC_MXU_Q8MAX
) {
25605 tcg_gen_smax_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25607 tcg_gen_smin_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25610 /* bytes 2, 1, 0 */
25611 for (i
= 2; i
>= 0; i
--) {
25612 /* extract the byte */
25613 tcg_gen_andi_i32(t0
, mxu_gpr
[XRx
- 1], 0xFF << (8 * i
));
25614 /* move the byte to the leftmost position */
25615 tcg_gen_shli_i32(t0
, t0
, 8 * (3 - i
));
25616 /* t0 will be max/min of t0 and t1 */
25617 if (opc
== OPC_MXU_Q8MAX
) {
25618 tcg_gen_smax_i32(t0
, t0
, t1
);
25620 tcg_gen_smin_i32(t0
, t0
, t1
);
25622 /* return resulting byte to its original position */
25623 tcg_gen_shri_i32(t0
, t0
, 8 * (3 - i
));
25624 /* finaly update the destination */
25625 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRa
- 1], t0
);
25630 } else if (unlikely(XRb
== XRc
)) {
25631 /* both operands same -> just set destination to one of them */
25632 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25634 /* the most general case */
25635 TCGv_i32 t0
= tcg_temp_new();
25636 TCGv_i32 t1
= tcg_temp_new();
25639 /* the leftmost bytes (bytes 3) first */
25640 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0xFF000000);
25641 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0xFF000000);
25642 if (opc
== OPC_MXU_Q8MAX
) {
25643 tcg_gen_smax_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25645 tcg_gen_smin_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25648 /* bytes 2, 1, 0 */
25649 for (i
= 2; i
>= 0; i
--) {
25650 /* extract corresponding bytes */
25651 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0xFF << (8 * i
));
25652 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0xFF << (8 * i
));
25653 /* move the bytes to the leftmost position */
25654 tcg_gen_shli_i32(t0
, t0
, 8 * (3 - i
));
25655 tcg_gen_shli_i32(t1
, t1
, 8 * (3 - i
));
25656 /* t0 will be max/min of t0 and t1 */
25657 if (opc
== OPC_MXU_Q8MAX
) {
25658 tcg_gen_smax_i32(t0
, t0
, t1
);
25660 tcg_gen_smin_i32(t0
, t0
, t1
);
25662 /* return resulting byte to its original position */
25663 tcg_gen_shri_i32(t0
, t0
, 8 * (3 - i
));
25664 /* finaly update the destination */
25665 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRa
- 1], t0
);
25675 * MXU instruction category: align
25676 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25682 * S32ALNI XRc, XRb, XRa, optn3
25683 * Arrange bytes from XRb and XRc according to one of five sets of
25684 * rules determined by optn3, and place the result in XRa.
25686 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25687 * +-----------+-----+---+-----+-------+-------+-------+-----------+
25688 * | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16|
25689 * +-----------+-----+---+-----+-------+-------+-------+-----------+
25692 static void gen_mxu_S32ALNI(DisasContext
*ctx
)
25694 uint32_t optn3
, pad
, XRc
, XRb
, XRa
;
25696 optn3
= extract32(ctx
->opcode
, 23, 3);
25697 pad
= extract32(ctx
->opcode
, 21, 2);
25698 XRc
= extract32(ctx
->opcode
, 14, 4);
25699 XRb
= extract32(ctx
->opcode
, 10, 4);
25700 XRa
= extract32(ctx
->opcode
, 6, 4);
25702 if (unlikely(pad
!= 0)) {
25703 /* opcode padding incorrect -> do nothing */
25704 } else if (unlikely(XRa
== 0)) {
25705 /* destination is zero register -> do nothing */
25706 } else if (unlikely((XRb
== 0) && (XRc
== 0))) {
25707 /* both operands zero registers -> just set destination to all 0s */
25708 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25709 } else if (unlikely(XRb
== 0)) {
25710 /* XRb zero register -> just appropriatelly shift XRc into XRa */
25712 case MXU_OPTN3_PTN0
:
25713 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25715 case MXU_OPTN3_PTN1
:
25716 case MXU_OPTN3_PTN2
:
25717 case MXU_OPTN3_PTN3
:
25718 tcg_gen_shri_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRc
- 1],
25721 case MXU_OPTN3_PTN4
:
25722 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRc
- 1]);
25725 } else if (unlikely(XRc
== 0)) {
25726 /* XRc zero register -> just appropriatelly shift XRb into XRa */
25728 case MXU_OPTN3_PTN0
:
25729 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25731 case MXU_OPTN3_PTN1
:
25732 case MXU_OPTN3_PTN2
:
25733 case MXU_OPTN3_PTN3
:
25734 tcg_gen_shri_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1], 8 * optn3
);
25736 case MXU_OPTN3_PTN4
:
25737 tcg_gen_movi_i32(mxu_gpr
[XRa
- 1], 0);
25740 } else if (unlikely(XRb
== XRc
)) {
25741 /* both operands same -> just rotation or moving from any of them */
25743 case MXU_OPTN3_PTN0
:
25744 case MXU_OPTN3_PTN4
:
25745 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25747 case MXU_OPTN3_PTN1
:
25748 case MXU_OPTN3_PTN2
:
25749 case MXU_OPTN3_PTN3
:
25750 tcg_gen_rotli_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1], 8 * optn3
);
25754 /* the most general case */
25756 case MXU_OPTN3_PTN0
:
25760 /* +---------------+ */
25761 /* | A B C D | E F G H */
25762 /* +-------+-------+ */
25767 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRb
- 1]);
25770 case MXU_OPTN3_PTN1
:
25774 /* +-------------------+ */
25775 /* A | B C D E | F G H */
25776 /* +---------+---------+ */
25781 TCGv_i32 t0
= tcg_temp_new();
25782 TCGv_i32 t1
= tcg_temp_new();
25784 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0x00FFFFFF);
25785 tcg_gen_shli_i32(t0
, t0
, 8);
25787 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0xFF000000);
25788 tcg_gen_shri_i32(t1
, t1
, 24);
25790 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25796 case MXU_OPTN3_PTN2
:
25800 /* +-------------------+ */
25801 /* A B | C D E F | G H */
25802 /* +---------+---------+ */
25807 TCGv_i32 t0
= tcg_temp_new();
25808 TCGv_i32 t1
= tcg_temp_new();
25810 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0x0000FFFF);
25811 tcg_gen_shli_i32(t0
, t0
, 16);
25813 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0xFFFF0000);
25814 tcg_gen_shri_i32(t1
, t1
, 16);
25816 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25822 case MXU_OPTN3_PTN3
:
25826 /* +-------------------+ */
25827 /* A B C | D E F G | H */
25828 /* +---------+---------+ */
25833 TCGv_i32 t0
= tcg_temp_new();
25834 TCGv_i32 t1
= tcg_temp_new();
25836 tcg_gen_andi_i32(t0
, mxu_gpr
[XRb
- 1], 0x000000FF);
25837 tcg_gen_shli_i32(t0
, t0
, 24);
25839 tcg_gen_andi_i32(t1
, mxu_gpr
[XRc
- 1], 0xFFFFFF00);
25840 tcg_gen_shri_i32(t1
, t1
, 8);
25842 tcg_gen_or_i32(mxu_gpr
[XRa
- 1], t0
, t1
);
25848 case MXU_OPTN3_PTN4
:
25852 /* +---------------+ */
25853 /* A B C D | E F G H | */
25854 /* +-------+-------+ */
25859 tcg_gen_mov_i32(mxu_gpr
[XRa
- 1], mxu_gpr
[XRc
- 1]);
25868 * Decoding engine for MXU
25869 * =======================
25874 * Decode MXU pool00
25876 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25877 * +-----------+---------+-----+-------+-------+-------+-----------+
25878 * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL00|
25879 * +-----------+---------+-----+-------+-------+-------+-----------+
25882 static void decode_opc_mxu__pool00(CPUMIPSState
*env
, DisasContext
*ctx
)
25884 uint32_t opcode
= extract32(ctx
->opcode
, 18, 3);
25887 case OPC_MXU_S32MAX
:
25888 case OPC_MXU_S32MIN
:
25889 gen_mxu_S32MAX_S32MIN(ctx
);
25891 case OPC_MXU_D16MAX
:
25892 case OPC_MXU_D16MIN
:
25893 gen_mxu_D16MAX_D16MIN(ctx
);
25895 case OPC_MXU_Q8MAX
:
25896 case OPC_MXU_Q8MIN
:
25897 gen_mxu_Q8MAX_Q8MIN(ctx
);
25899 case OPC_MXU_Q8SLT
:
25900 /* TODO: Implement emulation of Q8SLT instruction. */
25901 MIPS_INVAL("OPC_MXU_Q8SLT");
25902 generate_exception_end(ctx
, EXCP_RI
);
25904 case OPC_MXU_Q8SLTU
:
25905 /* TODO: Implement emulation of Q8SLTU instruction. */
25906 MIPS_INVAL("OPC_MXU_Q8SLTU");
25907 generate_exception_end(ctx
, EXCP_RI
);
25910 MIPS_INVAL("decode_opc_mxu");
25911 generate_exception_end(ctx
, EXCP_RI
);
25918 * Decode MXU pool01
25920 * S32SLT, D16SLT, D16AVG, D16AVGR, Q8AVG, Q8AVGR:
25921 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25922 * +-----------+---------+-----+-------+-------+-------+-----------+
25923 * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01|
25924 * +-----------+---------+-----+-------+-------+-------+-----------+
25927 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25928 * +-----------+---+-----+-----+-------+-------+-------+-----------+
25929 * | SPECIAL2 |en2|0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01|
25930 * +-----------+---+-----+-----+-------+-------+-------+-----------+
25933 static void decode_opc_mxu__pool01(CPUMIPSState
*env
, DisasContext
*ctx
)
25935 uint32_t opcode
= extract32(ctx
->opcode
, 18, 3);
25938 case OPC_MXU_S32SLT
:
25939 /* TODO: Implement emulation of S32SLT instruction. */
25940 MIPS_INVAL("OPC_MXU_S32SLT");
25941 generate_exception_end(ctx
, EXCP_RI
);
25943 case OPC_MXU_D16SLT
:
25944 /* TODO: Implement emulation of D16SLT instruction. */
25945 MIPS_INVAL("OPC_MXU_D16SLT");
25946 generate_exception_end(ctx
, EXCP_RI
);
25948 case OPC_MXU_D16AVG
:
25949 /* TODO: Implement emulation of D16AVG instruction. */
25950 MIPS_INVAL("OPC_MXU_D16AVG");
25951 generate_exception_end(ctx
, EXCP_RI
);
25953 case OPC_MXU_D16AVGR
:
25954 /* TODO: Implement emulation of D16AVGR instruction. */
25955 MIPS_INVAL("OPC_MXU_D16AVGR");
25956 generate_exception_end(ctx
, EXCP_RI
);
25958 case OPC_MXU_Q8AVG
:
25959 /* TODO: Implement emulation of Q8AVG instruction. */
25960 MIPS_INVAL("OPC_MXU_Q8AVG");
25961 generate_exception_end(ctx
, EXCP_RI
);
25963 case OPC_MXU_Q8AVGR
:
25964 /* TODO: Implement emulation of Q8AVGR instruction. */
25965 MIPS_INVAL("OPC_MXU_Q8AVGR");
25966 generate_exception_end(ctx
, EXCP_RI
);
25968 case OPC_MXU_Q8ADD
:
25969 /* TODO: Implement emulation of Q8ADD instruction. */
25970 MIPS_INVAL("OPC_MXU_Q8ADD");
25971 generate_exception_end(ctx
, EXCP_RI
);
25974 MIPS_INVAL("decode_opc_mxu");
25975 generate_exception_end(ctx
, EXCP_RI
);
25982 * Decode MXU pool02
25984 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
25985 * +-----------+---------+-----+-------+-------+-------+-----------+
25986 * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL02|
25987 * +-----------+---------+-----+-------+-------+-------+-----------+
25990 static void decode_opc_mxu__pool02(CPUMIPSState
*env
, DisasContext
*ctx
)
25992 uint32_t opcode
= extract32(ctx
->opcode
, 18, 3);
25995 case OPC_MXU_S32CPS
:
25996 /* TODO: Implement emulation of S32CPS instruction. */
25997 MIPS_INVAL("OPC_MXU_S32CPS");
25998 generate_exception_end(ctx
, EXCP_RI
);
26000 case OPC_MXU_D16CPS
:
26001 /* TODO: Implement emulation of D16CPS instruction. */
26002 MIPS_INVAL("OPC_MXU_D16CPS");
26003 generate_exception_end(ctx
, EXCP_RI
);
26005 case OPC_MXU_Q8ABD
:
26006 /* TODO: Implement emulation of Q8ABD instruction. */
26007 MIPS_INVAL("OPC_MXU_Q8ABD");
26008 generate_exception_end(ctx
, EXCP_RI
);
26010 case OPC_MXU_Q16SAT
:
26011 /* TODO: Implement emulation of Q16SAT instruction. */
26012 MIPS_INVAL("OPC_MXU_Q16SAT");
26013 generate_exception_end(ctx
, EXCP_RI
);
26016 MIPS_INVAL("decode_opc_mxu");
26017 generate_exception_end(ctx
, EXCP_RI
);
26024 * Decode MXU pool03
26027 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26028 * +-----------+---+---+-------+-------+-------+-------+-----------+
26029 * | SPECIAL2 |x x|on2|0 0 0 0| XRc | XRb | XRa |MXU__POOL03|
26030 * +-----------+---+---+-------+-------+-------+-------+-----------+
26033 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26034 * +-----------+---+---+-------+-------+-------+-------+-----------+
26035 * | SPECIAL2 |x x|on2| Xd | XRc | XRb | XRa |MXU__POOL03|
26036 * +-----------+---+---+-------+-------+-------+-------+-----------+
26039 static void decode_opc_mxu__pool03(CPUMIPSState
*env
, DisasContext
*ctx
)
26041 uint32_t opcode
= extract32(ctx
->opcode
, 24, 2);
26044 case OPC_MXU_D16MULF
:
26045 /* TODO: Implement emulation of D16MULF instruction. */
26046 MIPS_INVAL("OPC_MXU_D16MULF");
26047 generate_exception_end(ctx
, EXCP_RI
);
26049 case OPC_MXU_D16MULE
:
26050 /* TODO: Implement emulation of D16MULE instruction. */
26051 MIPS_INVAL("OPC_MXU_D16MULE");
26052 generate_exception_end(ctx
, EXCP_RI
);
26055 MIPS_INVAL("decode_opc_mxu");
26056 generate_exception_end(ctx
, EXCP_RI
);
26063 * Decode MXU pool04
26065 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26066 * +-----------+---------+-+-------------------+-------+-----------+
26067 * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL04|
26068 * +-----------+---------+-+-------------------+-------+-----------+
26071 static void decode_opc_mxu__pool04(CPUMIPSState
*env
, DisasContext
*ctx
)
26073 uint32_t opcode
= extract32(ctx
->opcode
, 20, 1);
26076 case OPC_MXU_S32LDD
:
26077 case OPC_MXU_S32LDDR
:
26078 gen_mxu_s32ldd_s32lddr(ctx
);
26081 MIPS_INVAL("decode_opc_mxu");
26082 generate_exception_end(ctx
, EXCP_RI
);
26089 * Decode MXU pool05
26091 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26092 * +-----------+---------+-+-------------------+-------+-----------+
26093 * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL05|
26094 * +-----------+---------+-+-------------------+-------+-----------+
26097 static void decode_opc_mxu__pool05(CPUMIPSState
*env
, DisasContext
*ctx
)
26099 uint32_t opcode
= extract32(ctx
->opcode
, 20, 1);
26102 case OPC_MXU_S32STD
:
26103 /* TODO: Implement emulation of S32STD instruction. */
26104 MIPS_INVAL("OPC_MXU_S32STD");
26105 generate_exception_end(ctx
, EXCP_RI
);
26107 case OPC_MXU_S32STDR
:
26108 /* TODO: Implement emulation of S32STDR instruction. */
26109 MIPS_INVAL("OPC_MXU_S32STDR");
26110 generate_exception_end(ctx
, EXCP_RI
);
26113 MIPS_INVAL("decode_opc_mxu");
26114 generate_exception_end(ctx
, EXCP_RI
);
26121 * Decode MXU pool06
26123 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26124 * +-----------+---------+---------+---+-------+-------+-----------+
26125 * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL06|
26126 * +-----------+---------+---------+---+-------+-------+-----------+
26129 static void decode_opc_mxu__pool06(CPUMIPSState
*env
, DisasContext
*ctx
)
26131 uint32_t opcode
= extract32(ctx
->opcode
, 10, 4);
26134 case OPC_MXU_S32LDDV
:
26135 /* TODO: Implement emulation of S32LDDV instruction. */
26136 MIPS_INVAL("OPC_MXU_S32LDDV");
26137 generate_exception_end(ctx
, EXCP_RI
);
26139 case OPC_MXU_S32LDDVR
:
26140 /* TODO: Implement emulation of S32LDDVR instruction. */
26141 MIPS_INVAL("OPC_MXU_S32LDDVR");
26142 generate_exception_end(ctx
, EXCP_RI
);
26145 MIPS_INVAL("decode_opc_mxu");
26146 generate_exception_end(ctx
, EXCP_RI
);
26153 * Decode MXU pool07
26155 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26156 * +-----------+---------+---------+---+-------+-------+-----------+
26157 * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL07|
26158 * +-----------+---------+---------+---+-------+-------+-----------+
26161 static void decode_opc_mxu__pool07(CPUMIPSState
*env
, DisasContext
*ctx
)
26163 uint32_t opcode
= extract32(ctx
->opcode
, 10, 4);
26166 case OPC_MXU_S32STDV
:
26167 /* TODO: Implement emulation of S32TDV instruction. */
26168 MIPS_INVAL("OPC_MXU_S32TDV");
26169 generate_exception_end(ctx
, EXCP_RI
);
26171 case OPC_MXU_S32STDVR
:
26172 /* TODO: Implement emulation of S32TDVR instruction. */
26173 MIPS_INVAL("OPC_MXU_S32TDVR");
26174 generate_exception_end(ctx
, EXCP_RI
);
26177 MIPS_INVAL("decode_opc_mxu");
26178 generate_exception_end(ctx
, EXCP_RI
);
26185 * Decode MXU pool08
26187 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26188 * +-----------+---------+-+-------------------+-------+-----------+
26189 * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL08|
26190 * +-----------+---------+-+-------------------+-------+-----------+
26193 static void decode_opc_mxu__pool08(CPUMIPSState
*env
, DisasContext
*ctx
)
26195 uint32_t opcode
= extract32(ctx
->opcode
, 20, 1);
26198 case OPC_MXU_S32LDI
:
26199 /* TODO: Implement emulation of S32LDI instruction. */
26200 MIPS_INVAL("OPC_MXU_S32LDI");
26201 generate_exception_end(ctx
, EXCP_RI
);
26203 case OPC_MXU_S32LDIR
:
26204 /* TODO: Implement emulation of S32LDIR instruction. */
26205 MIPS_INVAL("OPC_MXU_S32LDIR");
26206 generate_exception_end(ctx
, EXCP_RI
);
26209 MIPS_INVAL("decode_opc_mxu");
26210 generate_exception_end(ctx
, EXCP_RI
);
26217 * Decode MXU pool09
26219 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26220 * +-----------+---------+-+-------------------+-------+-----------+
26221 * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL09|
26222 * +-----------+---------+-+-------------------+-------+-----------+
26225 static void decode_opc_mxu__pool09(CPUMIPSState
*env
, DisasContext
*ctx
)
26227 uint32_t opcode
= extract32(ctx
->opcode
, 5, 0);
26230 case OPC_MXU_S32SDI
:
26231 /* TODO: Implement emulation of S32SDI instruction. */
26232 MIPS_INVAL("OPC_MXU_S32SDI");
26233 generate_exception_end(ctx
, EXCP_RI
);
26235 case OPC_MXU_S32SDIR
:
26236 /* TODO: Implement emulation of S32SDIR instruction. */
26237 MIPS_INVAL("OPC_MXU_S32SDIR");
26238 generate_exception_end(ctx
, EXCP_RI
);
26241 MIPS_INVAL("decode_opc_mxu");
26242 generate_exception_end(ctx
, EXCP_RI
);
26249 * Decode MXU pool10
26251 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26252 * +-----------+---------+---------+---+-------+-------+-----------+
26253 * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL10|
26254 * +-----------+---------+---------+---+-------+-------+-----------+
26257 static void decode_opc_mxu__pool10(CPUMIPSState
*env
, DisasContext
*ctx
)
26259 uint32_t opcode
= extract32(ctx
->opcode
, 5, 0);
26262 case OPC_MXU_S32LDIV
:
26263 /* TODO: Implement emulation of S32LDIV instruction. */
26264 MIPS_INVAL("OPC_MXU_S32LDIV");
26265 generate_exception_end(ctx
, EXCP_RI
);
26267 case OPC_MXU_S32LDIVR
:
26268 /* TODO: Implement emulation of S32LDIVR instruction. */
26269 MIPS_INVAL("OPC_MXU_S32LDIVR");
26270 generate_exception_end(ctx
, EXCP_RI
);
26273 MIPS_INVAL("decode_opc_mxu");
26274 generate_exception_end(ctx
, EXCP_RI
);
26281 * Decode MXU pool11
26283 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26284 * +-----------+---------+---------+---+-------+-------+-----------+
26285 * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL11|
26286 * +-----------+---------+---------+---+-------+-------+-----------+
26289 static void decode_opc_mxu__pool11(CPUMIPSState
*env
, DisasContext
*ctx
)
26291 uint32_t opcode
= extract32(ctx
->opcode
, 10, 4);
26294 case OPC_MXU_S32SDIV
:
26295 /* TODO: Implement emulation of S32SDIV instruction. */
26296 MIPS_INVAL("OPC_MXU_S32SDIV");
26297 generate_exception_end(ctx
, EXCP_RI
);
26299 case OPC_MXU_S32SDIVR
:
26300 /* TODO: Implement emulation of S32SDIVR instruction. */
26301 MIPS_INVAL("OPC_MXU_S32SDIVR");
26302 generate_exception_end(ctx
, EXCP_RI
);
26305 MIPS_INVAL("decode_opc_mxu");
26306 generate_exception_end(ctx
, EXCP_RI
);
26313 * Decode MXU pool12
26315 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26316 * +-----------+---+---+-------+-------+-------+-------+-----------+
26317 * | SPECIAL2 |an2|x x| Xd | XRc | XRb | XRa |MXU__POOL12|
26318 * +-----------+---+---+-------+-------+-------+-------+-----------+
26321 static void decode_opc_mxu__pool12(CPUMIPSState
*env
, DisasContext
*ctx
)
26323 uint32_t opcode
= extract32(ctx
->opcode
, 22, 2);
26326 case OPC_MXU_D32ACC
:
26327 /* TODO: Implement emulation of D32ACC instruction. */
26328 MIPS_INVAL("OPC_MXU_D32ACC");
26329 generate_exception_end(ctx
, EXCP_RI
);
26331 case OPC_MXU_D32ACCM
:
26332 /* TODO: Implement emulation of D32ACCM instruction. */
26333 MIPS_INVAL("OPC_MXU_D32ACCM");
26334 generate_exception_end(ctx
, EXCP_RI
);
26336 case OPC_MXU_D32ASUM
:
26337 /* TODO: Implement emulation of D32ASUM instruction. */
26338 MIPS_INVAL("OPC_MXU_D32ASUM");
26339 generate_exception_end(ctx
, EXCP_RI
);
26342 MIPS_INVAL("decode_opc_mxu");
26343 generate_exception_end(ctx
, EXCP_RI
);
26350 * Decode MXU pool13
26352 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26353 * +-----------+---+---+-------+-------+-------+-------+-----------+
26354 * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL13|
26355 * +-----------+---+---+-------+-------+-------+-------+-----------+
26358 static void decode_opc_mxu__pool13(CPUMIPSState
*env
, DisasContext
*ctx
)
26360 uint32_t opcode
= extract32(ctx
->opcode
, 22, 2);
26363 case OPC_MXU_Q16ACC
:
26364 /* TODO: Implement emulation of Q16ACC instruction. */
26365 MIPS_INVAL("OPC_MXU_Q16ACC");
26366 generate_exception_end(ctx
, EXCP_RI
);
26368 case OPC_MXU_Q16ACCM
:
26369 /* TODO: Implement emulation of Q16ACCM instruction. */
26370 MIPS_INVAL("OPC_MXU_Q16ACCM");
26371 generate_exception_end(ctx
, EXCP_RI
);
26373 case OPC_MXU_Q16ASUM
:
26374 /* TODO: Implement emulation of Q16ASUM instruction. */
26375 MIPS_INVAL("OPC_MXU_Q16ASUM");
26376 generate_exception_end(ctx
, EXCP_RI
);
26379 MIPS_INVAL("decode_opc_mxu");
26380 generate_exception_end(ctx
, EXCP_RI
);
26387 * Decode MXU pool14
26390 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26391 * +-----------+---+---+-------+-------+-------+-------+-----------+
26392 * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL14|
26393 * +-----------+---+---+-------+-------+-------+-------+-----------+
26396 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26397 * +-----------+---+---+-------+-------+-------+-------+-----------+
26398 * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL14|
26399 * +-----------+---+---+-------+-------+-------+-------+-----------+
26402 static void decode_opc_mxu__pool14(CPUMIPSState
*env
, DisasContext
*ctx
)
26404 uint32_t opcode
= extract32(ctx
->opcode
, 22, 2);
26407 case OPC_MXU_Q8ADDE
:
26408 /* TODO: Implement emulation of Q8ADDE instruction. */
26409 MIPS_INVAL("OPC_MXU_Q8ADDE");
26410 generate_exception_end(ctx
, EXCP_RI
);
26412 case OPC_MXU_D8SUM
:
26413 /* TODO: Implement emulation of D8SUM instruction. */
26414 MIPS_INVAL("OPC_MXU_D8SUM");
26415 generate_exception_end(ctx
, EXCP_RI
);
26417 case OPC_MXU_D8SUMC
:
26418 /* TODO: Implement emulation of D8SUMC instruction. */
26419 MIPS_INVAL("OPC_MXU_D8SUMC");
26420 generate_exception_end(ctx
, EXCP_RI
);
26423 MIPS_INVAL("decode_opc_mxu");
26424 generate_exception_end(ctx
, EXCP_RI
);
26431 * Decode MXU pool15
26433 * S32MUL, S32MULU, S32EXTRV:
26434 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26435 * +-----------+---------+---------+---+-------+-------+-----------+
26436 * | SPECIAL2 | rs | rt |x x| XRd | XRa |MXU__POOL15|
26437 * +-----------+---------+---------+---+-------+-------+-----------+
26440 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26441 * +-----------+---------+---------+---+-------+-------+-----------+
26442 * | SPECIAL2 | rb | sft5 |x x| XRd | XRa |MXU__POOL15|
26443 * +-----------+---------+---------+---+-------+-------+-----------+
26446 static void decode_opc_mxu__pool15(CPUMIPSState
*env
, DisasContext
*ctx
)
26448 uint32_t opcode
= extract32(ctx
->opcode
, 14, 2);
26451 case OPC_MXU_S32MUL
:
26452 /* TODO: Implement emulation of S32MUL instruction. */
26453 MIPS_INVAL("OPC_MXU_S32MUL");
26454 generate_exception_end(ctx
, EXCP_RI
);
26456 case OPC_MXU_S32MULU
:
26457 /* TODO: Implement emulation of S32MULU instruction. */
26458 MIPS_INVAL("OPC_MXU_S32MULU");
26459 generate_exception_end(ctx
, EXCP_RI
);
26461 case OPC_MXU_S32EXTR
:
26462 /* TODO: Implement emulation of S32EXTR instruction. */
26463 MIPS_INVAL("OPC_MXU_S32EXTR");
26464 generate_exception_end(ctx
, EXCP_RI
);
26466 case OPC_MXU_S32EXTRV
:
26467 /* TODO: Implement emulation of S32EXTRV instruction. */
26468 MIPS_INVAL("OPC_MXU_S32EXTRV");
26469 generate_exception_end(ctx
, EXCP_RI
);
26472 MIPS_INVAL("decode_opc_mxu");
26473 generate_exception_end(ctx
, EXCP_RI
);
26480 * Decode MXU pool16
26483 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26484 * +-----------+---------+-----+-------+-------+-------+-----------+
26485 * | SPECIAL2 | rb |x x x| XRc | XRb | XRa |MXU__POOL16|
26486 * +-----------+---------+-----+-------+-------+-------+-----------+
26489 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26490 * +-----------+---------+-----+-------+-------+-------+-----------+
26491 * | SPECIAL2 | rs |x x x| XRc | XRb | XRa |MXU__POOL16|
26492 * +-----------+---------+-----+-------+-------+-------+-----------+
26495 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26496 * +-----------+-----+---+-----+-------+-------+-------+-----------+
26497 * | SPECIAL2 | s3 |0 0|x x x| XRc | XRb | XRa |MXU__POOL16|
26498 * +-----------+-----+---+-----+-------+-------+-------+-----------+
26501 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26502 * +-----------+-----+---+-----+-------+---------------+-----------+
26503 * | SPECIAL2 |optn3|0 0|x x x| XRc | s8 |MXU__POOL16|
26504 * +-----------+-----+---+-----+-------+---------------+-----------+
26506 * S32NOR, S32AND, S32OR, S32XOR:
26507 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26508 * +-----------+---------+-----+-------+-------+-------+-----------+
26509 * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL16|
26510 * +-----------+---------+-----+-------+-------+-------+-----------+
26513 static void decode_opc_mxu__pool16(CPUMIPSState
*env
, DisasContext
*ctx
)
26515 uint32_t opcode
= extract32(ctx
->opcode
, 18, 3);
26518 case OPC_MXU_D32SARW
:
26519 /* TODO: Implement emulation of D32SARW instruction. */
26520 MIPS_INVAL("OPC_MXU_D32SARW");
26521 generate_exception_end(ctx
, EXCP_RI
);
26523 case OPC_MXU_S32ALN
:
26524 /* TODO: Implement emulation of S32ALN instruction. */
26525 MIPS_INVAL("OPC_MXU_S32ALN");
26526 generate_exception_end(ctx
, EXCP_RI
);
26528 case OPC_MXU_S32ALNI
:
26529 gen_mxu_S32ALNI(ctx
);
26531 case OPC_MXU_S32LUI
:
26532 /* TODO: Implement emulation of S32LUI instruction. */
26533 MIPS_INVAL("OPC_MXU_S32LUI");
26534 generate_exception_end(ctx
, EXCP_RI
);
26536 case OPC_MXU_S32NOR
:
26537 gen_mxu_S32NOR(ctx
);
26539 case OPC_MXU_S32AND
:
26540 gen_mxu_S32AND(ctx
);
26542 case OPC_MXU_S32OR
:
26543 gen_mxu_S32OR(ctx
);
26545 case OPC_MXU_S32XOR
:
26546 gen_mxu_S32XOR(ctx
);
26549 MIPS_INVAL("decode_opc_mxu");
26550 generate_exception_end(ctx
, EXCP_RI
);
26557 * Decode MXU pool17
26559 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26560 * +-----------+---------+---------+---+---------+-----+-----------+
26561 * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15|
26562 * +-----------+---------+---------+---+---------+-----+-----------+
26565 static void decode_opc_mxu__pool17(CPUMIPSState
*env
, DisasContext
*ctx
)
26567 uint32_t opcode
= extract32(ctx
->opcode
, 6, 2);
26571 /* TODO: Implement emulation of LXW instruction. */
26572 MIPS_INVAL("OPC_MXU_LXW");
26573 generate_exception_end(ctx
, EXCP_RI
);
26576 /* TODO: Implement emulation of LXH instruction. */
26577 MIPS_INVAL("OPC_MXU_LXH");
26578 generate_exception_end(ctx
, EXCP_RI
);
26581 /* TODO: Implement emulation of LXHU instruction. */
26582 MIPS_INVAL("OPC_MXU_LXHU");
26583 generate_exception_end(ctx
, EXCP_RI
);
26586 /* TODO: Implement emulation of LXB instruction. */
26587 MIPS_INVAL("OPC_MXU_LXB");
26588 generate_exception_end(ctx
, EXCP_RI
);
26591 /* TODO: Implement emulation of LXBU instruction. */
26592 MIPS_INVAL("OPC_MXU_LXBU");
26593 generate_exception_end(ctx
, EXCP_RI
);
26596 MIPS_INVAL("decode_opc_mxu");
26597 generate_exception_end(ctx
, EXCP_RI
);
26603 * Decode MXU pool18
26605 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26606 * +-----------+---------+-----+-------+-------+-------+-----------+
26607 * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18|
26608 * +-----------+---------+-----+-------+-------+-------+-----------+
26611 static void decode_opc_mxu__pool18(CPUMIPSState
*env
, DisasContext
*ctx
)
26613 uint32_t opcode
= extract32(ctx
->opcode
, 18, 3);
26616 case OPC_MXU_D32SLLV
:
26617 /* TODO: Implement emulation of D32SLLV instruction. */
26618 MIPS_INVAL("OPC_MXU_D32SLLV");
26619 generate_exception_end(ctx
, EXCP_RI
);
26621 case OPC_MXU_D32SLRV
:
26622 /* TODO: Implement emulation of D32SLRV instruction. */
26623 MIPS_INVAL("OPC_MXU_D32SLRV");
26624 generate_exception_end(ctx
, EXCP_RI
);
26626 case OPC_MXU_D32SARV
:
26627 /* TODO: Implement emulation of D32SARV instruction. */
26628 MIPS_INVAL("OPC_MXU_D32SARV");
26629 generate_exception_end(ctx
, EXCP_RI
);
26631 case OPC_MXU_Q16SLLV
:
26632 /* TODO: Implement emulation of Q16SLLV instruction. */
26633 MIPS_INVAL("OPC_MXU_Q16SLLV");
26634 generate_exception_end(ctx
, EXCP_RI
);
26636 case OPC_MXU_Q16SLRV
:
26637 /* TODO: Implement emulation of Q16SLRV instruction. */
26638 MIPS_INVAL("OPC_MXU_Q16SLRV");
26639 generate_exception_end(ctx
, EXCP_RI
);
26641 case OPC_MXU_Q16SARV
:
26642 /* TODO: Implement emulation of Q16SARV instruction. */
26643 MIPS_INVAL("OPC_MXU_Q16SARV");
26644 generate_exception_end(ctx
, EXCP_RI
);
26647 MIPS_INVAL("decode_opc_mxu");
26648 generate_exception_end(ctx
, EXCP_RI
);
26655 * Decode MXU pool19
26657 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26658 * +-----------+---+---+-------+-------+-------+-------+-----------+
26659 * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19|
26660 * +-----------+---+---+-------+-------+-------+-------+-----------+
26663 static void decode_opc_mxu__pool19(CPUMIPSState
*env
, DisasContext
*ctx
)
26665 uint32_t opcode
= extract32(ctx
->opcode
, 22, 2);
26668 case OPC_MXU_Q8MUL
:
26669 case OPC_MXU_Q8MULSU
:
26670 gen_mxu_q8mul_q8mulsu(ctx
);
26673 MIPS_INVAL("decode_opc_mxu");
26674 generate_exception_end(ctx
, EXCP_RI
);
26681 * Decode MXU pool20
26683 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26684 * +-----------+---------+-----+-------+-------+-------+-----------+
26685 * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20|
26686 * +-----------+---------+-----+-------+-------+-------+-----------+
26689 static void decode_opc_mxu__pool20(CPUMIPSState
*env
, DisasContext
*ctx
)
26691 uint32_t opcode
= extract32(ctx
->opcode
, 18, 3);
26694 case OPC_MXU_Q8MOVZ
:
26695 /* TODO: Implement emulation of Q8MOVZ instruction. */
26696 MIPS_INVAL("OPC_MXU_Q8MOVZ");
26697 generate_exception_end(ctx
, EXCP_RI
);
26699 case OPC_MXU_Q8MOVN
:
26700 /* TODO: Implement emulation of Q8MOVN instruction. */
26701 MIPS_INVAL("OPC_MXU_Q8MOVN");
26702 generate_exception_end(ctx
, EXCP_RI
);
26704 case OPC_MXU_D16MOVZ
:
26705 /* TODO: Implement emulation of D16MOVZ instruction. */
26706 MIPS_INVAL("OPC_MXU_D16MOVZ");
26707 generate_exception_end(ctx
, EXCP_RI
);
26709 case OPC_MXU_D16MOVN
:
26710 /* TODO: Implement emulation of D16MOVN instruction. */
26711 MIPS_INVAL("OPC_MXU_D16MOVN");
26712 generate_exception_end(ctx
, EXCP_RI
);
26714 case OPC_MXU_S32MOVZ
:
26715 /* TODO: Implement emulation of S32MOVZ instruction. */
26716 MIPS_INVAL("OPC_MXU_S32MOVZ");
26717 generate_exception_end(ctx
, EXCP_RI
);
26719 case OPC_MXU_S32MOVN
:
26720 /* TODO: Implement emulation of S32MOVN instruction. */
26721 MIPS_INVAL("OPC_MXU_S32MOVN");
26722 generate_exception_end(ctx
, EXCP_RI
);
26725 MIPS_INVAL("decode_opc_mxu");
26726 generate_exception_end(ctx
, EXCP_RI
);
26733 * Decode MXU pool21
26735 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26736 * +-----------+---+---+-------+-------+-------+-------+-----------+
26737 * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21|
26738 * +-----------+---+---+-------+-------+-------+-------+-----------+
26741 static void decode_opc_mxu__pool21(CPUMIPSState
*env
, DisasContext
*ctx
)
26743 uint32_t opcode
= extract32(ctx
->opcode
, 22, 2);
26746 case OPC_MXU_Q8MAC
:
26747 /* TODO: Implement emulation of Q8MAC instruction. */
26748 MIPS_INVAL("OPC_MXU_Q8MAC");
26749 generate_exception_end(ctx
, EXCP_RI
);
26751 case OPC_MXU_Q8MACSU
:
26752 /* TODO: Implement emulation of Q8MACSU instruction. */
26753 MIPS_INVAL("OPC_MXU_Q8MACSU");
26754 generate_exception_end(ctx
, EXCP_RI
);
26757 MIPS_INVAL("decode_opc_mxu");
26758 generate_exception_end(ctx
, EXCP_RI
);
26765 * Main MXU decoding function
26767 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
26768 * +-----------+---------------------------------------+-----------+
26769 * | SPECIAL2 | |x x x x x x|
26770 * +-----------+---------------------------------------+-----------+
26773 static void decode_opc_mxu(CPUMIPSState
*env
, DisasContext
*ctx
)
26776 * TODO: Investigate necessity of including handling of
26777 * CLZ, CLO, SDBB in this function, as they belong to
26778 * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
26780 uint32_t opcode
= extract32(ctx
->opcode
, 0, 6);
26782 if (opcode
== OPC__MXU_MUL
) {
26783 uint32_t rs
, rt
, rd
, op1
;
26785 rs
= extract32(ctx
->opcode
, 21, 5);
26786 rt
= extract32(ctx
->opcode
, 16, 5);
26787 rd
= extract32(ctx
->opcode
, 11, 5);
26788 op1
= MASK_SPECIAL2(ctx
->opcode
);
26790 gen_arith(ctx
, op1
, rd
, rs
, rt
);
26795 if (opcode
== OPC_MXU_S32M2I
) {
26796 gen_mxu_s32m2i(ctx
);
26800 if (opcode
== OPC_MXU_S32I2M
) {
26801 gen_mxu_s32i2m(ctx
);
26806 TCGv t_mxu_cr
= tcg_temp_new();
26807 TCGLabel
*l_exit
= gen_new_label();
26809 gen_load_mxu_cr(t_mxu_cr
);
26810 tcg_gen_andi_tl(t_mxu_cr
, t_mxu_cr
, MXU_CR_MXU_EN
);
26811 tcg_gen_brcondi_tl(TCG_COND_NE
, t_mxu_cr
, MXU_CR_MXU_EN
, l_exit
);
26814 case OPC_MXU_S32MADD
:
26815 /* TODO: Implement emulation of S32MADD instruction. */
26816 MIPS_INVAL("OPC_MXU_S32MADD");
26817 generate_exception_end(ctx
, EXCP_RI
);
26819 case OPC_MXU_S32MADDU
:
26820 /* TODO: Implement emulation of S32MADDU instruction. */
26821 MIPS_INVAL("OPC_MXU_S32MADDU");
26822 generate_exception_end(ctx
, EXCP_RI
);
26824 case OPC_MXU__POOL00
:
26825 decode_opc_mxu__pool00(env
, ctx
);
26827 case OPC_MXU_S32MSUB
:
26828 /* TODO: Implement emulation of S32MSUB instruction. */
26829 MIPS_INVAL("OPC_MXU_S32MSUB");
26830 generate_exception_end(ctx
, EXCP_RI
);
26832 case OPC_MXU_S32MSUBU
:
26833 /* TODO: Implement emulation of S32MSUBU instruction. */
26834 MIPS_INVAL("OPC_MXU_S32MSUBU");
26835 generate_exception_end(ctx
, EXCP_RI
);
26837 case OPC_MXU__POOL01
:
26838 decode_opc_mxu__pool01(env
, ctx
);
26840 case OPC_MXU__POOL02
:
26841 decode_opc_mxu__pool02(env
, ctx
);
26843 case OPC_MXU_D16MUL
:
26844 gen_mxu_d16mul(ctx
);
26846 case OPC_MXU__POOL03
:
26847 decode_opc_mxu__pool03(env
, ctx
);
26849 case OPC_MXU_D16MAC
:
26850 gen_mxu_d16mac(ctx
);
26852 case OPC_MXU_D16MACF
:
26853 /* TODO: Implement emulation of D16MACF instruction. */
26854 MIPS_INVAL("OPC_MXU_D16MACF");
26855 generate_exception_end(ctx
, EXCP_RI
);
26857 case OPC_MXU_D16MADL
:
26858 /* TODO: Implement emulation of D16MADL instruction. */
26859 MIPS_INVAL("OPC_MXU_D16MADL");
26860 generate_exception_end(ctx
, EXCP_RI
);
26862 case OPC_MXU_S16MAD
:
26863 /* TODO: Implement emulation of S16MAD instruction. */
26864 MIPS_INVAL("OPC_MXU_S16MAD");
26865 generate_exception_end(ctx
, EXCP_RI
);
26867 case OPC_MXU_Q16ADD
:
26868 /* TODO: Implement emulation of Q16ADD instruction. */
26869 MIPS_INVAL("OPC_MXU_Q16ADD");
26870 generate_exception_end(ctx
, EXCP_RI
);
26872 case OPC_MXU_D16MACE
:
26873 /* TODO: Implement emulation of D16MACE instruction. */
26874 MIPS_INVAL("OPC_MXU_D16MACE");
26875 generate_exception_end(ctx
, EXCP_RI
);
26877 case OPC_MXU__POOL04
:
26878 decode_opc_mxu__pool04(env
, ctx
);
26880 case OPC_MXU__POOL05
:
26881 decode_opc_mxu__pool05(env
, ctx
);
26883 case OPC_MXU__POOL06
:
26884 decode_opc_mxu__pool06(env
, ctx
);
26886 case OPC_MXU__POOL07
:
26887 decode_opc_mxu__pool07(env
, ctx
);
26889 case OPC_MXU__POOL08
:
26890 decode_opc_mxu__pool08(env
, ctx
);
26892 case OPC_MXU__POOL09
:
26893 decode_opc_mxu__pool09(env
, ctx
);
26895 case OPC_MXU__POOL10
:
26896 decode_opc_mxu__pool10(env
, ctx
);
26898 case OPC_MXU__POOL11
:
26899 decode_opc_mxu__pool11(env
, ctx
);
26901 case OPC_MXU_D32ADD
:
26902 /* TODO: Implement emulation of D32ADD instruction. */
26903 MIPS_INVAL("OPC_MXU_D32ADD");
26904 generate_exception_end(ctx
, EXCP_RI
);
26906 case OPC_MXU__POOL12
:
26907 decode_opc_mxu__pool12(env
, ctx
);
26909 case OPC_MXU__POOL13
:
26910 decode_opc_mxu__pool13(env
, ctx
);
26912 case OPC_MXU__POOL14
:
26913 decode_opc_mxu__pool14(env
, ctx
);
26915 case OPC_MXU_Q8ACCE
:
26916 /* TODO: Implement emulation of Q8ACCE instruction. */
26917 MIPS_INVAL("OPC_MXU_Q8ACCE");
26918 generate_exception_end(ctx
, EXCP_RI
);
26920 case OPC_MXU_S8LDD
:
26921 gen_mxu_s8ldd(ctx
);
26923 case OPC_MXU_S8STD
:
26924 /* TODO: Implement emulation of S8STD instruction. */
26925 MIPS_INVAL("OPC_MXU_S8STD");
26926 generate_exception_end(ctx
, EXCP_RI
);
26928 case OPC_MXU_S8LDI
:
26929 /* TODO: Implement emulation of S8LDI instruction. */
26930 MIPS_INVAL("OPC_MXU_S8LDI");
26931 generate_exception_end(ctx
, EXCP_RI
);
26933 case OPC_MXU_S8SDI
:
26934 /* TODO: Implement emulation of S8SDI instruction. */
26935 MIPS_INVAL("OPC_MXU_S8SDI");
26936 generate_exception_end(ctx
, EXCP_RI
);
26938 case OPC_MXU__POOL15
:
26939 decode_opc_mxu__pool15(env
, ctx
);
26941 case OPC_MXU__POOL16
:
26942 decode_opc_mxu__pool16(env
, ctx
);
26944 case OPC_MXU__POOL17
:
26945 decode_opc_mxu__pool17(env
, ctx
);
26947 case OPC_MXU_S16LDD
:
26948 /* TODO: Implement emulation of S16LDD instruction. */
26949 MIPS_INVAL("OPC_MXU_S16LDD");
26950 generate_exception_end(ctx
, EXCP_RI
);
26952 case OPC_MXU_S16STD
:
26953 /* TODO: Implement emulation of S16STD instruction. */
26954 MIPS_INVAL("OPC_MXU_S16STD");
26955 generate_exception_end(ctx
, EXCP_RI
);
26957 case OPC_MXU_S16LDI
:
26958 /* TODO: Implement emulation of S16LDI instruction. */
26959 MIPS_INVAL("OPC_MXU_S16LDI");
26960 generate_exception_end(ctx
, EXCP_RI
);
26962 case OPC_MXU_S16SDI
:
26963 /* TODO: Implement emulation of S16SDI instruction. */
26964 MIPS_INVAL("OPC_MXU_S16SDI");
26965 generate_exception_end(ctx
, EXCP_RI
);
26967 case OPC_MXU_D32SLL
:
26968 /* TODO: Implement emulation of D32SLL instruction. */
26969 MIPS_INVAL("OPC_MXU_D32SLL");
26970 generate_exception_end(ctx
, EXCP_RI
);
26972 case OPC_MXU_D32SLR
:
26973 /* TODO: Implement emulation of D32SLR instruction. */
26974 MIPS_INVAL("OPC_MXU_D32SLR");
26975 generate_exception_end(ctx
, EXCP_RI
);
26977 case OPC_MXU_D32SARL
:
26978 /* TODO: Implement emulation of D32SARL instruction. */
26979 MIPS_INVAL("OPC_MXU_D32SARL");
26980 generate_exception_end(ctx
, EXCP_RI
);
26982 case OPC_MXU_D32SAR
:
26983 /* TODO: Implement emulation of D32SAR instruction. */
26984 MIPS_INVAL("OPC_MXU_D32SAR");
26985 generate_exception_end(ctx
, EXCP_RI
);
26987 case OPC_MXU_Q16SLL
:
26988 /* TODO: Implement emulation of Q16SLL instruction. */
26989 MIPS_INVAL("OPC_MXU_Q16SLL");
26990 generate_exception_end(ctx
, EXCP_RI
);
26992 case OPC_MXU_Q16SLR
:
26993 /* TODO: Implement emulation of Q16SLR instruction. */
26994 MIPS_INVAL("OPC_MXU_Q16SLR");
26995 generate_exception_end(ctx
, EXCP_RI
);
26997 case OPC_MXU__POOL18
:
26998 decode_opc_mxu__pool18(env
, ctx
);
27000 case OPC_MXU_Q16SAR
:
27001 /* TODO: Implement emulation of Q16SAR instruction. */
27002 MIPS_INVAL("OPC_MXU_Q16SAR");
27003 generate_exception_end(ctx
, EXCP_RI
);
27005 case OPC_MXU__POOL19
:
27006 decode_opc_mxu__pool19(env
, ctx
);
27008 case OPC_MXU__POOL20
:
27009 decode_opc_mxu__pool20(env
, ctx
);
27011 case OPC_MXU__POOL21
:
27012 decode_opc_mxu__pool21(env
, ctx
);
27014 case OPC_MXU_Q16SCOP
:
27015 /* TODO: Implement emulation of Q16SCOP instruction. */
27016 MIPS_INVAL("OPC_MXU_Q16SCOP");
27017 generate_exception_end(ctx
, EXCP_RI
);
27019 case OPC_MXU_Q8MADL
:
27020 /* TODO: Implement emulation of Q8MADL instruction. */
27021 MIPS_INVAL("OPC_MXU_Q8MADL");
27022 generate_exception_end(ctx
, EXCP_RI
);
27024 case OPC_MXU_S32SFL
:
27025 /* TODO: Implement emulation of S32SFL instruction. */
27026 MIPS_INVAL("OPC_MXU_S32SFL");
27027 generate_exception_end(ctx
, EXCP_RI
);
27029 case OPC_MXU_Q8SAD
:
27030 /* TODO: Implement emulation of Q8SAD instruction. */
27031 MIPS_INVAL("OPC_MXU_Q8SAD");
27032 generate_exception_end(ctx
, EXCP_RI
);
27035 MIPS_INVAL("decode_opc_mxu");
27036 generate_exception_end(ctx
, EXCP_RI
);
27039 gen_set_label(l_exit
);
27040 tcg_temp_free(t_mxu_cr
);
27044 #endif /* !defined(TARGET_MIPS64) */
27047 static void decode_opc_special2_legacy(CPUMIPSState
*env
, DisasContext
*ctx
)
27052 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
27054 rs
= (ctx
->opcode
>> 21) & 0x1f;
27055 rt
= (ctx
->opcode
>> 16) & 0x1f;
27056 rd
= (ctx
->opcode
>> 11) & 0x1f;
27058 op1
= MASK_SPECIAL2(ctx
->opcode
);
27060 case OPC_MADD
: /* Multiply and add/sub */
27064 check_insn(ctx
, ISA_MIPS32
);
27065 gen_muldiv(ctx
, op1
, rd
& 3, rs
, rt
);
27068 gen_arith(ctx
, op1
, rd
, rs
, rt
);
27071 case OPC_DIVU_G_2F
:
27072 case OPC_MULT_G_2F
:
27073 case OPC_MULTU_G_2F
:
27075 case OPC_MODU_G_2F
:
27076 check_insn(ctx
, INSN_LOONGSON2F
);
27077 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
27081 check_insn(ctx
, ISA_MIPS32
);
27082 gen_cl(ctx
, op1
, rd
, rs
);
27085 if (is_uhi(extract32(ctx
->opcode
, 6, 20))) {
27086 gen_helper_do_semihosting(cpu_env
);
27089 * XXX: not clear which exception should be raised
27090 * when in debug mode...
27092 check_insn(ctx
, ISA_MIPS32
);
27093 generate_exception_end(ctx
, EXCP_DBp
);
27096 #if defined(TARGET_MIPS64)
27099 check_insn(ctx
, ISA_MIPS64
);
27100 check_mips_64(ctx
);
27101 gen_cl(ctx
, op1
, rd
, rs
);
27103 case OPC_DMULT_G_2F
:
27104 case OPC_DMULTU_G_2F
:
27105 case OPC_DDIV_G_2F
:
27106 case OPC_DDIVU_G_2F
:
27107 case OPC_DMOD_G_2F
:
27108 case OPC_DMODU_G_2F
:
27109 check_insn(ctx
, INSN_LOONGSON2F
);
27110 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
27113 default: /* Invalid */
27114 MIPS_INVAL("special2_legacy");
27115 generate_exception_end(ctx
, EXCP_RI
);
27120 static void decode_opc_special3_r6(CPUMIPSState
*env
, DisasContext
*ctx
)
27122 int rs
, rt
, rd
, sa
;
27126 rs
= (ctx
->opcode
>> 21) & 0x1f;
27127 rt
= (ctx
->opcode
>> 16) & 0x1f;
27128 rd
= (ctx
->opcode
>> 11) & 0x1f;
27129 sa
= (ctx
->opcode
>> 6) & 0x1f;
27130 imm
= (int16_t)ctx
->opcode
>> 7;
27132 op1
= MASK_SPECIAL3(ctx
->opcode
);
27136 /* hint codes 24-31 are reserved and signal RI */
27137 generate_exception_end(ctx
, EXCP_RI
);
27139 /* Treat as NOP. */
27142 check_cp0_enabled(ctx
);
27143 if (ctx
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
27144 gen_cache_operation(ctx
, rt
, rs
, imm
);
27148 gen_st_cond(ctx
, rt
, rs
, imm
, MO_TESL
, false);
27151 gen_ld(ctx
, op1
, rt
, rs
, imm
);
27156 /* Treat as NOP. */
27159 op2
= MASK_BSHFL(ctx
->opcode
);
27165 gen_align(ctx
, 32, rd
, rs
, rt
, sa
& 3);
27168 gen_bitswap(ctx
, op2
, rd
, rt
);
27173 #if defined(TARGET_MIPS64)
27175 gen_st_cond(ctx
, rt
, rs
, imm
, MO_TEQ
, false);
27178 gen_ld(ctx
, op1
, rt
, rs
, imm
);
27181 check_mips_64(ctx
);
27184 /* Treat as NOP. */
27187 op2
= MASK_DBSHFL(ctx
->opcode
);
27197 gen_align(ctx
, 64, rd
, rs
, rt
, sa
& 7);
27200 gen_bitswap(ctx
, op2
, rd
, rt
);
27207 default: /* Invalid */
27208 MIPS_INVAL("special3_r6");
27209 generate_exception_end(ctx
, EXCP_RI
);
27214 static void decode_opc_special3_legacy(CPUMIPSState
*env
, DisasContext
*ctx
)
27219 rs
= (ctx
->opcode
>> 21) & 0x1f;
27220 rt
= (ctx
->opcode
>> 16) & 0x1f;
27221 rd
= (ctx
->opcode
>> 11) & 0x1f;
27223 op1
= MASK_SPECIAL3(ctx
->opcode
);
27226 case OPC_DIVU_G_2E
:
27228 case OPC_MODU_G_2E
:
27229 case OPC_MULT_G_2E
:
27230 case OPC_MULTU_G_2E
:
27232 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
27233 * the same mask and op1.
27235 if ((ctx
->insn_flags
& ASE_DSP_R2
) && (op1
== OPC_MULT_G_2E
)) {
27236 op2
= MASK_ADDUH_QB(ctx
->opcode
);
27239 case OPC_ADDUH_R_QB
:
27241 case OPC_ADDQH_R_PH
:
27243 case OPC_ADDQH_R_W
:
27245 case OPC_SUBUH_R_QB
:
27247 case OPC_SUBQH_R_PH
:
27249 case OPC_SUBQH_R_W
:
27250 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27255 case OPC_MULQ_RS_W
:
27256 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
27259 MIPS_INVAL("MASK ADDUH.QB");
27260 generate_exception_end(ctx
, EXCP_RI
);
27263 } else if (ctx
->insn_flags
& INSN_LOONGSON2E
) {
27264 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
27266 generate_exception_end(ctx
, EXCP_RI
);
27270 op2
= MASK_LX(ctx
->opcode
);
27272 #if defined(TARGET_MIPS64)
27278 gen_mipsdsp_ld(ctx
, op2
, rd
, rs
, rt
);
27280 default: /* Invalid */
27281 MIPS_INVAL("MASK LX");
27282 generate_exception_end(ctx
, EXCP_RI
);
27286 case OPC_ABSQ_S_PH_DSP
:
27287 op2
= MASK_ABSQ_S_PH(ctx
->opcode
);
27289 case OPC_ABSQ_S_QB
:
27290 case OPC_ABSQ_S_PH
:
27292 case OPC_PRECEQ_W_PHL
:
27293 case OPC_PRECEQ_W_PHR
:
27294 case OPC_PRECEQU_PH_QBL
:
27295 case OPC_PRECEQU_PH_QBR
:
27296 case OPC_PRECEQU_PH_QBLA
:
27297 case OPC_PRECEQU_PH_QBRA
:
27298 case OPC_PRECEU_PH_QBL
:
27299 case OPC_PRECEU_PH_QBR
:
27300 case OPC_PRECEU_PH_QBLA
:
27301 case OPC_PRECEU_PH_QBRA
:
27302 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27309 gen_mipsdsp_bitinsn(ctx
, op1
, op2
, rd
, rt
);
27312 MIPS_INVAL("MASK ABSQ_S.PH");
27313 generate_exception_end(ctx
, EXCP_RI
);
27317 case OPC_ADDU_QB_DSP
:
27318 op2
= MASK_ADDU_QB(ctx
->opcode
);
27321 case OPC_ADDQ_S_PH
:
27324 case OPC_ADDU_S_QB
:
27326 case OPC_ADDU_S_PH
:
27328 case OPC_SUBQ_S_PH
:
27331 case OPC_SUBU_S_QB
:
27333 case OPC_SUBU_S_PH
:
27337 case OPC_RADDU_W_QB
:
27338 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27340 case OPC_MULEU_S_PH_QBL
:
27341 case OPC_MULEU_S_PH_QBR
:
27342 case OPC_MULQ_RS_PH
:
27343 case OPC_MULEQ_S_W_PHL
:
27344 case OPC_MULEQ_S_W_PHR
:
27345 case OPC_MULQ_S_PH
:
27346 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
27348 default: /* Invalid */
27349 MIPS_INVAL("MASK ADDU.QB");
27350 generate_exception_end(ctx
, EXCP_RI
);
27355 case OPC_CMPU_EQ_QB_DSP
:
27356 op2
= MASK_CMPU_EQ_QB(ctx
->opcode
);
27358 case OPC_PRECR_SRA_PH_W
:
27359 case OPC_PRECR_SRA_R_PH_W
:
27360 gen_mipsdsp_arith(ctx
, op1
, op2
, rt
, rs
, rd
);
27362 case OPC_PRECR_QB_PH
:
27363 case OPC_PRECRQ_QB_PH
:
27364 case OPC_PRECRQ_PH_W
:
27365 case OPC_PRECRQ_RS_PH_W
:
27366 case OPC_PRECRQU_S_QB_PH
:
27367 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27369 case OPC_CMPU_EQ_QB
:
27370 case OPC_CMPU_LT_QB
:
27371 case OPC_CMPU_LE_QB
:
27372 case OPC_CMP_EQ_PH
:
27373 case OPC_CMP_LT_PH
:
27374 case OPC_CMP_LE_PH
:
27375 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27377 case OPC_CMPGU_EQ_QB
:
27378 case OPC_CMPGU_LT_QB
:
27379 case OPC_CMPGU_LE_QB
:
27380 case OPC_CMPGDU_EQ_QB
:
27381 case OPC_CMPGDU_LT_QB
:
27382 case OPC_CMPGDU_LE_QB
:
27385 case OPC_PACKRL_PH
:
27386 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
27388 default: /* Invalid */
27389 MIPS_INVAL("MASK CMPU.EQ.QB");
27390 generate_exception_end(ctx
, EXCP_RI
);
27394 case OPC_SHLL_QB_DSP
:
27395 gen_mipsdsp_shift(ctx
, op1
, rd
, rs
, rt
);
27397 case OPC_DPA_W_PH_DSP
:
27398 op2
= MASK_DPA_W_PH(ctx
->opcode
);
27400 case OPC_DPAU_H_QBL
:
27401 case OPC_DPAU_H_QBR
:
27402 case OPC_DPSU_H_QBL
:
27403 case OPC_DPSU_H_QBR
:
27405 case OPC_DPAX_W_PH
:
27406 case OPC_DPAQ_S_W_PH
:
27407 case OPC_DPAQX_S_W_PH
:
27408 case OPC_DPAQX_SA_W_PH
:
27410 case OPC_DPSX_W_PH
:
27411 case OPC_DPSQ_S_W_PH
:
27412 case OPC_DPSQX_S_W_PH
:
27413 case OPC_DPSQX_SA_W_PH
:
27414 case OPC_MULSAQ_S_W_PH
:
27415 case OPC_DPAQ_SA_L_W
:
27416 case OPC_DPSQ_SA_L_W
:
27417 case OPC_MAQ_S_W_PHL
:
27418 case OPC_MAQ_S_W_PHR
:
27419 case OPC_MAQ_SA_W_PHL
:
27420 case OPC_MAQ_SA_W_PHR
:
27421 case OPC_MULSA_W_PH
:
27422 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27424 default: /* Invalid */
27425 MIPS_INVAL("MASK DPAW.PH");
27426 generate_exception_end(ctx
, EXCP_RI
);
27431 op2
= MASK_INSV(ctx
->opcode
);
27442 t0
= tcg_temp_new();
27443 t1
= tcg_temp_new();
27445 gen_load_gpr(t0
, rt
);
27446 gen_load_gpr(t1
, rs
);
27448 gen_helper_insv(cpu_gpr
[rt
], cpu_env
, t1
, t0
);
27454 default: /* Invalid */
27455 MIPS_INVAL("MASK INSV");
27456 generate_exception_end(ctx
, EXCP_RI
);
27460 case OPC_APPEND_DSP
:
27461 gen_mipsdsp_append(env
, ctx
, op1
, rt
, rs
, rd
);
27463 case OPC_EXTR_W_DSP
:
27464 op2
= MASK_EXTR_W(ctx
->opcode
);
27468 case OPC_EXTR_RS_W
:
27470 case OPC_EXTRV_S_H
:
27472 case OPC_EXTRV_R_W
:
27473 case OPC_EXTRV_RS_W
:
27478 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rt
, rs
, rd
, 1);
27481 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
27487 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27489 default: /* Invalid */
27490 MIPS_INVAL("MASK EXTR.W");
27491 generate_exception_end(ctx
, EXCP_RI
);
27495 #if defined(TARGET_MIPS64)
27496 case OPC_DDIV_G_2E
:
27497 case OPC_DDIVU_G_2E
:
27498 case OPC_DMULT_G_2E
:
27499 case OPC_DMULTU_G_2E
:
27500 case OPC_DMOD_G_2E
:
27501 case OPC_DMODU_G_2E
:
27502 check_insn(ctx
, INSN_LOONGSON2E
);
27503 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
27505 case OPC_ABSQ_S_QH_DSP
:
27506 op2
= MASK_ABSQ_S_QH(ctx
->opcode
);
27508 case OPC_PRECEQ_L_PWL
:
27509 case OPC_PRECEQ_L_PWR
:
27510 case OPC_PRECEQ_PW_QHL
:
27511 case OPC_PRECEQ_PW_QHR
:
27512 case OPC_PRECEQ_PW_QHLA
:
27513 case OPC_PRECEQ_PW_QHRA
:
27514 case OPC_PRECEQU_QH_OBL
:
27515 case OPC_PRECEQU_QH_OBR
:
27516 case OPC_PRECEQU_QH_OBLA
:
27517 case OPC_PRECEQU_QH_OBRA
:
27518 case OPC_PRECEU_QH_OBL
:
27519 case OPC_PRECEU_QH_OBR
:
27520 case OPC_PRECEU_QH_OBLA
:
27521 case OPC_PRECEU_QH_OBRA
:
27522 case OPC_ABSQ_S_OB
:
27523 case OPC_ABSQ_S_PW
:
27524 case OPC_ABSQ_S_QH
:
27525 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27533 gen_mipsdsp_bitinsn(ctx
, op1
, op2
, rd
, rt
);
27535 default: /* Invalid */
27536 MIPS_INVAL("MASK ABSQ_S.QH");
27537 generate_exception_end(ctx
, EXCP_RI
);
27541 case OPC_ADDU_OB_DSP
:
27542 op2
= MASK_ADDU_OB(ctx
->opcode
);
27544 case OPC_RADDU_L_OB
:
27546 case OPC_SUBQ_S_PW
:
27548 case OPC_SUBQ_S_QH
:
27550 case OPC_SUBU_S_OB
:
27552 case OPC_SUBU_S_QH
:
27554 case OPC_SUBUH_R_OB
:
27556 case OPC_ADDQ_S_PW
:
27558 case OPC_ADDQ_S_QH
:
27560 case OPC_ADDU_S_OB
:
27562 case OPC_ADDU_S_QH
:
27564 case OPC_ADDUH_R_OB
:
27565 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27567 case OPC_MULEQ_S_PW_QHL
:
27568 case OPC_MULEQ_S_PW_QHR
:
27569 case OPC_MULEU_S_QH_OBL
:
27570 case OPC_MULEU_S_QH_OBR
:
27571 case OPC_MULQ_RS_QH
:
27572 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
27574 default: /* Invalid */
27575 MIPS_INVAL("MASK ADDU.OB");
27576 generate_exception_end(ctx
, EXCP_RI
);
27580 case OPC_CMPU_EQ_OB_DSP
:
27581 op2
= MASK_CMPU_EQ_OB(ctx
->opcode
);
27583 case OPC_PRECR_SRA_QH_PW
:
27584 case OPC_PRECR_SRA_R_QH_PW
:
27585 /* Return value is rt. */
27586 gen_mipsdsp_arith(ctx
, op1
, op2
, rt
, rs
, rd
);
27588 case OPC_PRECR_OB_QH
:
27589 case OPC_PRECRQ_OB_QH
:
27590 case OPC_PRECRQ_PW_L
:
27591 case OPC_PRECRQ_QH_PW
:
27592 case OPC_PRECRQ_RS_QH_PW
:
27593 case OPC_PRECRQU_S_OB_QH
:
27594 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
27596 case OPC_CMPU_EQ_OB
:
27597 case OPC_CMPU_LT_OB
:
27598 case OPC_CMPU_LE_OB
:
27599 case OPC_CMP_EQ_QH
:
27600 case OPC_CMP_LT_QH
:
27601 case OPC_CMP_LE_QH
:
27602 case OPC_CMP_EQ_PW
:
27603 case OPC_CMP_LT_PW
:
27604 case OPC_CMP_LE_PW
:
27605 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27607 case OPC_CMPGDU_EQ_OB
:
27608 case OPC_CMPGDU_LT_OB
:
27609 case OPC_CMPGDU_LE_OB
:
27610 case OPC_CMPGU_EQ_OB
:
27611 case OPC_CMPGU_LT_OB
:
27612 case OPC_CMPGU_LE_OB
:
27613 case OPC_PACKRL_PW
:
27617 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
27619 default: /* Invalid */
27620 MIPS_INVAL("MASK CMPU_EQ.OB");
27621 generate_exception_end(ctx
, EXCP_RI
);
27625 case OPC_DAPPEND_DSP
:
27626 gen_mipsdsp_append(env
, ctx
, op1
, rt
, rs
, rd
);
27628 case OPC_DEXTR_W_DSP
:
27629 op2
= MASK_DEXTR_W(ctx
->opcode
);
27636 case OPC_DEXTR_R_L
:
27637 case OPC_DEXTR_RS_L
:
27639 case OPC_DEXTR_R_W
:
27640 case OPC_DEXTR_RS_W
:
27641 case OPC_DEXTR_S_H
:
27643 case OPC_DEXTRV_R_L
:
27644 case OPC_DEXTRV_RS_L
:
27645 case OPC_DEXTRV_S_H
:
27647 case OPC_DEXTRV_R_W
:
27648 case OPC_DEXTRV_RS_W
:
27649 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rt
, rs
, rd
, 1);
27654 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27656 default: /* Invalid */
27657 MIPS_INVAL("MASK EXTR.W");
27658 generate_exception_end(ctx
, EXCP_RI
);
27662 case OPC_DPAQ_W_QH_DSP
:
27663 op2
= MASK_DPAQ_W_QH(ctx
->opcode
);
27665 case OPC_DPAU_H_OBL
:
27666 case OPC_DPAU_H_OBR
:
27667 case OPC_DPSU_H_OBL
:
27668 case OPC_DPSU_H_OBR
:
27670 case OPC_DPAQ_S_W_QH
:
27672 case OPC_DPSQ_S_W_QH
:
27673 case OPC_MULSAQ_S_W_QH
:
27674 case OPC_DPAQ_SA_L_PW
:
27675 case OPC_DPSQ_SA_L_PW
:
27676 case OPC_MULSAQ_S_L_PW
:
27677 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27679 case OPC_MAQ_S_W_QHLL
:
27680 case OPC_MAQ_S_W_QHLR
:
27681 case OPC_MAQ_S_W_QHRL
:
27682 case OPC_MAQ_S_W_QHRR
:
27683 case OPC_MAQ_SA_W_QHLL
:
27684 case OPC_MAQ_SA_W_QHLR
:
27685 case OPC_MAQ_SA_W_QHRL
:
27686 case OPC_MAQ_SA_W_QHRR
:
27687 case OPC_MAQ_S_L_PWL
:
27688 case OPC_MAQ_S_L_PWR
:
27693 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
27695 default: /* Invalid */
27696 MIPS_INVAL("MASK DPAQ.W.QH");
27697 generate_exception_end(ctx
, EXCP_RI
);
27701 case OPC_DINSV_DSP
:
27702 op2
= MASK_INSV(ctx
->opcode
);
27713 t0
= tcg_temp_new();
27714 t1
= tcg_temp_new();
27716 gen_load_gpr(t0
, rt
);
27717 gen_load_gpr(t1
, rs
);
27719 gen_helper_dinsv(cpu_gpr
[rt
], cpu_env
, t1
, t0
);
27725 default: /* Invalid */
27726 MIPS_INVAL("MASK DINSV");
27727 generate_exception_end(ctx
, EXCP_RI
);
27731 case OPC_SHLL_OB_DSP
:
27732 gen_mipsdsp_shift(ctx
, op1
, rd
, rs
, rt
);
27735 default: /* Invalid */
27736 MIPS_INVAL("special3_legacy");
27737 generate_exception_end(ctx
, EXCP_RI
);
27743 #if defined(TARGET_MIPS64)
27745 static void decode_mmi0(CPUMIPSState
*env
, DisasContext
*ctx
)
27747 uint32_t opc
= MASK_MMI0(ctx
->opcode
);
27750 case MMI_OPC_0_PADDW
: /* TODO: MMI_OPC_0_PADDW */
27751 case MMI_OPC_0_PSUBW
: /* TODO: MMI_OPC_0_PSUBW */
27752 case MMI_OPC_0_PCGTW
: /* TODO: MMI_OPC_0_PCGTW */
27753 case MMI_OPC_0_PMAXW
: /* TODO: MMI_OPC_0_PMAXW */
27754 case MMI_OPC_0_PADDH
: /* TODO: MMI_OPC_0_PADDH */
27755 case MMI_OPC_0_PSUBH
: /* TODO: MMI_OPC_0_PSUBH */
27756 case MMI_OPC_0_PCGTH
: /* TODO: MMI_OPC_0_PCGTH */
27757 case MMI_OPC_0_PMAXH
: /* TODO: MMI_OPC_0_PMAXH */
27758 case MMI_OPC_0_PADDB
: /* TODO: MMI_OPC_0_PADDB */
27759 case MMI_OPC_0_PSUBB
: /* TODO: MMI_OPC_0_PSUBB */
27760 case MMI_OPC_0_PCGTB
: /* TODO: MMI_OPC_0_PCGTB */
27761 case MMI_OPC_0_PADDSW
: /* TODO: MMI_OPC_0_PADDSW */
27762 case MMI_OPC_0_PSUBSW
: /* TODO: MMI_OPC_0_PSUBSW */
27763 case MMI_OPC_0_PEXTLW
: /* TODO: MMI_OPC_0_PEXTLW */
27764 case MMI_OPC_0_PPACW
: /* TODO: MMI_OPC_0_PPACW */
27765 case MMI_OPC_0_PADDSH
: /* TODO: MMI_OPC_0_PADDSH */
27766 case MMI_OPC_0_PSUBSH
: /* TODO: MMI_OPC_0_PSUBSH */
27767 case MMI_OPC_0_PEXTLH
: /* TODO: MMI_OPC_0_PEXTLH */
27768 case MMI_OPC_0_PPACH
: /* TODO: MMI_OPC_0_PPACH */
27769 case MMI_OPC_0_PADDSB
: /* TODO: MMI_OPC_0_PADDSB */
27770 case MMI_OPC_0_PSUBSB
: /* TODO: MMI_OPC_0_PSUBSB */
27771 case MMI_OPC_0_PEXTLB
: /* TODO: MMI_OPC_0_PEXTLB */
27772 case MMI_OPC_0_PPACB
: /* TODO: MMI_OPC_0_PPACB */
27773 case MMI_OPC_0_PEXT5
: /* TODO: MMI_OPC_0_PEXT5 */
27774 case MMI_OPC_0_PPAC5
: /* TODO: MMI_OPC_0_PPAC5 */
27775 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_CLASS_MMI0 */
27778 MIPS_INVAL("TX79 MMI class MMI0");
27779 generate_exception_end(ctx
, EXCP_RI
);
27784 static void decode_mmi1(CPUMIPSState
*env
, DisasContext
*ctx
)
27786 uint32_t opc
= MASK_MMI1(ctx
->opcode
);
27789 case MMI_OPC_1_PABSW
: /* TODO: MMI_OPC_1_PABSW */
27790 case MMI_OPC_1_PCEQW
: /* TODO: MMI_OPC_1_PCEQW */
27791 case MMI_OPC_1_PMINW
: /* TODO: MMI_OPC_1_PMINW */
27792 case MMI_OPC_1_PADSBH
: /* TODO: MMI_OPC_1_PADSBH */
27793 case MMI_OPC_1_PABSH
: /* TODO: MMI_OPC_1_PABSH */
27794 case MMI_OPC_1_PCEQH
: /* TODO: MMI_OPC_1_PCEQH */
27795 case MMI_OPC_1_PMINH
: /* TODO: MMI_OPC_1_PMINH */
27796 case MMI_OPC_1_PCEQB
: /* TODO: MMI_OPC_1_PCEQB */
27797 case MMI_OPC_1_PADDUW
: /* TODO: MMI_OPC_1_PADDUW */
27798 case MMI_OPC_1_PSUBUW
: /* TODO: MMI_OPC_1_PSUBUW */
27799 case MMI_OPC_1_PEXTUW
: /* TODO: MMI_OPC_1_PEXTUW */
27800 case MMI_OPC_1_PADDUH
: /* TODO: MMI_OPC_1_PADDUH */
27801 case MMI_OPC_1_PSUBUH
: /* TODO: MMI_OPC_1_PSUBUH */
27802 case MMI_OPC_1_PEXTUH
: /* TODO: MMI_OPC_1_PEXTUH */
27803 case MMI_OPC_1_PADDUB
: /* TODO: MMI_OPC_1_PADDUB */
27804 case MMI_OPC_1_PSUBUB
: /* TODO: MMI_OPC_1_PSUBUB */
27805 case MMI_OPC_1_PEXTUB
: /* TODO: MMI_OPC_1_PEXTUB */
27806 case MMI_OPC_1_QFSRV
: /* TODO: MMI_OPC_1_QFSRV */
27807 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_CLASS_MMI1 */
27810 MIPS_INVAL("TX79 MMI class MMI1");
27811 generate_exception_end(ctx
, EXCP_RI
);
27816 static void decode_mmi2(CPUMIPSState
*env
, DisasContext
*ctx
)
27818 uint32_t opc
= MASK_MMI2(ctx
->opcode
);
27821 case MMI_OPC_2_PMADDW
: /* TODO: MMI_OPC_2_PMADDW */
27822 case MMI_OPC_2_PSLLVW
: /* TODO: MMI_OPC_2_PSLLVW */
27823 case MMI_OPC_2_PSRLVW
: /* TODO: MMI_OPC_2_PSRLVW */
27824 case MMI_OPC_2_PMSUBW
: /* TODO: MMI_OPC_2_PMSUBW */
27825 case MMI_OPC_2_PMFHI
: /* TODO: MMI_OPC_2_PMFHI */
27826 case MMI_OPC_2_PMFLO
: /* TODO: MMI_OPC_2_PMFLO */
27827 case MMI_OPC_2_PINTH
: /* TODO: MMI_OPC_2_PINTH */
27828 case MMI_OPC_2_PMULTW
: /* TODO: MMI_OPC_2_PMULTW */
27829 case MMI_OPC_2_PDIVW
: /* TODO: MMI_OPC_2_PDIVW */
27830 case MMI_OPC_2_PMADDH
: /* TODO: MMI_OPC_2_PMADDH */
27831 case MMI_OPC_2_PHMADH
: /* TODO: MMI_OPC_2_PHMADH */
27832 case MMI_OPC_2_PAND
: /* TODO: MMI_OPC_2_PAND */
27833 case MMI_OPC_2_PXOR
: /* TODO: MMI_OPC_2_PXOR */
27834 case MMI_OPC_2_PMSUBH
: /* TODO: MMI_OPC_2_PMSUBH */
27835 case MMI_OPC_2_PHMSBH
: /* TODO: MMI_OPC_2_PHMSBH */
27836 case MMI_OPC_2_PEXEH
: /* TODO: MMI_OPC_2_PEXEH */
27837 case MMI_OPC_2_PREVH
: /* TODO: MMI_OPC_2_PREVH */
27838 case MMI_OPC_2_PMULTH
: /* TODO: MMI_OPC_2_PMULTH */
27839 case MMI_OPC_2_PDIVBW
: /* TODO: MMI_OPC_2_PDIVBW */
27840 case MMI_OPC_2_PEXEW
: /* TODO: MMI_OPC_2_PEXEW */
27841 case MMI_OPC_2_PROT3W
: /* TODO: MMI_OPC_2_PROT3W */
27842 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_CLASS_MMI2 */
27844 case MMI_OPC_2_PCPYLD
:
27845 gen_mmi_pcpyld(ctx
);
27848 MIPS_INVAL("TX79 MMI class MMI2");
27849 generate_exception_end(ctx
, EXCP_RI
);
27854 static void decode_mmi3(CPUMIPSState
*env
, DisasContext
*ctx
)
27856 uint32_t opc
= MASK_MMI3(ctx
->opcode
);
27859 case MMI_OPC_3_PMADDUW
: /* TODO: MMI_OPC_3_PMADDUW */
27860 case MMI_OPC_3_PSRAVW
: /* TODO: MMI_OPC_3_PSRAVW */
27861 case MMI_OPC_3_PMTHI
: /* TODO: MMI_OPC_3_PMTHI */
27862 case MMI_OPC_3_PMTLO
: /* TODO: MMI_OPC_3_PMTLO */
27863 case MMI_OPC_3_PINTEH
: /* TODO: MMI_OPC_3_PINTEH */
27864 case MMI_OPC_3_PMULTUW
: /* TODO: MMI_OPC_3_PMULTUW */
27865 case MMI_OPC_3_PDIVUW
: /* TODO: MMI_OPC_3_PDIVUW */
27866 case MMI_OPC_3_POR
: /* TODO: MMI_OPC_3_POR */
27867 case MMI_OPC_3_PNOR
: /* TODO: MMI_OPC_3_PNOR */
27868 case MMI_OPC_3_PEXCH
: /* TODO: MMI_OPC_3_PEXCH */
27869 case MMI_OPC_3_PEXCW
: /* TODO: MMI_OPC_3_PEXCW */
27870 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_CLASS_MMI3 */
27872 case MMI_OPC_3_PCPYH
:
27873 gen_mmi_pcpyh(ctx
);
27875 case MMI_OPC_3_PCPYUD
:
27876 gen_mmi_pcpyud(ctx
);
27879 MIPS_INVAL("TX79 MMI class MMI3");
27880 generate_exception_end(ctx
, EXCP_RI
);
27885 static void decode_mmi(CPUMIPSState
*env
, DisasContext
*ctx
)
27887 uint32_t opc
= MASK_MMI(ctx
->opcode
);
27888 int rs
= extract32(ctx
->opcode
, 21, 5);
27889 int rt
= extract32(ctx
->opcode
, 16, 5);
27890 int rd
= extract32(ctx
->opcode
, 11, 5);
27893 case MMI_OPC_CLASS_MMI0
:
27894 decode_mmi0(env
, ctx
);
27896 case MMI_OPC_CLASS_MMI1
:
27897 decode_mmi1(env
, ctx
);
27899 case MMI_OPC_CLASS_MMI2
:
27900 decode_mmi2(env
, ctx
);
27902 case MMI_OPC_CLASS_MMI3
:
27903 decode_mmi3(env
, ctx
);
27905 case MMI_OPC_MULT1
:
27906 case MMI_OPC_MULTU1
:
27908 case MMI_OPC_MADDU
:
27909 case MMI_OPC_MADD1
:
27910 case MMI_OPC_MADDU1
:
27911 gen_mul_txx9(ctx
, opc
, rd
, rs
, rt
);
27914 case MMI_OPC_DIVU1
:
27915 gen_div1_tx79(ctx
, opc
, rs
, rt
);
27917 case MMI_OPC_MTLO1
:
27918 case MMI_OPC_MTHI1
:
27919 gen_HILO1_tx79(ctx
, opc
, rs
);
27921 case MMI_OPC_MFLO1
:
27922 case MMI_OPC_MFHI1
:
27923 gen_HILO1_tx79(ctx
, opc
, rd
);
27925 case MMI_OPC_PLZCW
: /* TODO: MMI_OPC_PLZCW */
27926 case MMI_OPC_PMFHL
: /* TODO: MMI_OPC_PMFHL */
27927 case MMI_OPC_PMTHL
: /* TODO: MMI_OPC_PMTHL */
27928 case MMI_OPC_PSLLH
: /* TODO: MMI_OPC_PSLLH */
27929 case MMI_OPC_PSRLH
: /* TODO: MMI_OPC_PSRLH */
27930 case MMI_OPC_PSRAH
: /* TODO: MMI_OPC_PSRAH */
27931 case MMI_OPC_PSLLW
: /* TODO: MMI_OPC_PSLLW */
27932 case MMI_OPC_PSRLW
: /* TODO: MMI_OPC_PSRLW */
27933 case MMI_OPC_PSRAW
: /* TODO: MMI_OPC_PSRAW */
27934 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_CLASS_MMI */
27937 MIPS_INVAL("TX79 MMI class");
27938 generate_exception_end(ctx
, EXCP_RI
);
27943 static void gen_mmi_lq(CPUMIPSState
*env
, DisasContext
*ctx
)
27945 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_LQ */
27948 static void gen_mmi_sq(DisasContext
*ctx
, int base
, int rt
, int offset
)
27950 generate_exception_end(ctx
, EXCP_RI
); /* TODO: MMI_OPC_SQ */
27954 * The TX79-specific instruction Store Quadword
27956 * +--------+-------+-------+------------------------+
27957 * | 011111 | base | rt | offset | SQ
27958 * +--------+-------+-------+------------------------+
27961 * has the same opcode as the Read Hardware Register instruction
27963 * +--------+-------+-------+-------+-------+--------+
27964 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
27965 * +--------+-------+-------+-------+-------+--------+
27968 * that is required, trapped and emulated by the Linux kernel. However, all
27969 * RDHWR encodings yield address error exceptions on the TX79 since the SQ
27970 * offset is odd. Therefore all valid SQ instructions can execute normally.
27971 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
27972 * between SQ and RDHWR, as the Linux kernel does.
27974 static void decode_mmi_sq(CPUMIPSState
*env
, DisasContext
*ctx
)
27976 int base
= extract32(ctx
->opcode
, 21, 5);
27977 int rt
= extract32(ctx
->opcode
, 16, 5);
27978 int offset
= extract32(ctx
->opcode
, 0, 16);
27980 #ifdef CONFIG_USER_ONLY
27981 uint32_t op1
= MASK_SPECIAL3(ctx
->opcode
);
27982 uint32_t op2
= extract32(ctx
->opcode
, 6, 5);
27984 if (base
== 0 && op2
== 0 && op1
== OPC_RDHWR
) {
27985 int rd
= extract32(ctx
->opcode
, 11, 5);
27987 gen_rdhwr(ctx
, rt
, rd
, 0);
27992 gen_mmi_sq(ctx
, base
, rt
, offset
);
27997 static void decode_opc_special3(CPUMIPSState
*env
, DisasContext
*ctx
)
27999 int rs
, rt
, rd
, sa
;
28003 rs
= (ctx
->opcode
>> 21) & 0x1f;
28004 rt
= (ctx
->opcode
>> 16) & 0x1f;
28005 rd
= (ctx
->opcode
>> 11) & 0x1f;
28006 sa
= (ctx
->opcode
>> 6) & 0x1f;
28007 imm
= sextract32(ctx
->opcode
, 7, 9);
28009 op1
= MASK_SPECIAL3(ctx
->opcode
);
28012 * EVA loads and stores overlap Loongson 2E instructions decoded by
28013 * decode_opc_special3_legacy(), so be careful to allow their decoding when
28020 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
28028 check_cp0_enabled(ctx
);
28029 gen_ld(ctx
, op1
, rt
, rs
, imm
);
28033 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
28038 check_cp0_enabled(ctx
);
28039 gen_st(ctx
, op1
, rt
, rs
, imm
);
28042 check_cp0_enabled(ctx
);
28043 gen_st_cond(ctx
, rt
, rs
, imm
, MO_TESL
, true);
28046 check_cp0_enabled(ctx
);
28047 if (ctx
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
28048 gen_cache_operation(ctx
, rt
, rs
, imm
);
28050 /* Treat as NOP. */
28053 check_cp0_enabled(ctx
);
28054 /* Treat as NOP. */
28062 check_insn(ctx
, ISA_MIPS32R2
);
28063 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
28066 op2
= MASK_BSHFL(ctx
->opcode
);
28073 check_insn(ctx
, ISA_MIPS32R6
);
28074 decode_opc_special3_r6(env
, ctx
);
28077 check_insn(ctx
, ISA_MIPS32R2
);
28078 gen_bshfl(ctx
, op2
, rt
, rd
);
28082 #if defined(TARGET_MIPS64)
28089 check_insn(ctx
, ISA_MIPS64R2
);
28090 check_mips_64(ctx
);
28091 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
28094 op2
= MASK_DBSHFL(ctx
->opcode
);
28105 check_insn(ctx
, ISA_MIPS32R6
);
28106 decode_opc_special3_r6(env
, ctx
);
28109 check_insn(ctx
, ISA_MIPS64R2
);
28110 check_mips_64(ctx
);
28111 op2
= MASK_DBSHFL(ctx
->opcode
);
28112 gen_bshfl(ctx
, op2
, rt
, rd
);
28118 gen_rdhwr(ctx
, rt
, rd
, extract32(ctx
->opcode
, 6, 3));
28123 TCGv t0
= tcg_temp_new();
28124 TCGv t1
= tcg_temp_new();
28126 gen_load_gpr(t0
, rt
);
28127 gen_load_gpr(t1
, rs
);
28128 gen_helper_fork(t0
, t1
);
28136 TCGv t0
= tcg_temp_new();
28138 gen_load_gpr(t0
, rs
);
28139 gen_helper_yield(t0
, cpu_env
, t0
);
28140 gen_store_gpr(t0
, rd
);
28145 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
28146 decode_opc_special3_r6(env
, ctx
);
28148 decode_opc_special3_legacy(env
, ctx
);
28153 /* MIPS SIMD Architecture (MSA) */
28154 static inline int check_msa_access(DisasContext
*ctx
)
28156 if (unlikely((ctx
->hflags
& MIPS_HFLAG_FPU
) &&
28157 !(ctx
->hflags
& MIPS_HFLAG_F64
))) {
28158 generate_exception_end(ctx
, EXCP_RI
);
28162 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_MSA
))) {
28163 if (ctx
->insn_flags
& ASE_MSA
) {
28164 generate_exception_end(ctx
, EXCP_MSADIS
);
28167 generate_exception_end(ctx
, EXCP_RI
);
28174 static void gen_check_zero_element(TCGv tresult
, uint8_t df
, uint8_t wt
)
28176 /* generates tcg ops to check if any element is 0 */
28177 /* Note this function only works with MSA_WRLEN = 128 */
28178 uint64_t eval_zero_or_big
= 0;
28179 uint64_t eval_big
= 0;
28180 TCGv_i64 t0
= tcg_temp_new_i64();
28181 TCGv_i64 t1
= tcg_temp_new_i64();
28184 eval_zero_or_big
= 0x0101010101010101ULL
;
28185 eval_big
= 0x8080808080808080ULL
;
28188 eval_zero_or_big
= 0x0001000100010001ULL
;
28189 eval_big
= 0x8000800080008000ULL
;
28192 eval_zero_or_big
= 0x0000000100000001ULL
;
28193 eval_big
= 0x8000000080000000ULL
;
28196 eval_zero_or_big
= 0x0000000000000001ULL
;
28197 eval_big
= 0x8000000000000000ULL
;
28200 tcg_gen_subi_i64(t0
, msa_wr_d
[wt
<< 1], eval_zero_or_big
);
28201 tcg_gen_andc_i64(t0
, t0
, msa_wr_d
[wt
<< 1]);
28202 tcg_gen_andi_i64(t0
, t0
, eval_big
);
28203 tcg_gen_subi_i64(t1
, msa_wr_d
[(wt
<< 1) + 1], eval_zero_or_big
);
28204 tcg_gen_andc_i64(t1
, t1
, msa_wr_d
[(wt
<< 1) + 1]);
28205 tcg_gen_andi_i64(t1
, t1
, eval_big
);
28206 tcg_gen_or_i64(t0
, t0
, t1
);
28207 /* if all bits are zero then all elements are not zero */
28208 /* if some bit is non-zero then some element is zero */
28209 tcg_gen_setcondi_i64(TCG_COND_NE
, t0
, t0
, 0);
28210 tcg_gen_trunc_i64_tl(tresult
, t0
);
28211 tcg_temp_free_i64(t0
);
28212 tcg_temp_free_i64(t1
);
28215 static void gen_msa_branch(CPUMIPSState
*env
, DisasContext
*ctx
, uint32_t op1
)
28217 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
28218 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
28219 int64_t s16
= (int16_t)ctx
->opcode
;
28221 check_msa_access(ctx
);
28223 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
28224 generate_exception_end(ctx
, EXCP_RI
);
28231 TCGv_i64 t0
= tcg_temp_new_i64();
28232 tcg_gen_or_i64(t0
, msa_wr_d
[wt
<< 1], msa_wr_d
[(wt
<< 1) + 1]);
28233 tcg_gen_setcondi_i64((op1
== OPC_BZ_V
) ?
28234 TCG_COND_EQ
: TCG_COND_NE
, t0
, t0
, 0);
28235 tcg_gen_trunc_i64_tl(bcond
, t0
);
28236 tcg_temp_free_i64(t0
);
28243 gen_check_zero_element(bcond
, df
, wt
);
28249 gen_check_zero_element(bcond
, df
, wt
);
28250 tcg_gen_setcondi_tl(TCG_COND_EQ
, bcond
, bcond
, 0);
28254 ctx
->btarget
= ctx
->base
.pc_next
+ (s16
<< 2) + 4;
28256 ctx
->hflags
|= MIPS_HFLAG_BC
;
28257 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
28260 static void gen_msa_i8(CPUMIPSState
*env
, DisasContext
*ctx
)
28262 #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
28263 uint8_t i8
= (ctx
->opcode
>> 16) & 0xff;
28264 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
28265 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
28267 TCGv_i32 twd
= tcg_const_i32(wd
);
28268 TCGv_i32 tws
= tcg_const_i32(ws
);
28269 TCGv_i32 ti8
= tcg_const_i32(i8
);
28271 switch (MASK_MSA_I8(ctx
->opcode
)) {
28273 gen_helper_msa_andi_b(cpu_env
, twd
, tws
, ti8
);
28276 gen_helper_msa_ori_b(cpu_env
, twd
, tws
, ti8
);
28279 gen_helper_msa_nori_b(cpu_env
, twd
, tws
, ti8
);
28282 gen_helper_msa_xori_b(cpu_env
, twd
, tws
, ti8
);
28285 gen_helper_msa_bmnzi_b(cpu_env
, twd
, tws
, ti8
);
28288 gen_helper_msa_bmzi_b(cpu_env
, twd
, tws
, ti8
);
28291 gen_helper_msa_bseli_b(cpu_env
, twd
, tws
, ti8
);
28297 uint8_t df
= (ctx
->opcode
>> 24) & 0x3;
28298 if (df
== DF_DOUBLE
) {
28299 generate_exception_end(ctx
, EXCP_RI
);
28301 TCGv_i32 tdf
= tcg_const_i32(df
);
28302 gen_helper_msa_shf_df(cpu_env
, tdf
, twd
, tws
, ti8
);
28303 tcg_temp_free_i32(tdf
);
28308 MIPS_INVAL("MSA instruction");
28309 generate_exception_end(ctx
, EXCP_RI
);
28313 tcg_temp_free_i32(twd
);
28314 tcg_temp_free_i32(tws
);
28315 tcg_temp_free_i32(ti8
);
28318 static void gen_msa_i5(CPUMIPSState
*env
, DisasContext
*ctx
)
28320 #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
28321 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
28322 int8_t s5
= (int8_t) sextract32(ctx
->opcode
, 16, 5);
28323 uint8_t u5
= (ctx
->opcode
>> 16) & 0x1f;
28324 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
28325 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
28327 TCGv_i32 tdf
= tcg_const_i32(df
);
28328 TCGv_i32 twd
= tcg_const_i32(wd
);
28329 TCGv_i32 tws
= tcg_const_i32(ws
);
28330 TCGv_i32 timm
= tcg_temp_new_i32();
28331 tcg_gen_movi_i32(timm
, u5
);
28333 switch (MASK_MSA_I5(ctx
->opcode
)) {
28335 gen_helper_msa_addvi_df(cpu_env
, tdf
, twd
, tws
, timm
);
28338 gen_helper_msa_subvi_df(cpu_env
, tdf
, twd
, tws
, timm
);
28340 case OPC_MAXI_S_df
:
28341 tcg_gen_movi_i32(timm
, s5
);
28342 gen_helper_msa_maxi_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
28344 case OPC_MAXI_U_df
:
28345 gen_helper_msa_maxi_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
28347 case OPC_MINI_S_df
:
28348 tcg_gen_movi_i32(timm
, s5
);
28349 gen_helper_msa_mini_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
28351 case OPC_MINI_U_df
:
28352 gen_helper_msa_mini_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
28355 tcg_gen_movi_i32(timm
, s5
);
28356 gen_helper_msa_ceqi_df(cpu_env
, tdf
, twd
, tws
, timm
);
28358 case OPC_CLTI_S_df
:
28359 tcg_gen_movi_i32(timm
, s5
);
28360 gen_helper_msa_clti_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
28362 case OPC_CLTI_U_df
:
28363 gen_helper_msa_clti_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
28365 case OPC_CLEI_S_df
:
28366 tcg_gen_movi_i32(timm
, s5
);
28367 gen_helper_msa_clei_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
28369 case OPC_CLEI_U_df
:
28370 gen_helper_msa_clei_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
28374 int32_t s10
= sextract32(ctx
->opcode
, 11, 10);
28375 tcg_gen_movi_i32(timm
, s10
);
28376 gen_helper_msa_ldi_df(cpu_env
, tdf
, twd
, timm
);
28380 MIPS_INVAL("MSA instruction");
28381 generate_exception_end(ctx
, EXCP_RI
);
28385 tcg_temp_free_i32(tdf
);
28386 tcg_temp_free_i32(twd
);
28387 tcg_temp_free_i32(tws
);
28388 tcg_temp_free_i32(timm
);
28391 static void gen_msa_bit(CPUMIPSState
*env
, DisasContext
*ctx
)
28393 #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
28394 uint8_t dfm
= (ctx
->opcode
>> 16) & 0x7f;
28395 uint32_t df
= 0, m
= 0;
28396 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
28397 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
28404 if ((dfm
& 0x40) == 0x00) {
28407 } else if ((dfm
& 0x60) == 0x40) {
28410 } else if ((dfm
& 0x70) == 0x60) {
28413 } else if ((dfm
& 0x78) == 0x70) {
28417 generate_exception_end(ctx
, EXCP_RI
);
28421 tdf
= tcg_const_i32(df
);
28422 tm
= tcg_const_i32(m
);
28423 twd
= tcg_const_i32(wd
);
28424 tws
= tcg_const_i32(ws
);
28426 switch (MASK_MSA_BIT(ctx
->opcode
)) {
28428 gen_helper_msa_slli_df(cpu_env
, tdf
, twd
, tws
, tm
);
28431 gen_helper_msa_srai_df(cpu_env
, tdf
, twd
, tws
, tm
);
28434 gen_helper_msa_srli_df(cpu_env
, tdf
, twd
, tws
, tm
);
28437 gen_helper_msa_bclri_df(cpu_env
, tdf
, twd
, tws
, tm
);
28440 gen_helper_msa_bseti_df(cpu_env
, tdf
, twd
, tws
, tm
);
28443 gen_helper_msa_bnegi_df(cpu_env
, tdf
, twd
, tws
, tm
);
28445 case OPC_BINSLI_df
:
28446 gen_helper_msa_binsli_df(cpu_env
, tdf
, twd
, tws
, tm
);
28448 case OPC_BINSRI_df
:
28449 gen_helper_msa_binsri_df(cpu_env
, tdf
, twd
, tws
, tm
);
28452 gen_helper_msa_sat_s_df(cpu_env
, tdf
, twd
, tws
, tm
);
28455 gen_helper_msa_sat_u_df(cpu_env
, tdf
, twd
, tws
, tm
);
28458 gen_helper_msa_srari_df(cpu_env
, tdf
, twd
, tws
, tm
);
28461 gen_helper_msa_srlri_df(cpu_env
, tdf
, twd
, tws
, tm
);
28464 MIPS_INVAL("MSA instruction");
28465 generate_exception_end(ctx
, EXCP_RI
);
28469 tcg_temp_free_i32(tdf
);
28470 tcg_temp_free_i32(tm
);
28471 tcg_temp_free_i32(twd
);
28472 tcg_temp_free_i32(tws
);
28475 static void gen_msa_3r(CPUMIPSState
*env
, DisasContext
*ctx
)
28477 #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
28478 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
28479 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
28480 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
28481 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
28483 TCGv_i32 tdf
= tcg_const_i32(df
);
28484 TCGv_i32 twd
= tcg_const_i32(wd
);
28485 TCGv_i32 tws
= tcg_const_i32(ws
);
28486 TCGv_i32 twt
= tcg_const_i32(wt
);
28488 switch (MASK_MSA_3R(ctx
->opcode
)) {
28492 gen_helper_msa_binsl_b(cpu_env
, twd
, tws
, twt
);
28495 gen_helper_msa_binsl_h(cpu_env
, twd
, tws
, twt
);
28498 gen_helper_msa_binsl_w(cpu_env
, twd
, tws
, twt
);
28501 gen_helper_msa_binsl_d(cpu_env
, twd
, tws
, twt
);
28508 gen_helper_msa_binsr_b(cpu_env
, twd
, tws
, twt
);
28511 gen_helper_msa_binsr_h(cpu_env
, twd
, tws
, twt
);
28514 gen_helper_msa_binsr_w(cpu_env
, twd
, tws
, twt
);
28517 gen_helper_msa_binsr_d(cpu_env
, twd
, tws
, twt
);
28524 gen_helper_msa_bclr_b(cpu_env
, twd
, tws
, twt
);
28527 gen_helper_msa_bclr_h(cpu_env
, twd
, tws
, twt
);
28530 gen_helper_msa_bclr_w(cpu_env
, twd
, tws
, twt
);
28533 gen_helper_msa_bclr_d(cpu_env
, twd
, tws
, twt
);
28540 gen_helper_msa_bneg_b(cpu_env
, twd
, tws
, twt
);
28543 gen_helper_msa_bneg_h(cpu_env
, twd
, tws
, twt
);
28546 gen_helper_msa_bneg_w(cpu_env
, twd
, tws
, twt
);
28549 gen_helper_msa_bneg_d(cpu_env
, twd
, tws
, twt
);
28556 gen_helper_msa_bset_b(cpu_env
, twd
, tws
, twt
);
28559 gen_helper_msa_bset_h(cpu_env
, twd
, tws
, twt
);
28562 gen_helper_msa_bset_w(cpu_env
, twd
, tws
, twt
);
28565 gen_helper_msa_bset_d(cpu_env
, twd
, tws
, twt
);
28572 gen_helper_msa_add_a_b(cpu_env
, twd
, tws
, twt
);
28575 gen_helper_msa_add_a_h(cpu_env
, twd
, tws
, twt
);
28578 gen_helper_msa_add_a_w(cpu_env
, twd
, tws
, twt
);
28581 gen_helper_msa_add_a_d(cpu_env
, twd
, tws
, twt
);
28585 case OPC_ADDS_A_df
:
28588 gen_helper_msa_adds_a_b(cpu_env
, twd
, tws
, twt
);
28591 gen_helper_msa_adds_a_h(cpu_env
, twd
, tws
, twt
);
28594 gen_helper_msa_adds_a_w(cpu_env
, twd
, tws
, twt
);
28597 gen_helper_msa_adds_a_d(cpu_env
, twd
, tws
, twt
);
28601 case OPC_ADDS_S_df
:
28604 gen_helper_msa_adds_s_b(cpu_env
, twd
, tws
, twt
);
28607 gen_helper_msa_adds_s_h(cpu_env
, twd
, tws
, twt
);
28610 gen_helper_msa_adds_s_w(cpu_env
, twd
, tws
, twt
);
28613 gen_helper_msa_adds_s_d(cpu_env
, twd
, tws
, twt
);
28617 case OPC_ADDS_U_df
:
28620 gen_helper_msa_adds_u_b(cpu_env
, twd
, tws
, twt
);
28623 gen_helper_msa_adds_u_h(cpu_env
, twd
, tws
, twt
);
28626 gen_helper_msa_adds_u_w(cpu_env
, twd
, tws
, twt
);
28629 gen_helper_msa_adds_u_d(cpu_env
, twd
, tws
, twt
);
28636 gen_helper_msa_addv_b(cpu_env
, twd
, tws
, twt
);
28639 gen_helper_msa_addv_h(cpu_env
, twd
, tws
, twt
);
28642 gen_helper_msa_addv_w(cpu_env
, twd
, tws
, twt
);
28645 gen_helper_msa_addv_d(cpu_env
, twd
, tws
, twt
);
28652 gen_helper_msa_ave_s_b(cpu_env
, twd
, tws
, twt
);
28655 gen_helper_msa_ave_s_h(cpu_env
, twd
, tws
, twt
);
28658 gen_helper_msa_ave_s_w(cpu_env
, twd
, tws
, twt
);
28661 gen_helper_msa_ave_s_d(cpu_env
, twd
, tws
, twt
);
28668 gen_helper_msa_ave_u_b(cpu_env
, twd
, tws
, twt
);
28671 gen_helper_msa_ave_u_h(cpu_env
, twd
, tws
, twt
);
28674 gen_helper_msa_ave_u_w(cpu_env
, twd
, tws
, twt
);
28677 gen_helper_msa_ave_u_d(cpu_env
, twd
, tws
, twt
);
28681 case OPC_AVER_S_df
:
28684 gen_helper_msa_aver_s_b(cpu_env
, twd
, tws
, twt
);
28687 gen_helper_msa_aver_s_h(cpu_env
, twd
, tws
, twt
);
28690 gen_helper_msa_aver_s_w(cpu_env
, twd
, tws
, twt
);
28693 gen_helper_msa_aver_s_d(cpu_env
, twd
, tws
, twt
);
28697 case OPC_AVER_U_df
:
28700 gen_helper_msa_aver_u_b(cpu_env
, twd
, tws
, twt
);
28703 gen_helper_msa_aver_u_h(cpu_env
, twd
, tws
, twt
);
28706 gen_helper_msa_aver_u_w(cpu_env
, twd
, tws
, twt
);
28709 gen_helper_msa_aver_u_d(cpu_env
, twd
, tws
, twt
);
28716 gen_helper_msa_ceq_b(cpu_env
, twd
, tws
, twt
);
28719 gen_helper_msa_ceq_h(cpu_env
, twd
, tws
, twt
);
28722 gen_helper_msa_ceq_w(cpu_env
, twd
, tws
, twt
);
28725 gen_helper_msa_ceq_d(cpu_env
, twd
, tws
, twt
);
28732 gen_helper_msa_cle_s_b(cpu_env
, twd
, tws
, twt
);
28735 gen_helper_msa_cle_s_h(cpu_env
, twd
, tws
, twt
);
28738 gen_helper_msa_cle_s_w(cpu_env
, twd
, tws
, twt
);
28741 gen_helper_msa_cle_s_d(cpu_env
, twd
, tws
, twt
);
28748 gen_helper_msa_cle_u_b(cpu_env
, twd
, tws
, twt
);
28751 gen_helper_msa_cle_u_h(cpu_env
, twd
, tws
, twt
);
28754 gen_helper_msa_cle_u_w(cpu_env
, twd
, tws
, twt
);
28757 gen_helper_msa_cle_u_d(cpu_env
, twd
, tws
, twt
);
28764 gen_helper_msa_clt_s_b(cpu_env
, twd
, tws
, twt
);
28767 gen_helper_msa_clt_s_h(cpu_env
, twd
, tws
, twt
);
28770 gen_helper_msa_clt_s_w(cpu_env
, twd
, tws
, twt
);
28773 gen_helper_msa_clt_s_d(cpu_env
, twd
, tws
, twt
);
28780 gen_helper_msa_clt_u_b(cpu_env
, twd
, tws
, twt
);
28783 gen_helper_msa_clt_u_h(cpu_env
, twd
, tws
, twt
);
28786 gen_helper_msa_clt_u_w(cpu_env
, twd
, tws
, twt
);
28789 gen_helper_msa_clt_u_d(cpu_env
, twd
, tws
, twt
);
28796 gen_helper_msa_div_s_b(cpu_env
, twd
, tws
, twt
);
28799 gen_helper_msa_div_s_h(cpu_env
, twd
, tws
, twt
);
28802 gen_helper_msa_div_s_w(cpu_env
, twd
, tws
, twt
);
28805 gen_helper_msa_div_s_d(cpu_env
, twd
, tws
, twt
);
28812 gen_helper_msa_div_u_b(cpu_env
, twd
, tws
, twt
);
28815 gen_helper_msa_div_u_h(cpu_env
, twd
, tws
, twt
);
28818 gen_helper_msa_div_u_w(cpu_env
, twd
, tws
, twt
);
28821 gen_helper_msa_div_u_d(cpu_env
, twd
, tws
, twt
);
28828 gen_helper_msa_max_a_b(cpu_env
, twd
, tws
, twt
);
28831 gen_helper_msa_max_a_h(cpu_env
, twd
, tws
, twt
);
28834 gen_helper_msa_max_a_w(cpu_env
, twd
, tws
, twt
);
28837 gen_helper_msa_max_a_d(cpu_env
, twd
, tws
, twt
);
28844 gen_helper_msa_max_s_b(cpu_env
, twd
, tws
, twt
);
28847 gen_helper_msa_max_s_h(cpu_env
, twd
, tws
, twt
);
28850 gen_helper_msa_max_s_w(cpu_env
, twd
, tws
, twt
);
28853 gen_helper_msa_max_s_d(cpu_env
, twd
, tws
, twt
);
28860 gen_helper_msa_max_u_b(cpu_env
, twd
, tws
, twt
);
28863 gen_helper_msa_max_u_h(cpu_env
, twd
, tws
, twt
);
28866 gen_helper_msa_max_u_w(cpu_env
, twd
, tws
, twt
);
28869 gen_helper_msa_max_u_d(cpu_env
, twd
, tws
, twt
);
28876 gen_helper_msa_min_a_b(cpu_env
, twd
, tws
, twt
);
28879 gen_helper_msa_min_a_h(cpu_env
, twd
, tws
, twt
);
28882 gen_helper_msa_min_a_w(cpu_env
, twd
, tws
, twt
);
28885 gen_helper_msa_min_a_d(cpu_env
, twd
, tws
, twt
);
28892 gen_helper_msa_min_s_b(cpu_env
, twd
, tws
, twt
);
28895 gen_helper_msa_min_s_h(cpu_env
, twd
, tws
, twt
);
28898 gen_helper_msa_min_s_w(cpu_env
, twd
, tws
, twt
);
28901 gen_helper_msa_min_s_d(cpu_env
, twd
, tws
, twt
);
28908 gen_helper_msa_min_u_b(cpu_env
, twd
, tws
, twt
);
28911 gen_helper_msa_min_u_h(cpu_env
, twd
, tws
, twt
);
28914 gen_helper_msa_min_u_w(cpu_env
, twd
, tws
, twt
);
28917 gen_helper_msa_min_u_d(cpu_env
, twd
, tws
, twt
);
28924 gen_helper_msa_mod_s_b(cpu_env
, twd
, tws
, twt
);
28927 gen_helper_msa_mod_s_h(cpu_env
, twd
, tws
, twt
);
28930 gen_helper_msa_mod_s_w(cpu_env
, twd
, tws
, twt
);
28933 gen_helper_msa_mod_s_d(cpu_env
, twd
, tws
, twt
);
28940 gen_helper_msa_mod_u_b(cpu_env
, twd
, tws
, twt
);
28943 gen_helper_msa_mod_u_h(cpu_env
, twd
, tws
, twt
);
28946 gen_helper_msa_mod_u_w(cpu_env
, twd
, tws
, twt
);
28949 gen_helper_msa_mod_u_d(cpu_env
, twd
, tws
, twt
);
28953 case OPC_ASUB_S_df
:
28956 gen_helper_msa_asub_s_b(cpu_env
, twd
, tws
, twt
);
28959 gen_helper_msa_asub_s_h(cpu_env
, twd
, tws
, twt
);
28962 gen_helper_msa_asub_s_w(cpu_env
, twd
, tws
, twt
);
28965 gen_helper_msa_asub_s_d(cpu_env
, twd
, tws
, twt
);
28969 case OPC_ASUB_U_df
:
28972 gen_helper_msa_asub_u_b(cpu_env
, twd
, tws
, twt
);
28975 gen_helper_msa_asub_u_h(cpu_env
, twd
, tws
, twt
);
28978 gen_helper_msa_asub_u_w(cpu_env
, twd
, tws
, twt
);
28981 gen_helper_msa_asub_u_d(cpu_env
, twd
, tws
, twt
);
28988 gen_helper_msa_ilvev_b(cpu_env
, twd
, tws
, twt
);
28991 gen_helper_msa_ilvev_h(cpu_env
, twd
, tws
, twt
);
28994 gen_helper_msa_ilvev_w(cpu_env
, twd
, tws
, twt
);
28997 gen_helper_msa_ilvev_d(cpu_env
, twd
, tws
, twt
);
29004 gen_helper_msa_ilvod_b(cpu_env
, twd
, tws
, twt
);
29007 gen_helper_msa_ilvod_h(cpu_env
, twd
, tws
, twt
);
29010 gen_helper_msa_ilvod_w(cpu_env
, twd
, tws
, twt
);
29013 gen_helper_msa_ilvod_d(cpu_env
, twd
, tws
, twt
);
29020 gen_helper_msa_ilvl_b(cpu_env
, twd
, tws
, twt
);
29023 gen_helper_msa_ilvl_h(cpu_env
, twd
, tws
, twt
);
29026 gen_helper_msa_ilvl_w(cpu_env
, twd
, tws
, twt
);
29029 gen_helper_msa_ilvl_d(cpu_env
, twd
, tws
, twt
);
29036 gen_helper_msa_ilvr_b(cpu_env
, twd
, tws
, twt
);
29039 gen_helper_msa_ilvr_h(cpu_env
, twd
, tws
, twt
);
29042 gen_helper_msa_ilvr_w(cpu_env
, twd
, tws
, twt
);
29045 gen_helper_msa_ilvr_d(cpu_env
, twd
, tws
, twt
);
29052 gen_helper_msa_pckev_b(cpu_env
, twd
, tws
, twt
);
29055 gen_helper_msa_pckev_h(cpu_env
, twd
, tws
, twt
);
29058 gen_helper_msa_pckev_w(cpu_env
, twd
, tws
, twt
);
29061 gen_helper_msa_pckev_d(cpu_env
, twd
, tws
, twt
);
29068 gen_helper_msa_pckod_b(cpu_env
, twd
, tws
, twt
);
29071 gen_helper_msa_pckod_h(cpu_env
, twd
, tws
, twt
);
29074 gen_helper_msa_pckod_w(cpu_env
, twd
, tws
, twt
);
29077 gen_helper_msa_pckod_d(cpu_env
, twd
, tws
, twt
);
29084 gen_helper_msa_sll_b(cpu_env
, twd
, tws
, twt
);
29087 gen_helper_msa_sll_h(cpu_env
, twd
, tws
, twt
);
29090 gen_helper_msa_sll_w(cpu_env
, twd
, tws
, twt
);
29093 gen_helper_msa_sll_d(cpu_env
, twd
, tws
, twt
);
29100 gen_helper_msa_sra_b(cpu_env
, twd
, tws
, twt
);
29103 gen_helper_msa_sra_h(cpu_env
, twd
, tws
, twt
);
29106 gen_helper_msa_sra_w(cpu_env
, twd
, tws
, twt
);
29109 gen_helper_msa_sra_d(cpu_env
, twd
, tws
, twt
);
29116 gen_helper_msa_srar_b(cpu_env
, twd
, tws
, twt
);
29119 gen_helper_msa_srar_h(cpu_env
, twd
, tws
, twt
);
29122 gen_helper_msa_srar_w(cpu_env
, twd
, tws
, twt
);
29125 gen_helper_msa_srar_d(cpu_env
, twd
, tws
, twt
);
29132 gen_helper_msa_srl_b(cpu_env
, twd
, tws
, twt
);
29135 gen_helper_msa_srl_h(cpu_env
, twd
, tws
, twt
);
29138 gen_helper_msa_srl_w(cpu_env
, twd
, tws
, twt
);
29141 gen_helper_msa_srl_d(cpu_env
, twd
, tws
, twt
);
29148 gen_helper_msa_srlr_b(cpu_env
, twd
, tws
, twt
);
29151 gen_helper_msa_srlr_h(cpu_env
, twd
, tws
, twt
);
29154 gen_helper_msa_srlr_w(cpu_env
, twd
, tws
, twt
);
29157 gen_helper_msa_srlr_d(cpu_env
, twd
, tws
, twt
);
29161 case OPC_SUBS_S_df
:
29162 gen_helper_msa_subs_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
29165 gen_helper_msa_mulv_df(cpu_env
, tdf
, twd
, tws
, twt
);
29168 gen_helper_msa_sld_df(cpu_env
, tdf
, twd
, tws
, twt
);
29171 gen_helper_msa_vshf_df(cpu_env
, tdf
, twd
, tws
, twt
);
29174 gen_helper_msa_subv_df(cpu_env
, tdf
, twd
, tws
, twt
);
29176 case OPC_SUBS_U_df
:
29177 gen_helper_msa_subs_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
29180 gen_helper_msa_maddv_df(cpu_env
, tdf
, twd
, tws
, twt
);
29183 gen_helper_msa_splat_df(cpu_env
, tdf
, twd
, tws
, twt
);
29185 case OPC_SUBSUS_U_df
:
29186 gen_helper_msa_subsus_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
29189 gen_helper_msa_msubv_df(cpu_env
, tdf
, twd
, tws
, twt
);
29191 case OPC_SUBSUU_S_df
:
29192 gen_helper_msa_subsuu_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
29195 case OPC_DOTP_S_df
:
29196 case OPC_DOTP_U_df
:
29197 case OPC_DPADD_S_df
:
29198 case OPC_DPADD_U_df
:
29199 case OPC_DPSUB_S_df
:
29200 case OPC_HADD_S_df
:
29201 case OPC_DPSUB_U_df
:
29202 case OPC_HADD_U_df
:
29203 case OPC_HSUB_S_df
:
29204 case OPC_HSUB_U_df
:
29205 if (df
== DF_BYTE
) {
29206 generate_exception_end(ctx
, EXCP_RI
);
29209 switch (MASK_MSA_3R(ctx
->opcode
)) {
29210 case OPC_HADD_S_df
:
29213 gen_helper_msa_hadd_s_h(cpu_env
, twd
, tws
, twt
);
29216 gen_helper_msa_hadd_s_w(cpu_env
, twd
, tws
, twt
);
29219 gen_helper_msa_hadd_s_d(cpu_env
, twd
, tws
, twt
);
29223 case OPC_HADD_U_df
:
29226 gen_helper_msa_hadd_u_h(cpu_env
, twd
, tws
, twt
);
29229 gen_helper_msa_hadd_u_w(cpu_env
, twd
, tws
, twt
);
29232 gen_helper_msa_hadd_u_d(cpu_env
, twd
, tws
, twt
);
29236 case OPC_HSUB_S_df
:
29239 gen_helper_msa_hsub_s_h(cpu_env
, twd
, tws
, twt
);
29242 gen_helper_msa_hsub_s_w(cpu_env
, twd
, tws
, twt
);
29245 gen_helper_msa_hsub_s_d(cpu_env
, twd
, tws
, twt
);
29249 case OPC_HSUB_U_df
:
29252 gen_helper_msa_hsub_u_h(cpu_env
, twd
, tws
, twt
);
29255 gen_helper_msa_hsub_u_w(cpu_env
, twd
, tws
, twt
);
29258 gen_helper_msa_hsub_u_d(cpu_env
, twd
, tws
, twt
);
29262 case OPC_DOTP_S_df
:
29263 gen_helper_msa_dotp_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
29265 case OPC_DOTP_U_df
:
29266 gen_helper_msa_dotp_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
29268 case OPC_DPADD_S_df
:
29269 gen_helper_msa_dpadd_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
29271 case OPC_DPADD_U_df
:
29272 gen_helper_msa_dpadd_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
29274 case OPC_DPSUB_S_df
:
29275 gen_helper_msa_dpsub_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
29277 case OPC_DPSUB_U_df
:
29278 gen_helper_msa_dpsub_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
29283 MIPS_INVAL("MSA instruction");
29284 generate_exception_end(ctx
, EXCP_RI
);
29287 tcg_temp_free_i32(twd
);
29288 tcg_temp_free_i32(tws
);
29289 tcg_temp_free_i32(twt
);
29290 tcg_temp_free_i32(tdf
);
29293 static void gen_msa_elm_3e(CPUMIPSState
*env
, DisasContext
*ctx
)
29295 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
29296 uint8_t source
= (ctx
->opcode
>> 11) & 0x1f;
29297 uint8_t dest
= (ctx
->opcode
>> 6) & 0x1f;
29298 TCGv telm
= tcg_temp_new();
29299 TCGv_i32 tsr
= tcg_const_i32(source
);
29300 TCGv_i32 tdt
= tcg_const_i32(dest
);
29302 switch (MASK_MSA_ELM_DF3E(ctx
->opcode
)) {
29304 gen_load_gpr(telm
, source
);
29305 gen_helper_msa_ctcmsa(cpu_env
, telm
, tdt
);
29308 gen_helper_msa_cfcmsa(telm
, cpu_env
, tsr
);
29309 gen_store_gpr(telm
, dest
);
29312 gen_helper_msa_move_v(cpu_env
, tdt
, tsr
);
29315 MIPS_INVAL("MSA instruction");
29316 generate_exception_end(ctx
, EXCP_RI
);
29320 tcg_temp_free(telm
);
29321 tcg_temp_free_i32(tdt
);
29322 tcg_temp_free_i32(tsr
);
29325 static void gen_msa_elm_df(CPUMIPSState
*env
, DisasContext
*ctx
, uint32_t df
,
29328 #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
29329 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
29330 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
29332 TCGv_i32 tws
= tcg_const_i32(ws
);
29333 TCGv_i32 twd
= tcg_const_i32(wd
);
29334 TCGv_i32 tn
= tcg_const_i32(n
);
29335 TCGv_i32 tdf
= tcg_const_i32(df
);
29337 switch (MASK_MSA_ELM(ctx
->opcode
)) {
29339 gen_helper_msa_sldi_df(cpu_env
, tdf
, twd
, tws
, tn
);
29341 case OPC_SPLATI_df
:
29342 gen_helper_msa_splati_df(cpu_env
, tdf
, twd
, tws
, tn
);
29345 gen_helper_msa_insve_df(cpu_env
, tdf
, twd
, tws
, tn
);
29347 case OPC_COPY_S_df
:
29348 case OPC_COPY_U_df
:
29349 case OPC_INSERT_df
:
29350 #if !defined(TARGET_MIPS64)
29351 /* Double format valid only for MIPS64 */
29352 if (df
== DF_DOUBLE
) {
29353 generate_exception_end(ctx
, EXCP_RI
);
29356 if ((MASK_MSA_ELM(ctx
->opcode
) == OPC_COPY_U_df
) &&
29358 generate_exception_end(ctx
, EXCP_RI
);
29362 switch (MASK_MSA_ELM(ctx
->opcode
)) {
29363 case OPC_COPY_S_df
:
29364 if (likely(wd
!= 0)) {
29367 gen_helper_msa_copy_s_b(cpu_env
, twd
, tws
, tn
);
29370 gen_helper_msa_copy_s_h(cpu_env
, twd
, tws
, tn
);
29373 gen_helper_msa_copy_s_w(cpu_env
, twd
, tws
, tn
);
29375 #if defined(TARGET_MIPS64)
29377 gen_helper_msa_copy_s_d(cpu_env
, twd
, tws
, tn
);
29385 case OPC_COPY_U_df
:
29386 if (likely(wd
!= 0)) {
29389 gen_helper_msa_copy_u_b(cpu_env
, twd
, tws
, tn
);
29392 gen_helper_msa_copy_u_h(cpu_env
, twd
, tws
, tn
);
29394 #if defined(TARGET_MIPS64)
29396 gen_helper_msa_copy_u_w(cpu_env
, twd
, tws
, tn
);
29404 case OPC_INSERT_df
:
29407 gen_helper_msa_insert_b(cpu_env
, twd
, tws
, tn
);
29410 gen_helper_msa_insert_h(cpu_env
, twd
, tws
, tn
);
29413 gen_helper_msa_insert_w(cpu_env
, twd
, tws
, tn
);
29415 #if defined(TARGET_MIPS64)
29417 gen_helper_msa_insert_d(cpu_env
, twd
, tws
, tn
);
29427 MIPS_INVAL("MSA instruction");
29428 generate_exception_end(ctx
, EXCP_RI
);
29430 tcg_temp_free_i32(twd
);
29431 tcg_temp_free_i32(tws
);
29432 tcg_temp_free_i32(tn
);
29433 tcg_temp_free_i32(tdf
);
29436 static void gen_msa_elm(CPUMIPSState
*env
, DisasContext
*ctx
)
29438 uint8_t dfn
= (ctx
->opcode
>> 16) & 0x3f;
29439 uint32_t df
= 0, n
= 0;
29441 if ((dfn
& 0x30) == 0x00) {
29444 } else if ((dfn
& 0x38) == 0x20) {
29447 } else if ((dfn
& 0x3c) == 0x30) {
29450 } else if ((dfn
& 0x3e) == 0x38) {
29453 } else if (dfn
== 0x3E) {
29454 /* CTCMSA, CFCMSA, MOVE.V */
29455 gen_msa_elm_3e(env
, ctx
);
29458 generate_exception_end(ctx
, EXCP_RI
);
29462 gen_msa_elm_df(env
, ctx
, df
, n
);
29465 static void gen_msa_3rf(CPUMIPSState
*env
, DisasContext
*ctx
)
29467 #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
29468 uint8_t df
= (ctx
->opcode
>> 21) & 0x1;
29469 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
29470 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
29471 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
29473 TCGv_i32 twd
= tcg_const_i32(wd
);
29474 TCGv_i32 tws
= tcg_const_i32(ws
);
29475 TCGv_i32 twt
= tcg_const_i32(wt
);
29476 TCGv_i32 tdf
= tcg_temp_new_i32();
29478 /* adjust df value for floating-point instruction */
29479 tcg_gen_movi_i32(tdf
, df
+ 2);
29481 switch (MASK_MSA_3RF(ctx
->opcode
)) {
29483 gen_helper_msa_fcaf_df(cpu_env
, tdf
, twd
, tws
, twt
);
29486 gen_helper_msa_fadd_df(cpu_env
, tdf
, twd
, tws
, twt
);
29489 gen_helper_msa_fcun_df(cpu_env
, tdf
, twd
, tws
, twt
);
29492 gen_helper_msa_fsub_df(cpu_env
, tdf
, twd
, tws
, twt
);
29495 gen_helper_msa_fcor_df(cpu_env
, tdf
, twd
, tws
, twt
);
29498 gen_helper_msa_fceq_df(cpu_env
, tdf
, twd
, tws
, twt
);
29501 gen_helper_msa_fmul_df(cpu_env
, tdf
, twd
, tws
, twt
);
29504 gen_helper_msa_fcune_df(cpu_env
, tdf
, twd
, tws
, twt
);
29507 gen_helper_msa_fcueq_df(cpu_env
, tdf
, twd
, tws
, twt
);
29510 gen_helper_msa_fdiv_df(cpu_env
, tdf
, twd
, tws
, twt
);
29513 gen_helper_msa_fcne_df(cpu_env
, tdf
, twd
, tws
, twt
);
29516 gen_helper_msa_fclt_df(cpu_env
, tdf
, twd
, tws
, twt
);
29519 gen_helper_msa_fmadd_df(cpu_env
, tdf
, twd
, tws
, twt
);
29522 tcg_gen_movi_i32(tdf
, df
+ 1);
29523 gen_helper_msa_mul_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
29526 gen_helper_msa_fcult_df(cpu_env
, tdf
, twd
, tws
, twt
);
29529 gen_helper_msa_fmsub_df(cpu_env
, tdf
, twd
, tws
, twt
);
29531 case OPC_MADD_Q_df
:
29532 tcg_gen_movi_i32(tdf
, df
+ 1);
29533 gen_helper_msa_madd_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
29536 gen_helper_msa_fcle_df(cpu_env
, tdf
, twd
, tws
, twt
);
29538 case OPC_MSUB_Q_df
:
29539 tcg_gen_movi_i32(tdf
, df
+ 1);
29540 gen_helper_msa_msub_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
29543 gen_helper_msa_fcule_df(cpu_env
, tdf
, twd
, tws
, twt
);
29546 gen_helper_msa_fexp2_df(cpu_env
, tdf
, twd
, tws
, twt
);
29549 gen_helper_msa_fsaf_df(cpu_env
, tdf
, twd
, tws
, twt
);
29552 gen_helper_msa_fexdo_df(cpu_env
, tdf
, twd
, tws
, twt
);
29555 gen_helper_msa_fsun_df(cpu_env
, tdf
, twd
, tws
, twt
);
29558 gen_helper_msa_fsor_df(cpu_env
, tdf
, twd
, tws
, twt
);
29561 gen_helper_msa_fseq_df(cpu_env
, tdf
, twd
, tws
, twt
);
29564 gen_helper_msa_ftq_df(cpu_env
, tdf
, twd
, tws
, twt
);
29567 gen_helper_msa_fsune_df(cpu_env
, tdf
, twd
, tws
, twt
);
29570 gen_helper_msa_fsueq_df(cpu_env
, tdf
, twd
, tws
, twt
);
29573 gen_helper_msa_fsne_df(cpu_env
, tdf
, twd
, tws
, twt
);
29576 gen_helper_msa_fslt_df(cpu_env
, tdf
, twd
, tws
, twt
);
29579 gen_helper_msa_fmin_df(cpu_env
, tdf
, twd
, tws
, twt
);
29581 case OPC_MULR_Q_df
:
29582 tcg_gen_movi_i32(tdf
, df
+ 1);
29583 gen_helper_msa_mulr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
29586 gen_helper_msa_fsult_df(cpu_env
, tdf
, twd
, tws
, twt
);
29588 case OPC_FMIN_A_df
:
29589 gen_helper_msa_fmin_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
29591 case OPC_MADDR_Q_df
:
29592 tcg_gen_movi_i32(tdf
, df
+ 1);
29593 gen_helper_msa_maddr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
29596 gen_helper_msa_fsle_df(cpu_env
, tdf
, twd
, tws
, twt
);
29599 gen_helper_msa_fmax_df(cpu_env
, tdf
, twd
, tws
, twt
);
29601 case OPC_MSUBR_Q_df
:
29602 tcg_gen_movi_i32(tdf
, df
+ 1);
29603 gen_helper_msa_msubr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
29606 gen_helper_msa_fsule_df(cpu_env
, tdf
, twd
, tws
, twt
);
29608 case OPC_FMAX_A_df
:
29609 gen_helper_msa_fmax_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
29612 MIPS_INVAL("MSA instruction");
29613 generate_exception_end(ctx
, EXCP_RI
);
29617 tcg_temp_free_i32(twd
);
29618 tcg_temp_free_i32(tws
);
29619 tcg_temp_free_i32(twt
);
29620 tcg_temp_free_i32(tdf
);
29623 static void gen_msa_2r(CPUMIPSState
*env
, DisasContext
*ctx
)
29625 #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
29626 (op & (0x7 << 18)))
29627 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
29628 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
29629 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
29630 uint8_t df
= (ctx
->opcode
>> 16) & 0x3;
29631 TCGv_i32 twd
= tcg_const_i32(wd
);
29632 TCGv_i32 tws
= tcg_const_i32(ws
);
29633 TCGv_i32 twt
= tcg_const_i32(wt
);
29634 TCGv_i32 tdf
= tcg_const_i32(df
);
29636 switch (MASK_MSA_2R(ctx
->opcode
)) {
29638 #if !defined(TARGET_MIPS64)
29639 /* Double format valid only for MIPS64 */
29640 if (df
== DF_DOUBLE
) {
29641 generate_exception_end(ctx
, EXCP_RI
);
29645 gen_helper_msa_fill_df(cpu_env
, tdf
, twd
, tws
); /* trs */
29650 gen_helper_msa_nloc_b(cpu_env
, twd
, tws
);
29653 gen_helper_msa_nloc_h(cpu_env
, twd
, tws
);
29656 gen_helper_msa_nloc_w(cpu_env
, twd
, tws
);
29659 gen_helper_msa_nloc_d(cpu_env
, twd
, tws
);
29666 gen_helper_msa_nlzc_b(cpu_env
, twd
, tws
);
29669 gen_helper_msa_nlzc_h(cpu_env
, twd
, tws
);
29672 gen_helper_msa_nlzc_w(cpu_env
, twd
, tws
);
29675 gen_helper_msa_nlzc_d(cpu_env
, twd
, tws
);
29682 gen_helper_msa_pcnt_b(cpu_env
, twd
, tws
);
29685 gen_helper_msa_pcnt_h(cpu_env
, twd
, tws
);
29688 gen_helper_msa_pcnt_w(cpu_env
, twd
, tws
);
29691 gen_helper_msa_pcnt_d(cpu_env
, twd
, tws
);
29696 MIPS_INVAL("MSA instruction");
29697 generate_exception_end(ctx
, EXCP_RI
);
29701 tcg_temp_free_i32(twd
);
29702 tcg_temp_free_i32(tws
);
29703 tcg_temp_free_i32(twt
);
29704 tcg_temp_free_i32(tdf
);
29707 static void gen_msa_2rf(CPUMIPSState
*env
, DisasContext
*ctx
)
29709 #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
29710 (op & (0xf << 17)))
29711 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
29712 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
29713 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
29714 uint8_t df
= (ctx
->opcode
>> 16) & 0x1;
29715 TCGv_i32 twd
= tcg_const_i32(wd
);
29716 TCGv_i32 tws
= tcg_const_i32(ws
);
29717 TCGv_i32 twt
= tcg_const_i32(wt
);
29718 /* adjust df value for floating-point instruction */
29719 TCGv_i32 tdf
= tcg_const_i32(df
+ 2);
29721 switch (MASK_MSA_2RF(ctx
->opcode
)) {
29722 case OPC_FCLASS_df
:
29723 gen_helper_msa_fclass_df(cpu_env
, tdf
, twd
, tws
);
29725 case OPC_FTRUNC_S_df
:
29726 gen_helper_msa_ftrunc_s_df(cpu_env
, tdf
, twd
, tws
);
29728 case OPC_FTRUNC_U_df
:
29729 gen_helper_msa_ftrunc_u_df(cpu_env
, tdf
, twd
, tws
);
29732 gen_helper_msa_fsqrt_df(cpu_env
, tdf
, twd
, tws
);
29734 case OPC_FRSQRT_df
:
29735 gen_helper_msa_frsqrt_df(cpu_env
, tdf
, twd
, tws
);
29738 gen_helper_msa_frcp_df(cpu_env
, tdf
, twd
, tws
);
29741 gen_helper_msa_frint_df(cpu_env
, tdf
, twd
, tws
);
29744 gen_helper_msa_flog2_df(cpu_env
, tdf
, twd
, tws
);
29746 case OPC_FEXUPL_df
:
29747 gen_helper_msa_fexupl_df(cpu_env
, tdf
, twd
, tws
);
29749 case OPC_FEXUPR_df
:
29750 gen_helper_msa_fexupr_df(cpu_env
, tdf
, twd
, tws
);
29753 gen_helper_msa_ffql_df(cpu_env
, tdf
, twd
, tws
);
29756 gen_helper_msa_ffqr_df(cpu_env
, tdf
, twd
, tws
);
29758 case OPC_FTINT_S_df
:
29759 gen_helper_msa_ftint_s_df(cpu_env
, tdf
, twd
, tws
);
29761 case OPC_FTINT_U_df
:
29762 gen_helper_msa_ftint_u_df(cpu_env
, tdf
, twd
, tws
);
29764 case OPC_FFINT_S_df
:
29765 gen_helper_msa_ffint_s_df(cpu_env
, tdf
, twd
, tws
);
29767 case OPC_FFINT_U_df
:
29768 gen_helper_msa_ffint_u_df(cpu_env
, tdf
, twd
, tws
);
29772 tcg_temp_free_i32(twd
);
29773 tcg_temp_free_i32(tws
);
29774 tcg_temp_free_i32(twt
);
29775 tcg_temp_free_i32(tdf
);
29778 static void gen_msa_vec_v(CPUMIPSState
*env
, DisasContext
*ctx
)
29780 #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
29781 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
29782 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
29783 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
29784 TCGv_i32 twd
= tcg_const_i32(wd
);
29785 TCGv_i32 tws
= tcg_const_i32(ws
);
29786 TCGv_i32 twt
= tcg_const_i32(wt
);
29788 switch (MASK_MSA_VEC(ctx
->opcode
)) {
29790 gen_helper_msa_and_v(cpu_env
, twd
, tws
, twt
);
29793 gen_helper_msa_or_v(cpu_env
, twd
, tws
, twt
);
29796 gen_helper_msa_nor_v(cpu_env
, twd
, tws
, twt
);
29799 gen_helper_msa_xor_v(cpu_env
, twd
, tws
, twt
);
29802 gen_helper_msa_bmnz_v(cpu_env
, twd
, tws
, twt
);
29805 gen_helper_msa_bmz_v(cpu_env
, twd
, tws
, twt
);
29808 gen_helper_msa_bsel_v(cpu_env
, twd
, tws
, twt
);
29811 MIPS_INVAL("MSA instruction");
29812 generate_exception_end(ctx
, EXCP_RI
);
29816 tcg_temp_free_i32(twd
);
29817 tcg_temp_free_i32(tws
);
29818 tcg_temp_free_i32(twt
);
29821 static void gen_msa_vec(CPUMIPSState
*env
, DisasContext
*ctx
)
29823 switch (MASK_MSA_VEC(ctx
->opcode
)) {
29831 gen_msa_vec_v(env
, ctx
);
29834 gen_msa_2r(env
, ctx
);
29837 gen_msa_2rf(env
, ctx
);
29840 MIPS_INVAL("MSA instruction");
29841 generate_exception_end(ctx
, EXCP_RI
);
29846 static void gen_msa(CPUMIPSState
*env
, DisasContext
*ctx
)
29848 uint32_t opcode
= ctx
->opcode
;
29849 check_insn(ctx
, ASE_MSA
);
29850 check_msa_access(ctx
);
29852 switch (MASK_MSA_MINOR(opcode
)) {
29853 case OPC_MSA_I8_00
:
29854 case OPC_MSA_I8_01
:
29855 case OPC_MSA_I8_02
:
29856 gen_msa_i8(env
, ctx
);
29858 case OPC_MSA_I5_06
:
29859 case OPC_MSA_I5_07
:
29860 gen_msa_i5(env
, ctx
);
29862 case OPC_MSA_BIT_09
:
29863 case OPC_MSA_BIT_0A
:
29864 gen_msa_bit(env
, ctx
);
29866 case OPC_MSA_3R_0D
:
29867 case OPC_MSA_3R_0E
:
29868 case OPC_MSA_3R_0F
:
29869 case OPC_MSA_3R_10
:
29870 case OPC_MSA_3R_11
:
29871 case OPC_MSA_3R_12
:
29872 case OPC_MSA_3R_13
:
29873 case OPC_MSA_3R_14
:
29874 case OPC_MSA_3R_15
:
29875 gen_msa_3r(env
, ctx
);
29878 gen_msa_elm(env
, ctx
);
29880 case OPC_MSA_3RF_1A
:
29881 case OPC_MSA_3RF_1B
:
29882 case OPC_MSA_3RF_1C
:
29883 gen_msa_3rf(env
, ctx
);
29886 gen_msa_vec(env
, ctx
);
29897 int32_t s10
= sextract32(ctx
->opcode
, 16, 10);
29898 uint8_t rs
= (ctx
->opcode
>> 11) & 0x1f;
29899 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
29900 uint8_t df
= (ctx
->opcode
>> 0) & 0x3;
29902 TCGv_i32 twd
= tcg_const_i32(wd
);
29903 TCGv taddr
= tcg_temp_new();
29904 gen_base_offset_addr(ctx
, taddr
, rs
, s10
<< df
);
29906 switch (MASK_MSA_MINOR(opcode
)) {
29908 gen_helper_msa_ld_b(cpu_env
, twd
, taddr
);
29911 gen_helper_msa_ld_h(cpu_env
, twd
, taddr
);
29914 gen_helper_msa_ld_w(cpu_env
, twd
, taddr
);
29917 gen_helper_msa_ld_d(cpu_env
, twd
, taddr
);
29920 gen_helper_msa_st_b(cpu_env
, twd
, taddr
);
29923 gen_helper_msa_st_h(cpu_env
, twd
, taddr
);
29926 gen_helper_msa_st_w(cpu_env
, twd
, taddr
);
29929 gen_helper_msa_st_d(cpu_env
, twd
, taddr
);
29933 tcg_temp_free_i32(twd
);
29934 tcg_temp_free(taddr
);
29938 MIPS_INVAL("MSA instruction");
29939 generate_exception_end(ctx
, EXCP_RI
);
29945 static void decode_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
29948 int rs
, rt
, rd
, sa
;
29952 /* make sure instructions are on a word boundary */
29953 if (ctx
->base
.pc_next
& 0x3) {
29954 env
->CP0_BadVAddr
= ctx
->base
.pc_next
;
29955 generate_exception_err(ctx
, EXCP_AdEL
, EXCP_INST_NOTAVAIL
);
29959 /* Handle blikely not taken case */
29960 if ((ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) == MIPS_HFLAG_BL
) {
29961 TCGLabel
*l1
= gen_new_label();
29963 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
29964 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
29965 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
+ 4);
29969 op
= MASK_OP_MAJOR(ctx
->opcode
);
29970 rs
= (ctx
->opcode
>> 21) & 0x1f;
29971 rt
= (ctx
->opcode
>> 16) & 0x1f;
29972 rd
= (ctx
->opcode
>> 11) & 0x1f;
29973 sa
= (ctx
->opcode
>> 6) & 0x1f;
29974 imm
= (int16_t)ctx
->opcode
;
29977 decode_opc_special(env
, ctx
);
29980 #if defined(TARGET_MIPS64)
29981 if ((ctx
->insn_flags
& INSN_R5900
) && (ctx
->insn_flags
& ASE_MMI
)) {
29982 decode_mmi(env
, ctx
);
29984 if (ctx
->insn_flags
& ASE_MXU
) {
29985 decode_opc_mxu(env
, ctx
);
29988 decode_opc_special2_legacy(env
, ctx
);
29992 #if defined(TARGET_MIPS64)
29993 if (ctx
->insn_flags
& INSN_R5900
) {
29994 decode_mmi_sq(env
, ctx
); /* MMI_OPC_SQ */
29996 decode_opc_special3(env
, ctx
);
29999 decode_opc_special3(env
, ctx
);
30003 op1
= MASK_REGIMM(ctx
->opcode
);
30005 case OPC_BLTZL
: /* REGIMM branches */
30009 check_insn(ctx
, ISA_MIPS2
);
30010 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30014 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2, 4);
30018 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30020 /* OPC_NAL, OPC_BAL */
30021 gen_compute_branch(ctx
, op1
, 4, 0, -1, imm
<< 2, 4);
30023 generate_exception_end(ctx
, EXCP_RI
);
30026 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2, 4);
30029 case OPC_TGEI
: /* REGIMM traps */
30036 check_insn(ctx
, ISA_MIPS2
);
30037 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30038 gen_trap(ctx
, op1
, rs
, -1, imm
);
30041 check_insn(ctx
, ISA_MIPS32R6
);
30042 generate_exception_end(ctx
, EXCP_RI
);
30045 check_insn(ctx
, ISA_MIPS32R2
);
30047 * Break the TB to be able to sync copied instructions
30050 ctx
->base
.is_jmp
= DISAS_STOP
;
30052 case OPC_BPOSGE32
: /* MIPS DSP branch */
30053 #if defined(TARGET_MIPS64)
30057 gen_compute_branch(ctx
, op1
, 4, -1, -2, (int32_t)imm
<< 2, 4);
30059 #if defined(TARGET_MIPS64)
30061 check_insn(ctx
, ISA_MIPS32R6
);
30062 check_mips_64(ctx
);
30064 tcg_gen_addi_tl(cpu_gpr
[rs
], cpu_gpr
[rs
], (int64_t)imm
<< 32);
30068 check_insn(ctx
, ISA_MIPS32R6
);
30069 check_mips_64(ctx
);
30071 tcg_gen_addi_tl(cpu_gpr
[rs
], cpu_gpr
[rs
], (int64_t)imm
<< 48);
30075 default: /* Invalid */
30076 MIPS_INVAL("regimm");
30077 generate_exception_end(ctx
, EXCP_RI
);
30082 check_cp0_enabled(ctx
);
30083 op1
= MASK_CP0(ctx
->opcode
);
30091 #if defined(TARGET_MIPS64)
30095 #ifndef CONFIG_USER_ONLY
30096 gen_cp0(env
, ctx
, op1
, rt
, rd
);
30097 #endif /* !CONFIG_USER_ONLY */
30115 #ifndef CONFIG_USER_ONLY
30116 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
30117 #endif /* !CONFIG_USER_ONLY */
30120 #ifndef CONFIG_USER_ONLY
30123 TCGv t0
= tcg_temp_new();
30125 op2
= MASK_MFMC0(ctx
->opcode
);
30129 gen_helper_dmt(t0
);
30130 gen_store_gpr(t0
, rt
);
30134 gen_helper_emt(t0
);
30135 gen_store_gpr(t0
, rt
);
30139 gen_helper_dvpe(t0
, cpu_env
);
30140 gen_store_gpr(t0
, rt
);
30144 gen_helper_evpe(t0
, cpu_env
);
30145 gen_store_gpr(t0
, rt
);
30148 check_insn(ctx
, ISA_MIPS32R6
);
30150 gen_helper_dvp(t0
, cpu_env
);
30151 gen_store_gpr(t0
, rt
);
30155 check_insn(ctx
, ISA_MIPS32R6
);
30157 gen_helper_evp(t0
, cpu_env
);
30158 gen_store_gpr(t0
, rt
);
30162 check_insn(ctx
, ISA_MIPS32R2
);
30163 save_cpu_state(ctx
, 1);
30164 gen_helper_di(t0
, cpu_env
);
30165 gen_store_gpr(t0
, rt
);
30167 * Stop translation as we may have switched
30168 * the execution mode.
30170 ctx
->base
.is_jmp
= DISAS_STOP
;
30173 check_insn(ctx
, ISA_MIPS32R2
);
30174 save_cpu_state(ctx
, 1);
30175 gen_helper_ei(t0
, cpu_env
);
30176 gen_store_gpr(t0
, rt
);
30178 * DISAS_STOP isn't sufficient, we need to ensure we break
30179 * out of translated code to check for pending interrupts.
30181 gen_save_pc(ctx
->base
.pc_next
+ 4);
30182 ctx
->base
.is_jmp
= DISAS_EXIT
;
30184 default: /* Invalid */
30185 MIPS_INVAL("mfmc0");
30186 generate_exception_end(ctx
, EXCP_RI
);
30191 #endif /* !CONFIG_USER_ONLY */
30194 check_insn(ctx
, ISA_MIPS32R2
);
30195 gen_load_srsgpr(rt
, rd
);
30198 check_insn(ctx
, ISA_MIPS32R2
);
30199 gen_store_srsgpr(rt
, rd
);
30203 generate_exception_end(ctx
, EXCP_RI
);
30207 case OPC_BOVC
: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
30208 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30209 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
30210 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30213 /* Arithmetic with immediate opcode */
30214 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
30218 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
30220 case OPC_SLTI
: /* Set on less than with immediate opcode */
30222 gen_slt_imm(ctx
, op
, rt
, rs
, imm
);
30224 case OPC_ANDI
: /* Arithmetic with immediate opcode */
30225 case OPC_LUI
: /* OPC_AUI */
30228 gen_logic_imm(ctx
, op
, rt
, rs
, imm
);
30230 case OPC_J
: /* Jump */
30232 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
30233 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
, 4);
30236 case OPC_BLEZC
: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
30237 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30239 generate_exception_end(ctx
, EXCP_RI
);
30242 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
30243 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30246 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
30249 case OPC_BGTZC
: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
30250 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30252 generate_exception_end(ctx
, EXCP_RI
);
30255 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
30256 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30259 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
30262 case OPC_BLEZALC
: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
30265 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
30267 check_insn(ctx
, ISA_MIPS32R6
);
30268 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
30269 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30272 case OPC_BGTZALC
: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
30275 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
30277 check_insn(ctx
, ISA_MIPS32R6
);
30278 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
30279 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30284 check_insn(ctx
, ISA_MIPS2
);
30285 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30289 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
30291 case OPC_LL
: /* Load and stores */
30292 check_insn(ctx
, ISA_MIPS2
);
30293 if (ctx
->insn_flags
& INSN_R5900
) {
30294 check_insn_opc_user_only(ctx
, INSN_R5900
);
30299 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30307 gen_ld(ctx
, op
, rt
, rs
, imm
);
30311 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30316 gen_st(ctx
, op
, rt
, rs
, imm
);
30319 check_insn(ctx
, ISA_MIPS2
);
30320 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30321 if (ctx
->insn_flags
& INSN_R5900
) {
30322 check_insn_opc_user_only(ctx
, INSN_R5900
);
30324 gen_st_cond(ctx
, rt
, rs
, imm
, MO_TESL
, false);
30327 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30328 check_cp0_enabled(ctx
);
30329 check_insn(ctx
, ISA_MIPS3
| ISA_MIPS32
);
30330 if (ctx
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
30331 gen_cache_operation(ctx
, rt
, rs
, imm
);
30333 /* Treat as NOP. */
30336 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30337 if (ctx
->insn_flags
& INSN_R5900
) {
30338 /* Treat as NOP. */
30340 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
);
30341 /* Treat as NOP. */
30345 /* Floating point (COP1). */
30350 gen_cop1_ldst(ctx
, op
, rt
, rs
, imm
);
30354 op1
= MASK_CP1(ctx
->opcode
);
30359 check_cp1_enabled(ctx
);
30360 check_insn(ctx
, ISA_MIPS32R2
);
30366 check_cp1_enabled(ctx
);
30367 gen_cp1(ctx
, op1
, rt
, rd
);
30369 #if defined(TARGET_MIPS64)
30372 check_cp1_enabled(ctx
);
30373 check_insn(ctx
, ISA_MIPS3
);
30374 check_mips_64(ctx
);
30375 gen_cp1(ctx
, op1
, rt
, rd
);
30378 case OPC_BC1EQZ
: /* OPC_BC1ANY2 */
30379 check_cp1_enabled(ctx
);
30380 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30382 gen_compute_branch1_r6(ctx
, MASK_CP1(ctx
->opcode
),
30387 check_insn(ctx
, ASE_MIPS3D
);
30388 gen_compute_branch1(ctx
, MASK_BC1(ctx
->opcode
),
30389 (rt
>> 2) & 0x7, imm
<< 2);
30393 check_cp1_enabled(ctx
);
30394 check_insn(ctx
, ISA_MIPS32R6
);
30395 gen_compute_branch1_r6(ctx
, MASK_CP1(ctx
->opcode
),
30399 check_cp1_enabled(ctx
);
30400 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30402 check_insn(ctx
, ASE_MIPS3D
);
30405 check_cp1_enabled(ctx
);
30406 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30407 gen_compute_branch1(ctx
, MASK_BC1(ctx
->opcode
),
30408 (rt
>> 2) & 0x7, imm
<< 2);
30415 check_cp1_enabled(ctx
);
30416 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f), rt
, rd
, sa
,
30422 int r6_op
= ctx
->opcode
& FOP(0x3f, 0x1f);
30423 check_cp1_enabled(ctx
);
30424 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30426 case R6_OPC_CMP_AF_S
:
30427 case R6_OPC_CMP_UN_S
:
30428 case R6_OPC_CMP_EQ_S
:
30429 case R6_OPC_CMP_UEQ_S
:
30430 case R6_OPC_CMP_LT_S
:
30431 case R6_OPC_CMP_ULT_S
:
30432 case R6_OPC_CMP_LE_S
:
30433 case R6_OPC_CMP_ULE_S
:
30434 case R6_OPC_CMP_SAF_S
:
30435 case R6_OPC_CMP_SUN_S
:
30436 case R6_OPC_CMP_SEQ_S
:
30437 case R6_OPC_CMP_SEUQ_S
:
30438 case R6_OPC_CMP_SLT_S
:
30439 case R6_OPC_CMP_SULT_S
:
30440 case R6_OPC_CMP_SLE_S
:
30441 case R6_OPC_CMP_SULE_S
:
30442 case R6_OPC_CMP_OR_S
:
30443 case R6_OPC_CMP_UNE_S
:
30444 case R6_OPC_CMP_NE_S
:
30445 case R6_OPC_CMP_SOR_S
:
30446 case R6_OPC_CMP_SUNE_S
:
30447 case R6_OPC_CMP_SNE_S
:
30448 gen_r6_cmp_s(ctx
, ctx
->opcode
& 0x1f, rt
, rd
, sa
);
30450 case R6_OPC_CMP_AF_D
:
30451 case R6_OPC_CMP_UN_D
:
30452 case R6_OPC_CMP_EQ_D
:
30453 case R6_OPC_CMP_UEQ_D
:
30454 case R6_OPC_CMP_LT_D
:
30455 case R6_OPC_CMP_ULT_D
:
30456 case R6_OPC_CMP_LE_D
:
30457 case R6_OPC_CMP_ULE_D
:
30458 case R6_OPC_CMP_SAF_D
:
30459 case R6_OPC_CMP_SUN_D
:
30460 case R6_OPC_CMP_SEQ_D
:
30461 case R6_OPC_CMP_SEUQ_D
:
30462 case R6_OPC_CMP_SLT_D
:
30463 case R6_OPC_CMP_SULT_D
:
30464 case R6_OPC_CMP_SLE_D
:
30465 case R6_OPC_CMP_SULE_D
:
30466 case R6_OPC_CMP_OR_D
:
30467 case R6_OPC_CMP_UNE_D
:
30468 case R6_OPC_CMP_NE_D
:
30469 case R6_OPC_CMP_SOR_D
:
30470 case R6_OPC_CMP_SUNE_D
:
30471 case R6_OPC_CMP_SNE_D
:
30472 gen_r6_cmp_d(ctx
, ctx
->opcode
& 0x1f, rt
, rd
, sa
);
30475 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f),
30476 rt
, rd
, sa
, (imm
>> 8) & 0x7);
30481 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f), rt
, rd
, sa
,
30496 check_insn(ctx
, ASE_MSA
);
30497 gen_msa_branch(env
, ctx
, op1
);
30501 generate_exception_end(ctx
, EXCP_RI
);
30506 /* Compact branches [R6] and COP2 [non-R6] */
30507 case OPC_BC
: /* OPC_LWC2 */
30508 case OPC_BALC
: /* OPC_SWC2 */
30509 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30510 /* OPC_BC, OPC_BALC */
30511 gen_compute_compact_branch(ctx
, op
, 0, 0,
30512 sextract32(ctx
->opcode
<< 2, 0, 28));
30514 /* OPC_LWC2, OPC_SWC2 */
30515 /* COP2: Not implemented. */
30516 generate_exception_err(ctx
, EXCP_CpU
, 2);
30519 case OPC_BEQZC
: /* OPC_JIC, OPC_LDC2 */
30520 case OPC_BNEZC
: /* OPC_JIALC, OPC_SDC2 */
30521 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30523 /* OPC_BEQZC, OPC_BNEZC */
30524 gen_compute_compact_branch(ctx
, op
, rs
, 0,
30525 sextract32(ctx
->opcode
<< 2, 0, 23));
30527 /* OPC_JIC, OPC_JIALC */
30528 gen_compute_compact_branch(ctx
, op
, 0, rt
, imm
);
30531 /* OPC_LWC2, OPC_SWC2 */
30532 /* COP2: Not implemented. */
30533 generate_exception_err(ctx
, EXCP_CpU
, 2);
30537 check_insn(ctx
, INSN_LOONGSON2F
);
30538 /* Note that these instructions use different fields. */
30539 gen_loongson_multimedia(ctx
, sa
, rd
, rt
);
30543 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30544 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
30545 check_cp1_enabled(ctx
);
30546 op1
= MASK_CP3(ctx
->opcode
);
30550 check_insn(ctx
, ISA_MIPS5
| ISA_MIPS32R2
);
30556 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32R2
);
30557 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
30560 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32R2
);
30561 /* Treat as NOP. */
30564 check_insn(ctx
, ISA_MIPS5
| ISA_MIPS32R2
);
30578 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32R2
);
30579 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
30583 generate_exception_end(ctx
, EXCP_RI
);
30587 generate_exception_err(ctx
, EXCP_CpU
, 1);
30591 #if defined(TARGET_MIPS64)
30592 /* MIPS64 opcodes */
30594 if (ctx
->insn_flags
& INSN_R5900
) {
30595 check_insn_opc_user_only(ctx
, INSN_R5900
);
30600 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30604 check_insn(ctx
, ISA_MIPS3
);
30605 check_mips_64(ctx
);
30606 gen_ld(ctx
, op
, rt
, rs
, imm
);
30610 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30613 check_insn(ctx
, ISA_MIPS3
);
30614 check_mips_64(ctx
);
30615 gen_st(ctx
, op
, rt
, rs
, imm
);
30618 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
30619 check_insn(ctx
, ISA_MIPS3
);
30620 if (ctx
->insn_flags
& INSN_R5900
) {
30621 check_insn_opc_user_only(ctx
, INSN_R5900
);
30623 check_mips_64(ctx
);
30624 gen_st_cond(ctx
, rt
, rs
, imm
, MO_TEQ
, false);
30626 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
30627 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30628 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
30629 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30632 check_insn(ctx
, ISA_MIPS3
);
30633 check_mips_64(ctx
);
30634 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
30638 check_insn(ctx
, ISA_MIPS3
);
30639 check_mips_64(ctx
);
30640 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
30643 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC */
30644 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30645 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
30647 MIPS_INVAL("major opcode");
30648 generate_exception_end(ctx
, EXCP_RI
);
30652 case OPC_DAUI
: /* OPC_JALX */
30653 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
30654 #if defined(TARGET_MIPS64)
30656 check_mips_64(ctx
);
30658 generate_exception(ctx
, EXCP_RI
);
30659 } else if (rt
!= 0) {
30660 TCGv t0
= tcg_temp_new();
30661 gen_load_gpr(t0
, rs
);
30662 tcg_gen_addi_tl(cpu_gpr
[rt
], t0
, imm
<< 16);
30666 generate_exception_end(ctx
, EXCP_RI
);
30667 MIPS_INVAL("major opcode");
30671 check_insn(ctx
, ASE_MIPS16
| ASE_MICROMIPS
);
30672 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
30673 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
, 4);
30676 case OPC_MSA
: /* OPC_MDMX */
30677 if (ctx
->insn_flags
& INSN_R5900
) {
30678 #if defined(TARGET_MIPS64)
30679 gen_mmi_lq(env
, ctx
); /* MMI_OPC_LQ */
30682 /* MDMX: Not implemented. */
30687 check_insn(ctx
, ISA_MIPS32R6
);
30688 gen_pcrel(ctx
, ctx
->opcode
, ctx
->base
.pc_next
, rs
);
30690 default: /* Invalid */
30691 MIPS_INVAL("major opcode");
30692 generate_exception_end(ctx
, EXCP_RI
);
30697 static void mips_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
30699 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
30700 CPUMIPSState
*env
= cs
->env_ptr
;
30702 ctx
->page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
30703 ctx
->saved_pc
= -1;
30704 ctx
->insn_flags
= env
->insn_flags
;
30705 ctx
->CP0_Config1
= env
->CP0_Config1
;
30706 ctx
->CP0_Config2
= env
->CP0_Config2
;
30707 ctx
->CP0_Config3
= env
->CP0_Config3
;
30708 ctx
->CP0_Config5
= env
->CP0_Config5
;
30710 ctx
->kscrexist
= (env
->CP0_Config4
>> CP0C4_KScrExist
) & 0xff;
30711 ctx
->rxi
= (env
->CP0_Config3
>> CP0C3_RXI
) & 1;
30712 ctx
->ie
= (env
->CP0_Config4
>> CP0C4_IE
) & 3;
30713 ctx
->bi
= (env
->CP0_Config3
>> CP0C3_BI
) & 1;
30714 ctx
->bp
= (env
->CP0_Config3
>> CP0C3_BP
) & 1;
30715 ctx
->PAMask
= env
->PAMask
;
30716 ctx
->mvh
= (env
->CP0_Config5
>> CP0C5_MVH
) & 1;
30717 ctx
->eva
= (env
->CP0_Config5
>> CP0C5_EVA
) & 1;
30718 ctx
->sc
= (env
->CP0_Config3
>> CP0C3_SC
) & 1;
30719 ctx
->CP0_LLAddr_shift
= env
->CP0_LLAddr_shift
;
30720 ctx
->cmgcr
= (env
->CP0_Config3
>> CP0C3_CMGCR
) & 1;
30721 /* Restore delay slot state from the tb context. */
30722 ctx
->hflags
= (uint32_t)ctx
->base
.tb
->flags
; /* FIXME: maybe use 64 bits? */
30723 ctx
->ulri
= (env
->CP0_Config3
>> CP0C3_ULRI
) & 1;
30724 ctx
->ps
= ((env
->active_fpu
.fcr0
>> FCR0_PS
) & 1) ||
30725 (env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
));
30726 ctx
->vp
= (env
->CP0_Config5
>> CP0C5_VP
) & 1;
30727 ctx
->mrp
= (env
->CP0_Config5
>> CP0C5_MRP
) & 1;
30728 ctx
->nan2008
= (env
->active_fpu
.fcr31
>> FCR31_NAN2008
) & 1;
30729 ctx
->abs2008
= (env
->active_fpu
.fcr31
>> FCR31_ABS2008
) & 1;
30730 restore_cpu_state(env
, ctx
);
30731 #ifdef CONFIG_USER_ONLY
30732 ctx
->mem_idx
= MIPS_HFLAG_UM
;
30734 ctx
->mem_idx
= hflags_mmu_index(ctx
->hflags
);
30736 ctx
->default_tcg_memop_mask
= (ctx
->insn_flags
& ISA_MIPS32R6
) ?
30737 MO_UNALN
: MO_ALIGN
;
30739 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx
->base
.tb
, ctx
->mem_idx
,
30743 static void mips_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
30747 static void mips_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
30749 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
30751 tcg_gen_insn_start(ctx
->base
.pc_next
, ctx
->hflags
& MIPS_HFLAG_BMASK
,
30755 static bool mips_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
30756 const CPUBreakpoint
*bp
)
30758 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
30760 save_cpu_state(ctx
, 1);
30761 ctx
->base
.is_jmp
= DISAS_NORETURN
;
30762 gen_helper_raise_exception_debug(cpu_env
);
30764 * The address covered by the breakpoint must be included in
30765 * [tb->pc, tb->pc + tb->size) in order to for it to be
30766 * properly cleared -- thus we increment the PC here so that
30767 * the logic setting tb->size below does the right thing.
30769 ctx
->base
.pc_next
+= 4;
30773 static void mips_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
30775 CPUMIPSState
*env
= cs
->env_ptr
;
30776 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
30780 is_slot
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
30781 if (ctx
->insn_flags
& ISA_NANOMIPS32
) {
30782 ctx
->opcode
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
30783 insn_bytes
= decode_nanomips_opc(env
, ctx
);
30784 } else if (!(ctx
->hflags
& MIPS_HFLAG_M16
)) {
30785 ctx
->opcode
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
30787 decode_opc(env
, ctx
);
30788 } else if (ctx
->insn_flags
& ASE_MICROMIPS
) {
30789 ctx
->opcode
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
30790 insn_bytes
= decode_micromips_opc(env
, ctx
);
30791 } else if (ctx
->insn_flags
& ASE_MIPS16
) {
30792 ctx
->opcode
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
30793 insn_bytes
= decode_mips16_opc(env
, ctx
);
30795 generate_exception_end(ctx
, EXCP_RI
);
30796 g_assert(ctx
->base
.is_jmp
== DISAS_NORETURN
);
30800 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
30801 if (!(ctx
->hflags
& (MIPS_HFLAG_BDS16
| MIPS_HFLAG_BDS32
|
30802 MIPS_HFLAG_FBNSLOT
))) {
30804 * Force to generate branch as there is neither delay nor
30809 if ((ctx
->hflags
& MIPS_HFLAG_M16
) &&
30810 (ctx
->hflags
& MIPS_HFLAG_FBNSLOT
)) {
30812 * Force to generate branch as microMIPS R6 doesn't restrict
30813 * branches in the forbidden slot.
30819 gen_branch(ctx
, insn_bytes
);
30821 ctx
->base
.pc_next
+= insn_bytes
;
30823 if (ctx
->base
.is_jmp
!= DISAS_NEXT
) {
30827 * Execute a branch and its delay slot as a single instruction.
30828 * This is what GDB expects and is consistent with what the
30829 * hardware does (e.g. if a delay slot instruction faults, the
30830 * reported PC is the PC of the branch).
30832 if (ctx
->base
.singlestep_enabled
&&
30833 (ctx
->hflags
& MIPS_HFLAG_BMASK
) == 0) {
30834 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
30836 if (ctx
->base
.pc_next
- ctx
->page_start
>= TARGET_PAGE_SIZE
) {
30837 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
30841 static void mips_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
30843 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
30845 if (ctx
->base
.singlestep_enabled
&& ctx
->base
.is_jmp
!= DISAS_NORETURN
) {
30846 save_cpu_state(ctx
, ctx
->base
.is_jmp
!= DISAS_EXIT
);
30847 gen_helper_raise_exception_debug(cpu_env
);
30849 switch (ctx
->base
.is_jmp
) {
30851 gen_save_pc(ctx
->base
.pc_next
);
30852 tcg_gen_lookup_and_goto_ptr();
30855 case DISAS_TOO_MANY
:
30856 save_cpu_state(ctx
, 0);
30857 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
30860 tcg_gen_exit_tb(NULL
, 0);
30862 case DISAS_NORETURN
:
30865 g_assert_not_reached();
30870 static void mips_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
30872 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
30873 log_target_disas(cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
30876 static const TranslatorOps mips_tr_ops
= {
30877 .init_disas_context
= mips_tr_init_disas_context
,
30878 .tb_start
= mips_tr_tb_start
,
30879 .insn_start
= mips_tr_insn_start
,
30880 .breakpoint_check
= mips_tr_breakpoint_check
,
30881 .translate_insn
= mips_tr_translate_insn
,
30882 .tb_stop
= mips_tr_tb_stop
,
30883 .disas_log
= mips_tr_disas_log
,
30886 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
30890 translator_loop(&mips_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
30893 static void fpu_dump_state(CPUMIPSState
*env
, FILE * f
, int flags
)
30896 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
30898 #define printfpr(fp) \
30901 qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
30902 " fd:%13g fs:%13g psu: %13g\n", \
30903 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
30904 (double)(fp)->fd, \
30905 (double)(fp)->fs[FP_ENDIAN_IDX], \
30906 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
30909 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
30910 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
30911 qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
30912 " fd:%13g fs:%13g psu:%13g\n", \
30913 tmp.w[FP_ENDIAN_IDX], tmp.d, \
30915 (double)tmp.fs[FP_ENDIAN_IDX], \
30916 (double)tmp.fs[!FP_ENDIAN_IDX]); \
30922 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
30923 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
,
30924 get_float_exception_flags(&env
->active_fpu
.fp_status
));
30925 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
30926 qemu_fprintf(f
, "%3s: ", fregnames
[i
]);
30927 printfpr(&env
->active_fpu
.fpr
[i
]);
30933 void mips_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
30935 MIPSCPU
*cpu
= MIPS_CPU(cs
);
30936 CPUMIPSState
*env
= &cpu
->env
;
30939 qemu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
30940 " LO=0x" TARGET_FMT_lx
" ds %04x "
30941 TARGET_FMT_lx
" " TARGET_FMT_ld
"\n",
30942 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
30943 env
->hflags
, env
->btarget
, env
->bcond
);
30944 for (i
= 0; i
< 32; i
++) {
30945 if ((i
& 3) == 0) {
30946 qemu_fprintf(f
, "GPR%02d:", i
);
30948 qemu_fprintf(f
, " %s " TARGET_FMT_lx
,
30949 regnames
[i
], env
->active_tc
.gpr
[i
]);
30950 if ((i
& 3) == 3) {
30951 qemu_fprintf(f
, "\n");
30955 qemu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
30956 TARGET_FMT_lx
"\n",
30957 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
30958 qemu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
30960 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
30961 qemu_fprintf(f
, " Config2 0x%08x Config3 0x%08x\n",
30962 env
->CP0_Config2
, env
->CP0_Config3
);
30963 qemu_fprintf(f
, " Config4 0x%08x Config5 0x%08x\n",
30964 env
->CP0_Config4
, env
->CP0_Config5
);
30965 if ((flags
& CPU_DUMP_FPU
) && (env
->hflags
& MIPS_HFLAG_FPU
)) {
30966 fpu_dump_state(env
, f
, flags
);
30970 void mips_tcg_init(void)
30975 for (i
= 1; i
< 32; i
++)
30976 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
30977 offsetof(CPUMIPSState
,
30981 for (i
= 0; i
< 32; i
++) {
30982 int off
= offsetof(CPUMIPSState
, active_fpu
.fpr
[i
].wr
.d
[0]);
30984 tcg_global_mem_new_i64(cpu_env
, off
, msaregnames
[i
* 2]);
30986 * The scalar floating-point unit (FPU) registers are mapped on
30987 * the MSA vector registers.
30989 fpu_f64
[i
] = msa_wr_d
[i
* 2];
30990 off
= offsetof(CPUMIPSState
, active_fpu
.fpr
[i
].wr
.d
[1]);
30991 msa_wr_d
[i
* 2 + 1] =
30992 tcg_global_mem_new_i64(cpu_env
, off
, msaregnames
[i
* 2 + 1]);
30995 cpu_PC
= tcg_global_mem_new(cpu_env
,
30996 offsetof(CPUMIPSState
, active_tc
.PC
), "PC");
30997 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
30998 cpu_HI
[i
] = tcg_global_mem_new(cpu_env
,
30999 offsetof(CPUMIPSState
, active_tc
.HI
[i
]),
31001 cpu_LO
[i
] = tcg_global_mem_new(cpu_env
,
31002 offsetof(CPUMIPSState
, active_tc
.LO
[i
]),
31005 cpu_dspctrl
= tcg_global_mem_new(cpu_env
,
31006 offsetof(CPUMIPSState
,
31007 active_tc
.DSPControl
),
31009 bcond
= tcg_global_mem_new(cpu_env
,
31010 offsetof(CPUMIPSState
, bcond
), "bcond");
31011 btarget
= tcg_global_mem_new(cpu_env
,
31012 offsetof(CPUMIPSState
, btarget
), "btarget");
31013 hflags
= tcg_global_mem_new_i32(cpu_env
,
31014 offsetof(CPUMIPSState
, hflags
), "hflags");
31016 fpu_fcr0
= tcg_global_mem_new_i32(cpu_env
,
31017 offsetof(CPUMIPSState
, active_fpu
.fcr0
),
31019 fpu_fcr31
= tcg_global_mem_new_i32(cpu_env
,
31020 offsetof(CPUMIPSState
, active_fpu
.fcr31
),
31022 cpu_lladdr
= tcg_global_mem_new(cpu_env
, offsetof(CPUMIPSState
, lladdr
),
31024 cpu_llval
= tcg_global_mem_new(cpu_env
, offsetof(CPUMIPSState
, llval
),
31027 #if defined(TARGET_MIPS64)
31029 for (i
= 1; i
< 32; i
++) {
31030 cpu_mmr
[i
] = tcg_global_mem_new_i64(cpu_env
,
31031 offsetof(CPUMIPSState
,
31037 #if !defined(TARGET_MIPS64)
31038 for (i
= 0; i
< NUMBER_OF_MXU_REGISTERS
- 1; i
++) {
31039 mxu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
31040 offsetof(CPUMIPSState
,
31041 active_tc
.mxu_gpr
[i
]),
31045 mxu_CR
= tcg_global_mem_new(cpu_env
,
31046 offsetof(CPUMIPSState
, active_tc
.mxu_cr
),
31047 mxuregnames
[NUMBER_OF_MXU_REGISTERS
- 1]);
31051 #include "translate_init.inc.c"
31053 void cpu_mips_realize_env(CPUMIPSState
*env
)
31055 env
->exception_base
= (int32_t)0xBFC00000;
31057 #ifndef CONFIG_USER_ONLY
31058 mmu_init(env
, env
->cpu_model
);
31060 fpu_init(env
, env
->cpu_model
);
31061 mvp_init(env
, env
->cpu_model
);
31064 bool cpu_supports_cps_smp(const char *cpu_type
)
31066 const MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(object_class_by_name(cpu_type
));
31067 return (mcc
->cpu_def
->CP0_Config3
& (1 << CP0C3_CMGCR
)) != 0;
31070 bool cpu_supports_isa(const char *cpu_type
, uint64_t isa
)
31072 const MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(object_class_by_name(cpu_type
));
31073 return (mcc
->cpu_def
->insn_flags
& isa
) != 0;
31076 void cpu_set_exception_base(int vp_index
, target_ulong address
)
31078 MIPSCPU
*vp
= MIPS_CPU(qemu_get_cpu(vp_index
));
31079 vp
->env
.exception_base
= address
;
31082 void cpu_state_reset(CPUMIPSState
*env
)
31084 CPUState
*cs
= env_cpu(env
);
31086 /* Reset registers to their default values */
31087 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
31088 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
31089 #ifdef TARGET_WORDS_BIGENDIAN
31090 env
->CP0_Config0
|= (1 << CP0C0_BE
);
31092 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
31093 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
31094 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
31095 env
->CP0_Config4
= env
->cpu_model
->CP0_Config4
;
31096 env
->CP0_Config4_rw_bitmask
= env
->cpu_model
->CP0_Config4_rw_bitmask
;
31097 env
->CP0_Config5
= env
->cpu_model
->CP0_Config5
;
31098 env
->CP0_Config5_rw_bitmask
= env
->cpu_model
->CP0_Config5_rw_bitmask
;
31099 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
31100 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
31101 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
31102 << env
->cpu_model
->CP0_LLAddr_shift
;
31103 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
31104 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
31105 env
->CCRes
= env
->cpu_model
->CCRes
;
31106 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
31107 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
31108 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
31109 env
->current_tc
= 0;
31110 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
31111 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
31112 #if defined(TARGET_MIPS64)
31113 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
31114 env
->SEGMask
|= 3ULL << 62;
31117 env
->PABITS
= env
->cpu_model
->PABITS
;
31118 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
31119 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
31120 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
31121 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
31122 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
31123 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
31124 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
31125 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
31126 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
31127 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
31128 env
->CP0_PageGrain_rw_bitmask
= env
->cpu_model
->CP0_PageGrain_rw_bitmask
;
31129 env
->CP0_PageGrain
= env
->cpu_model
->CP0_PageGrain
;
31130 env
->CP0_EBaseWG_rw_bitmask
= env
->cpu_model
->CP0_EBaseWG_rw_bitmask
;
31131 env
->active_fpu
.fcr0
= env
->cpu_model
->CP1_fcr0
;
31132 env
->active_fpu
.fcr31_rw_bitmask
= env
->cpu_model
->CP1_fcr31_rw_bitmask
;
31133 env
->active_fpu
.fcr31
= env
->cpu_model
->CP1_fcr31
;
31134 env
->msair
= env
->cpu_model
->MSAIR
;
31135 env
->insn_flags
= env
->cpu_model
->insn_flags
;
31137 #if defined(CONFIG_USER_ONLY)
31138 env
->CP0_Status
= (MIPS_HFLAG_UM
<< CP0St_KSU
);
31139 # ifdef TARGET_MIPS64
31140 /* Enable 64-bit register mode. */
31141 env
->CP0_Status
|= (1 << CP0St_PX
);
31143 # ifdef TARGET_ABI_MIPSN64
31144 /* Enable 64-bit address mode. */
31145 env
->CP0_Status
|= (1 << CP0St_UX
);
31148 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
31149 * hardware registers.
31151 env
->CP0_HWREna
|= 0x0000000F;
31152 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
31153 env
->CP0_Status
|= (1 << CP0St_CU1
);
31155 if (env
->CP0_Config3
& (1 << CP0C3_DSPP
)) {
31156 env
->CP0_Status
|= (1 << CP0St_MX
);
31158 # if defined(TARGET_MIPS64)
31159 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
31160 if ((env
->CP0_Config1
& (1 << CP0C1_FP
)) &&
31161 (env
->CP0_Status_rw_bitmask
& (1 << CP0St_FR
))) {
31162 env
->CP0_Status
|= (1 << CP0St_FR
);
31166 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
31168 * If the exception was raised from a delay slot,
31169 * come back to the jump.
31171 env
->CP0_ErrorEPC
= (env
->active_tc
.PC
31172 - (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4));
31174 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
31176 env
->active_tc
.PC
= env
->exception_base
;
31177 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
31178 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
31179 env
->CP0_Wired
= 0;
31180 env
->CP0_GlobalNumber
= (cs
->cpu_index
& 0xFF) << CP0GN_VPId
;
31181 env
->CP0_EBase
= (cs
->cpu_index
& 0x3FF);
31182 if (mips_um_ksegs_enabled()) {
31183 env
->CP0_EBase
|= 0x40000000;
31185 env
->CP0_EBase
|= (int32_t)0x80000000;
31187 if (env
->CP0_Config3
& (1 << CP0C3_CMGCR
)) {
31188 env
->CP0_CMGCRBase
= 0x1fbf8000 >> 4;
31190 env
->CP0_EntryHi_ASID_mask
= (env
->CP0_Config4
& (1 << CP0C4_AE
)) ?
31192 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
31194 * Vectored interrupts not implemented, timer on int 7,
31195 * no performance counters.
31197 env
->CP0_IntCtl
= 0xe0000000;
31201 for (i
= 0; i
< 7; i
++) {
31202 env
->CP0_WatchLo
[i
] = 0;
31203 env
->CP0_WatchHi
[i
] = 0x80000000;
31205 env
->CP0_WatchLo
[7] = 0;
31206 env
->CP0_WatchHi
[7] = 0;
31208 /* Count register increments in debug mode, EJTAG version 1 */
31209 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
31211 cpu_mips_store_count(env
, 1);
31213 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
31216 /* Only TC0 on VPE 0 starts as active. */
31217 for (i
= 0; i
< ARRAY_SIZE(env
->tcs
); i
++) {
31218 env
->tcs
[i
].CP0_TCBind
= cs
->cpu_index
<< CP0TCBd_CurVPE
;
31219 env
->tcs
[i
].CP0_TCHalt
= 1;
31221 env
->active_tc
.CP0_TCHalt
= 1;
31224 if (cs
->cpu_index
== 0) {
31225 /* VPE0 starts up enabled. */
31226 env
->mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
31227 env
->CP0_VPEConf0
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
31229 /* TC0 starts up unhalted. */
31231 env
->active_tc
.CP0_TCHalt
= 0;
31232 env
->tcs
[0].CP0_TCHalt
= 0;
31233 /* With thread 0 active. */
31234 env
->active_tc
.CP0_TCStatus
= (1 << CP0TCSt_A
);
31235 env
->tcs
[0].CP0_TCStatus
= (1 << CP0TCSt_A
);
31240 * Configure default legacy segmentation control. We use this regardless of
31241 * whether segmentation control is presented to the guest.
31243 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
31244 env
->CP0_SegCtl0
= (CP0SC_AM_MK
<< CP0SC_AM
);
31245 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
31246 env
->CP0_SegCtl0
|= ((CP0SC_AM_MSK
<< CP0SC_AM
)) << 16;
31247 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
31248 env
->CP0_SegCtl1
= (0 << CP0SC_PA
) | (CP0SC_AM_UK
<< CP0SC_AM
) |
31250 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
31251 env
->CP0_SegCtl1
|= ((0 << CP0SC_PA
) | (CP0SC_AM_UK
<< CP0SC_AM
) |
31252 (3 << CP0SC_C
)) << 16;
31253 /* USeg (seg4 0x40000000..0x7FFFFFFF) */
31254 env
->CP0_SegCtl2
= (2 << CP0SC_PA
) | (CP0SC_AM_MUSK
<< CP0SC_AM
) |
31255 (1 << CP0SC_EU
) | (2 << CP0SC_C
);
31256 /* USeg (seg5 0x00000000..0x3FFFFFFF) */
31257 env
->CP0_SegCtl2
|= ((0 << CP0SC_PA
) | (CP0SC_AM_MUSK
<< CP0SC_AM
) |
31258 (1 << CP0SC_EU
) | (2 << CP0SC_C
)) << 16;
31259 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
31260 env
->CP0_SegCtl1
|= (CP0SC_AM_UK
<< CP0SC1_XAM
);
31262 if ((env
->insn_flags
& ISA_MIPS32R6
) &&
31263 (env
->active_fpu
.fcr0
& (1 << FCR0_F64
))) {
31264 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
31265 env
->CP0_Status
|= (1 << CP0St_FR
);
31268 if (env
->insn_flags
& ISA_MIPS32R6
) {
31270 env
->CP0_PWSize
= 0x40;
31276 env
->CP0_PWField
= 0x0C30C302;
31283 env
->CP0_PWField
= 0x02;
31286 if (env
->CP0_Config3
& (1 << CP0C3_ISA
) & (1 << (CP0C3_ISA
+ 1))) {
31287 /* microMIPS on reset when Config3.ISA is 3 */
31288 env
->hflags
|= MIPS_HFLAG_M16
;
31292 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
31296 compute_hflags(env
);
31297 restore_fp_status(env
);
31298 restore_pamask(env
);
31299 cs
->exception_index
= EXCP_NONE
;
31301 if (semihosting_get_argc()) {
31302 /* UHI interface can be used to obtain argc and argv */
31303 env
->active_tc
.gpr
[4] = -1;
31307 void restore_state_to_opc(CPUMIPSState
*env
, TranslationBlock
*tb
,
31308 target_ulong
*data
)
31310 env
->active_tc
.PC
= data
[0];
31311 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
31312 env
->hflags
|= data
[1];
31313 switch (env
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
31314 case MIPS_HFLAG_BR
:
31316 case MIPS_HFLAG_BC
:
31317 case MIPS_HFLAG_BL
:
31319 env
->btarget
= data
[2];