2 * CRISv10 emulation for qemu: main translation routines.
4 * Copyright (c) 2010 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "crisv10-decode.h"
24 static const char * const regnames_v10[] =
26 "$r0", "$r1", "$r2", "$r3",
27 "$r4", "$r5", "$r6", "$r7",
28 "$r8", "$r9", "$r10", "$r11",
29 "$r12", "$r13", "$sp", "$pc",
32 static const char * const pregnames_v10[] =
34 "$bz", "$vr", "$p2", "$p3",
35 "$wz", "$ccr", "$p6-prefix", "$mof",
36 "$dz", "$ibr", "$irp", "$srp",
37 "$bar", "$dccr", "$brp", "$usp",
40 /* We need this table to handle preg-moves with implicit width. */
41 static const int preg_sizes_v10[] = {
52 static inline int dec10_size(unsigned int size)
60 static inline void cris_illegal_insn(DisasContext *dc)
62 qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc);
63 t_gen_raise_exception(EXCP_BREAK);
64 dc->base.is_jmp = DISAS_NORETURN;
67 static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
68 unsigned int size, int mem_index)
70 TCGLabel *l1 = gen_new_label();
71 TCGv taddr = tcg_temp_new();
72 TCGv tval = tcg_temp_new();
73 TCGv t1 = tcg_temp_new();
75 cris_evaluate_flags(dc);
77 tcg_gen_mov_tl(taddr, addr);
78 tcg_gen_mov_tl(tval, val);
80 /* Store only if F flag isn't set */
81 tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
82 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
84 tcg_gen_qemu_st8(tval, taddr, mem_index);
85 } else if (size == 2) {
86 tcg_gen_qemu_st16(tval, taddr, mem_index);
88 tcg_gen_qemu_st32(tval, taddr, mem_index);
91 tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
92 tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
98 static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
101 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
103 /* If we get a fault on a delayslot we must keep the jmp state in
104 the cpu-state to be able to re-execute the jmp. */
105 if (dc->delayed_branch == 1) {
106 cris_store_direct_jmp(dc);
109 /* Conditional writes. */
111 gen_store_v10_conditional(dc, addr, val, size, mem_index);
116 tcg_gen_qemu_st8(val, addr, mem_index);
117 } else if (size == 2) {
118 tcg_gen_qemu_st16(val, addr, mem_index);
120 tcg_gen_qemu_st32(val, addr, mem_index);
125 /* Prefix flag and register are used to handle the more complex
127 static void cris_set_prefix(DisasContext *dc)
129 dc->clear_prefix = 0;
130 dc->tb_flags |= PFIX_FLAG;
131 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG);
133 /* prefix insns don't clear the x flag. */
138 static void crisv10_prepare_memaddr(DisasContext *dc,
139 TCGv addr, unsigned int size)
141 if (dc->tb_flags & PFIX_FLAG) {
142 tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]);
144 tcg_gen_mov_tl(addr, cpu_R[dc->src]);
148 static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
150 unsigned int insn_len = 0;
152 if (dc->tb_flags & PFIX_FLAG) {
153 if (dc->mode == CRISV10_MODE_AUTOINC) {
154 tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
157 if (dc->mode == CRISV10_MODE_AUTOINC) {
159 insn_len += size & ~1;
161 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
168 static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
169 int s_ext, int memsize, TCGv dst)
177 is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
178 LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
179 rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
181 /* Load [$rs] onto T1. */
186 imm = cpu_ldsb_code(env, dc->pc + 2);
188 imm = cpu_ldsw_code(env, dc->pc + 2);
191 imm = cpu_ldub_code(env, dc->pc + 2);
193 imm = cpu_lduw_code(env, dc->pc + 2);
196 imm = cpu_ldl_code(env, dc->pc + 2);
198 tcg_gen_movi_tl(dst, imm);
200 if (dc->mode == CRISV10_MODE_AUTOINC) {
204 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len);
209 addr = tcg_temp_new();
210 cris_flush_cc_state(dc);
211 crisv10_prepare_memaddr(dc, addr, memsize);
212 gen_load(dc, dst, addr, memsize, 0);
214 t_gen_sext(dst, dst, memsize);
216 t_gen_zext(dst, dst, memsize);
217 insn_len += crisv10_post_memaddr(dc, memsize);
221 if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
227 static unsigned int dec10_quick_imm(DisasContext *dc)
234 imm = dc->ir & ((1 << 6) - 1);
235 simm = (int8_t) (imm << 2);
237 switch (dc->opcode) {
238 case CRISV10_QIMM_BDAP_R0:
239 case CRISV10_QIMM_BDAP_R1:
240 case CRISV10_QIMM_BDAP_R2:
241 case CRISV10_QIMM_BDAP_R3:
242 simm = (int8_t)dc->ir;
243 LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
244 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
245 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
248 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
250 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
254 case CRISV10_QIMM_MOVEQ:
255 LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
257 cris_cc_mask(dc, CC_MASK_NZVC);
258 c = tcg_const_tl(simm);
259 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
260 cpu_R[dc->dst], c, 4);
263 case CRISV10_QIMM_CMPQ:
264 LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
266 cris_cc_mask(dc, CC_MASK_NZVC);
267 c = tcg_const_tl(simm);
268 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
269 cpu_R[dc->dst], c, 4);
272 case CRISV10_QIMM_ADDQ:
273 LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
275 cris_cc_mask(dc, CC_MASK_NZVC);
276 c = tcg_const_tl(imm);
277 cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
278 cpu_R[dc->dst], c, 4);
281 case CRISV10_QIMM_ANDQ:
282 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
284 cris_cc_mask(dc, CC_MASK_NZVC);
285 c = tcg_const_tl(simm);
286 cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
287 cpu_R[dc->dst], c, 4);
290 case CRISV10_QIMM_ASHQ:
291 LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
293 cris_cc_mask(dc, CC_MASK_NZVC);
296 c = tcg_const_tl(imm);
298 cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
299 cpu_R[dc->dst], c, 4);
302 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
303 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
308 case CRISV10_QIMM_LSHQ:
309 LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
312 if (imm & (1 << 5)) {
316 cris_cc_mask(dc, CC_MASK_NZVC);
317 c = tcg_const_tl(imm);
318 cris_alu(dc, op, cpu_R[dc->dst],
319 cpu_R[dc->dst], c, 4);
322 case CRISV10_QIMM_SUBQ:
323 LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
325 cris_cc_mask(dc, CC_MASK_NZVC);
326 c = tcg_const_tl(imm);
327 cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
328 cpu_R[dc->dst], c, 4);
331 case CRISV10_QIMM_ORQ:
332 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
334 cris_cc_mask(dc, CC_MASK_NZVC);
335 c = tcg_const_tl(simm);
336 cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
337 cpu_R[dc->dst], c, 4);
341 case CRISV10_QIMM_BCC_R0:
342 case CRISV10_QIMM_BCC_R1:
343 case CRISV10_QIMM_BCC_R2:
344 case CRISV10_QIMM_BCC_R3:
346 /* bit 0 is a sign bit. */
348 imm |= 0xffffff00; /* sign extend. */
349 imm &= ~1; /* get rid of the sign bit. */
352 LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
355 cris_prepare_cc_branch(dc, imm, dc->cond);
359 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
360 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
361 cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
367 static unsigned int dec10_setclrf(DisasContext *dc)
370 unsigned int set = ~dc->opcode & 1;
372 flags = EXTRACT_FIELD(dc->ir, 0, 3)
373 | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
374 LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
377 if (flags & X_FLAG) {
379 dc->flags_x = X_FLAG;
384 cris_evaluate_flags (dc);
385 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
386 cris_update_cc_x(dc);
387 tcg_gen_movi_tl(cc_op, dc->cc_op);
390 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
392 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
393 ~(flags|F_FLAG_V10|P_FLAG_V10));
396 dc->flags_uptodate = 1;
402 static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
403 TCGv dd, TCGv ds, TCGv sd, TCGv ss)
406 t_gen_sext(dd, sd, size);
407 t_gen_sext(ds, ss, size);
409 t_gen_zext(dd, sd, size);
410 t_gen_zext(ds, ss, size);
414 static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
418 t[0] = tcg_temp_new();
419 t[1] = tcg_temp_new();
420 dec10_reg_prep_sext(dc, size, sext,
421 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
423 if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
424 tcg_gen_andi_tl(t[1], t[1], 63);
427 assert(dc->dst != 15);
428 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
433 static void dec10_reg_bound(DisasContext *dc, int size)
438 t_gen_zext(t, cpu_R[dc->src], size);
439 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
443 static void dec10_reg_mul(DisasContext *dc, int size, int sext)
445 int op = sext ? CC_OP_MULS : CC_OP_MULU;
448 t[0] = tcg_temp_new();
449 t[1] = tcg_temp_new();
450 dec10_reg_prep_sext(dc, size, sext,
451 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
453 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
460 static void dec10_reg_movs(DisasContext *dc)
462 int size = (dc->size & 1) + 1;
465 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
466 cris_cc_mask(dc, CC_MASK_NZVC);
470 t_gen_sext(t, cpu_R[dc->src], size);
472 t_gen_zext(t, cpu_R[dc->src], size);
474 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
478 static void dec10_reg_alux(DisasContext *dc, int op)
480 int size = (dc->size & 1) + 1;
483 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
484 cris_cc_mask(dc, CC_MASK_NZVC);
488 t_gen_sext(t, cpu_R[dc->src], size);
490 t_gen_zext(t, cpu_R[dc->src], size);
492 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
496 static void dec10_reg_mov_pr(DisasContext *dc)
498 LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
501 tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
502 cris_prepare_jmp(dc, JMP_INDIRECT);
505 if (dc->dst == PR_CCS) {
506 cris_evaluate_flags(dc);
508 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
509 cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
512 static void dec10_reg_abs(DisasContext *dc)
516 LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
518 assert(dc->dst != 15);
520 tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
521 tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
522 tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
524 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
528 static void dec10_reg_swap(DisasContext *dc)
532 LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
534 cris_cc_mask(dc, CC_MASK_NZVC);
536 tcg_gen_mov_tl(t0, cpu_R[dc->src]);
538 tcg_gen_not_tl(t0, t0);
545 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
549 static void dec10_reg_scc(DisasContext *dc)
553 LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
555 gen_tst_cc(dc, cpu_R[dc->src], cond);
556 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0);
561 static unsigned int dec10_reg(DisasContext *dc)
564 unsigned int insn_len = 2;
565 unsigned int size = dec10_size(dc->size);
569 switch (dc->opcode) {
570 case CRISV10_REG_MOVE_R:
571 LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
572 cris_cc_mask(dc, CC_MASK_NZVC);
573 dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
575 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
576 cris_prepare_jmp(dc, JMP_INDIRECT);
577 dc->delayed_branch = 1;
580 case CRISV10_REG_MOVX:
581 cris_cc_mask(dc, CC_MASK_NZVC);
584 case CRISV10_REG_ADDX:
585 cris_cc_mask(dc, CC_MASK_NZVC);
586 dec10_reg_alux(dc, CC_OP_ADD);
588 case CRISV10_REG_SUBX:
589 cris_cc_mask(dc, CC_MASK_NZVC);
590 dec10_reg_alux(dc, CC_OP_SUB);
592 case CRISV10_REG_ADD:
593 LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
594 cris_cc_mask(dc, CC_MASK_NZVC);
595 dec10_reg_alu(dc, CC_OP_ADD, size, 0);
597 case CRISV10_REG_SUB:
598 LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
599 cris_cc_mask(dc, CC_MASK_NZVC);
600 dec10_reg_alu(dc, CC_OP_SUB, size, 0);
602 case CRISV10_REG_CMP:
603 LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
604 cris_cc_mask(dc, CC_MASK_NZVC);
605 dec10_reg_alu(dc, CC_OP_CMP, size, 0);
607 case CRISV10_REG_BOUND:
608 LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
609 cris_cc_mask(dc, CC_MASK_NZVC);
610 dec10_reg_bound(dc, size);
612 case CRISV10_REG_AND:
613 LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
614 cris_cc_mask(dc, CC_MASK_NZVC);
615 dec10_reg_alu(dc, CC_OP_AND, size, 0);
617 case CRISV10_REG_ADDI:
623 LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
624 tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
625 tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
628 case CRISV10_REG_LSL:
629 LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
630 cris_cc_mask(dc, CC_MASK_NZVC);
631 dec10_reg_alu(dc, CC_OP_LSL, size, 0);
633 case CRISV10_REG_LSR:
634 LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
635 cris_cc_mask(dc, CC_MASK_NZVC);
636 dec10_reg_alu(dc, CC_OP_LSR, size, 0);
638 case CRISV10_REG_ASR:
639 LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
640 cris_cc_mask(dc, CC_MASK_NZVC);
641 dec10_reg_alu(dc, CC_OP_ASR, size, 1);
644 LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
645 cris_cc_mask(dc, CC_MASK_NZVC);
646 dec10_reg_alu(dc, CC_OP_OR, size, 0);
648 case CRISV10_REG_NEG:
649 LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
650 cris_cc_mask(dc, CC_MASK_NZVC);
651 dec10_reg_alu(dc, CC_OP_NEG, size, 0);
653 case CRISV10_REG_BIAP:
654 LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
655 dc->opcode, dc->src, dc->dst, size);
657 case 4: tmp = 2; break;
658 case 2: tmp = 1; break;
659 case 1: tmp = 0; break;
661 cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
666 tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
668 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
670 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
677 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
678 dc->opcode, dc->src, dc->dst);
679 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
683 switch (dc->opcode) {
684 case CRISV10_REG_MOVX:
685 cris_cc_mask(dc, CC_MASK_NZVC);
688 case CRISV10_REG_ADDX:
689 cris_cc_mask(dc, CC_MASK_NZVC);
690 dec10_reg_alux(dc, CC_OP_ADD);
692 case CRISV10_REG_SUBX:
693 cris_cc_mask(dc, CC_MASK_NZVC);
694 dec10_reg_alux(dc, CC_OP_SUB);
696 case CRISV10_REG_MOVE_SPR_R:
697 cris_evaluate_flags(dc);
699 dec10_reg_mov_pr(dc);
701 case CRISV10_REG_MOVE_R_SPR:
702 LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
703 cris_evaluate_flags(dc);
704 if (dc->src != 11) /* fast for srp. */
705 dc->cpustate_changed = 1;
706 t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
708 case CRISV10_REG_SETF:
709 case CRISV10_REG_CLEARF:
712 case CRISV10_REG_SWAP:
715 case CRISV10_REG_ABS:
716 cris_cc_mask(dc, CC_MASK_NZVC);
720 LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
721 cris_cc_mask(dc, CC_MASK_NZVC);
722 dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
724 case CRISV10_REG_XOR:
725 LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
726 cris_cc_mask(dc, CC_MASK_NZVC);
727 dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
729 case CRISV10_REG_BTST:
730 LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
731 cris_cc_mask(dc, CC_MASK_NZVC);
732 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
733 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
734 cpu_R[dc->src], cpu_PR[PR_CCS]);
736 case CRISV10_REG_DSTEP:
737 LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
738 cris_cc_mask(dc, CC_MASK_NZVC);
739 cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
740 cpu_R[dc->dst], cpu_R[dc->src], 4);
742 case CRISV10_REG_MSTEP:
743 LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
744 cris_evaluate_flags(dc);
745 cris_cc_mask(dc, CC_MASK_NZVC);
746 cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
747 cpu_R[dc->dst], cpu_R[dc->src], 4);
749 case CRISV10_REG_SCC:
753 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
754 dc->opcode, dc->src, dc->dst);
755 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
762 static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
765 unsigned int insn_len = 2;
768 LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
769 size, dc->src, dc->dst);
771 cris_cc_mask(dc, CC_MASK_NZVC);
773 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
774 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
776 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
777 cris_prepare_jmp(dc, JMP_INDIRECT);
778 dc->delayed_branch = 1;
785 static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
787 unsigned int insn_len = 2;
790 LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
791 addr = tcg_temp_new();
792 crisv10_prepare_memaddr(dc, addr, size);
793 gen_store_v10(dc, addr, cpu_R[dc->dst], size);
794 insn_len += crisv10_post_memaddr(dc, size);
800 static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
802 unsigned int insn_len = 2, rd = dc->dst;
805 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
809 insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
811 tcg_gen_mov_tl(env_btarget, t);
812 cris_prepare_jmp(dc, JMP_INDIRECT);
813 dc->delayed_branch = 1;
815 tcg_gen_mov_tl(cpu_PR[rd], t);
816 dc->cpustate_changed = 1;
822 static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
824 unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
827 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
829 addr = tcg_temp_new();
830 crisv10_prepare_memaddr(dc, addr, size);
831 if (dc->dst == PR_CCS) {
833 cris_evaluate_flags(dc);
834 tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
835 gen_store_v10(dc, addr, t0, size);
838 gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
840 insn_len += crisv10_post_memaddr(dc, size);
847 static void dec10_movem_r_m(DisasContext *dc)
849 int i, pfix = dc->tb_flags & PFIX_FLAG;
852 LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
853 dc->dst, dc->src, dc->postinc, dc->ir);
855 addr = tcg_temp_new();
857 crisv10_prepare_memaddr(dc, addr, 4);
858 tcg_gen_mov_tl(t0, addr);
859 for (i = dc->dst; i >= 0; i--) {
860 if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
861 gen_store_v10(dc, addr, t0, 4);
863 gen_store_v10(dc, addr, cpu_R[i], 4);
865 tcg_gen_addi_tl(addr, addr, 4);
868 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
869 tcg_gen_mov_tl(cpu_R[dc->src], t0);
872 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
873 tcg_gen_mov_tl(cpu_R[dc->src], addr);
879 static void dec10_movem_m_r(DisasContext *dc)
881 int i, pfix = dc->tb_flags & PFIX_FLAG;
884 LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
885 dc->src, dc->dst, dc->postinc, dc->ir);
887 addr = tcg_temp_new();
889 crisv10_prepare_memaddr(dc, addr, 4);
890 tcg_gen_mov_tl(t0, addr);
891 for (i = dc->dst; i >= 0; i--) {
892 gen_load(dc, cpu_R[i], addr, 4, 0);
893 tcg_gen_addi_tl(addr, addr, 4);
896 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
897 tcg_gen_mov_tl(cpu_R[dc->src], t0);
900 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
901 tcg_gen_mov_tl(cpu_R[dc->src], addr);
907 static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
908 int op, unsigned int size)
914 cris_alu_m_alloc_temps(t);
915 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
916 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
918 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
919 cris_prepare_jmp(dc, JMP_INDIRECT);
920 dc->delayed_branch = 1;
926 static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
934 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
935 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
937 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
938 cris_prepare_jmp(dc, JMP_INDIRECT);
939 dc->delayed_branch = 1;
946 static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
948 unsigned int size = (dc->size & 1) ? 2 : 1;
949 unsigned int sx = !!(dc->size & 2);
954 LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
958 cris_cc_mask(dc, CC_MASK_NZVC);
959 insn_len += dec10_prep_move_m(env, dc, sx, size, t);
960 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
962 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
963 cris_prepare_jmp(dc, JMP_INDIRECT);
964 dc->delayed_branch = 1;
971 static int dec10_dip(CPUCRISState *env, DisasContext *dc)
976 LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
977 dc->pc, dc->opcode, dc->src, dc->dst);
979 imm = cpu_ldl_code(env, dc->pc + 2);
980 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
983 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2);
985 gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
987 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
994 static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
999 LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
1000 dc->pc, dc->opcode, dc->src, dc->dst, size);
1002 assert(dc->dst != 15);
1004 /* 8bit embedded offset? */
1005 if (!dc->postinc && (dc->ir & (1 << 11))) {
1006 int simm = dc->ir & 0xff;
1008 /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
1009 /* sign extended. */
1010 simm = (int8_t)simm;
1012 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
1014 cris_set_prefix(dc);
1018 /* Now the rest of the modes are truly indirect. */
1019 insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
1020 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
1021 cris_set_prefix(dc);
1025 static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
1027 unsigned int insn_len = 2;
1028 unsigned int size = dec10_size(dc->size);
1033 if (dc->size != 3) {
1034 switch (dc->opcode) {
1035 case CRISV10_IND_MOVE_M_R:
1036 return dec10_ind_move_m_r(env, dc, size);
1037 case CRISV10_IND_MOVE_R_M:
1038 return dec10_ind_move_r_m(dc, size);
1039 case CRISV10_IND_CMP:
1040 LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
1041 cris_cc_mask(dc, CC_MASK_NZVC);
1042 insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
1044 case CRISV10_IND_TEST:
1045 LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
1047 cris_evaluate_flags(dc);
1048 cris_cc_mask(dc, CC_MASK_NZVC);
1049 cris_alu_m_alloc_temps(t);
1050 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
1051 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
1052 c = tcg_const_tl(0);
1053 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
1057 case CRISV10_IND_ADD:
1058 LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
1059 cris_cc_mask(dc, CC_MASK_NZVC);
1060 insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
1062 case CRISV10_IND_SUB:
1063 LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
1064 cris_cc_mask(dc, CC_MASK_NZVC);
1065 insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
1067 case CRISV10_IND_BOUND:
1068 LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
1069 cris_cc_mask(dc, CC_MASK_NZVC);
1070 insn_len += dec10_ind_bound(env, dc, size);
1072 case CRISV10_IND_AND:
1073 LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
1074 cris_cc_mask(dc, CC_MASK_NZVC);
1075 insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
1077 case CRISV10_IND_OR:
1078 LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
1079 cris_cc_mask(dc, CC_MASK_NZVC);
1080 insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
1082 case CRISV10_IND_MOVX:
1083 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
1085 case CRISV10_IND_ADDX:
1086 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
1088 case CRISV10_IND_SUBX:
1089 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
1091 case CRISV10_IND_CMPX:
1092 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
1094 case CRISV10_IND_MUL:
1095 /* This is a reg insn coded in the mem indir space. */
1096 LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
1097 cris_cc_mask(dc, CC_MASK_NZVC);
1098 dec10_reg_mul(dc, size, dc->ir & (1 << 10));
1100 case CRISV10_IND_BDAP_M:
1101 insn_len = dec10_bdap_m(env, dc, size);
1107 * Instruction format: ADDC [Rs],Rd
1109 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
1110 * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)|
1111 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
1113 * Instruction format: ADDC [Rs+],Rd
1115 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
1116 * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)|
1117 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
1119 if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
1120 env->pregs[PR_VR] == 17) {
1121 LOG_DIS("addc op=%d %d\n", dc->src, dc->dst);
1122 cris_cc_mask(dc, CC_MASK_NZVC);
1123 insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);
1127 LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
1128 dc->pc, size, dc->opcode, dc->src, dc->dst);
1129 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
1135 switch (dc->opcode) {
1136 case CRISV10_IND_MOVE_M_SPR:
1137 insn_len = dec10_ind_move_m_pr(env, dc);
1139 case CRISV10_IND_MOVE_SPR_M:
1140 insn_len = dec10_ind_move_pr_m(dc);
1142 case CRISV10_IND_JUMP_M:
1143 if (dc->src == 15) {
1144 LOG_DIS("jump.%d %d r%d r%d direct\n", size,
1145 dc->opcode, dc->src, dc->dst);
1146 imm = cpu_ldl_code(env, dc->pc + 2);
1147 if (dc->mode == CRISV10_MODE_AUTOINC)
1150 c = tcg_const_tl(dc->pc + insn_len);
1151 t_gen_mov_preg_TN(dc, dc->dst, c);
1154 cris_prepare_jmp(dc, JMP_DIRECT);
1155 dc->delayed_branch--; /* v10 has no dslot here. */
1157 if (dc->dst == 14) {
1158 LOG_DIS("break %d\n", dc->src);
1159 cris_evaluate_flags(dc);
1160 tcg_gen_movi_tl(env_pc, dc->pc + 2);
1161 c = tcg_const_tl(dc->src + 2);
1162 t_gen_mov_env_TN(trap_vector, c);
1164 t_gen_raise_exception(EXCP_BREAK);
1165 dc->base.is_jmp = DISAS_NORETURN;
1168 LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
1169 dc->opcode, dc->src, dc->dst);
1170 t[0] = tcg_temp_new();
1171 c = tcg_const_tl(dc->pc + insn_len);
1172 t_gen_mov_preg_TN(dc, dc->dst, c);
1174 crisv10_prepare_memaddr(dc, t[0], size);
1175 gen_load(dc, env_btarget, t[0], 4, 0);
1176 insn_len += crisv10_post_memaddr(dc, size);
1177 cris_prepare_jmp(dc, JMP_INDIRECT);
1178 dc->delayed_branch--; /* v10 has no dslot here. */
1179 tcg_temp_free(t[0]);
1183 case CRISV10_IND_MOVEM_R_M:
1184 LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
1185 dc->pc, dc->opcode, dc->dst, dc->src);
1186 dec10_movem_r_m(dc);
1188 case CRISV10_IND_MOVEM_M_R:
1189 LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
1190 dec10_movem_m_r(dc);
1192 case CRISV10_IND_JUMP_R:
1193 LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
1194 dc->pc, dc->opcode, dc->dst, dc->src);
1195 tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
1196 c = tcg_const_tl(dc->pc + insn_len);
1197 t_gen_mov_preg_TN(dc, dc->dst, c);
1199 cris_prepare_jmp(dc, JMP_INDIRECT);
1200 dc->delayed_branch--; /* v10 has no dslot here. */
1202 case CRISV10_IND_MOVX:
1203 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
1205 case CRISV10_IND_ADDX:
1206 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
1208 case CRISV10_IND_SUBX:
1209 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
1211 case CRISV10_IND_CMPX:
1212 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
1214 case CRISV10_IND_DIP:
1215 insn_len = dec10_dip(env, dc);
1217 case CRISV10_IND_BCC_M:
1219 cris_cc_mask(dc, 0);
1220 simm = cpu_ldsw_code(env, dc->pc + 2);
1223 LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
1224 cris_prepare_cc_branch(dc, simm, dc->cond);
1228 LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
1229 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
1236 static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
1238 unsigned int insn_len = 2;
1240 /* Load a halfword onto the instruction register. */
1241 dc->ir = cpu_lduw_code(env, dc->pc);
1243 /* Now decode it. */
1244 dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
1245 dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
1246 dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
1247 dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
1248 dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
1249 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
1251 dc->clear_prefix = 1;
1253 /* FIXME: What if this insn insn't 2 in length?? */
1254 if (dc->src == 15 || dc->dst == 15)
1255 tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
1258 case CRISV10_MODE_QIMMEDIATE:
1259 insn_len = dec10_quick_imm(dc);
1261 case CRISV10_MODE_REG:
1262 insn_len = dec10_reg(dc);
1264 case CRISV10_MODE_AUTOINC:
1265 case CRISV10_MODE_INDIRECT:
1266 insn_len = dec10_ind(env, dc);
1270 if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
1271 dc->tb_flags &= ~PFIX_FLAG;
1272 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
1273 if (dc->tb_flags != dc->base.tb->flags) {
1274 dc->cpustate_changed = 1;
1278 /* CRISv10 locks out interrupts on dslots. */
1279 if (dc->delayed_branch == 2) {
1285 void cris_initialize_crisv10_tcg(void)
1289 cc_x = tcg_global_mem_new(cpu_env,
1290 offsetof(CPUCRISState, cc_x), "cc_x");
1291 cc_src = tcg_global_mem_new(cpu_env,
1292 offsetof(CPUCRISState, cc_src), "cc_src");
1293 cc_dest = tcg_global_mem_new(cpu_env,
1294 offsetof(CPUCRISState, cc_dest),
1296 cc_result = tcg_global_mem_new(cpu_env,
1297 offsetof(CPUCRISState, cc_result),
1299 cc_op = tcg_global_mem_new(cpu_env,
1300 offsetof(CPUCRISState, cc_op), "cc_op");
1301 cc_size = tcg_global_mem_new(cpu_env,
1302 offsetof(CPUCRISState, cc_size),
1304 cc_mask = tcg_global_mem_new(cpu_env,
1305 offsetof(CPUCRISState, cc_mask),
1308 env_pc = tcg_global_mem_new(cpu_env,
1309 offsetof(CPUCRISState, pc),
1311 env_btarget = tcg_global_mem_new(cpu_env,
1312 offsetof(CPUCRISState, btarget),
1314 env_btaken = tcg_global_mem_new(cpu_env,
1315 offsetof(CPUCRISState, btaken),
1317 for (i = 0; i < 16; i++) {
1318 cpu_R[i] = tcg_global_mem_new(cpu_env,
1319 offsetof(CPUCRISState, regs[i]),
1322 for (i = 0; i < 16; i++) {
1323 cpu_PR[i] = tcg_global_mem_new(cpu_env,
1324 offsetof(CPUCRISState, pregs[i]),