hw/pci-host/bonito.c

   1 /*
   2  * bonito north bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   6  *
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 /*
  14  * fulong 2e mini pc has a bonito north bridge.
  15  */
  16
  17 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
  18  *
  19  * devfn   pci_slot<<3  + funno
  20  * one pci bus can have 32 devices and each device can have 8 functions.
  21  *
  22  * In bonito north bridge, pci slot = IDSEL bit - 12.
  23  * For example, PCI_IDSEL_VIA686B = 17,
  24  * pci slot = 17-12=5
  25  *
  26  * so
  27  * VT686B_FUN0's devfn = (5<<3)+0
  28  * VT686B_FUN1's devfn = (5<<3)+1
  29  *
  30  * qemu also uses pci address for north bridge to access pci config register.
  31  * bus_no   [23:16]
  32  * dev_no   [15:11]
  33  * fun_no   [10:8]
  34  * reg_no   [7:2]
  35  *
  36  * so function bonito_sbridge_pciaddr for the translation from
  37  * north bridge address to pci address.
  38  */
  39
  40 #include "qemu/osdep.h"
  41 #include "qemu/error-report.h"
  42 #include "hw/hw.h"
  43 #include "hw/pci/pci.h"
  44 #include "hw/i386/pc.h"
  45 #include "hw/mips/mips.h"
  46 #include "hw/pci/pci_host.h"
  47 #include "sysemu/sysemu.h"
  48 #include "exec/address-spaces.h"
  49
  50 //#define DEBUG_BONITO
  51
  52 #ifdef DEBUG_BONITO
  53 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
  54 #else
  55 #define DPRINTF(fmt, ...)
  56 #endif
  57
  58 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
  59 #define BONITO_BOOT_BASE        0x1fc00000
  60 #define BONITO_BOOT_SIZE        0x00100000
  61 #define BONITO_BOOT_TOP         (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
  62 #define BONITO_FLASH_BASE       0x1c000000
  63 #define BONITO_FLASH_SIZE       0x03000000
  64 #define BONITO_FLASH_TOP        (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
  65 #define BONITO_SOCKET_BASE      0x1f800000
  66 #define BONITO_SOCKET_SIZE      0x00400000
  67 #define BONITO_SOCKET_TOP       (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
  68 #define BONITO_REG_BASE         0x1fe00000
  69 #define BONITO_REG_SIZE         0x00040000
  70 #define BONITO_REG_TOP          (BONITO_REG_BASE+BONITO_REG_SIZE-1)
  71 #define BONITO_DEV_BASE         0x1ff00000
  72 #define BONITO_DEV_SIZE         0x00100000
  73 #define BONITO_DEV_TOP          (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
  74 #define BONITO_PCILO_BASE       0x10000000
  75 #define BONITO_PCILO_BASE_VA    0xb0000000
  76 #define BONITO_PCILO_SIZE       0x0c000000
  77 #define BONITO_PCILO_TOP        (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
  78 #define BONITO_PCILO0_BASE      0x10000000
  79 #define BONITO_PCILO1_BASE      0x14000000
  80 #define BONITO_PCILO2_BASE      0x18000000
  81 #define BONITO_PCIHI_BASE       0x20000000
  82 #define BONITO_PCIHI_SIZE       0x20000000
  83 #define BONITO_PCIHI_TOP        (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
  84 #define BONITO_PCIIO_BASE       0x1fd00000
  85 #define BONITO_PCIIO_BASE_VA    0xbfd00000
  86 #define BONITO_PCIIO_SIZE       0x00010000
  87 #define BONITO_PCIIO_TOP        (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
  88 #define BONITO_PCICFG_BASE      0x1fe80000
  89 #define BONITO_PCICFG_SIZE      0x00080000
  90 #define BONITO_PCICFG_TOP       (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
  91
  92
  93 #define BONITO_PCICONFIGBASE    0x00
  94 #define BONITO_REGBASE          0x100
  95
  96 #define BONITO_PCICONFIG_BASE   (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
  97 #define BONITO_PCICONFIG_SIZE   (0x100)
  98
  99 #define BONITO_INTERNAL_REG_BASE  (BONITO_REGBASE+BONITO_REG_BASE)
 100 #define BONITO_INTERNAL_REG_SIZE  (0x70)
 101
 102 #define BONITO_SPCICONFIG_BASE  (BONITO_PCICFG_BASE)
 103 #define BONITO_SPCICONFIG_SIZE  (BONITO_PCICFG_SIZE)
 104
 105
 106
 107 /* 1. Bonito h/w Configuration */
 108 /* Power on register */
 109
 110 #define BONITO_BONPONCFG        (0x00 >> 2)      /* 0x100 */
 111 #define BONITO_BONGENCFG_OFFSET 0x4
 112 #define BONITO_BONGENCFG        (BONITO_BONGENCFG_OFFSET>>2)   /*0x104 */
 113
 114 /* 2. IO & IDE configuration */
 115 #define BONITO_IODEVCFG         (0x08 >> 2)      /* 0x108 */
 116
 117 /* 3. IO & IDE configuration */
 118 #define BONITO_SDCFG            (0x0c >> 2)      /* 0x10c */
 119
 120 /* 4. PCI address map control */
 121 #define BONITO_PCIMAP           (0x10 >> 2)      /* 0x110 */
 122 #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
 123 #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
 124
 125 /* 5. ICU & GPIO regs */
 126 /* GPIO Regs - r/w */
 127 #define BONITO_GPIODATA_OFFSET  0x1c
 128 #define BONITO_GPIODATA         (BONITO_GPIODATA_OFFSET >> 2)   /* 0x11c */
 129 #define BONITO_GPIOIE           (0x20 >> 2)      /* 0x120 */
 130
 131 /* ICU Configuration Regs - r/w */
 132 #define BONITO_INTEDGE          (0x24 >> 2)      /* 0x124 */
 133 #define BONITO_INTSTEER         (0x28 >> 2)      /* 0x128 */
 134 #define BONITO_INTPOL           (0x2c >> 2)      /* 0x12c */
 135
 136 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 137 #define BONITO_INTENSET         (0x30 >> 2)      /* 0x130 */
 138 #define BONITO_INTENCLR         (0x34 >> 2)      /* 0x134 */
 139 #define BONITO_INTEN            (0x38 >> 2)      /* 0x138 */
 140 #define BONITO_INTISR           (0x3c >> 2)      /* 0x13c */
 141
 142 /* PCI mail boxes */
 143 #define BONITO_PCIMAIL0_OFFSET    0x40
 144 #define BONITO_PCIMAIL1_OFFSET    0x44
 145 #define BONITO_PCIMAIL2_OFFSET    0x48
 146 #define BONITO_PCIMAIL3_OFFSET    0x4c
 147 #define BONITO_PCIMAIL0         (0x40 >> 2)      /* 0x140 */
 148 #define BONITO_PCIMAIL1         (0x44 >> 2)      /* 0x144 */
 149 #define BONITO_PCIMAIL2         (0x48 >> 2)      /* 0x148 */
 150 #define BONITO_PCIMAIL3         (0x4c >> 2)      /* 0x14c */
 151
 152 /* 6. PCI cache */
 153 #define BONITO_PCICACHECTRL     (0x50 >> 2)      /* 0x150 */
 154 #define BONITO_PCICACHETAG      (0x54 >> 2)      /* 0x154 */
 155 #define BONITO_PCIBADADDR       (0x58 >> 2)      /* 0x158 */
 156 #define BONITO_PCIMSTAT         (0x5c >> 2)      /* 0x15c */
 157
 158 /* 7. other*/
 159 #define BONITO_TIMECFG          (0x60 >> 2)      /* 0x160 */
 160 #define BONITO_CPUCFG           (0x64 >> 2)      /* 0x164 */
 161 #define BONITO_DQCFG            (0x68 >> 2)      /* 0x168 */
 162 #define BONITO_MEMSIZE          (0x6C >> 2)      /* 0x16c */
 163
 164 #define BONITO_REGS             (0x70 >> 2)
 165
 166 /* PCI config for south bridge. type 0 */
 167 #define BONITO_PCICONF_IDSEL_MASK      0xfffff800     /* [31:11] */
 168 #define BONITO_PCICONF_IDSEL_OFFSET    11
 169 #define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */
 170 #define BONITO_PCICONF_FUN_OFFSET      8
 171 #define BONITO_PCICONF_REG_MASK        0xFC
 172 #define BONITO_PCICONF_REG_OFFSET      0
 173
 174
 175 /* idsel BIT = pci slot number +12 */
 176 #define PCI_SLOT_BASE              12
 177 #define PCI_IDSEL_VIA686B_BIT      (17)
 178 #define PCI_IDSEL_VIA686B          (1<<PCI_IDSEL_VIA686B_BIT)
 179
 180 #define PCI_ADDR(busno,devno,funno,regno)  \
 181     ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
 182
 183 typedef struct BonitoState BonitoState;
 184
 185 typedef struct PCIBonitoState
 186 {
 187     PCIDevice dev;
 188
 189     BonitoState *pcihost;
 190     uint32_t regs[BONITO_REGS];
 191
 192     struct bonldma {
 193         uint32_t ldmactrl;
 194         uint32_t ldmastat;
 195         uint32_t ldmaaddr;
 196         uint32_t ldmago;
 197     } bonldma;
 198
 199     /* Based at 1fe00300, bonito Copier */
 200     struct boncop {
 201         uint32_t copctrl;
 202         uint32_t copstat;
 203         uint32_t coppaddr;
 204         uint32_t copgo;
 205     } boncop;
 206
 207     /* Bonito registers */
 208     MemoryRegion iomem;
 209     MemoryRegion iomem_ldma;
 210     MemoryRegion iomem_cop;
 211     MemoryRegion bonito_pciio;
 212     MemoryRegion bonito_localio;
 213
 214 } PCIBonitoState;
 215
 216 struct BonitoState {
 217     PCIHostState parent_obj;
 218     qemu_irq *pic;
 219     PCIBonitoState *pci_dev;
 220     MemoryRegion pci_mem;
 221 };
 222
 223 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
 224 #define BONITO_PCI_HOST_BRIDGE(obj) \
 225     OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE)
 226
 227 #define TYPE_PCI_BONITO "Bonito"
 228 #define PCI_BONITO(obj) \
 229     OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO)
 230
 231 static void bonito_writel(void *opaque, hwaddr addr,
 232                           uint64_t val, unsigned size)
 233 {
 234     PCIBonitoState *s = opaque;
 235     uint32_t saddr;
 236     int reset = 0;
 237
 238     saddr = addr >> 2;
 239
 240     DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
 241     switch (saddr) {
 242     case BONITO_BONPONCFG:
 243     case BONITO_IODEVCFG:
 244     case BONITO_SDCFG:
 245     case BONITO_PCIMAP:
 246     case BONITO_PCIMEMBASECFG:
 247     case BONITO_PCIMAP_CFG:
 248     case BONITO_GPIODATA:
 249     case BONITO_GPIOIE:
 250     case BONITO_INTEDGE:
 251     case BONITO_INTSTEER:
 252     case BONITO_INTPOL:
 253     case BONITO_PCIMAIL0:
 254     case BONITO_PCIMAIL1:
 255     case BONITO_PCIMAIL2:
 256     case BONITO_PCIMAIL3:
 257     case BONITO_PCICACHECTRL:
 258     case BONITO_PCICACHETAG:
 259     case BONITO_PCIBADADDR:
 260     case BONITO_PCIMSTAT:
 261     case BONITO_TIMECFG:
 262     case BONITO_CPUCFG:
 263     case BONITO_DQCFG:
 264     case BONITO_MEMSIZE:
 265         s->regs[saddr] = val;
 266         break;
 267     case BONITO_BONGENCFG:
 268         if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
 269             reset = 1; /* bit 2 jump from 0 to 1 cause reset */
 270         }
 271         s->regs[saddr] = val;
 272         if (reset) {
 273             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 274         }
 275         break;
 276     case BONITO_INTENSET:
 277         s->regs[BONITO_INTENSET] = val;
 278         s->regs[BONITO_INTEN] |= val;
 279         break;
 280     case BONITO_INTENCLR:
 281         s->regs[BONITO_INTENCLR] = val;
 282         s->regs[BONITO_INTEN] &= ~val;
 283         break;
 284     case BONITO_INTEN:
 285     case BONITO_INTISR:
 286         DPRINTF("write to readonly bonito register %x\n", saddr);
 287         break;
 288     default:
 289         DPRINTF("write to unknown bonito register %x\n", saddr);
 290         break;
 291     }
 292 }
 293
 294 static uint64_t bonito_readl(void *opaque, hwaddr addr,
 295                              unsigned size)
 296 {
 297     PCIBonitoState *s = opaque;
 298     uint32_t saddr;
 299
 300     saddr = addr >> 2;
 301
 302     DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
 303     switch (saddr) {
 304     case BONITO_INTISR:
 305         return s->regs[saddr];
 306     default:
 307         return s->regs[saddr];
 308     }
 309 }
 310
 311 static const MemoryRegionOps bonito_ops = {
 312     .read = bonito_readl,
 313     .write = bonito_writel,
 314     .endianness = DEVICE_NATIVE_ENDIAN,
 315     .valid = {
 316         .min_access_size = 4,
 317         .max_access_size = 4,
 318     },
 319 };
 320
 321 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
 322                                   uint64_t val, unsigned size)
 323 {
 324     PCIBonitoState *s = opaque;
 325     PCIDevice *d = PCI_DEVICE(s);
 326
 327     DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
 328     d->config_write(d, addr, val, 4);
 329 }
 330
 331 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
 332                                      unsigned size)
 333 {
 334
 335     PCIBonitoState *s = opaque;
 336     PCIDevice *d = PCI_DEVICE(s);
 337
 338     DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
 339     return d->config_read(d, addr, 4);
 340 }
 341
 342 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
 343
 344 static const MemoryRegionOps bonito_pciconf_ops = {
 345     .read = bonito_pciconf_readl,
 346     .write = bonito_pciconf_writel,
 347     .endianness = DEVICE_NATIVE_ENDIAN,
 348     .valid = {
 349         .min_access_size = 4,
 350         .max_access_size = 4,
 351     },
 352 };
 353
 354 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
 355                                   unsigned size)
 356 {
 357     uint32_t val;
 358     PCIBonitoState *s = opaque;
 359
 360     if (addr >= sizeof(s->bonldma)) {
 361         return 0;
 362     }
 363
 364     val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
 365
 366     return val;
 367 }
 368
 369 static void bonito_ldma_writel(void *opaque, hwaddr addr,
 370                                uint64_t val, unsigned size)
 371 {
 372     PCIBonitoState *s = opaque;
 373
 374     if (addr >= sizeof(s->bonldma)) {
 375         return;
 376     }
 377
 378     ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
 379 }
 380
 381 static const MemoryRegionOps bonito_ldma_ops = {
 382     .read = bonito_ldma_readl,
 383     .write = bonito_ldma_writel,
 384     .endianness = DEVICE_NATIVE_ENDIAN,
 385     .valid = {
 386         .min_access_size = 4,
 387         .max_access_size = 4,
 388     },
 389 };
 390
 391 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
 392                                  unsigned size)
 393 {
 394     uint32_t val;
 395     PCIBonitoState *s = opaque;
 396
 397     if (addr >= sizeof(s->boncop)) {
 398         return 0;
 399     }
 400
 401     val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
 402
 403     return val;
 404 }
 405
 406 static void bonito_cop_writel(void *opaque, hwaddr addr,
 407                               uint64_t val, unsigned size)
 408 {
 409     PCIBonitoState *s = opaque;
 410
 411     if (addr >= sizeof(s->boncop)) {
 412         return;
 413     }
 414
 415     ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
 416 }
 417
 418 static const MemoryRegionOps bonito_cop_ops = {
 419     .read = bonito_cop_readl,
 420     .write = bonito_cop_writel,
 421     .endianness = DEVICE_NATIVE_ENDIAN,
 422     .valid = {
 423         .min_access_size = 4,
 424         .max_access_size = 4,
 425     },
 426 };
 427
 428 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
 429 {
 430     PCIBonitoState *s = opaque;
 431     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 432     uint32_t cfgaddr;
 433     uint32_t idsel;
 434     uint32_t devno;
 435     uint32_t funno;
 436     uint32_t regno;
 437     uint32_t pciaddr;
 438
 439     /* support type0 pci config */
 440     if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
 441         return 0xffffffff;
 442     }
 443
 444     cfgaddr = addr & 0xffff;
 445     cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
 446
 447     idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
 448     devno = ctz32(idsel);
 449     funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
 450     regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
 451
 452     if (idsel == 0) {
 453         error_report("error in bonito pci config address " TARGET_FMT_plx
 454                      ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]);
 455         exit(1);
 456     }
 457     pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
 458     DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
 459         cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
 460
 461     return pciaddr;
 462 }
 463
 464 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
 465                                   unsigned size)
 466 {
 467     PCIBonitoState *s = opaque;
 468     PCIDevice *d = PCI_DEVICE(s);
 469     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 470     uint32_t pciaddr;
 471     uint16_t status;
 472
 473     DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n",
 474             addr, size, val);
 475
 476     pciaddr = bonito_sbridge_pciaddr(s, addr);
 477
 478     if (pciaddr == 0xffffffff) {
 479         return;
 480     }
 481
 482     /* set the pci address in s->config_reg */
 483     phb->config_reg = (pciaddr) | (1u << 31);
 484     pci_data_write(phb->bus, phb->config_reg, val, size);
 485
 486     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 487     status = pci_get_word(d->config + PCI_STATUS);
 488     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 489     pci_set_word(d->config + PCI_STATUS, status);
 490 }
 491
 492 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
 493 {
 494     PCIBonitoState *s = opaque;
 495     PCIDevice *d = PCI_DEVICE(s);
 496     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 497     uint32_t pciaddr;
 498     uint16_t status;
 499
 500     DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
 501
 502     pciaddr = bonito_sbridge_pciaddr(s, addr);
 503
 504     if (pciaddr == 0xffffffff) {
 505         return MAKE_64BIT_MASK(0, size * 8);
 506     }
 507
 508     /* set the pci address in s->config_reg */
 509     phb->config_reg = (pciaddr) | (1u << 31);
 510
 511     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 512     status = pci_get_word(d->config + PCI_STATUS);
 513     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 514     pci_set_word(d->config + PCI_STATUS, status);
 515
 516     return pci_data_read(phb->bus, phb->config_reg, size);
 517 }
 518
 519 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
 520 static const MemoryRegionOps bonito_spciconf_ops = {
 521     .read = bonito_spciconf_read,
 522     .write = bonito_spciconf_write,
 523     .valid.min_access_size = 1,
 524     .valid.max_access_size = 4,
 525     .impl.min_access_size = 1,
 526     .impl.max_access_size = 4,
 527     .endianness = DEVICE_NATIVE_ENDIAN,
 528 };
 529
 530 #define BONITO_IRQ_BASE 32
 531
 532 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
 533 {
 534     BonitoState *s = opaque;
 535     qemu_irq *pic = s->pic;
 536     PCIBonitoState *bonito_state = s->pci_dev;
 537     int internal_irq = irq_num - BONITO_IRQ_BASE;
 538
 539     if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
 540         qemu_irq_pulse(*pic);
 541     } else {   /* level triggered */
 542         if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
 543             qemu_irq_raise(*pic);
 544         } else {
 545             qemu_irq_lower(*pic);
 546         }
 547     }
 548 }
 549
 550 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
 551 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
 552 {
 553     int slot;
 554
 555     slot = (pci_dev->devfn >> 3);
 556
 557     switch (slot) {
 558     case 5:   /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
 559         return irq_num % 4 + BONITO_IRQ_BASE;
 560     case 6:   /* FULONG2E_ATI_SLOT, VGA */
 561         return 4 + BONITO_IRQ_BASE;
 562     case 7:   /* FULONG2E_RTL_SLOT, RTL8139 */
 563         return 5 + BONITO_IRQ_BASE;
 564     case 8 ... 12: /* PCI slot 1 to 4 */
 565         return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
 566     default:  /* Unknown device, don't do any translation */
 567         return irq_num;
 568     }
 569 }
 570
 571 static void bonito_reset(void *opaque)
 572 {
 573     PCIBonitoState *s = opaque;
 574
 575     /* set the default value of north bridge registers */
 576
 577     s->regs[BONITO_BONPONCFG] = 0xc40;
 578     s->regs[BONITO_BONGENCFG] = 0x1384;
 579     s->regs[BONITO_IODEVCFG] = 0x2bff8010;
 580     s->regs[BONITO_SDCFG] = 0x255e0091;
 581
 582     s->regs[BONITO_GPIODATA] = 0x1ff;
 583     s->regs[BONITO_GPIOIE] = 0x1ff;
 584     s->regs[BONITO_DQCFG] = 0x8;
 585     s->regs[BONITO_MEMSIZE] = 0x10000000;
 586     s->regs[BONITO_PCIMAP] = 0x6140;
 587 }
 588
 589 static const VMStateDescription vmstate_bonito = {
 590     .name = "Bonito",
 591     .version_id = 1,
 592     .minimum_version_id = 1,
 593     .fields = (VMStateField[]) {
 594         VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
 595         VMSTATE_END_OF_LIST()
 596     }
 597 };
 598
 599 static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
 600 {
 601     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 602     BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
 603
 604     memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCILO_SIZE);
 605     phb->bus = pci_register_root_bus(DEVICE(dev), "pci",
 606                                      pci_bonito_set_irq, pci_bonito_map_irq,
 607                                      dev, &bs->pci_mem, get_system_io(),
 608                                      0x28, 32, TYPE_PCI_BUS);
 609     memory_region_add_subregion(get_system_memory(), BONITO_PCILO_BASE,
 610                                 &bs->pci_mem);
 611 }
 612
 613 static void bonito_realize(PCIDevice *dev, Error **errp)
 614 {
 615     PCIBonitoState *s = PCI_BONITO(dev);
 616     SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
 617     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 618
 619     /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
 620     pci_config_set_prog_interface(dev->config, 0x00);
 621
 622     /* set the north bridge register mapping */
 623     memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
 624                           "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
 625     sysbus_init_mmio(sysbus, &s->iomem);
 626     sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
 627
 628     /* set the north bridge pci configure  mapping */
 629     memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
 630                           "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
 631     sysbus_init_mmio(sysbus, &phb->conf_mem);
 632     sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
 633
 634     /* set the south bridge pci configure  mapping */
 635     memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
 636                           "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
 637     sysbus_init_mmio(sysbus, &phb->data_mem);
 638     sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
 639
 640     memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
 641                           "ldma", 0x100);
 642     sysbus_init_mmio(sysbus, &s->iomem_ldma);
 643     sysbus_mmio_map(sysbus, 3, 0xbfe00200);
 644
 645     memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
 646                           "cop", 0x100);
 647     sysbus_init_mmio(sysbus, &s->iomem_cop);
 648     sysbus_mmio_map(sysbus, 4, 0xbfe00300);
 649
 650     /* Map PCI IO Space  0x1fd0 0000 - 0x1fd1 0000 */
 651     memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
 652                              get_system_io(), 0, BONITO_PCIIO_SIZE);
 653     sysbus_init_mmio(sysbus, &s->bonito_pciio);
 654     sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
 655
 656     /* add pci local io mapping */
 657     memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio",
 658                              get_system_io(), 0, BONITO_DEV_SIZE);
 659     sysbus_init_mmio(sysbus, &s->bonito_localio);
 660     sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
 661
 662     /* set the default value of north bridge pci config */
 663     pci_set_word(dev->config + PCI_COMMAND, 0x0000);
 664     pci_set_word(dev->config + PCI_STATUS, 0x0000);
 665     pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
 666     pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
 667
 668     pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
 669     pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
 670     pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
 671     pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
 672
 673     qemu_register_reset(bonito_reset, s);
 674 }
 675
 676 PCIBus *bonito_init(qemu_irq *pic)
 677 {
 678     DeviceState *dev;
 679     BonitoState *pcihost;
 680     PCIHostState *phb;
 681     PCIBonitoState *s;
 682     PCIDevice *d;
 683
 684     dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE);
 685     phb = PCI_HOST_BRIDGE(dev);
 686     pcihost = BONITO_PCI_HOST_BRIDGE(dev);
 687     pcihost->pic = pic;
 688     qdev_init_nofail(dev);
 689
 690     d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
 691     s = PCI_BONITO(d);
 692     s->pcihost = pcihost;
 693     pcihost->pci_dev = s;
 694     qdev_init_nofail(DEVICE(d));
 695
 696     return phb->bus;
 697 }
 698
 699 static void bonito_class_init(ObjectClass *klass, void *data)
 700 {
 701     DeviceClass *dc = DEVICE_CLASS(klass);
 702     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 703
 704     k->realize = bonito_realize;
 705     k->vendor_id = 0xdf53;
 706     k->device_id = 0x00d5;
 707     k->revision = 0x01;
 708     k->class_id = PCI_CLASS_BRIDGE_HOST;
 709     dc->desc = "Host bridge";
 710     dc->vmsd = &vmstate_bonito;
 711     /*
 712      * PCI-facing part of the host bridge, not usable without the
 713      * host-facing part, which can't be device_add'ed, yet.
 714      */
 715     dc->user_creatable = false;
 716 }
 717
 718 static const TypeInfo bonito_info = {
 719     .name          = TYPE_PCI_BONITO,
 720     .parent        = TYPE_PCI_DEVICE,
 721     .instance_size = sizeof(PCIBonitoState),
 722     .class_init    = bonito_class_init,
 723     .interfaces = (InterfaceInfo[]) {
 724         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 725         { },
 726     },
 727 };
 728
 729 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
 730 {
 731     DeviceClass *dc = DEVICE_CLASS(klass);
 732
 733     dc->realize = bonito_pcihost_realize;
 734 }
 735
 736 static const TypeInfo bonito_pcihost_info = {
 737     .name          = TYPE_BONITO_PCI_HOST_BRIDGE,
 738     .parent        = TYPE_PCI_HOST_BRIDGE,
 739     .instance_size = sizeof(BonitoState),
 740     .class_init    = bonito_pcihost_class_init,
 741 };
 742
 743 static void bonito_register_types(void)
 744 {
 745     type_register_static(&bonito_pcihost_info);
 746     type_register_static(&bonito_info);
 747 }
 748
 749 type_init(bonito_register_types)