2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-timer.h"
34 #define DPRINTF(fmt, ...) \
35 do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
40 //#define DEBUG_IRQ_LATENCY
41 //#define DEBUG_IRQ_COUNT
43 typedef struct PicState
{
44 uint8_t last_irr
; /* edge detection */
45 uint8_t irr
; /* interrupt request register */
46 uint8_t imr
; /* interrupt mask register */
47 uint8_t isr
; /* interrupt service register */
48 uint8_t priority_add
; /* highest irq priority */
50 uint8_t read_reg_select
;
55 uint8_t rotate_on_auto_eoi
;
56 uint8_t special_fully_nested_mode
;
57 uint8_t init4
; /* true if 4 byte init */
58 uint8_t single_mode
; /* true if slave pic is not initialized */
59 uint8_t elcr
; /* PIIX edge/trigger selection*/
62 PicState2
*pics_state
;
68 /* 0 is master pic, 1 is slave pic */
69 /* XXX: better separation between the two pics */
71 void *irq_request_opaque
;
74 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
75 static int irq_level
[16];
77 #ifdef DEBUG_IRQ_COUNT
78 static uint64_t irq_count
[16];
82 /* return the highest priority found in mask (highest = smallest
83 number). Return 8 if no irq */
84 static int get_priority(PicState
*s
, int mask
)
90 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
95 /* return the pic wanted interrupt. return -1 if none */
96 static int pic_get_irq(PicState
*s
)
98 int mask
, cur_priority
, priority
;
100 mask
= s
->irr
& ~s
->imr
;
101 priority
= get_priority(s
, mask
);
104 /* compute current priority. If special fully nested mode on the
105 master, the IRQ coming from the slave is not taken into account
106 for the priority computation. */
110 if (s
->special_fully_nested_mode
&& s
== &s
->pics_state
->pics
[0])
112 cur_priority
= get_priority(s
, mask
);
113 if (priority
< cur_priority
) {
114 /* higher priority found: an irq should be generated */
115 return (priority
+ s
->priority_add
) & 7;
121 static void pic_set_irq1(PicState
*s
, int irq
, int level
);
123 /* raise irq to CPU if necessary. must be called every time the active
125 static void pic_update_irq(PicState2
*s
)
129 /* first look at slave pic */
130 irq2
= pic_get_irq(&s
->pics
[1]);
132 /* if irq request by slave pic, signal master PIC */
133 pic_set_irq1(&s
->pics
[0], 2, 1);
134 pic_set_irq1(&s
->pics
[0], 2, 0);
136 /* look at requested irq */
137 irq
= pic_get_irq(&s
->pics
[0]);
139 #if defined(DEBUG_PIC)
142 for(i
= 0; i
< 2; i
++) {
143 printf("pic%d: imr=%x irr=%x padd=%d\n",
144 i
, s
->pics
[i
].imr
, s
->pics
[i
].irr
,
145 s
->pics
[i
].priority_add
);
149 printf("pic: cpu_interrupt\n");
151 qemu_irq_raise(s
->pics
[0].int_out
);
153 qemu_irq_lower(s
->pics
[0].int_out
);
157 /* set irq level. If an edge is detected, then the IRR is set to 1 */
158 static void pic_set_irq1(PicState
*s
, int irq
, int level
)
162 if (s
->elcr
& mask
) {
163 /* level triggered */
169 s
->last_irr
&= ~mask
;
174 if ((s
->last_irr
& mask
) == 0) {
179 s
->last_irr
&= ~mask
;
184 #ifdef DEBUG_IRQ_LATENCY
185 int64_t irq_time
[16];
188 static void i8259_set_irq(void *opaque
, int irq
, int level
)
190 PicState2
*s
= opaque
;
192 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
193 if (level
!= irq_level
[irq
]) {
194 DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq
, level
);
195 irq_level
[irq
] = level
;
196 #ifdef DEBUG_IRQ_COUNT
202 #ifdef DEBUG_IRQ_LATENCY
204 irq_time
[irq
] = qemu_get_clock_ns(vm_clock
);
207 pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
211 /* acknowledge interrupt 'irq' */
212 static void pic_intack(PicState
*s
, int irq
)
215 if (s
->rotate_on_auto_eoi
)
216 s
->priority_add
= (irq
+ 1) & 7;
218 s
->isr
|= (1 << irq
);
220 /* We don't clear a level sensitive interrupt here */
221 if (!(s
->elcr
& (1 << irq
)))
222 s
->irr
&= ~(1 << irq
);
225 int pic_read_irq(PicState2
*s
)
227 int irq
, irq2
, intno
;
229 irq
= pic_get_irq(&s
->pics
[0]);
232 irq2
= pic_get_irq(&s
->pics
[1]);
234 pic_intack(&s
->pics
[1], irq2
);
236 /* spurious IRQ on slave controller */
239 intno
= s
->pics
[1].irq_base
+ irq2
;
241 intno
= s
->pics
[0].irq_base
+ irq
;
243 pic_intack(&s
->pics
[0], irq
);
245 /* spurious IRQ on host controller */
247 intno
= s
->pics
[0].irq_base
+ irq
;
251 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
256 #ifdef DEBUG_IRQ_LATENCY
257 printf("IRQ%d latency=%0.3fus\n",
259 (double)(qemu_get_clock_ns(vm_clock
) -
260 irq_time
[irq
]) * 1000000.0 / get_ticks_per_sec());
262 DPRINTF("pic_interrupt: irq=%d\n", irq
);
266 static void pic_reset(void *opaque
)
268 PicState
*s
= opaque
;
276 s
->read_reg_select
= 0;
281 s
->rotate_on_auto_eoi
= 0;
282 s
->special_fully_nested_mode
= 0;
285 /* Note: ELCR is not reset */
288 static void pic_ioport_write(void *opaque
, target_phys_addr_t addr64
,
289 uint64_t val64
, unsigned size
)
291 PicState
*s
= opaque
;
292 uint32_t addr
= addr64
;
293 uint32_t val
= val64
;
294 int priority
, cmd
, irq
;
296 DPRINTF("write: addr=0x%02x val=0x%02x\n", addr
, val
);
301 /* deassert a pending interrupt */
302 qemu_irq_lower(s
->pics_state
->pics
[0].int_out
);
305 s
->single_mode
= val
& 2;
307 hw_error("level sensitive irq not supported");
308 } else if (val
& 0x08) {
312 s
->read_reg_select
= val
& 1;
314 s
->special_mask
= (val
>> 5) & 1;
320 s
->rotate_on_auto_eoi
= cmd
>> 2;
322 case 1: /* end of interrupt */
324 priority
= get_priority(s
, s
->isr
);
326 irq
= (priority
+ s
->priority_add
) & 7;
327 s
->isr
&= ~(1 << irq
);
329 s
->priority_add
= (irq
+ 1) & 7;
330 pic_update_irq(s
->pics_state
);
335 s
->isr
&= ~(1 << irq
);
336 pic_update_irq(s
->pics_state
);
339 s
->priority_add
= (val
+ 1) & 7;
340 pic_update_irq(s
->pics_state
);
344 s
->isr
&= ~(1 << irq
);
345 s
->priority_add
= (irq
+ 1) & 7;
346 pic_update_irq(s
->pics_state
);
354 switch(s
->init_state
) {
358 pic_update_irq(s
->pics_state
);
361 s
->irq_base
= val
& 0xf8;
362 s
->init_state
= s
->single_mode
? (s
->init4
? 3 : 0) : 2;
372 s
->special_fully_nested_mode
= (val
>> 4) & 1;
373 s
->auto_eoi
= (val
>> 1) & 1;
380 static uint32_t pic_poll_read(PicState
*s
)
384 ret
= pic_get_irq(s
);
386 bool slave
= (s
== &isa_pic
->pics
[1]);
389 s
->pics_state
->pics
[0].isr
&= ~(1 << 2);
390 s
->pics_state
->pics
[0].irr
&= ~(1 << 2);
392 s
->irr
&= ~(1 << ret
);
393 s
->isr
&= ~(1 << ret
);
394 if (slave
|| ret
!= 2)
395 pic_update_irq(s
->pics_state
);
403 static uint64_t pic_ioport_read(void *opaque
, target_phys_addr_t addr1
,
406 PicState
*s
= opaque
;
407 unsigned int addr
= addr1
;
411 ret
= pic_poll_read(s
);
415 if (s
->read_reg_select
)
423 DPRINTF("read: addr=0x%02x val=0x%02x\n", addr
, ret
);
427 /* memory mapped interrupt status */
428 /* XXX: may be the same than pic_read_irq() */
429 uint32_t pic_intack_read(PicState2
*s
)
433 ret
= pic_poll_read(&s
->pics
[0]);
435 ret
= pic_poll_read(&s
->pics
[1]) + 8;
436 /* Prepare for ISR read */
437 s
->pics
[0].read_reg_select
= 1;
442 int pic_get_output(PicState2
*s
)
444 return (pic_get_irq(&s
->pics
[0]) >= 0);
447 static void elcr_ioport_write(void *opaque
, target_phys_addr_t addr
,
448 uint64_t val
, unsigned size
)
450 PicState
*s
= opaque
;
451 s
->elcr
= val
& s
->elcr_mask
;
454 static uint64_t elcr_ioport_read(void *opaque
, target_phys_addr_t addr
,
457 PicState
*s
= opaque
;
461 static const VMStateDescription vmstate_pic
= {
464 .minimum_version_id
= 1,
465 .minimum_version_id_old
= 1,
466 .fields
= (VMStateField
[]) {
467 VMSTATE_UINT8(last_irr
, PicState
),
468 VMSTATE_UINT8(irr
, PicState
),
469 VMSTATE_UINT8(imr
, PicState
),
470 VMSTATE_UINT8(isr
, PicState
),
471 VMSTATE_UINT8(priority_add
, PicState
),
472 VMSTATE_UINT8(irq_base
, PicState
),
473 VMSTATE_UINT8(read_reg_select
, PicState
),
474 VMSTATE_UINT8(poll
, PicState
),
475 VMSTATE_UINT8(special_mask
, PicState
),
476 VMSTATE_UINT8(init_state
, PicState
),
477 VMSTATE_UINT8(auto_eoi
, PicState
),
478 VMSTATE_UINT8(rotate_on_auto_eoi
, PicState
),
479 VMSTATE_UINT8(special_fully_nested_mode
, PicState
),
480 VMSTATE_UINT8(init4
, PicState
),
481 VMSTATE_UINT8(single_mode
, PicState
),
482 VMSTATE_UINT8(elcr
, PicState
),
483 VMSTATE_END_OF_LIST()
487 static const MemoryRegionOps pic_base_ioport_ops
= {
488 .read
= pic_ioport_read
,
489 .write
= pic_ioport_write
,
491 .min_access_size
= 1,
492 .max_access_size
= 1,
496 static const MemoryRegionOps pic_elcr_ioport_ops
= {
497 .read
= elcr_ioport_read
,
498 .write
= elcr_ioport_write
,
500 .min_access_size
= 1,
501 .max_access_size
= 1,
505 /* XXX: add generic master/slave system */
506 static void pic_init(int io_addr
, int elcr_addr
, PicState
*s
, qemu_irq int_out
)
508 s
->int_out
= int_out
;
510 memory_region_init_io(&s
->base_io
, &pic_base_ioport_ops
, s
, "pic", 2);
511 memory_region_init_io(&s
->elcr_io
, &pic_elcr_ioport_ops
, s
, "elcr", 1);
513 isa_register_ioport(NULL
, &s
->base_io
, io_addr
);
514 if (elcr_addr
>= 0) {
515 isa_register_ioport(NULL
, &s
->elcr_io
, elcr_addr
);
518 vmstate_register(NULL
, io_addr
, &vmstate_pic
, s
);
519 qemu_register_reset(pic_reset
, s
);
522 void pic_info(Monitor
*mon
)
531 s
= &isa_pic
->pics
[i
];
532 monitor_printf(mon
, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
533 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
534 i
, s
->irr
, s
->imr
, s
->isr
, s
->priority_add
,
535 s
->irq_base
, s
->read_reg_select
, s
->elcr
,
536 s
->special_fully_nested_mode
);
540 void irq_info(Monitor
*mon
)
542 #ifndef DEBUG_IRQ_COUNT
543 monitor_printf(mon
, "irq statistic code not compiled.\n");
548 monitor_printf(mon
, "IRQ statistics:\n");
549 for (i
= 0; i
< 16; i
++) {
550 count
= irq_count
[i
];
552 monitor_printf(mon
, "%2d: %" PRId64
"\n", i
, count
);
557 qemu_irq
*i8259_init(qemu_irq parent_irq
)
562 s
= g_malloc0(sizeof(PicState2
));
563 irqs
= qemu_allocate_irqs(i8259_set_irq
, s
, 16);
564 pic_init(0x20, 0x4d0, &s
->pics
[0], parent_irq
);
565 pic_init(0xa0, 0x4d1, &s
->pics
[1], irqs
[2]);
566 s
->pics
[0].elcr_mask
= 0xf8;
567 s
->pics
[1].elcr_mask
= 0xde;
568 s
->pics
[0].pics_state
= s
;
569 s
->pics
[1].pics_state
= s
;