hw/char/pl011.c

   1 /*
   2  * Arm PrimeCell PL011 UART
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/sysbus.h"
  12 #include "sysemu/char.h"
  13
  14 #define TYPE_PL011 "pl011"
  15 #define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
  16
  17 typedef struct PL011State {
  18     SysBusDevice parent_obj;
  19
  20     MemoryRegion iomem;
  21     uint32_t readbuff;
  22     uint32_t flags;
  23     uint32_t lcr;
  24     uint32_t rsr;
  25     uint32_t cr;
  26     uint32_t dmacr;
  27     uint32_t int_enabled;
  28     uint32_t int_level;
  29     uint32_t read_fifo[16];
  30     uint32_t ilpr;
  31     uint32_t ibrd;
  32     uint32_t fbrd;
  33     uint32_t ifl;
  34     int read_pos;
  35     int read_count;
  36     int read_trigger;
  37     CharDriverState *chr;
  38     qemu_irq irq;
  39     const unsigned char *id;
  40 } PL011State;
  41
  42 #define PL011_INT_TX 0x20
  43 #define PL011_INT_RX 0x10
  44
  45 #define PL011_FLAG_TXFE 0x80
  46 #define PL011_FLAG_RXFF 0x40
  47 #define PL011_FLAG_TXFF 0x20
  48 #define PL011_FLAG_RXFE 0x10
  49
  50 static const unsigned char pl011_id_arm[8] =
  51   { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  52 static const unsigned char pl011_id_luminary[8] =
  53   { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  54
  55 static void pl011_update(PL011State *s)
  56 {
  57     uint32_t flags;
  58
  59     flags = s->int_level & s->int_enabled;
  60     qemu_set_irq(s->irq, flags != 0);
  61 }
  62
  63 static uint64_t pl011_read(void *opaque, hwaddr offset,
  64                            unsigned size)
  65 {
  66     PL011State *s = (PL011State *)opaque;
  67     uint32_t c;
  68
  69     if (offset >= 0xfe0 && offset < 0x1000) {
  70         return s->id[(offset - 0xfe0) >> 2];
  71     }
  72     switch (offset >> 2) {
  73     case 0: /* UARTDR */
  74         s->flags &= ~PL011_FLAG_RXFF;
  75         c = s->read_fifo[s->read_pos];
  76         if (s->read_count > 0) {
  77             s->read_count--;
  78             if (++s->read_pos == 16)
  79                 s->read_pos = 0;
  80         }
  81         if (s->read_count == 0) {
  82             s->flags |= PL011_FLAG_RXFE;
  83         }
  84         if (s->read_count == s->read_trigger - 1)
  85             s->int_level &= ~ PL011_INT_RX;
  86         s->rsr = c >> 8;
  87         pl011_update(s);
  88         if (s->chr) {
  89             qemu_chr_accept_input(s->chr);
  90         }
  91         return c;
  92     case 1: /* UARTRSR */
  93         return s->rsr;
  94     case 6: /* UARTFR */
  95         return s->flags;
  96     case 8: /* UARTILPR */
  97         return s->ilpr;
  98     case 9: /* UARTIBRD */
  99         return s->ibrd;
 100     case 10: /* UARTFBRD */
 101         return s->fbrd;
 102     case 11: /* UARTLCR_H */
 103         return s->lcr;
 104     case 12: /* UARTCR */
 105         return s->cr;
 106     case 13: /* UARTIFLS */
 107         return s->ifl;
 108     case 14: /* UARTIMSC */
 109         return s->int_enabled;
 110     case 15: /* UARTRIS */
 111         return s->int_level;
 112     case 16: /* UARTMIS */
 113         return s->int_level & s->int_enabled;
 114     case 18: /* UARTDMACR */
 115         return s->dmacr;
 116     default:
 117         qemu_log_mask(LOG_GUEST_ERROR,
 118                       "pl011_read: Bad offset %x\n", (int)offset);
 119         return 0;
 120     }
 121 }
 122
 123 static void pl011_set_read_trigger(PL011State *s)
 124 {
 125 #if 0
 126     /* The docs say the RX interrupt is triggered when the FIFO exceeds
 127        the threshold.  However linux only reads the FIFO in response to an
 128        interrupt.  Triggering the interrupt when the FIFO is non-empty seems
 129        to make things work.  */
 130     if (s->lcr & 0x10)
 131         s->read_trigger = (s->ifl >> 1) & 0x1c;
 132     else
 133 #endif
 134         s->read_trigger = 1;
 135 }
 136
 137 static void pl011_write(void *opaque, hwaddr offset,
 138                         uint64_t value, unsigned size)
 139 {
 140     PL011State *s = (PL011State *)opaque;
 141     unsigned char ch;
 142
 143     switch (offset >> 2) {
 144     case 0: /* UARTDR */
 145         /* ??? Check if transmitter is enabled.  */
 146         ch = value;
 147         if (s->chr)
 148             qemu_chr_fe_write(s->chr, &ch, 1);
 149         s->int_level |= PL011_INT_TX;
 150         pl011_update(s);
 151         break;
 152     case 1: /* UARTRSR/UARTECR */
 153         s->rsr = 0;
 154         break;
 155     case 6: /* UARTFR */
 156         /* Writes to Flag register are ignored.  */
 157         break;
 158     case 8: /* UARTUARTILPR */
 159         s->ilpr = value;
 160         break;
 161     case 9: /* UARTIBRD */
 162         s->ibrd = value;
 163         break;
 164     case 10: /* UARTFBRD */
 165         s->fbrd = value;
 166         break;
 167     case 11: /* UARTLCR_H */
 168         /* Reset the FIFO state on FIFO enable or disable */
 169         if ((s->lcr ^ value) & 0x10) {
 170             s->read_count = 0;
 171             s->read_pos = 0;
 172         }
 173         s->lcr = value;
 174         pl011_set_read_trigger(s);
 175         break;
 176     case 12: /* UARTCR */
 177         /* ??? Need to implement the enable and loopback bits.  */
 178         s->cr = value;
 179         break;
 180     case 13: /* UARTIFS */
 181         s->ifl = value;
 182         pl011_set_read_trigger(s);
 183         break;
 184     case 14: /* UARTIMSC */
 185         s->int_enabled = value;
 186         pl011_update(s);
 187         break;
 188     case 17: /* UARTICR */
 189         s->int_level &= ~value;
 190         pl011_update(s);
 191         break;
 192     case 18: /* UARTDMACR */
 193         s->dmacr = value;
 194         if (value & 3) {
 195             qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");
 196         }
 197         break;
 198     default:
 199         qemu_log_mask(LOG_GUEST_ERROR,
 200                       "pl011_write: Bad offset %x\n", (int)offset);
 201     }
 202 }
 203
 204 static int pl011_can_receive(void *opaque)
 205 {
 206     PL011State *s = (PL011State *)opaque;
 207
 208     if (s->lcr & 0x10)
 209         return s->read_count < 16;
 210     else
 211         return s->read_count < 1;
 212 }
 213
 214 static void pl011_put_fifo(void *opaque, uint32_t value)
 215 {
 216     PL011State *s = (PL011State *)opaque;
 217     int slot;
 218
 219     slot = s->read_pos + s->read_count;
 220     if (slot >= 16)
 221         slot -= 16;
 222     s->read_fifo[slot] = value;
 223     s->read_count++;
 224     s->flags &= ~PL011_FLAG_RXFE;
 225     if (!(s->lcr & 0x10) || s->read_count == 16) {
 226         s->flags |= PL011_FLAG_RXFF;
 227     }
 228     if (s->read_count == s->read_trigger) {
 229         s->int_level |= PL011_INT_RX;
 230         pl011_update(s);
 231     }
 232 }
 233
 234 static void pl011_receive(void *opaque, const uint8_t *buf, int size)
 235 {
 236     pl011_put_fifo(opaque, *buf);
 237 }
 238
 239 static void pl011_event(void *opaque, int event)
 240 {
 241     if (event == CHR_EVENT_BREAK)
 242         pl011_put_fifo(opaque, 0x400);
 243 }
 244
 245 static const MemoryRegionOps pl011_ops = {
 246     .read = pl011_read,
 247     .write = pl011_write,
 248     .endianness = DEVICE_NATIVE_ENDIAN,
 249 };
 250
 251 static const VMStateDescription vmstate_pl011 = {
 252     .name = "pl011",
 253     .version_id = 2,
 254     .minimum_version_id = 2,
 255     .fields = (VMStateField[]) {
 256         VMSTATE_UINT32(readbuff, PL011State),
 257         VMSTATE_UINT32(flags, PL011State),
 258         VMSTATE_UINT32(lcr, PL011State),
 259         VMSTATE_UINT32(rsr, PL011State),
 260         VMSTATE_UINT32(cr, PL011State),
 261         VMSTATE_UINT32(dmacr, PL011State),
 262         VMSTATE_UINT32(int_enabled, PL011State),
 263         VMSTATE_UINT32(int_level, PL011State),
 264         VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
 265         VMSTATE_UINT32(ilpr, PL011State),
 266         VMSTATE_UINT32(ibrd, PL011State),
 267         VMSTATE_UINT32(fbrd, PL011State),
 268         VMSTATE_UINT32(ifl, PL011State),
 269         VMSTATE_INT32(read_pos, PL011State),
 270         VMSTATE_INT32(read_count, PL011State),
 271         VMSTATE_INT32(read_trigger, PL011State),
 272         VMSTATE_END_OF_LIST()
 273     }
 274 };
 275
 276 static void pl011_init(Object *obj)
 277 {
 278     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 279     PL011State *s = PL011(obj);
 280
 281     memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
 282     sysbus_init_mmio(sbd, &s->iomem);
 283     sysbus_init_irq(sbd, &s->irq);
 284
 285     s->read_trigger = 1;
 286     s->ifl = 0x12;
 287     s->cr = 0x300;
 288     s->flags = 0x90;
 289
 290     s->id = pl011_id_arm;
 291 }
 292
 293 static void pl011_realize(DeviceState *dev, Error **errp)
 294 {
 295     PL011State *s = PL011(dev);
 296
 297     /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
 298     s->chr = qemu_char_get_next_serial();
 299
 300     if (s->chr) {
 301         qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
 302                               pl011_event, s);
 303     }
 304 }
 305
 306 static void pl011_class_init(ObjectClass *oc, void *data)
 307 {
 308     DeviceClass *dc = DEVICE_CLASS(oc);
 309
 310     dc->realize = pl011_realize;
 311     dc->vmsd = &vmstate_pl011;
 312     /* Reason: realize() method uses qemu_char_get_next_serial() */
 313     dc->cannot_instantiate_with_device_add_yet = true;
 314 }
 315
 316 static const TypeInfo pl011_arm_info = {
 317     .name          = TYPE_PL011,
 318     .parent        = TYPE_SYS_BUS_DEVICE,
 319     .instance_size = sizeof(PL011State),
 320     .instance_init = pl011_init,
 321     .class_init    = pl011_class_init,
 322 };
 323
 324 static void pl011_luminary_init(Object *obj)
 325 {
 326     PL011State *s = PL011(obj);
 327
 328     s->id = pl011_id_luminary;
 329 }
 330
 331 static const TypeInfo pl011_luminary_info = {
 332     .name          = "pl011_luminary",
 333     .parent        = TYPE_PL011,
 334     .instance_init = pl011_luminary_init,
 335 };
 336
 337 static void pl011_register_types(void)
 338 {
 339     type_register_static(&pl011_arm_info);
 340     type_register_static(&pl011_luminary_info);
 341 }
 342
 343 type_init(pl011_register_types)