hw/pci-host/gpex-acpi.c

   1 #include "qemu/osdep.h"
   2 #include "hw/acpi/aml-build.h"
   3 #include "hw/pci-host/gpex.h"
   4 #include "hw/arm/virt.h"
   5 #include "hw/pci/pci_bus.h"
   6 #include "hw/pci/pci_bridge.h"
   7 #include "hw/pci/pcie_host.h"
   8
   9 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
  10 {
  11     Aml *method, *crs;
  12     int i, slot_no;
  13
  14     /* Declare the PCI Routing Table. */
  15     Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
  16     for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
  17         for (i = 0; i < PCI_NUM_PINS; i++) {
  18             int gsi = (i + slot_no) % PCI_NUM_PINS;
  19             Aml *pkg = aml_package(4);
  20             aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
  21             aml_append(pkg, aml_int(i));
  22             aml_append(pkg, aml_name("GSI%d", gsi));
  23             aml_append(pkg, aml_int(0));
  24             aml_append(rt_pkg, pkg);
  25         }
  26     }
  27     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
  28
  29     /* Create GSI link device */
  30     for (i = 0; i < PCI_NUM_PINS; i++) {
  31         uint32_t irqs = irq + i;
  32         Aml *dev_gsi = aml_device("GSI%d", i);
  33         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
  34         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
  35         crs = aml_resource_template();
  36         aml_append(crs,
  37                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  38                                  AML_EXCLUSIVE, &irqs, 1));
  39         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
  40         crs = aml_resource_template();
  41         aml_append(crs,
  42                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  43                                  AML_EXCLUSIVE, &irqs, 1));
  44         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
  45         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
  46         aml_append(dev_gsi, method);
  47         aml_append(dev, dev_gsi);
  48     }
  49 }
  50
  51 static void acpi_dsdt_add_pci_osc(Aml *dev)
  52 {
  53     Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
  54
  55     /* Declare an _OSC (OS Control Handoff) method */
  56     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
  57     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
  58     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
  59     aml_append(method,
  60         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
  61
  62     /* PCI Firmware Specification 3.0
  63      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
  64      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
  65      * identified by the Universal Unique IDentifier (UUID)
  66      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
  67      */
  68     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
  69     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
  70     aml_append(ifctx,
  71         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
  72     aml_append(ifctx,
  73         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
  74     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
  75     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
  76
  77     /*
  78      * Allow OS control for all 5 features:
  79      * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
  80      */
  81     aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
  82                               aml_name("CTRL")));
  83
  84     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
  85     aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
  86                               aml_name("CDW1")));
  87     aml_append(ifctx, ifctx1);
  88
  89     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
  90     aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
  91                               aml_name("CDW1")));
  92     aml_append(ifctx, ifctx1);
  93
  94     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
  95     aml_append(ifctx, aml_return(aml_arg(3)));
  96     aml_append(method, ifctx);
  97
  98     elsectx = aml_else();
  99     aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
 100                                aml_name("CDW1")));
 101     aml_append(elsectx, aml_return(aml_arg(3)));
 102     aml_append(method, elsectx);
 103     aml_append(dev, method);
 104
 105     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 106
 107     /* PCI Firmware Specification 3.0
 108      * 4.6.1. _DSM for PCI Express Slot Information
 109      * The UUID in _DSM in this context is
 110      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 111      */
 112     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 113     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 114     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 115     uint8_t byte_list[] = {
 116                 0x1 << 0 /* support for functions other than function 0 */ |
 117                 0x1 << 5 /* support for function 5 */
 118                 };
 119     buf = aml_buffer(ARRAY_SIZE(byte_list), byte_list);
 120     aml_append(ifctx1, aml_return(buf));
 121     aml_append(ifctx, ifctx1);
 122
 123     /*
 124      * PCI Firmware Specification 3.1
 125      * 4.6.5. _DSM for Ignoring PCI Boot Configurations
 126      */
 127     /* Arg2: Function Index: 5 */
 128     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(5)));
 129     /*
 130      * 0 - The operating system must not ignore the PCI configuration that
 131      *     firmware has done at boot time.
 132      */
 133     aml_append(ifctx1, aml_return(aml_int(0)));
 134     aml_append(ifctx, ifctx1);
 135     aml_append(method, ifctx);
 136
 137     byte_list[0] = 0;
 138     buf = aml_buffer(1, byte_list);
 139     aml_append(method, aml_return(buf));
 140     aml_append(dev, method);
 141 }
 142
 143 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
 144 {
 145     int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
 146     Aml *method, *crs, *dev, *rbuf;
 147     PCIBus *bus = cfg->bus;
 148     CrsRangeSet crs_range_set;
 149     CrsRangeEntry *entry;
 150     int i;
 151
 152     /* start to construct the tables for pxb */
 153     crs_range_set_init(&crs_range_set);
 154     if (bus) {
 155         QLIST_FOREACH(bus, &bus->child, sibling) {
 156             uint8_t bus_num = pci_bus_num(bus);
 157             uint8_t numa_node = pci_bus_numa_node(bus);
 158
 159             if (!pci_bus_is_root(bus)) {
 160                 continue;
 161             }
 162
 163             /*
 164              * 0 - (nr_pcie_buses - 1) is the bus range for the main
 165              * host-bridge and it equals the MIN of the
 166              * busNr defined for pxb-pcie.
 167              */
 168             if (bus_num < nr_pcie_buses) {
 169                 nr_pcie_buses = bus_num;
 170             }
 171
 172             dev = aml_device("PC%.02X", bus_num);
 173             aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 174             aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 175             aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
 176             aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
 177             aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
 178             aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 179             if (numa_node != NUMA_NODE_UNASSIGNED) {
 180                 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
 181             }
 182
 183             acpi_dsdt_add_pci_route_table(dev, cfg->irq);
 184
 185             /*
 186              * Resources defined for PXBs are composed by the folling parts:
 187              * 1. The resources the pci-brige/pcie-root-port need.
 188              * 2. The resources the devices behind pxb need.
 189              */
 190             crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
 191                             cfg->pio.base, 0, 0, 0);
 192             aml_append(dev, aml_name_decl("_CRS", crs));
 193
 194             acpi_dsdt_add_pci_osc(dev);
 195
 196             aml_append(scope, dev);
 197         }
 198     }
 199
 200     /* tables for the main */
 201     dev = aml_device("%s", "PCI0");
 202     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 203     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 204     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 205     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 206     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 207     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 208     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 209
 210     acpi_dsdt_add_pci_route_table(dev, cfg->irq);
 211
 212     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 213     aml_append(method, aml_return(aml_int(cfg->ecam.base)));
 214     aml_append(dev, method);
 215
 216     /*
 217      * At this point crs_range_set has all the ranges used by pci
 218      * busses *other* than PCI0.  These ranges will be excluded from
 219      * the PCI0._CRS.
 220      */
 221     rbuf = aml_resource_template();
 222     aml_append(rbuf,
 223         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 224                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 225                             nr_pcie_buses));
 226     if (cfg->mmio32.size) {
 227         crs_replace_with_free_ranges(crs_range_set.mem_ranges,
 228                                      cfg->mmio32.base,
 229                                      cfg->mmio32.base + cfg->mmio32.size - 1);
 230         for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
 231             entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
 232             aml_append(rbuf,
 233                 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 234                                  AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 235                                  entry->base, entry->limit,
 236                                  0x0000, entry->limit - entry->base + 1));
 237         }
 238     }
 239     if (cfg->pio.size) {
 240         crs_replace_with_free_ranges(crs_range_set.io_ranges,
 241                                      0x0000,
 242                                      cfg->pio.size - 1);
 243         for (i = 0; i < crs_range_set.io_ranges->len; i++) {
 244             entry = g_ptr_array_index(crs_range_set.io_ranges, i);
 245             aml_append(rbuf,
 246                 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 247                              AML_ENTIRE_RANGE, 0x0000, entry->base,
 248                              entry->limit, cfg->pio.base,
 249                              entry->limit - entry->base + 1));
 250         }
 251     }
 252     if (cfg->mmio64.size) {
 253         crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
 254                                      cfg->mmio64.base,
 255                                      cfg->mmio64.base + cfg->mmio64.size - 1);
 256         for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
 257             entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
 258             aml_append(rbuf,
 259                 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 260                                  AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 261                                  entry->base,
 262                                  entry->limit, 0x0000,
 263                                  entry->limit - entry->base + 1));
 264         }
 265     }
 266     aml_append(dev, aml_name_decl("_CRS", rbuf));
 267
 268     acpi_dsdt_add_pci_osc(dev);
 269
 270     Aml *dev_res0 = aml_device("%s", "RES0");
 271     aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
 272     crs = aml_resource_template();
 273     aml_append(crs,
 274         aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 275                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 276                          cfg->ecam.base,
 277                          cfg->ecam.base + cfg->ecam.size - 1,
 278                          0x0000,
 279                          cfg->ecam.size));
 280     aml_append(dev_res0, aml_name_decl("_CRS", crs));
 281     aml_append(dev, dev_res0);
 282     aml_append(scope, dev);
 283
 284     crs_range_set_free(&crs_range_set);
 285 }