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target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
[qemu/ar7.git] / target-i386 / kvm.c
blob41d09e52dedd692f6a6c8e69187c9c306e289313
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "qapi/qmp/qerror.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_bndcfgs;
77 static bool has_msr_kvm_steal_time;
78 static int lm_capable_kernel;
79 static bool has_msr_hv_hypercall;
80 static bool has_msr_hv_vapic;
81 static bool has_msr_hv_tsc;
82 static bool has_msr_mtrr;
83 static bool has_msr_xss;
84
85 static bool has_msr_architectural_pmu;
86 static uint32_t num_architectural_pmu_counters;
87
88 bool kvm_allows_irq0_override(void)
89 {
90 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
91 }
92
93 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
94 {
95 struct kvm_cpuid2 *cpuid;
96 int r, size;
97
98 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
99 cpuid = g_malloc0(size);
100 cpuid->nent = max;
101 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
102 if (r == 0 && cpuid->nent >= max) {
103 r = -E2BIG;
104 }
105 if (r < 0) {
106 if (r == -E2BIG) {
107 g_free(cpuid);
108 return NULL;
109 } else {
110 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
111 strerror(-r));
112 exit(1);
113 }
114 }
115 return cpuid;
116 }
117
118 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
119 * for all entries.
120 */
121 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
122 {
123 struct kvm_cpuid2 *cpuid;
124 int max = 1;
125 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
126 max *= 2;
127 }
128 return cpuid;
129 }
130
131 static const struct kvm_para_features {
132 int cap;
133 int feature;
134 } para_features[] = {
135 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
136 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
137 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
138 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
139 };
140
141 static int get_para_features(KVMState *s)
142 {
143 int i, features = 0;
144
145 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
146 if (kvm_check_extension(s, para_features[i].cap)) {
147 features |= (1 << para_features[i].feature);
148 }
149 }
150
151 return features;
152 }
153
154
155 /* Returns the value for a specific register on the cpuid entry
156 */
157 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
158 {
159 uint32_t ret = 0;
160 switch (reg) {
161 case R_EAX:
162 ret = entry->eax;
163 break;
164 case R_EBX:
165 ret = entry->ebx;
166 break;
167 case R_ECX:
168 ret = entry->ecx;
169 break;
170 case R_EDX:
171 ret = entry->edx;
172 break;
173 }
174 return ret;
175 }
176
177 /* Find matching entry for function/index on kvm_cpuid2 struct
178 */
179 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
180 uint32_t function,
181 uint32_t index)
182 {
183 int i;
184 for (i = 0; i < cpuid->nent; ++i) {
185 if (cpuid->entries[i].function == function &&
186 cpuid->entries[i].index == index) {
187 return &cpuid->entries[i];
188 }
189 }
190 /* not found: */
191 return NULL;
192 }
193
194 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
195 uint32_t index, int reg)
196 {
197 struct kvm_cpuid2 *cpuid;
198 uint32_t ret = 0;
199 uint32_t cpuid_1_edx;
200 bool found = false;
201
202 cpuid = get_supported_cpuid(s);
203
204 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
205 if (entry) {
206 found = true;
207 ret = cpuid_entry_get_reg(entry, reg);
208 }
209
210 /* Fixups for the data returned by KVM, below */
211
212 if (function == 1 && reg == R_EDX) {
213 /* KVM before 2.6.30 misreports the following features */
214 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
215 } else if (function == 1 && reg == R_ECX) {
216 /* We can set the hypervisor flag, even if KVM does not return it on
217 * GET_SUPPORTED_CPUID
218 */
219 ret |= CPUID_EXT_HYPERVISOR;
220 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
221 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
222 * and the irqchip is in the kernel.
223 */
224 if (kvm_irqchip_in_kernel() &&
225 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
226 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
227 }
228
229 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
230 * without the in-kernel irqchip
231 */
232 if (!kvm_irqchip_in_kernel()) {
233 ret &= ~CPUID_EXT_X2APIC;
234 }
235 } else if (function == 0x80000001 && reg == R_EDX) {
236 /* On Intel, kvm returns cpuid according to the Intel spec,
237 * so add missing bits according to the AMD spec:
238 */
239 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
240 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
241 }
242
243 g_free(cpuid);
244
245 /* fallback for older kernels */
246 if ((function == KVM_CPUID_FEATURES) && !found) {
247 ret = get_para_features(s);
248 }
249
250 return ret;
251 }
252
253 typedef struct HWPoisonPage {
254 ram_addr_t ram_addr;
255 QLIST_ENTRY(HWPoisonPage) list;
256 } HWPoisonPage;
257
258 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
259 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
260
261 static void kvm_unpoison_all(void *param)
262 {
263 HWPoisonPage *page, *next_page;
264
265 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
266 QLIST_REMOVE(page, list);
267 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
268 g_free(page);
269 }
270 }
271
272 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
273 {
274 HWPoisonPage *page;
275
276 QLIST_FOREACH(page, &hwpoison_page_list, list) {
277 if (page->ram_addr == ram_addr) {
278 return;
279 }
280 }
281 page = g_new(HWPoisonPage, 1);
282 page->ram_addr = ram_addr;
283 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
284 }
285
286 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
287 int *max_banks)
288 {
289 int r;
290
291 r = kvm_check_extension(s, KVM_CAP_MCE);
292 if (r > 0) {
293 *max_banks = r;
294 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
295 }
296 return -ENOSYS;
297 }
298
299 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
300 {
301 CPUX86State *env = &cpu->env;
302 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
303 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
304 uint64_t mcg_status = MCG_STATUS_MCIP;
305
306 if (code == BUS_MCEERR_AR) {
307 status |= MCI_STATUS_AR | 0x134;
308 mcg_status |= MCG_STATUS_EIPV;
309 } else {
310 status |= 0xc0;
311 mcg_status |= MCG_STATUS_RIPV;
312 }
313 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
314 (MCM_ADDR_PHYS << 6) | 0xc,
315 cpu_x86_support_mca_broadcast(env) ?
316 MCE_INJECT_BROADCAST : 0);
317 }
318
319 static void hardware_memory_error(void)
320 {
321 fprintf(stderr, "Hardware memory error!\n");
322 exit(1);
323 }
324
325 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
326 {
327 X86CPU *cpu = X86_CPU(c);
328 CPUX86State *env = &cpu->env;
329 ram_addr_t ram_addr;
330 hwaddr paddr;
331
332 if ((env->mcg_cap & MCG_SER_P) && addr
333 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
334 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
335 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
336 fprintf(stderr, "Hardware memory error for memory used by "
337 "QEMU itself instead of guest system!\n");
338 /* Hope we are lucky for AO MCE */
339 if (code == BUS_MCEERR_AO) {
340 return 0;
341 } else {
342 hardware_memory_error();
343 }
344 }
345 kvm_hwpoison_page_add(ram_addr);
346 kvm_mce_inject(cpu, paddr, code);
347 } else {
348 if (code == BUS_MCEERR_AO) {
349 return 0;
350 } else if (code == BUS_MCEERR_AR) {
351 hardware_memory_error();
352 } else {
353 return 1;
354 }
355 }
356 return 0;
357 }
358
359 int kvm_arch_on_sigbus(int code, void *addr)
360 {
361 X86CPU *cpu = X86_CPU(first_cpu);
362
363 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
364 ram_addr_t ram_addr;
365 hwaddr paddr;
366
367 /* Hope we are lucky for AO MCE */
368 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
369 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
370 addr, &paddr)) {
371 fprintf(stderr, "Hardware memory error for memory used by "
372 "QEMU itself instead of guest system!: %p\n", addr);
373 return 0;
374 }
375 kvm_hwpoison_page_add(ram_addr);
376 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
377 } else {
378 if (code == BUS_MCEERR_AO) {
379 return 0;
380 } else if (code == BUS_MCEERR_AR) {
381 hardware_memory_error();
382 } else {
383 return 1;
384 }
385 }
386 return 0;
387 }
388
389 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
390 {
391 CPUX86State *env = &cpu->env;
392
393 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
394 unsigned int bank, bank_num = env->mcg_cap & 0xff;
395 struct kvm_x86_mce mce;
396
397 env->exception_injected = -1;
398
399 /*
400 * There must be at least one bank in use if an MCE is pending.
401 * Find it and use its values for the event injection.
402 */
403 for (bank = 0; bank < bank_num; bank++) {
404 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
405 break;
406 }
407 }
408 assert(bank < bank_num);
409
410 mce.bank = bank;
411 mce.status = env->mce_banks[bank * 4 + 1];
412 mce.mcg_status = env->mcg_status;
413 mce.addr = env->mce_banks[bank * 4 + 2];
414 mce.misc = env->mce_banks[bank * 4 + 3];
415
416 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
417 }
418 return 0;
419 }
420
421 static void cpu_update_state(void *opaque, int running, RunState state)
422 {
423 CPUX86State *env = opaque;
424
425 if (running) {
426 env->tsc_valid = false;
427 }
428 }
429
430 unsigned long kvm_arch_vcpu_id(CPUState *cs)
431 {
432 X86CPU *cpu = X86_CPU(cs);
433 return cpu->apic_id;
434 }
435
436 #ifndef KVM_CPUID_SIGNATURE_NEXT
437 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
438 #endif
439
440 static bool hyperv_hypercall_available(X86CPU *cpu)
441 {
442 return cpu->hyperv_vapic ||
443 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
444 }
445
446 static bool hyperv_enabled(X86CPU *cpu)
447 {
448 CPUState *cs = CPU(cpu);
449 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
450 (hyperv_hypercall_available(cpu) ||
451 cpu->hyperv_time ||
452 cpu->hyperv_relaxed_timing);
453 }
454
455 static Error *invtsc_mig_blocker;
456
457 #define KVM_MAX_CPUID_ENTRIES 100
458
459 int kvm_arch_init_vcpu(CPUState *cs)
460 {
461 struct {
462 struct kvm_cpuid2 cpuid;
463 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
464 } QEMU_PACKED cpuid_data;
465 X86CPU *cpu = X86_CPU(cs);
466 CPUX86State *env = &cpu->env;
467 uint32_t limit, i, j, cpuid_i;
468 uint32_t unused;
469 struct kvm_cpuid_entry2 *c;
470 uint32_t signature[3];
471 int kvm_base = KVM_CPUID_SIGNATURE;
472 int r;
473
474 memset(&cpuid_data, 0, sizeof(cpuid_data));
475
476 cpuid_i = 0;
477
478 /* Paravirtualization CPUIDs */
479 if (hyperv_enabled(cpu)) {
480 c = &cpuid_data.entries[cpuid_i++];
481 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
482 memcpy(signature, "Microsoft Hv", 12);
483 c->eax = HYPERV_CPUID_MIN;
484 c->ebx = signature[0];
485 c->ecx = signature[1];
486 c->edx = signature[2];
487
488 c = &cpuid_data.entries[cpuid_i++];
489 c->function = HYPERV_CPUID_INTERFACE;
490 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
491 c->eax = signature[0];
492 c->ebx = 0;
493 c->ecx = 0;
494 c->edx = 0;
495
496 c = &cpuid_data.entries[cpuid_i++];
497 c->function = HYPERV_CPUID_VERSION;
498 c->eax = 0x00001bbc;
499 c->ebx = 0x00060001;
500
501 c = &cpuid_data.entries[cpuid_i++];
502 c->function = HYPERV_CPUID_FEATURES;
503 if (cpu->hyperv_relaxed_timing) {
504 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
505 }
506 if (cpu->hyperv_vapic) {
507 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
508 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
509 has_msr_hv_vapic = true;
510 }
511 if (cpu->hyperv_time &&
512 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
513 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
514 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
515 c->eax |= 0x200;
516 has_msr_hv_tsc = true;
517 }
518 c = &cpuid_data.entries[cpuid_i++];
519 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
520 if (cpu->hyperv_relaxed_timing) {
521 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
522 }
523 if (has_msr_hv_vapic) {
524 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
525 }
526 c->ebx = cpu->hyperv_spinlock_attempts;
527
528 c = &cpuid_data.entries[cpuid_i++];
529 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
530 c->eax = 0x40;
531 c->ebx = 0x40;
532
533 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
534 has_msr_hv_hypercall = true;
535 }
536
537 if (cpu->expose_kvm) {
538 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
539 c = &cpuid_data.entries[cpuid_i++];
540 c->function = KVM_CPUID_SIGNATURE | kvm_base;
541 c->eax = KVM_CPUID_FEATURES | kvm_base;
542 c->ebx = signature[0];
543 c->ecx = signature[1];
544 c->edx = signature[2];
545
546 c = &cpuid_data.entries[cpuid_i++];
547 c->function = KVM_CPUID_FEATURES | kvm_base;
548 c->eax = env->features[FEAT_KVM];
549
550 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
551
552 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
553
554 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
555 }
556
557 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
558
559 for (i = 0; i <= limit; i++) {
560 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
561 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
562 abort();
563 }
564 c = &cpuid_data.entries[cpuid_i++];
565
566 switch (i) {
567 case 2: {
568 /* Keep reading function 2 till all the input is received */
569 int times;
570
571 c->function = i;
572 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
573 KVM_CPUID_FLAG_STATE_READ_NEXT;
574 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
575 times = c->eax & 0xff;
576
577 for (j = 1; j < times; ++j) {
578 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
579 fprintf(stderr, "cpuid_data is full, no space for "
580 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
581 abort();
582 }
583 c = &cpuid_data.entries[cpuid_i++];
584 c->function = i;
585 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
586 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
587 }
588 break;
589 }
590 case 4:
591 case 0xb:
592 case 0xd:
593 for (j = 0; ; j++) {
594 if (i == 0xd && j == 64) {
595 break;
596 }
597 c->function = i;
598 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
599 c->index = j;
600 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
601
602 if (i == 4 && c->eax == 0) {
603 break;
604 }
605 if (i == 0xb && !(c->ecx & 0xff00)) {
606 break;
607 }
608 if (i == 0xd && c->eax == 0) {
609 continue;
610 }
611 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
612 fprintf(stderr, "cpuid_data is full, no space for "
613 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
614 abort();
615 }
616 c = &cpuid_data.entries[cpuid_i++];
617 }
618 break;
619 default:
620 c->function = i;
621 c->flags = 0;
622 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
623 break;
624 }
625 }
626
627 if (limit >= 0x0a) {
628 uint32_t ver;
629
630 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
631 if ((ver & 0xff) > 0) {
632 has_msr_architectural_pmu = true;
633 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
634
635 /* Shouldn't be more than 32, since that's the number of bits
636 * available in EBX to tell us _which_ counters are available.
637 * Play it safe.
638 */
639 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
640 num_architectural_pmu_counters = MAX_GP_COUNTERS;
641 }
642 }
643 }
644
645 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
646
647 for (i = 0x80000000; i <= limit; i++) {
648 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
649 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
650 abort();
651 }
652 c = &cpuid_data.entries[cpuid_i++];
653
654 c->function = i;
655 c->flags = 0;
656 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
657 }
658
659 /* Call Centaur's CPUID instructions they are supported. */
660 if (env->cpuid_xlevel2 > 0) {
661 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
662
663 for (i = 0xC0000000; i <= limit; i++) {
664 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
665 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
666 abort();
667 }
668 c = &cpuid_data.entries[cpuid_i++];
669
670 c->function = i;
671 c->flags = 0;
672 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
673 }
674 }
675
676 cpuid_data.cpuid.nent = cpuid_i;
677
678 if (((env->cpuid_version >> 8)&0xF) >= 6
679 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
680 (CPUID_MCE | CPUID_MCA)
681 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
682 uint64_t mcg_cap;
683 int banks;
684 int ret;
685
686 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
687 if (ret < 0) {
688 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
689 return ret;
690 }
691
692 if (banks > MCE_BANKS_DEF) {
693 banks = MCE_BANKS_DEF;
694 }
695 mcg_cap &= MCE_CAP_DEF;
696 mcg_cap |= banks;
697 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
698 if (ret < 0) {
699 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
700 return ret;
701 }
702
703 env->mcg_cap = mcg_cap;
704 }
705
706 qemu_add_vm_change_state_handler(cpu_update_state, env);
707
708 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
709 if (c) {
710 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
711 !!(c->ecx & CPUID_EXT_SMX);
712 }
713
714 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
715 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
716 /* for migration */
717 error_setg(&invtsc_mig_blocker,
718 "State blocked by non-migratable CPU device"
719 " (invtsc flag)");
720 migrate_add_blocker(invtsc_mig_blocker);
721 /* for savevm */
722 vmstate_x86_cpu.unmigratable = 1;
723 }
724
725 cpuid_data.cpuid.padding = 0;
726 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
727 if (r) {
728 return r;
729 }
730
731 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
732 if (r && env->tsc_khz) {
733 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
734 if (r < 0) {
735 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
736 return r;
737 }
738 }
739
740 if (kvm_has_xsave()) {
741 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
742 }
743
744 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
745 has_msr_mtrr = true;
746 }
747
748 return 0;
749 }
750
751 void kvm_arch_reset_vcpu(X86CPU *cpu)
752 {
753 CPUX86State *env = &cpu->env;
754
755 env->exception_injected = -1;
756 env->interrupt_injected = -1;
757 env->xcr0 = 1;
758 if (kvm_irqchip_in_kernel()) {
759 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
760 KVM_MP_STATE_UNINITIALIZED;
761 } else {
762 env->mp_state = KVM_MP_STATE_RUNNABLE;
763 }
764 }
765
766 void kvm_arch_do_init_vcpu(X86CPU *cpu)
767 {
768 CPUX86State *env = &cpu->env;
769
770 /* APs get directly into wait-for-SIPI state. */
771 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
772 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
773 }
774 }
775
776 static int kvm_get_supported_msrs(KVMState *s)
777 {
778 static int kvm_supported_msrs;
779 int ret = 0;
780
781 /* first time */
782 if (kvm_supported_msrs == 0) {
783 struct kvm_msr_list msr_list, *kvm_msr_list;
784
785 kvm_supported_msrs = -1;
786
787 /* Obtain MSR list from KVM. These are the MSRs that we must
788 * save/restore */
789 msr_list.nmsrs = 0;
790 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
791 if (ret < 0 && ret != -E2BIG) {
792 return ret;
793 }
794 /* Old kernel modules had a bug and could write beyond the provided
795 memory. Allocate at least a safe amount of 1K. */
796 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
797 msr_list.nmsrs *
798 sizeof(msr_list.indices[0])));
799
800 kvm_msr_list->nmsrs = msr_list.nmsrs;
801 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
802 if (ret >= 0) {
803 int i;
804
805 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
806 if (kvm_msr_list->indices[i] == MSR_STAR) {
807 has_msr_star = true;
808 continue;
809 }
810 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
811 has_msr_hsave_pa = true;
812 continue;
813 }
814 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
815 has_msr_tsc_adjust = true;
816 continue;
817 }
818 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
819 has_msr_tsc_deadline = true;
820 continue;
821 }
822 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
823 has_msr_misc_enable = true;
824 continue;
825 }
826 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
827 has_msr_bndcfgs = true;
828 continue;
829 }
830 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
831 has_msr_xss = true;
832 continue;
833 }
834 }
835 }
836
837 g_free(kvm_msr_list);
838 }
839
840 return ret;
841 }
842
843 int kvm_arch_init(MachineState *ms, KVMState *s)
844 {
845 uint64_t identity_base = 0xfffbc000;
846 uint64_t shadow_mem;
847 int ret;
848 struct utsname utsname;
849
850 ret = kvm_get_supported_msrs(s);
851 if (ret < 0) {
852 return ret;
853 }
854
855 uname(&utsname);
856 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
857
858 /*
859 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
860 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
861 * Since these must be part of guest physical memory, we need to allocate
862 * them, both by setting their start addresses in the kernel and by
863 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
864 *
865 * Older KVM versions may not support setting the identity map base. In
866 * that case we need to stick with the default, i.e. a 256K maximum BIOS
867 * size.
868 */
869 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
870 /* Allows up to 16M BIOSes. */
871 identity_base = 0xfeffc000;
872
873 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
874 if (ret < 0) {
875 return ret;
876 }
877 }
878
879 /* Set TSS base one page after EPT identity map. */
880 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
881 if (ret < 0) {
882 return ret;
883 }
884
885 /* Tell fw_cfg to notify the BIOS to reserve the range. */
886 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
887 if (ret < 0) {
888 fprintf(stderr, "e820_add_entry() table is full\n");
889 return ret;
890 }
891 qemu_register_reset(kvm_unpoison_all, NULL);
892
893 shadow_mem = machine_kvm_shadow_mem(ms);
894 if (shadow_mem != -1) {
895 shadow_mem /= 4096;
896 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
897 if (ret < 0) {
898 return ret;
899 }
900 }
901 return 0;
902 }
903
904 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
905 {
906 lhs->selector = rhs->selector;
907 lhs->base = rhs->base;
908 lhs->limit = rhs->limit;
909 lhs->type = 3;
910 lhs->present = 1;
911 lhs->dpl = 3;
912 lhs->db = 0;
913 lhs->s = 1;
914 lhs->l = 0;
915 lhs->g = 0;
916 lhs->avl = 0;
917 lhs->unusable = 0;
918 }
919
920 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
921 {
922 unsigned flags = rhs->flags;
923 lhs->selector = rhs->selector;
924 lhs->base = rhs->base;
925 lhs->limit = rhs->limit;
926 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
927 lhs->present = (flags & DESC_P_MASK) != 0;
928 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
929 lhs->db = (flags >> DESC_B_SHIFT) & 1;
930 lhs->s = (flags & DESC_S_MASK) != 0;
931 lhs->l = (flags >> DESC_L_SHIFT) & 1;
932 lhs->g = (flags & DESC_G_MASK) != 0;
933 lhs->avl = (flags & DESC_AVL_MASK) != 0;
934 lhs->unusable = 0;
935 lhs->padding = 0;
936 }
937
938 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
939 {
940 lhs->selector = rhs->selector;
941 lhs->base = rhs->base;
942 lhs->limit = rhs->limit;
943 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
944 (rhs->present * DESC_P_MASK) |
945 (rhs->dpl << DESC_DPL_SHIFT) |
946 (rhs->db << DESC_B_SHIFT) |
947 (rhs->s * DESC_S_MASK) |
948 (rhs->l << DESC_L_SHIFT) |
949 (rhs->g * DESC_G_MASK) |
950 (rhs->avl * DESC_AVL_MASK);
951 }
952
953 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
954 {
955 if (set) {
956 *kvm_reg = *qemu_reg;
957 } else {
958 *qemu_reg = *kvm_reg;
959 }
960 }
961
962 static int kvm_getput_regs(X86CPU *cpu, int set)
963 {
964 CPUX86State *env = &cpu->env;
965 struct kvm_regs regs;
966 int ret = 0;
967
968 if (!set) {
969 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
970 if (ret < 0) {
971 return ret;
972 }
973 }
974
975 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
976 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
977 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
978 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
979 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
980 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
981 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
982 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
983 #ifdef TARGET_X86_64
984 kvm_getput_reg(&regs.r8, &env->regs[8], set);
985 kvm_getput_reg(&regs.r9, &env->regs[9], set);
986 kvm_getput_reg(&regs.r10, &env->regs[10], set);
987 kvm_getput_reg(&regs.r11, &env->regs[11], set);
988 kvm_getput_reg(&regs.r12, &env->regs[12], set);
989 kvm_getput_reg(&regs.r13, &env->regs[13], set);
990 kvm_getput_reg(&regs.r14, &env->regs[14], set);
991 kvm_getput_reg(&regs.r15, &env->regs[15], set);
992 #endif
993
994 kvm_getput_reg(&regs.rflags, &env->eflags, set);
995 kvm_getput_reg(&regs.rip, &env->eip, set);
996
997 if (set) {
998 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
999 }
1000
1001 return ret;
1002 }
1003
1004 static int kvm_put_fpu(X86CPU *cpu)
1005 {
1006 CPUX86State *env = &cpu->env;
1007 struct kvm_fpu fpu;
1008 int i;
1009
1010 memset(&fpu, 0, sizeof fpu);
1011 fpu.fsw = env->fpus & ~(7 << 11);
1012 fpu.fsw |= (env->fpstt & 7) << 11;
1013 fpu.fcw = env->fpuc;
1014 fpu.last_opcode = env->fpop;
1015 fpu.last_ip = env->fpip;
1016 fpu.last_dp = env->fpdp;
1017 for (i = 0; i < 8; ++i) {
1018 fpu.ftwx |= (!env->fptags[i]) << i;
1019 }
1020 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1021 for (i = 0; i < CPU_NB_REGS; i++) {
1022 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1023 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1024 }
1025 fpu.mxcsr = env->mxcsr;
1026
1027 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1028 }
1029
1030 #define XSAVE_FCW_FSW 0
1031 #define XSAVE_FTW_FOP 1
1032 #define XSAVE_CWD_RIP 2
1033 #define XSAVE_CWD_RDP 4
1034 #define XSAVE_MXCSR 6
1035 #define XSAVE_ST_SPACE 8
1036 #define XSAVE_XMM_SPACE 40
1037 #define XSAVE_XSTATE_BV 128
1038 #define XSAVE_YMMH_SPACE 144
1039 #define XSAVE_BNDREGS 240
1040 #define XSAVE_BNDCSR 256
1041 #define XSAVE_OPMASK 272
1042 #define XSAVE_ZMM_Hi256 288
1043 #define XSAVE_Hi16_ZMM 416
1044
1045 static int kvm_put_xsave(X86CPU *cpu)
1046 {
1047 CPUX86State *env = &cpu->env;
1048 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1049 uint16_t cwd, swd, twd;
1050 uint8_t *xmm, *ymmh, *zmmh;
1051 int i, r;
1052
1053 if (!kvm_has_xsave()) {
1054 return kvm_put_fpu(cpu);
1055 }
1056
1057 memset(xsave, 0, sizeof(struct kvm_xsave));
1058 twd = 0;
1059 swd = env->fpus & ~(7 << 11);
1060 swd |= (env->fpstt & 7) << 11;
1061 cwd = env->fpuc;
1062 for (i = 0; i < 8; ++i) {
1063 twd |= (!env->fptags[i]) << i;
1064 }
1065 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1066 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1067 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1068 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1069 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1070 sizeof env->fpregs);
1071 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1072 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1073 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1074 sizeof env->bnd_regs);
1075 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1076 sizeof(env->bndcs_regs));
1077 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1078 sizeof env->opmask_regs);
1079
1080 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1081 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1082 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1083 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1084 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1085 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1086 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1087 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1088 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1089 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1090 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1091 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1092 }
1093
1094 #ifdef TARGET_X86_64
1095 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1096 16 * sizeof env->xmm_regs[16]);
1097 #endif
1098 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1099 return r;
1100 }
1101
1102 static int kvm_put_xcrs(X86CPU *cpu)
1103 {
1104 CPUX86State *env = &cpu->env;
1105 struct kvm_xcrs xcrs = {};
1106
1107 if (!kvm_has_xcrs()) {
1108 return 0;
1109 }
1110
1111 xcrs.nr_xcrs = 1;
1112 xcrs.flags = 0;
1113 xcrs.xcrs[0].xcr = 0;
1114 xcrs.xcrs[0].value = env->xcr0;
1115 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1116 }
1117
1118 static int kvm_put_sregs(X86CPU *cpu)
1119 {
1120 CPUX86State *env = &cpu->env;
1121 struct kvm_sregs sregs;
1122
1123 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1124 if (env->interrupt_injected >= 0) {
1125 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1126 (uint64_t)1 << (env->interrupt_injected % 64);
1127 }
1128
1129 if ((env->eflags & VM_MASK)) {
1130 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1131 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1132 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1133 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1134 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1135 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1136 } else {
1137 set_seg(&sregs.cs, &env->segs[R_CS]);
1138 set_seg(&sregs.ds, &env->segs[R_DS]);
1139 set_seg(&sregs.es, &env->segs[R_ES]);
1140 set_seg(&sregs.fs, &env->segs[R_FS]);
1141 set_seg(&sregs.gs, &env->segs[R_GS]);
1142 set_seg(&sregs.ss, &env->segs[R_SS]);
1143 }
1144
1145 set_seg(&sregs.tr, &env->tr);
1146 set_seg(&sregs.ldt, &env->ldt);
1147
1148 sregs.idt.limit = env->idt.limit;
1149 sregs.idt.base = env->idt.base;
1150 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1151 sregs.gdt.limit = env->gdt.limit;
1152 sregs.gdt.base = env->gdt.base;
1153 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1154
1155 sregs.cr0 = env->cr[0];
1156 sregs.cr2 = env->cr[2];
1157 sregs.cr3 = env->cr[3];
1158 sregs.cr4 = env->cr[4];
1159
1160 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1161 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1162
1163 sregs.efer = env->efer;
1164
1165 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1166 }
1167
1168 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1169 uint32_t index, uint64_t value)
1170 {
1171 entry->index = index;
1172 entry->reserved = 0;
1173 entry->data = value;
1174 }
1175
1176 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1177 {
1178 CPUX86State *env = &cpu->env;
1179 struct {
1180 struct kvm_msrs info;
1181 struct kvm_msr_entry entries[1];
1182 } msr_data;
1183 struct kvm_msr_entry *msrs = msr_data.entries;
1184
1185 if (!has_msr_tsc_deadline) {
1186 return 0;
1187 }
1188
1189 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1190
1191 msr_data.info = (struct kvm_msrs) {
1192 .nmsrs = 1,
1193 };
1194
1195 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1196 }
1197
1198 /*
1199 * Provide a separate write service for the feature control MSR in order to
1200 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1201 * before writing any other state because forcibly leaving nested mode
1202 * invalidates the VCPU state.
1203 */
1204 static int kvm_put_msr_feature_control(X86CPU *cpu)
1205 {
1206 struct {
1207 struct kvm_msrs info;
1208 struct kvm_msr_entry entry;
1209 } msr_data;
1210
1211 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1212 cpu->env.msr_ia32_feature_control);
1213
1214 msr_data.info = (struct kvm_msrs) {
1215 .nmsrs = 1,
1216 };
1217
1218 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1219 }
1220
1221 static int kvm_put_msrs(X86CPU *cpu, int level)
1222 {
1223 CPUX86State *env = &cpu->env;
1224 struct {
1225 struct kvm_msrs info;
1226 struct kvm_msr_entry entries[150];
1227 } msr_data;
1228 struct kvm_msr_entry *msrs = msr_data.entries;
1229 int n = 0, i;
1230
1231 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1232 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1233 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1234 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1235 if (has_msr_star) {
1236 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1237 }
1238 if (has_msr_hsave_pa) {
1239 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1240 }
1241 if (has_msr_tsc_adjust) {
1242 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1243 }
1244 if (has_msr_misc_enable) {
1245 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1246 env->msr_ia32_misc_enable);
1247 }
1248 if (has_msr_bndcfgs) {
1249 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1250 }
1251 if (has_msr_xss) {
1252 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1253 }
1254 #ifdef TARGET_X86_64
1255 if (lm_capable_kernel) {
1256 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1257 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1258 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1259 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1260 }
1261 #endif
1262 /*
1263 * The following MSRs have side effects on the guest or are too heavy
1264 * for normal writeback. Limit them to reset or full state updates.
1265 */
1266 if (level >= KVM_PUT_RESET_STATE) {
1267 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1268 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1269 env->system_time_msr);
1270 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1271 if (has_msr_async_pf_en) {
1272 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1273 env->async_pf_en_msr);
1274 }
1275 if (has_msr_pv_eoi_en) {
1276 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1277 env->pv_eoi_en_msr);
1278 }
1279 if (has_msr_kvm_steal_time) {
1280 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1281 env->steal_time_msr);
1282 }
1283 if (has_msr_architectural_pmu) {
1284 /* Stop the counter. */
1285 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1286 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1287
1288 /* Set the counter values. */
1289 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1290 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1291 env->msr_fixed_counters[i]);
1292 }
1293 for (i = 0; i < num_architectural_pmu_counters; i++) {
1294 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1295 env->msr_gp_counters[i]);
1296 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1297 env->msr_gp_evtsel[i]);
1298 }
1299 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1300 env->msr_global_status);
1301 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1302 env->msr_global_ovf_ctrl);
1303
1304 /* Now start the PMU. */
1305 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1306 env->msr_fixed_ctr_ctrl);
1307 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1308 env->msr_global_ctrl);
1309 }
1310 if (has_msr_hv_hypercall) {
1311 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1312 env->msr_hv_guest_os_id);
1313 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1314 env->msr_hv_hypercall);
1315 }
1316 if (has_msr_hv_vapic) {
1317 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1318 env->msr_hv_vapic);
1319 }
1320 if (has_msr_hv_tsc) {
1321 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1322 env->msr_hv_tsc);
1323 }
1324 if (has_msr_mtrr) {
1325 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1326 kvm_msr_entry_set(&msrs[n++],
1327 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1328 kvm_msr_entry_set(&msrs[n++],
1329 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1330 kvm_msr_entry_set(&msrs[n++],
1331 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1332 kvm_msr_entry_set(&msrs[n++],
1333 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1334 kvm_msr_entry_set(&msrs[n++],
1335 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1336 kvm_msr_entry_set(&msrs[n++],
1337 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1338 kvm_msr_entry_set(&msrs[n++],
1339 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1340 kvm_msr_entry_set(&msrs[n++],
1341 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1342 kvm_msr_entry_set(&msrs[n++],
1343 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1344 kvm_msr_entry_set(&msrs[n++],
1345 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1346 kvm_msr_entry_set(&msrs[n++],
1347 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1348 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1349 kvm_msr_entry_set(&msrs[n++],
1350 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1351 kvm_msr_entry_set(&msrs[n++],
1352 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1353 }
1354 }
1355
1356 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1357 * kvm_put_msr_feature_control. */
1358 }
1359 if (env->mcg_cap) {
1360 int i;
1361
1362 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1363 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1364 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1365 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1366 }
1367 }
1368
1369 msr_data.info = (struct kvm_msrs) {
1370 .nmsrs = n,
1371 };
1372
1373 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1374
1375 }
1376
1377
1378 static int kvm_get_fpu(X86CPU *cpu)
1379 {
1380 CPUX86State *env = &cpu->env;
1381 struct kvm_fpu fpu;
1382 int i, ret;
1383
1384 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1385 if (ret < 0) {
1386 return ret;
1387 }
1388
1389 env->fpstt = (fpu.fsw >> 11) & 7;
1390 env->fpus = fpu.fsw;
1391 env->fpuc = fpu.fcw;
1392 env->fpop = fpu.last_opcode;
1393 env->fpip = fpu.last_ip;
1394 env->fpdp = fpu.last_dp;
1395 for (i = 0; i < 8; ++i) {
1396 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1397 }
1398 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1399 for (i = 0; i < CPU_NB_REGS; i++) {
1400 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1401 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1402 }
1403 env->mxcsr = fpu.mxcsr;
1404
1405 return 0;
1406 }
1407
1408 static int kvm_get_xsave(X86CPU *cpu)
1409 {
1410 CPUX86State *env = &cpu->env;
1411 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1412 int ret, i;
1413 const uint8_t *xmm, *ymmh, *zmmh;
1414 uint16_t cwd, swd, twd;
1415
1416 if (!kvm_has_xsave()) {
1417 return kvm_get_fpu(cpu);
1418 }
1419
1420 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1421 if (ret < 0) {
1422 return ret;
1423 }
1424
1425 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1426 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1427 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1428 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1429 env->fpstt = (swd >> 11) & 7;
1430 env->fpus = swd;
1431 env->fpuc = cwd;
1432 for (i = 0; i < 8; ++i) {
1433 env->fptags[i] = !((twd >> i) & 1);
1434 }
1435 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1436 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1437 env->mxcsr = xsave->region[XSAVE_MXCSR];
1438 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1439 sizeof env->fpregs);
1440 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1441 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1442 sizeof env->bnd_regs);
1443 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1444 sizeof(env->bndcs_regs));
1445 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1446 sizeof env->opmask_regs);
1447
1448 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1449 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1450 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1451 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1452 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1453 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1454 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1455 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1456 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1457 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1458 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1459 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1460 }
1461
1462 #ifdef TARGET_X86_64
1463 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1464 16 * sizeof env->xmm_regs[16]);
1465 #endif
1466 return 0;
1467 }
1468
1469 static int kvm_get_xcrs(X86CPU *cpu)
1470 {
1471 CPUX86State *env = &cpu->env;
1472 int i, ret;
1473 struct kvm_xcrs xcrs;
1474
1475 if (!kvm_has_xcrs()) {
1476 return 0;
1477 }
1478
1479 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1480 if (ret < 0) {
1481 return ret;
1482 }
1483
1484 for (i = 0; i < xcrs.nr_xcrs; i++) {
1485 /* Only support xcr0 now */
1486 if (xcrs.xcrs[i].xcr == 0) {
1487 env->xcr0 = xcrs.xcrs[i].value;
1488 break;
1489 }
1490 }
1491 return 0;
1492 }
1493
1494 static int kvm_get_sregs(X86CPU *cpu)
1495 {
1496 CPUX86State *env = &cpu->env;
1497 struct kvm_sregs sregs;
1498 uint32_t hflags;
1499 int bit, i, ret;
1500
1501 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1502 if (ret < 0) {
1503 return ret;
1504 }
1505
1506 /* There can only be one pending IRQ set in the bitmap at a time, so try
1507 to find it and save its number instead (-1 for none). */
1508 env->interrupt_injected = -1;
1509 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1510 if (sregs.interrupt_bitmap[i]) {
1511 bit = ctz64(sregs.interrupt_bitmap[i]);
1512 env->interrupt_injected = i * 64 + bit;
1513 break;
1514 }
1515 }
1516
1517 get_seg(&env->segs[R_CS], &sregs.cs);
1518 get_seg(&env->segs[R_DS], &sregs.ds);
1519 get_seg(&env->segs[R_ES], &sregs.es);
1520 get_seg(&env->segs[R_FS], &sregs.fs);
1521 get_seg(&env->segs[R_GS], &sregs.gs);
1522 get_seg(&env->segs[R_SS], &sregs.ss);
1523
1524 get_seg(&env->tr, &sregs.tr);
1525 get_seg(&env->ldt, &sregs.ldt);
1526
1527 env->idt.limit = sregs.idt.limit;
1528 env->idt.base = sregs.idt.base;
1529 env->gdt.limit = sregs.gdt.limit;
1530 env->gdt.base = sregs.gdt.base;
1531
1532 env->cr[0] = sregs.cr0;
1533 env->cr[2] = sregs.cr2;
1534 env->cr[3] = sregs.cr3;
1535 env->cr[4] = sregs.cr4;
1536
1537 env->efer = sregs.efer;
1538
1539 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1540
1541 #define HFLAG_COPY_MASK \
1542 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1543 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1544 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1545 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1546
1547 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1548 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1549 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1550 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1551 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1552 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1553 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1554
1555 if (env->efer & MSR_EFER_LMA) {
1556 hflags |= HF_LMA_MASK;
1557 }
1558
1559 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1560 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1561 } else {
1562 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1563 (DESC_B_SHIFT - HF_CS32_SHIFT);
1564 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1565 (DESC_B_SHIFT - HF_SS32_SHIFT);
1566 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1567 !(hflags & HF_CS32_MASK)) {
1568 hflags |= HF_ADDSEG_MASK;
1569 } else {
1570 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1571 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1572 }
1573 }
1574 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1575
1576 return 0;
1577 }
1578
1579 static int kvm_get_msrs(X86CPU *cpu)
1580 {
1581 CPUX86State *env = &cpu->env;
1582 struct {
1583 struct kvm_msrs info;
1584 struct kvm_msr_entry entries[150];
1585 } msr_data;
1586 struct kvm_msr_entry *msrs = msr_data.entries;
1587 int ret, i, n;
1588
1589 n = 0;
1590 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1591 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1592 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1593 msrs[n++].index = MSR_PAT;
1594 if (has_msr_star) {
1595 msrs[n++].index = MSR_STAR;
1596 }
1597 if (has_msr_hsave_pa) {
1598 msrs[n++].index = MSR_VM_HSAVE_PA;
1599 }
1600 if (has_msr_tsc_adjust) {
1601 msrs[n++].index = MSR_TSC_ADJUST;
1602 }
1603 if (has_msr_tsc_deadline) {
1604 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1605 }
1606 if (has_msr_misc_enable) {
1607 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1608 }
1609 if (has_msr_feature_control) {
1610 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1611 }
1612 if (has_msr_bndcfgs) {
1613 msrs[n++].index = MSR_IA32_BNDCFGS;
1614 }
1615 if (has_msr_xss) {
1616 msrs[n++].index = MSR_IA32_XSS;
1617 }
1618
1619
1620 if (!env->tsc_valid) {
1621 msrs[n++].index = MSR_IA32_TSC;
1622 env->tsc_valid = !runstate_is_running();
1623 }
1624
1625 #ifdef TARGET_X86_64
1626 if (lm_capable_kernel) {
1627 msrs[n++].index = MSR_CSTAR;
1628 msrs[n++].index = MSR_KERNELGSBASE;
1629 msrs[n++].index = MSR_FMASK;
1630 msrs[n++].index = MSR_LSTAR;
1631 }
1632 #endif
1633 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1634 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1635 if (has_msr_async_pf_en) {
1636 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1637 }
1638 if (has_msr_pv_eoi_en) {
1639 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1640 }
1641 if (has_msr_kvm_steal_time) {
1642 msrs[n++].index = MSR_KVM_STEAL_TIME;
1643 }
1644 if (has_msr_architectural_pmu) {
1645 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1646 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1647 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1648 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1649 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1650 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1651 }
1652 for (i = 0; i < num_architectural_pmu_counters; i++) {
1653 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1654 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1655 }
1656 }
1657
1658 if (env->mcg_cap) {
1659 msrs[n++].index = MSR_MCG_STATUS;
1660 msrs[n++].index = MSR_MCG_CTL;
1661 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1662 msrs[n++].index = MSR_MC0_CTL + i;
1663 }
1664 }
1665
1666 if (has_msr_hv_hypercall) {
1667 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1668 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1669 }
1670 if (has_msr_hv_vapic) {
1671 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1672 }
1673 if (has_msr_hv_tsc) {
1674 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1675 }
1676 if (has_msr_mtrr) {
1677 msrs[n++].index = MSR_MTRRdefType;
1678 msrs[n++].index = MSR_MTRRfix64K_00000;
1679 msrs[n++].index = MSR_MTRRfix16K_80000;
1680 msrs[n++].index = MSR_MTRRfix16K_A0000;
1681 msrs[n++].index = MSR_MTRRfix4K_C0000;
1682 msrs[n++].index = MSR_MTRRfix4K_C8000;
1683 msrs[n++].index = MSR_MTRRfix4K_D0000;
1684 msrs[n++].index = MSR_MTRRfix4K_D8000;
1685 msrs[n++].index = MSR_MTRRfix4K_E0000;
1686 msrs[n++].index = MSR_MTRRfix4K_E8000;
1687 msrs[n++].index = MSR_MTRRfix4K_F0000;
1688 msrs[n++].index = MSR_MTRRfix4K_F8000;
1689 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1690 msrs[n++].index = MSR_MTRRphysBase(i);
1691 msrs[n++].index = MSR_MTRRphysMask(i);
1692 }
1693 }
1694
1695 msr_data.info = (struct kvm_msrs) {
1696 .nmsrs = n,
1697 };
1698
1699 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1700 if (ret < 0) {
1701 return ret;
1702 }
1703
1704 for (i = 0; i < ret; i++) {
1705 uint32_t index = msrs[i].index;
1706 switch (index) {
1707 case MSR_IA32_SYSENTER_CS:
1708 env->sysenter_cs = msrs[i].data;
1709 break;
1710 case MSR_IA32_SYSENTER_ESP:
1711 env->sysenter_esp = msrs[i].data;
1712 break;
1713 case MSR_IA32_SYSENTER_EIP:
1714 env->sysenter_eip = msrs[i].data;
1715 break;
1716 case MSR_PAT:
1717 env->pat = msrs[i].data;
1718 break;
1719 case MSR_STAR:
1720 env->star = msrs[i].data;
1721 break;
1722 #ifdef TARGET_X86_64
1723 case MSR_CSTAR:
1724 env->cstar = msrs[i].data;
1725 break;
1726 case MSR_KERNELGSBASE:
1727 env->kernelgsbase = msrs[i].data;
1728 break;
1729 case MSR_FMASK:
1730 env->fmask = msrs[i].data;
1731 break;
1732 case MSR_LSTAR:
1733 env->lstar = msrs[i].data;
1734 break;
1735 #endif
1736 case MSR_IA32_TSC:
1737 env->tsc = msrs[i].data;
1738 break;
1739 case MSR_TSC_ADJUST:
1740 env->tsc_adjust = msrs[i].data;
1741 break;
1742 case MSR_IA32_TSCDEADLINE:
1743 env->tsc_deadline = msrs[i].data;
1744 break;
1745 case MSR_VM_HSAVE_PA:
1746 env->vm_hsave = msrs[i].data;
1747 break;
1748 case MSR_KVM_SYSTEM_TIME:
1749 env->system_time_msr = msrs[i].data;
1750 break;
1751 case MSR_KVM_WALL_CLOCK:
1752 env->wall_clock_msr = msrs[i].data;
1753 break;
1754 case MSR_MCG_STATUS:
1755 env->mcg_status = msrs[i].data;
1756 break;
1757 case MSR_MCG_CTL:
1758 env->mcg_ctl = msrs[i].data;
1759 break;
1760 case MSR_IA32_MISC_ENABLE:
1761 env->msr_ia32_misc_enable = msrs[i].data;
1762 break;
1763 case MSR_IA32_FEATURE_CONTROL:
1764 env->msr_ia32_feature_control = msrs[i].data;
1765 break;
1766 case MSR_IA32_BNDCFGS:
1767 env->msr_bndcfgs = msrs[i].data;
1768 break;
1769 case MSR_IA32_XSS:
1770 env->xss = msrs[i].data;
1771 break;
1772 default:
1773 if (msrs[i].index >= MSR_MC0_CTL &&
1774 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1775 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1776 }
1777 break;
1778 case MSR_KVM_ASYNC_PF_EN:
1779 env->async_pf_en_msr = msrs[i].data;
1780 break;
1781 case MSR_KVM_PV_EOI_EN:
1782 env->pv_eoi_en_msr = msrs[i].data;
1783 break;
1784 case MSR_KVM_STEAL_TIME:
1785 env->steal_time_msr = msrs[i].data;
1786 break;
1787 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1788 env->msr_fixed_ctr_ctrl = msrs[i].data;
1789 break;
1790 case MSR_CORE_PERF_GLOBAL_CTRL:
1791 env->msr_global_ctrl = msrs[i].data;
1792 break;
1793 case MSR_CORE_PERF_GLOBAL_STATUS:
1794 env->msr_global_status = msrs[i].data;
1795 break;
1796 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1797 env->msr_global_ovf_ctrl = msrs[i].data;
1798 break;
1799 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1800 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1801 break;
1802 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1803 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1804 break;
1805 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1806 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1807 break;
1808 case HV_X64_MSR_HYPERCALL:
1809 env->msr_hv_hypercall = msrs[i].data;
1810 break;
1811 case HV_X64_MSR_GUEST_OS_ID:
1812 env->msr_hv_guest_os_id = msrs[i].data;
1813 break;
1814 case HV_X64_MSR_APIC_ASSIST_PAGE:
1815 env->msr_hv_vapic = msrs[i].data;
1816 break;
1817 case HV_X64_MSR_REFERENCE_TSC:
1818 env->msr_hv_tsc = msrs[i].data;
1819 break;
1820 case MSR_MTRRdefType:
1821 env->mtrr_deftype = msrs[i].data;
1822 break;
1823 case MSR_MTRRfix64K_00000:
1824 env->mtrr_fixed[0] = msrs[i].data;
1825 break;
1826 case MSR_MTRRfix16K_80000:
1827 env->mtrr_fixed[1] = msrs[i].data;
1828 break;
1829 case MSR_MTRRfix16K_A0000:
1830 env->mtrr_fixed[2] = msrs[i].data;
1831 break;
1832 case MSR_MTRRfix4K_C0000:
1833 env->mtrr_fixed[3] = msrs[i].data;
1834 break;
1835 case MSR_MTRRfix4K_C8000:
1836 env->mtrr_fixed[4] = msrs[i].data;
1837 break;
1838 case MSR_MTRRfix4K_D0000:
1839 env->mtrr_fixed[5] = msrs[i].data;
1840 break;
1841 case MSR_MTRRfix4K_D8000:
1842 env->mtrr_fixed[6] = msrs[i].data;
1843 break;
1844 case MSR_MTRRfix4K_E0000:
1845 env->mtrr_fixed[7] = msrs[i].data;
1846 break;
1847 case MSR_MTRRfix4K_E8000:
1848 env->mtrr_fixed[8] = msrs[i].data;
1849 break;
1850 case MSR_MTRRfix4K_F0000:
1851 env->mtrr_fixed[9] = msrs[i].data;
1852 break;
1853 case MSR_MTRRfix4K_F8000:
1854 env->mtrr_fixed[10] = msrs[i].data;
1855 break;
1856 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1857 if (index & 1) {
1858 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1859 } else {
1860 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1861 }
1862 break;
1863 }
1864 }
1865
1866 return 0;
1867 }
1868
1869 static int kvm_put_mp_state(X86CPU *cpu)
1870 {
1871 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1872
1873 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1874 }
1875
1876 static int kvm_get_mp_state(X86CPU *cpu)
1877 {
1878 CPUState *cs = CPU(cpu);
1879 CPUX86State *env = &cpu->env;
1880 struct kvm_mp_state mp_state;
1881 int ret;
1882
1883 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1884 if (ret < 0) {
1885 return ret;
1886 }
1887 env->mp_state = mp_state.mp_state;
1888 if (kvm_irqchip_in_kernel()) {
1889 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1890 }
1891 return 0;
1892 }
1893
1894 static int kvm_get_apic(X86CPU *cpu)
1895 {
1896 DeviceState *apic = cpu->apic_state;
1897 struct kvm_lapic_state kapic;
1898 int ret;
1899
1900 if (apic && kvm_irqchip_in_kernel()) {
1901 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1902 if (ret < 0) {
1903 return ret;
1904 }
1905
1906 kvm_get_apic_state(apic, &kapic);
1907 }
1908 return 0;
1909 }
1910
1911 static int kvm_put_apic(X86CPU *cpu)
1912 {
1913 DeviceState *apic = cpu->apic_state;
1914 struct kvm_lapic_state kapic;
1915
1916 if (apic && kvm_irqchip_in_kernel()) {
1917 kvm_put_apic_state(apic, &kapic);
1918
1919 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1920 }
1921 return 0;
1922 }
1923
1924 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1925 {
1926 CPUX86State *env = &cpu->env;
1927 struct kvm_vcpu_events events = {};
1928
1929 if (!kvm_has_vcpu_events()) {
1930 return 0;
1931 }
1932
1933 events.exception.injected = (env->exception_injected >= 0);
1934 events.exception.nr = env->exception_injected;
1935 events.exception.has_error_code = env->has_error_code;
1936 events.exception.error_code = env->error_code;
1937 events.exception.pad = 0;
1938
1939 events.interrupt.injected = (env->interrupt_injected >= 0);
1940 events.interrupt.nr = env->interrupt_injected;
1941 events.interrupt.soft = env->soft_interrupt;
1942
1943 events.nmi.injected = env->nmi_injected;
1944 events.nmi.pending = env->nmi_pending;
1945 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1946 events.nmi.pad = 0;
1947
1948 events.sipi_vector = env->sipi_vector;
1949
1950 events.flags = 0;
1951 if (level >= KVM_PUT_RESET_STATE) {
1952 events.flags |=
1953 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1954 }
1955
1956 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1957 }
1958
1959 static int kvm_get_vcpu_events(X86CPU *cpu)
1960 {
1961 CPUX86State *env = &cpu->env;
1962 struct kvm_vcpu_events events;
1963 int ret;
1964
1965 if (!kvm_has_vcpu_events()) {
1966 return 0;
1967 }
1968
1969 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1970 if (ret < 0) {
1971 return ret;
1972 }
1973 env->exception_injected =
1974 events.exception.injected ? events.exception.nr : -1;
1975 env->has_error_code = events.exception.has_error_code;
1976 env->error_code = events.exception.error_code;
1977
1978 env->interrupt_injected =
1979 events.interrupt.injected ? events.interrupt.nr : -1;
1980 env->soft_interrupt = events.interrupt.soft;
1981
1982 env->nmi_injected = events.nmi.injected;
1983 env->nmi_pending = events.nmi.pending;
1984 if (events.nmi.masked) {
1985 env->hflags2 |= HF2_NMI_MASK;
1986 } else {
1987 env->hflags2 &= ~HF2_NMI_MASK;
1988 }
1989
1990 env->sipi_vector = events.sipi_vector;
1991
1992 return 0;
1993 }
1994
1995 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1996 {
1997 CPUState *cs = CPU(cpu);
1998 CPUX86State *env = &cpu->env;
1999 int ret = 0;
2000 unsigned long reinject_trap = 0;
2001
2002 if (!kvm_has_vcpu_events()) {
2003 if (env->exception_injected == 1) {
2004 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2005 } else if (env->exception_injected == 3) {
2006 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2007 }
2008 env->exception_injected = -1;
2009 }
2010
2011 /*
2012 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2013 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2014 * by updating the debug state once again if single-stepping is on.
2015 * Another reason to call kvm_update_guest_debug here is a pending debug
2016 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2017 * reinject them via SET_GUEST_DEBUG.
2018 */
2019 if (reinject_trap ||
2020 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2021 ret = kvm_update_guest_debug(cs, reinject_trap);
2022 }
2023 return ret;
2024 }
2025
2026 static int kvm_put_debugregs(X86CPU *cpu)
2027 {
2028 CPUX86State *env = &cpu->env;
2029 struct kvm_debugregs dbgregs;
2030 int i;
2031
2032 if (!kvm_has_debugregs()) {
2033 return 0;
2034 }
2035
2036 for (i = 0; i < 4; i++) {
2037 dbgregs.db[i] = env->dr[i];
2038 }
2039 dbgregs.dr6 = env->dr[6];
2040 dbgregs.dr7 = env->dr[7];
2041 dbgregs.flags = 0;
2042
2043 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2044 }
2045
2046 static int kvm_get_debugregs(X86CPU *cpu)
2047 {
2048 CPUX86State *env = &cpu->env;
2049 struct kvm_debugregs dbgregs;
2050 int i, ret;
2051
2052 if (!kvm_has_debugregs()) {
2053 return 0;
2054 }
2055
2056 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2057 if (ret < 0) {
2058 return ret;
2059 }
2060 for (i = 0; i < 4; i++) {
2061 env->dr[i] = dbgregs.db[i];
2062 }
2063 env->dr[4] = env->dr[6] = dbgregs.dr6;
2064 env->dr[5] = env->dr[7] = dbgregs.dr7;
2065
2066 return 0;
2067 }
2068
2069 int kvm_arch_put_registers(CPUState *cpu, int level)
2070 {
2071 X86CPU *x86_cpu = X86_CPU(cpu);
2072 int ret;
2073
2074 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2075
2076 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2077 ret = kvm_put_msr_feature_control(x86_cpu);
2078 if (ret < 0) {
2079 return ret;
2080 }
2081 }
2082
2083 ret = kvm_getput_regs(x86_cpu, 1);
2084 if (ret < 0) {
2085 return ret;
2086 }
2087 ret = kvm_put_xsave(x86_cpu);
2088 if (ret < 0) {
2089 return ret;
2090 }
2091 ret = kvm_put_xcrs(x86_cpu);
2092 if (ret < 0) {
2093 return ret;
2094 }
2095 ret = kvm_put_sregs(x86_cpu);
2096 if (ret < 0) {
2097 return ret;
2098 }
2099 /* must be before kvm_put_msrs */
2100 ret = kvm_inject_mce_oldstyle(x86_cpu);
2101 if (ret < 0) {
2102 return ret;
2103 }
2104 ret = kvm_put_msrs(x86_cpu, level);
2105 if (ret < 0) {
2106 return ret;
2107 }
2108 if (level >= KVM_PUT_RESET_STATE) {
2109 ret = kvm_put_mp_state(x86_cpu);
2110 if (ret < 0) {
2111 return ret;
2112 }
2113 ret = kvm_put_apic(x86_cpu);
2114 if (ret < 0) {
2115 return ret;
2116 }
2117 }
2118
2119 ret = kvm_put_tscdeadline_msr(x86_cpu);
2120 if (ret < 0) {
2121 return ret;
2122 }
2123
2124 ret = kvm_put_vcpu_events(x86_cpu, level);
2125 if (ret < 0) {
2126 return ret;
2127 }
2128 ret = kvm_put_debugregs(x86_cpu);
2129 if (ret < 0) {
2130 return ret;
2131 }
2132 /* must be last */
2133 ret = kvm_guest_debug_workarounds(x86_cpu);
2134 if (ret < 0) {
2135 return ret;
2136 }
2137 return 0;
2138 }
2139
2140 int kvm_arch_get_registers(CPUState *cs)
2141 {
2142 X86CPU *cpu = X86_CPU(cs);
2143 int ret;
2144
2145 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2146
2147 ret = kvm_getput_regs(cpu, 0);
2148 if (ret < 0) {
2149 return ret;
2150 }
2151 ret = kvm_get_xsave(cpu);
2152 if (ret < 0) {
2153 return ret;
2154 }
2155 ret = kvm_get_xcrs(cpu);
2156 if (ret < 0) {
2157 return ret;
2158 }
2159 ret = kvm_get_sregs(cpu);
2160 if (ret < 0) {
2161 return ret;
2162 }
2163 ret = kvm_get_msrs(cpu);
2164 if (ret < 0) {
2165 return ret;
2166 }
2167 ret = kvm_get_mp_state(cpu);
2168 if (ret < 0) {
2169 return ret;
2170 }
2171 ret = kvm_get_apic(cpu);
2172 if (ret < 0) {
2173 return ret;
2174 }
2175 ret = kvm_get_vcpu_events(cpu);
2176 if (ret < 0) {
2177 return ret;
2178 }
2179 ret = kvm_get_debugregs(cpu);
2180 if (ret < 0) {
2181 return ret;
2182 }
2183 return 0;
2184 }
2185
2186 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2187 {
2188 X86CPU *x86_cpu = X86_CPU(cpu);
2189 CPUX86State *env = &x86_cpu->env;
2190 int ret;
2191
2192 /* Inject NMI */
2193 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2194 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2195 DPRINTF("injected NMI\n");
2196 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2197 if (ret < 0) {
2198 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2199 strerror(-ret));
2200 }
2201 }
2202
2203 /* Force the VCPU out of its inner loop to process any INIT requests
2204 * or (for userspace APIC, but it is cheap to combine the checks here)
2205 * pending TPR access reports.
2206 */
2207 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2208 cpu->exit_request = 1;
2209 }
2210
2211 if (!kvm_irqchip_in_kernel()) {
2212 /* Try to inject an interrupt if the guest can accept it */
2213 if (run->ready_for_interrupt_injection &&
2214 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2215 (env->eflags & IF_MASK)) {
2216 int irq;
2217
2218 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2219 irq = cpu_get_pic_interrupt(env);
2220 if (irq >= 0) {
2221 struct kvm_interrupt intr;
2222
2223 intr.irq = irq;
2224 DPRINTF("injected interrupt %d\n", irq);
2225 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2226 if (ret < 0) {
2227 fprintf(stderr,
2228 "KVM: injection failed, interrupt lost (%s)\n",
2229 strerror(-ret));
2230 }
2231 }
2232 }
2233
2234 /* If we have an interrupt but the guest is not ready to receive an
2235 * interrupt, request an interrupt window exit. This will
2236 * cause a return to userspace as soon as the guest is ready to
2237 * receive interrupts. */
2238 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2239 run->request_interrupt_window = 1;
2240 } else {
2241 run->request_interrupt_window = 0;
2242 }
2243
2244 DPRINTF("setting tpr\n");
2245 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2246 }
2247 }
2248
2249 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2250 {
2251 X86CPU *x86_cpu = X86_CPU(cpu);
2252 CPUX86State *env = &x86_cpu->env;
2253
2254 if (run->if_flag) {
2255 env->eflags |= IF_MASK;
2256 } else {
2257 env->eflags &= ~IF_MASK;
2258 }
2259 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2260 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2261 }
2262
2263 int kvm_arch_process_async_events(CPUState *cs)
2264 {
2265 X86CPU *cpu = X86_CPU(cs);
2266 CPUX86State *env = &cpu->env;
2267
2268 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2269 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2270 assert(env->mcg_cap);
2271
2272 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2273
2274 kvm_cpu_synchronize_state(cs);
2275
2276 if (env->exception_injected == EXCP08_DBLE) {
2277 /* this means triple fault */
2278 qemu_system_reset_request();
2279 cs->exit_request = 1;
2280 return 0;
2281 }
2282 env->exception_injected = EXCP12_MCHK;
2283 env->has_error_code = 0;
2284
2285 cs->halted = 0;
2286 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2287 env->mp_state = KVM_MP_STATE_RUNNABLE;
2288 }
2289 }
2290
2291 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2292 kvm_cpu_synchronize_state(cs);
2293 do_cpu_init(cpu);
2294 }
2295
2296 if (kvm_irqchip_in_kernel()) {
2297 return 0;
2298 }
2299
2300 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2301 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2302 apic_poll_irq(cpu->apic_state);
2303 }
2304 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2305 (env->eflags & IF_MASK)) ||
2306 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2307 cs->halted = 0;
2308 }
2309 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2310 kvm_cpu_synchronize_state(cs);
2311 do_cpu_sipi(cpu);
2312 }
2313 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2314 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2315 kvm_cpu_synchronize_state(cs);
2316 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2317 env->tpr_access_type);
2318 }
2319
2320 return cs->halted;
2321 }
2322
2323 static int kvm_handle_halt(X86CPU *cpu)
2324 {
2325 CPUState *cs = CPU(cpu);
2326 CPUX86State *env = &cpu->env;
2327
2328 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2329 (env->eflags & IF_MASK)) &&
2330 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2331 cs->halted = 1;
2332 return EXCP_HLT;
2333 }
2334
2335 return 0;
2336 }
2337
2338 static int kvm_handle_tpr_access(X86CPU *cpu)
2339 {
2340 CPUState *cs = CPU(cpu);
2341 struct kvm_run *run = cs->kvm_run;
2342
2343 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2344 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2345 : TPR_ACCESS_READ);
2346 return 1;
2347 }
2348
2349 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2350 {
2351 static const uint8_t int3 = 0xcc;
2352
2353 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2354 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2355 return -EINVAL;
2356 }
2357 return 0;
2358 }
2359
2360 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2361 {
2362 uint8_t int3;
2363
2364 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2365 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2366 return -EINVAL;
2367 }
2368 return 0;
2369 }
2370
2371 static struct {
2372 target_ulong addr;
2373 int len;
2374 int type;
2375 } hw_breakpoint[4];
2376
2377 static int nb_hw_breakpoint;
2378
2379 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2380 {
2381 int n;
2382
2383 for (n = 0; n < nb_hw_breakpoint; n++) {
2384 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2385 (hw_breakpoint[n].len == len || len == -1)) {
2386 return n;
2387 }
2388 }
2389 return -1;
2390 }
2391
2392 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2393 target_ulong len, int type)
2394 {
2395 switch (type) {
2396 case GDB_BREAKPOINT_HW:
2397 len = 1;
2398 break;
2399 case GDB_WATCHPOINT_WRITE:
2400 case GDB_WATCHPOINT_ACCESS:
2401 switch (len) {
2402 case 1:
2403 break;
2404 case 2:
2405 case 4:
2406 case 8:
2407 if (addr & (len - 1)) {
2408 return -EINVAL;
2409 }
2410 break;
2411 default:
2412 return -EINVAL;
2413 }
2414 break;
2415 default:
2416 return -ENOSYS;
2417 }
2418
2419 if (nb_hw_breakpoint == 4) {
2420 return -ENOBUFS;
2421 }
2422 if (find_hw_breakpoint(addr, len, type) >= 0) {
2423 return -EEXIST;
2424 }
2425 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2426 hw_breakpoint[nb_hw_breakpoint].len = len;
2427 hw_breakpoint[nb_hw_breakpoint].type = type;
2428 nb_hw_breakpoint++;
2429
2430 return 0;
2431 }
2432
2433 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2434 target_ulong len, int type)
2435 {
2436 int n;
2437
2438 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2439 if (n < 0) {
2440 return -ENOENT;
2441 }
2442 nb_hw_breakpoint--;
2443 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2444
2445 return 0;
2446 }
2447
2448 void kvm_arch_remove_all_hw_breakpoints(void)
2449 {
2450 nb_hw_breakpoint = 0;
2451 }
2452
2453 static CPUWatchpoint hw_watchpoint;
2454
2455 static int kvm_handle_debug(X86CPU *cpu,
2456 struct kvm_debug_exit_arch *arch_info)
2457 {
2458 CPUState *cs = CPU(cpu);
2459 CPUX86State *env = &cpu->env;
2460 int ret = 0;
2461 int n;
2462
2463 if (arch_info->exception == 1) {
2464 if (arch_info->dr6 & (1 << 14)) {
2465 if (cs->singlestep_enabled) {
2466 ret = EXCP_DEBUG;
2467 }
2468 } else {
2469 for (n = 0; n < 4; n++) {
2470 if (arch_info->dr6 & (1 << n)) {
2471 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2472 case 0x0:
2473 ret = EXCP_DEBUG;
2474 break;
2475 case 0x1:
2476 ret = EXCP_DEBUG;
2477 cs->watchpoint_hit = &hw_watchpoint;
2478 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2479 hw_watchpoint.flags = BP_MEM_WRITE;
2480 break;
2481 case 0x3:
2482 ret = EXCP_DEBUG;
2483 cs->watchpoint_hit = &hw_watchpoint;
2484 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2485 hw_watchpoint.flags = BP_MEM_ACCESS;
2486 break;
2487 }
2488 }
2489 }
2490 }
2491 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2492 ret = EXCP_DEBUG;
2493 }
2494 if (ret == 0) {
2495 cpu_synchronize_state(cs);
2496 assert(env->exception_injected == -1);
2497
2498 /* pass to guest */
2499 env->exception_injected = arch_info->exception;
2500 env->has_error_code = 0;
2501 }
2502
2503 return ret;
2504 }
2505
2506 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2507 {
2508 const uint8_t type_code[] = {
2509 [GDB_BREAKPOINT_HW] = 0x0,
2510 [GDB_WATCHPOINT_WRITE] = 0x1,
2511 [GDB_WATCHPOINT_ACCESS] = 0x3
2512 };
2513 const uint8_t len_code[] = {
2514 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2515 };
2516 int n;
2517
2518 if (kvm_sw_breakpoints_active(cpu)) {
2519 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2520 }
2521 if (nb_hw_breakpoint > 0) {
2522 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2523 dbg->arch.debugreg[7] = 0x0600;
2524 for (n = 0; n < nb_hw_breakpoint; n++) {
2525 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2526 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2527 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2528 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2529 }
2530 }
2531 }
2532
2533 static bool host_supports_vmx(void)
2534 {
2535 uint32_t ecx, unused;
2536
2537 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2538 return ecx & CPUID_EXT_VMX;
2539 }
2540
2541 #define VMX_INVALID_GUEST_STATE 0x80000021
2542
2543 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2544 {
2545 X86CPU *cpu = X86_CPU(cs);
2546 uint64_t code;
2547 int ret;
2548
2549 switch (run->exit_reason) {
2550 case KVM_EXIT_HLT:
2551 DPRINTF("handle_hlt\n");
2552 ret = kvm_handle_halt(cpu);
2553 break;
2554 case KVM_EXIT_SET_TPR:
2555 ret = 0;
2556 break;
2557 case KVM_EXIT_TPR_ACCESS:
2558 ret = kvm_handle_tpr_access(cpu);
2559 break;
2560 case KVM_EXIT_FAIL_ENTRY:
2561 code = run->fail_entry.hardware_entry_failure_reason;
2562 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2563 code);
2564 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2565 fprintf(stderr,
2566 "\nIf you're running a guest on an Intel machine without "
2567 "unrestricted mode\n"
2568 "support, the failure can be most likely due to the guest "
2569 "entering an invalid\n"
2570 "state for Intel VT. For example, the guest maybe running "
2571 "in big real mode\n"
2572 "which is not supported on less recent Intel processors."
2573 "\n\n");
2574 }
2575 ret = -1;
2576 break;
2577 case KVM_EXIT_EXCEPTION:
2578 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2579 run->ex.exception, run->ex.error_code);
2580 ret = -1;
2581 break;
2582 case KVM_EXIT_DEBUG:
2583 DPRINTF("kvm_exit_debug\n");
2584 ret = kvm_handle_debug(cpu, &run->debug.arch);
2585 break;
2586 default:
2587 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2588 ret = -1;
2589 break;
2590 }
2591
2592 return ret;
2593 }
2594
2595 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2596 {
2597 X86CPU *cpu = X86_CPU(cs);
2598 CPUX86State *env = &cpu->env;
2599
2600 kvm_cpu_synchronize_state(cs);
2601 return !(env->cr[0] & CR0_PE_MASK) ||
2602 ((env->segs[R_CS].selector & 3) != 3);
2603 }
2604
2605 void kvm_arch_init_irq_routing(KVMState *s)
2606 {
2607 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2608 /* If kernel can't do irq routing, interrupt source
2609 * override 0->2 cannot be set up as required by HPET.
2610 * So we have to disable it.
2611 */
2612 no_hpet = 1;
2613 }
2614 /* We know at this point that we're using the in-kernel
2615 * irqchip, so we can use irqfds, and on x86 we know
2616 * we can use msi via irqfd and GSI routing.
2617 */
2618 kvm_msi_via_irqfd_allowed = true;
2619 kvm_gsi_routing_allowed = true;
2620 }
2621
2622 /* Classic KVM device assignment interface. Will remain x86 only. */
2623 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2624 uint32_t flags, uint32_t *dev_id)
2625 {
2626 struct kvm_assigned_pci_dev dev_data = {
2627 .segnr = dev_addr->domain,
2628 .busnr = dev_addr->bus,
2629 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2630 .flags = flags,
2631 };
2632 int ret;
2633
2634 dev_data.assigned_dev_id =
2635 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2636
2637 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2638 if (ret < 0) {
2639 return ret;
2640 }
2641
2642 *dev_id = dev_data.assigned_dev_id;
2643
2644 return 0;
2645 }
2646
2647 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2648 {
2649 struct kvm_assigned_pci_dev dev_data = {
2650 .assigned_dev_id = dev_id,
2651 };
2652
2653 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2654 }
2655
2656 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2657 uint32_t irq_type, uint32_t guest_irq)
2658 {
2659 struct kvm_assigned_irq assigned_irq = {
2660 .assigned_dev_id = dev_id,
2661 .guest_irq = guest_irq,
2662 .flags = irq_type,
2663 };
2664
2665 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2666 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2667 } else {
2668 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2669 }
2670 }
2671
2672 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2673 uint32_t guest_irq)
2674 {
2675 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2676 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2677
2678 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2679 }
2680
2681 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2682 {
2683 struct kvm_assigned_pci_dev dev_data = {
2684 .assigned_dev_id = dev_id,
2685 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2686 };
2687
2688 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2689 }
2690
2691 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2692 uint32_t type)
2693 {
2694 struct kvm_assigned_irq assigned_irq = {
2695 .assigned_dev_id = dev_id,
2696 .flags = type,
2697 };
2698
2699 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2700 }
2701
2702 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2703 {
2704 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2705 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2706 }
2707
2708 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2709 {
2710 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2711 KVM_DEV_IRQ_GUEST_MSI, virq);
2712 }
2713
2714 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2715 {
2716 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2717 KVM_DEV_IRQ_HOST_MSI);
2718 }
2719
2720 bool kvm_device_msix_supported(KVMState *s)
2721 {
2722 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2723 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2724 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2725 }
2726
2727 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2728 uint32_t nr_vectors)
2729 {
2730 struct kvm_assigned_msix_nr msix_nr = {
2731 .assigned_dev_id = dev_id,
2732 .entry_nr = nr_vectors,
2733 };
2734
2735 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2736 }
2737
2738 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2739 int virq)
2740 {
2741 struct kvm_assigned_msix_entry msix_entry = {
2742 .assigned_dev_id = dev_id,
2743 .gsi = virq,
2744 .entry = vector,
2745 };
2746
2747 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2748 }
2749
2750 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2751 {
2752 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2753 KVM_DEV_IRQ_GUEST_MSIX, 0);
2754 }
2755
2756 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2757 {
2758 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2759 KVM_DEV_IRQ_HOST_MSIX);
2760 }
2761
2762 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2763 uint64_t address, uint32_t data)
2764 {
2765 return 0;
2766 }
AR7 emulation for QEMU