hw/arm11mpcore.c

   1 /*
   2  * ARM11MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "qemu-timer.h"
  12
  13 #define NCPU 4
  14
  15 static inline int
  16 gic_get_current_cpu(void)
  17 {
  18   return cpu_single_env->cpu_index;
  19 }
  20
  21 #include "arm_gic.c"
  22
  23 /* MPCore private memory region.  */
  24
  25 typedef struct mpcore_priv_state {
  26     gic_state gic;
  27     uint32_t scu_control;
  28     int iomemtype;
  29     uint32_t old_timer_status[8];
  30     uint32_t num_cpu;
  31     qemu_irq *timer_irq;
  32     MemoryRegion iomem;
  33     MemoryRegion container;
  34     DeviceState *mptimer;
  35     uint32_t num_irq;
  36 } mpcore_priv_state;
  37
  38 /* Per-CPU private memory mapped IO.  */
  39
  40 static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
  41                                 unsigned size)
  42 {
  43     mpcore_priv_state *s = (mpcore_priv_state *)opaque;
  44     int id;
  45     /* SCU */
  46     switch (offset) {
  47     case 0x00: /* Control.  */
  48         return s->scu_control;
  49     case 0x04: /* Configuration.  */
  50         id = ((1 << s->num_cpu) - 1) << 4;
  51         return id | (s->num_cpu - 1);
  52     case 0x08: /* CPU status.  */
  53         return 0;
  54     case 0x0c: /* Invalidate all.  */
  55         return 0;
  56     default:
  57         hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
  58     }
  59 }
  60
  61 static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
  62                              uint64_t value, unsigned size)
  63 {
  64     mpcore_priv_state *s = (mpcore_priv_state *)opaque;
  65     /* SCU */
  66     switch (offset) {
  67     case 0: /* Control register.  */
  68         s->scu_control = value & 1;
  69         break;
  70     case 0x0c: /* Invalidate all.  */
  71         /* This is a no-op as cache is not emulated.  */
  72         break;
  73     default:
  74         hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
  75     }
  76 }
  77
  78 static const MemoryRegionOps mpcore_scu_ops = {
  79     .read = mpcore_scu_read,
  80     .write = mpcore_scu_write,
  81     .endianness = DEVICE_NATIVE_ENDIAN,
  82 };
  83
  84 static void mpcore_timer_irq_handler(void *opaque, int irq, int level)
  85 {
  86     mpcore_priv_state *s = (mpcore_priv_state *)opaque;
  87     if (level && !s->old_timer_status[irq]) {
  88         gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
  89     }
  90     s->old_timer_status[irq] = level;
  91 }
  92
  93 static void mpcore_priv_map_setup(mpcore_priv_state *s)
  94 {
  95     int i;
  96     SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
  97     memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
  98     memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
  99     memory_region_add_subregion(&s->container, 0, &s->iomem);
 100     /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
 101      * at 0x200, 0x300...
 102      */
 103     for (i = 0; i < (s->num_cpu + 1); i++) {
 104         target_phys_addr_t offset = 0x100 + (i * 0x100);
 105         memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]);
 106     }
 107     /* Add the regions for timer and watchdog for "current CPU" and
 108      * for each specific CPU.
 109      */
 110     s->timer_irq = qemu_allocate_irqs(mpcore_timer_irq_handler,
 111                                       s, (s->num_cpu + 1) * 2);
 112     for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
 113         /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
 114         target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
 115         memory_region_add_subregion(&s->container, offset,
 116                                     sysbus_mmio_get_region(busdev, i));
 117     }
 118     memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
 119     /* Wire up the interrupt from each watchdog and timer. */
 120     for (i = 0; i < s->num_cpu * 2; i++) {
 121         sysbus_connect_irq(busdev, i, s->timer_irq[i]);
 122     }
 123 }
 124
 125 static int mpcore_priv_init(SysBusDevice *dev)
 126 {
 127     mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
 128
 129     gic_init(&s->gic, s->num_cpu, s->num_irq);
 130     s->mptimer = qdev_create(NULL, "arm_mptimer");
 131     qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
 132     qdev_init_nofail(s->mptimer);
 133     mpcore_priv_map_setup(s);
 134     sysbus_init_mmio(dev, &s->container);
 135     return 0;
 136 }
 137
 138 /* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
 139    controllers.  The output of these, plus some of the raw input lines
 140    are fed into a single SMP-aware interrupt controller on the CPU.  */
 141 typedef struct {
 142     SysBusDevice busdev;
 143     SysBusDevice *priv;
 144     qemu_irq cpuic[32];
 145     qemu_irq rvic[4][64];
 146     uint32_t num_cpu;
 147 } mpcore_rirq_state;
 148
 149 /* Map baseboard IRQs onto CPU IRQ lines.  */
 150 static const int mpcore_irq_map[32] = {
 151     -1, -1, -1, -1,  1,  2, -1, -1,
 152     -1, -1,  6, -1,  4,  5, -1, -1,
 153     -1, 14, 15,  0,  7,  8, -1, -1,
 154     -1, -1, -1, -1,  9,  3, -1, -1,
 155 };
 156
 157 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
 158 {
 159     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
 160     int i;
 161
 162     for (i = 0; i < 4; i++) {
 163         qemu_set_irq(s->rvic[i][irq], level);
 164     }
 165     if (irq < 32) {
 166         irq = mpcore_irq_map[irq];
 167         if (irq >= 0) {
 168             qemu_set_irq(s->cpuic[irq], level);
 169         }
 170     }
 171 }
 172
 173 static int realview_mpcore_init(SysBusDevice *dev)
 174 {
 175     mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
 176     DeviceState *gic;
 177     DeviceState *priv;
 178     int n;
 179     int i;
 180
 181     priv = qdev_create(NULL, "arm11mpcore_priv");
 182     qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
 183     qdev_init_nofail(priv);
 184     s->priv = sysbus_from_qdev(priv);
 185     sysbus_pass_irq(dev, s->priv);
 186     for (i = 0; i < 32; i++) {
 187         s->cpuic[i] = qdev_get_gpio_in(priv, i);
 188     }
 189     /* ??? IRQ routing is hardcoded to "normal" mode.  */
 190     for (n = 0; n < 4; n++) {
 191         gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
 192                                    s->cpuic[10 + n]);
 193         for (i = 0; i < 64; i++) {
 194             s->rvic[n][i] = qdev_get_gpio_in(gic, i);
 195         }
 196     }
 197     qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
 198     sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
 199     return 0;
 200 }
 201
 202 static Property mpcore_rirq_properties[] = {
 203     DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
 204     DEFINE_PROP_END_OF_LIST(),
 205 };
 206
 207 static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
 208 {
 209     DeviceClass *dc = DEVICE_CLASS(klass);
 210     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 211
 212     k->init = realview_mpcore_init;
 213     dc->props = mpcore_rirq_properties;
 214 }
 215
 216 static TypeInfo mpcore_rirq_info = {
 217     .name          = "realview_mpcore",
 218     .parent        = TYPE_SYS_BUS_DEVICE,
 219     .instance_size = sizeof(mpcore_rirq_state),
 220     .class_init    = mpcore_rirq_class_init,
 221 };
 222
 223 static Property mpcore_priv_properties[] = {
 224     DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
 225     /* The ARM11 MPCORE TRM says the on-chip controller may have
 226      * anything from 0 to 224 external interrupt IRQ lines (with another
 227      * 32 internal). We default to 32+32, which is the number provided by
 228      * the ARM11 MPCore test chip in the Realview Versatile Express
 229      * coretile. Other boards may differ and should set this property
 230      * appropriately. Some Linux kernels may not boot if the hardware
 231      * has more IRQ lines than the kernel expects.
 232      */
 233     DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
 234     DEFINE_PROP_END_OF_LIST(),
 235 };
 236
 237 static void mpcore_priv_class_init(ObjectClass *klass, void *data)
 238 {
 239     DeviceClass *dc = DEVICE_CLASS(klass);
 240     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 241
 242     k->init = mpcore_priv_init;
 243     dc->props = mpcore_priv_properties;
 244 }
 245
 246 static TypeInfo mpcore_priv_info = {
 247     .name          = "arm11mpcore_priv",
 248     .parent        = TYPE_SYS_BUS_DEVICE,
 249     .instance_size = sizeof(mpcore_priv_state),
 250     .class_init    = mpcore_priv_class_init,
 251 };
 252
 253 static void arm11mpcore_register_types(void)
 254 {
 255     type_register_static(&mpcore_rirq_info);
 256     type_register_static(&mpcore_priv_info);
 257 }
 258
 259 type_init(arm11mpcore_register_types)