hw/arm/nrf51_soc.c

   1 /*
   2  * Nordic Semiconductor nRF51 SoC
   3  * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
   4  *
   5  * Copyright 2018 Joel Stanley <joel@jms.id.au>
   6  *
   7  * This code is licensed under the GPL version 2 or later.  See
   8  * the COPYING file in the top-level directory.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qapi/error.h"
  13 #include "hw/arm/boot.h"
  14 #include "hw/sysbus.h"
  15 #include "hw/misc/unimp.h"
  16 #include "exec/address-spaces.h"
  17 #include "qemu/log.h"
  18 #include "cpu.h"
  19
  20 #include "hw/arm/nrf51.h"
  21 #include "hw/arm/nrf51_soc.h"
  22
  23 /*
  24  * The size and base is for the NRF51822 part. If other parts
  25  * are supported in the future, add a sub-class of NRF51SoC for
  26  * the specific variants
  27  */
  28 #define NRF51822_FLASH_PAGES    256
  29 #define NRF51822_SRAM_PAGES     16
  30 #define NRF51822_FLASH_SIZE     (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
  31 #define NRF51822_SRAM_SIZE      (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
  32
  33 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
  34
  35 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
  36 {
  37     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  38                   __func__, addr, size);
  39     return 1;
  40 }
  41
  42 static void clock_write(void *opaque, hwaddr addr, uint64_t data,
  43                         unsigned int size)
  44 {
  45     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  46                   __func__, addr, data, size);
  47 }
  48
  49 static const MemoryRegionOps clock_ops = {
  50     .read = clock_read,
  51     .write = clock_write
  52 };
  53
  54
  55 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
  56 {
  57     NRF51State *s = NRF51_SOC(dev_soc);
  58     MemoryRegion *mr;
  59     Error *err = NULL;
  60     uint8_t i = 0;
  61     hwaddr base_addr = 0;
  62
  63     if (!s->board_memory) {
  64         error_setg(errp, "memory property was not set");
  65         return;
  66     }
  67
  68     object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
  69                              &error_abort);
  70     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err)) {
  71         error_propagate(errp, err);
  72         return;
  73     }
  74
  75     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
  76
  77     memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
  78                            &err);
  79     if (err) {
  80         error_propagate(errp, err);
  81         return;
  82     }
  83     memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
  84
  85     /* UART */
  86     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err)) {
  87         error_propagate(errp, err);
  88         return;
  89     }
  90     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
  91     memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
  92     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
  93                        qdev_get_gpio_in(DEVICE(&s->cpu),
  94                        BASE_TO_IRQ(NRF51_UART_BASE)));
  95
  96     /* RNG */
  97     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err)) {
  98         error_propagate(errp, err);
  99         return;
 100     }
 101
 102     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
 103     memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
 104     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
 105                        qdev_get_gpio_in(DEVICE(&s->cpu),
 106                        BASE_TO_IRQ(NRF51_RNG_BASE)));
 107
 108     /* UICR, FICR, NVMC, FLASH */
 109     if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size",
 110                                   s->flash_size, &err)) {
 111         error_propagate(errp, err);
 112         return;
 113     }
 114
 115     if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), &err)) {
 116         error_propagate(errp, err);
 117         return;
 118     }
 119
 120     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
 121     memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
 122     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
 123     memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
 124     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
 125     memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
 126     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
 127     memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
 128
 129     /* GPIO */
 130     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err)) {
 131         error_propagate(errp, err);
 132         return;
 133     }
 134
 135     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
 136     memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
 137
 138     /* Pass all GPIOs to the SOC layer so they are available to the board */
 139     qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
 140
 141     /* TIMER */
 142     for (i = 0; i < NRF51_NUM_TIMERS; i++) {
 143         if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, &err)) {
 144             error_propagate(errp, err);
 145             return;
 146         }
 147         if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err)) {
 148             error_propagate(errp, err);
 149             return;
 150         }
 151
 152         base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
 153
 154         sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
 155         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
 156                            qdev_get_gpio_in(DEVICE(&s->cpu),
 157                                             BASE_TO_IRQ(base_addr)));
 158     }
 159
 160     /* STUB Peripherals */
 161     memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
 162                           "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
 163     memory_region_add_subregion_overlap(&s->container,
 164                                         NRF51_IOMEM_BASE, &s->clock, -1);
 165
 166     create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
 167                                 NRF51_IOMEM_SIZE);
 168     create_unimplemented_device("nrf51_soc.private",
 169                                 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
 170 }
 171
 172 static void nrf51_soc_init(Object *obj)
 173 {
 174     uint8_t i = 0;
 175
 176     NRF51State *s = NRF51_SOC(obj);
 177
 178     memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
 179
 180     object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
 181     qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
 182                          ARM_CPU_TYPE_NAME("cortex-m0"));
 183     qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
 184
 185     object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
 186     object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
 187
 188     object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
 189
 190     object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
 191
 192     object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
 193
 194     for (i = 0; i < NRF51_NUM_TIMERS; i++) {
 195         object_initialize_child(obj, "timer[*]", &s->timer[i],
 196                                 TYPE_NRF51_TIMER);
 197
 198     }
 199 }
 200
 201 static Property nrf51_soc_properties[] = {
 202     DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
 203                      MemoryRegion *),
 204     DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
 205     DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
 206                        NRF51822_FLASH_SIZE),
 207     DEFINE_PROP_END_OF_LIST(),
 208 };
 209
 210 static void nrf51_soc_class_init(ObjectClass *klass, void *data)
 211 {
 212     DeviceClass *dc = DEVICE_CLASS(klass);
 213
 214     dc->realize = nrf51_soc_realize;
 215     device_class_set_props(dc, nrf51_soc_properties);
 216 }
 217
 218 static const TypeInfo nrf51_soc_info = {
 219     .name          = TYPE_NRF51_SOC,
 220     .parent        = TYPE_SYS_BUS_DEVICE,
 221     .instance_size = sizeof(NRF51State),
 222     .instance_init = nrf51_soc_init,
 223     .class_init    = nrf51_soc_class_init,
 224 };
 225
 226 static void nrf51_soc_types(void)
 227 {
 228     type_register_static(&nrf51_soc_info);
 229 }
 230 type_init(nrf51_soc_types)