target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13 #include "exec/semihost.h"
  14
  15 #ifndef CONFIG_USER_ONLY
  16 static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
  17                                  int access_type, ARMMMUIdx mmu_idx,
  18                                  hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  19                                  target_ulong *page_size, uint32_t *fsr);
  20
  21 /* Definitions for the PMCCNTR and PMCR registers */
  22 #define PMCRD   0x8
  23 #define PMCRC   0x4
  24 #define PMCRE   0x1
  25 #endif
  26
  27 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  28 {
  29     int nregs;
  30
  31     /* VFP data registers are always little-endian.  */
  32     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  33     if (reg < nregs) {
  34         stfq_le_p(buf, env->vfp.regs[reg]);
  35         return 8;
  36     }
  37     if (arm_feature(env, ARM_FEATURE_NEON)) {
  38         /* Aliases for Q regs.  */
  39         nregs += 16;
  40         if (reg < nregs) {
  41             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  42             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  43             return 16;
  44         }
  45     }
  46     switch (reg - nregs) {
  47     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  48     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  49     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  50     }
  51     return 0;
  52 }
  53
  54 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  55 {
  56     int nregs;
  57
  58     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  59     if (reg < nregs) {
  60         env->vfp.regs[reg] = ldfq_le_p(buf);
  61         return 8;
  62     }
  63     if (arm_feature(env, ARM_FEATURE_NEON)) {
  64         nregs += 16;
  65         if (reg < nregs) {
  66             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  67             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  68             return 16;
  69         }
  70     }
  71     switch (reg - nregs) {
  72     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  73     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  74     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  75     }
  76     return 0;
  77 }
  78
  79 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  80 {
  81     switch (reg) {
  82     case 0 ... 31:
  83         /* 128 bit FP register */
  84         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  85         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  86         return 16;
  87     case 32:
  88         /* FPSR */
  89         stl_p(buf, vfp_get_fpsr(env));
  90         return 4;
  91     case 33:
  92         /* FPCR */
  93         stl_p(buf, vfp_get_fpcr(env));
  94         return 4;
  95     default:
  96         return 0;
  97     }
  98 }
  99
 100 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 101 {
 102     switch (reg) {
 103     case 0 ... 31:
 104         /* 128 bit FP register */
 105         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 106         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 107         return 16;
 108     case 32:
 109         /* FPSR */
 110         vfp_set_fpsr(env, ldl_p(buf));
 111         return 4;
 112     case 33:
 113         /* FPCR */
 114         vfp_set_fpcr(env, ldl_p(buf));
 115         return 4;
 116     default:
 117         return 0;
 118     }
 119 }
 120
 121 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 122 {
 123     assert(ri->fieldoffset);
 124     if (cpreg_field_is_64bit(ri)) {
 125         return CPREG_FIELD64(env, ri);
 126     } else {
 127         return CPREG_FIELD32(env, ri);
 128     }
 129 }
 130
 131 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 132                       uint64_t value)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         CPREG_FIELD64(env, ri) = value;
 137     } else {
 138         CPREG_FIELD32(env, ri) = value;
 139     }
 140 }
 141
 142 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 143 {
 144     return (char *)env + ri->fieldoffset;
 145 }
 146
 147 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 148 {
 149     /* Raw read of a coprocessor register (as needed for migration, etc). */
 150     if (ri->type & ARM_CP_CONST) {
 151         return ri->resetvalue;
 152     } else if (ri->raw_readfn) {
 153         return ri->raw_readfn(env, ri);
 154     } else if (ri->readfn) {
 155         return ri->readfn(env, ri);
 156     } else {
 157         return raw_read(env, ri);
 158     }
 159 }
 160
 161 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 162                              uint64_t v)
 163 {
 164     /* Raw write of a coprocessor register (as needed for migration, etc).
 165      * Note that constant registers are treated as write-ignored; the
 166      * caller should check for success by whether a readback gives the
 167      * value written.
 168      */
 169     if (ri->type & ARM_CP_CONST) {
 170         return;
 171     } else if (ri->raw_writefn) {
 172         ri->raw_writefn(env, ri, v);
 173     } else if (ri->writefn) {
 174         ri->writefn(env, ri, v);
 175     } else {
 176         raw_write(env, ri, v);
 177     }
 178 }
 179
 180 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 181 {
 182    /* Return true if the regdef would cause an assertion if you called
 183     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 184     * program bug for it not to have the NO_RAW flag).
 185     * NB that returning false here doesn't necessarily mean that calling
 186     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 187     * read/write access functions which are safe for raw use" from "has
 188     * read/write access functions which have side effects but has forgotten
 189     * to provide raw access functions".
 190     * The tests here line up with the conditions in read/write_raw_cp_reg()
 191     * and assertions in raw_read()/raw_write().
 192     */
 193     if ((ri->type & ARM_CP_CONST) ||
 194         ri->fieldoffset ||
 195         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 196         return false;
 197     }
 198     return true;
 199 }
 200
 201 bool write_cpustate_to_list(ARMCPU *cpu)
 202 {
 203     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 204     int i;
 205     bool ok = true;
 206
 207     for (i = 0; i < cpu->cpreg_array_len; i++) {
 208         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 209         const ARMCPRegInfo *ri;
 210
 211         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 212         if (!ri) {
 213             ok = false;
 214             continue;
 215         }
 216         if (ri->type & ARM_CP_NO_RAW) {
 217             continue;
 218         }
 219         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 220     }
 221     return ok;
 222 }
 223
 224 bool write_list_to_cpustate(ARMCPU *cpu)
 225 {
 226     int i;
 227     bool ok = true;
 228
 229     for (i = 0; i < cpu->cpreg_array_len; i++) {
 230         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 231         uint64_t v = cpu->cpreg_values[i];
 232         const ARMCPRegInfo *ri;
 233
 234         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 235         if (!ri) {
 236             ok = false;
 237             continue;
 238         }
 239         if (ri->type & ARM_CP_NO_RAW) {
 240             continue;
 241         }
 242         /* Write value and confirm it reads back as written
 243          * (to catch read-only registers and partially read-only
 244          * registers where the incoming migration value doesn't match)
 245          */
 246         write_raw_cp_reg(&cpu->env, ri, v);
 247         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 248             ok = false;
 249         }
 250     }
 251     return ok;
 252 }
 253
 254 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 255 {
 256     ARMCPU *cpu = opaque;
 257     uint64_t regidx;
 258     const ARMCPRegInfo *ri;
 259
 260     regidx = *(uint32_t *)key;
 261     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 262
 263     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 264         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 265         /* The value array need not be initialized at this point */
 266         cpu->cpreg_array_len++;
 267     }
 268 }
 269
 270 static void count_cpreg(gpointer key, gpointer opaque)
 271 {
 272     ARMCPU *cpu = opaque;
 273     uint64_t regidx;
 274     const ARMCPRegInfo *ri;
 275
 276     regidx = *(uint32_t *)key;
 277     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 278
 279     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 280         cpu->cpreg_array_len++;
 281     }
 282 }
 283
 284 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 285 {
 286     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 287     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 288
 289     if (aidx > bidx) {
 290         return 1;
 291     }
 292     if (aidx < bidx) {
 293         return -1;
 294     }
 295     return 0;
 296 }
 297
 298 void init_cpreg_list(ARMCPU *cpu)
 299 {
 300     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 301      * Note that we require cpreg_tuples[] to be sorted by key ID.
 302      */
 303     GList *keys;
 304     int arraylen;
 305
 306     keys = g_hash_table_get_keys(cpu->cp_regs);
 307     keys = g_list_sort(keys, cpreg_key_compare);
 308
 309     cpu->cpreg_array_len = 0;
 310
 311     g_list_foreach(keys, count_cpreg, cpu);
 312
 313     arraylen = cpu->cpreg_array_len;
 314     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 315     cpu->cpreg_values = g_new(uint64_t, arraylen);
 316     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 317     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 318     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 319     cpu->cpreg_array_len = 0;
 320
 321     g_list_foreach(keys, add_cpreg_to_list, cpu);
 322
 323     assert(cpu->cpreg_array_len == arraylen);
 324
 325     g_list_free(keys);
 326 }
 327
 328 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 329 {
 330     ARMCPU *cpu = arm_env_get_cpu(env);
 331
 332     raw_write(env, ri, value);
 333     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 334 }
 335
 336 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 337 {
 338     ARMCPU *cpu = arm_env_get_cpu(env);
 339
 340     if (raw_read(env, ri) != value) {
 341         /* Unlike real hardware the qemu TLB uses virtual addresses,
 342          * not modified virtual addresses, so this causes a TLB flush.
 343          */
 344         tlb_flush(CPU(cpu), 1);
 345         raw_write(env, ri, value);
 346     }
 347 }
 348
 349 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 350                              uint64_t value)
 351 {
 352     ARMCPU *cpu = arm_env_get_cpu(env);
 353
 354     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 355         && !extended_addresses_enabled(env)) {
 356         /* For VMSA (when not using the LPAE long descriptor page table
 357          * format) this register includes the ASID, so do a TLB flush.
 358          * For PMSA it is purely a process ID and no action is needed.
 359          */
 360         tlb_flush(CPU(cpu), 1);
 361     }
 362     raw_write(env, ri, value);
 363 }
 364
 365 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 366                           uint64_t value)
 367 {
 368     /* Invalidate all (TLBIALL) */
 369     ARMCPU *cpu = arm_env_get_cpu(env);
 370
 371     tlb_flush(CPU(cpu), 1);
 372 }
 373
 374 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 375                           uint64_t value)
 376 {
 377     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 378     ARMCPU *cpu = arm_env_get_cpu(env);
 379
 380     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 381 }
 382
 383 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 384                            uint64_t value)
 385 {
 386     /* Invalidate by ASID (TLBIASID) */
 387     ARMCPU *cpu = arm_env_get_cpu(env);
 388
 389     tlb_flush(CPU(cpu), value == 0);
 390 }
 391
 392 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 393                            uint64_t value)
 394 {
 395     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 396     ARMCPU *cpu = arm_env_get_cpu(env);
 397
 398     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 399 }
 400
 401 /* IS variants of TLB operations must affect all cores */
 402 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 403                              uint64_t value)
 404 {
 405     CPUState *other_cs;
 406
 407     CPU_FOREACH(other_cs) {
 408         tlb_flush(other_cs, 1);
 409     }
 410 }
 411
 412 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 413                              uint64_t value)
 414 {
 415     CPUState *other_cs;
 416
 417     CPU_FOREACH(other_cs) {
 418         tlb_flush(other_cs, value == 0);
 419     }
 420 }
 421
 422 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 423                              uint64_t value)
 424 {
 425     CPUState *other_cs;
 426
 427     CPU_FOREACH(other_cs) {
 428         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 429     }
 430 }
 431
 432 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 433                              uint64_t value)
 434 {
 435     CPUState *other_cs;
 436
 437     CPU_FOREACH(other_cs) {
 438         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 439     }
 440 }
 441
 442 static const ARMCPRegInfo cp_reginfo[] = {
 443     /* Define the secure and non-secure FCSE identifier CP registers
 444      * separately because there is no secure bank in V8 (no _EL3).  This allows
 445      * the secure register to be properly reset and migrated. There is also no
 446      * v8 EL1 version of the register so the non-secure instance stands alone.
 447      */
 448     { .name = "FCSEIDR(NS)",
 449       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 450       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 451       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 452       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 453     { .name = "FCSEIDR(S)",
 454       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 455       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 456       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 457       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 458     /* Define the secure and non-secure context identifier CP registers
 459      * separately because there is no secure bank in V8 (no _EL3).  This allows
 460      * the secure register to be properly reset and migrated.  In the
 461      * non-secure case, the 32-bit register will have reset and migration
 462      * disabled during registration as it is handled by the 64-bit instance.
 463      */
 464     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 465       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 466       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 467       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 468       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 469     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 470       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 471       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 472       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 473       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 474     REGINFO_SENTINEL
 475 };
 476
 477 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 478     /* NB: Some of these registers exist in v8 but with more precise
 479      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 480      */
 481     /* MMU Domain access control / MPU write buffer control */
 482     { .name = "DACR",
 483       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 484       .access = PL1_RW, .resetvalue = 0,
 485       .writefn = dacr_write, .raw_writefn = raw_write,
 486       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 487                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 488     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 489      * For v6 and v5, these mappings are overly broad.
 490      */
 491     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 492       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 493     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 494       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 495     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 496       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 497     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 498       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 499     /* Cache maintenance ops; some of this space may be overridden later. */
 500     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 501       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 502       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 503     REGINFO_SENTINEL
 504 };
 505
 506 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 507     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 508      * over-broad.
 509      */
 510     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 511       .access = PL1_W, .type = ARM_CP_WFI },
 512     REGINFO_SENTINEL
 513 };
 514
 515 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 516     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 517      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 518      */
 519     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 520       .access = PL1_W, .type = ARM_CP_WFI },
 521     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 522      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 523      * OMAPCP will override this space.
 524      */
 525     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 526       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 527       .resetvalue = 0 },
 528     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 529       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 530       .resetvalue = 0 },
 531     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 532     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 533       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 534       .resetvalue = 0 },
 535     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 536      * implementing it as RAZ means the "debug architecture version" bits
 537      * will read as a reserved value, which should cause Linux to not try
 538      * to use the debug hardware.
 539      */
 540     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 541       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 542     /* MMU TLB control. Note that the wildcarding means we cover not just
 543      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 544      */
 545     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 546       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 547       .type = ARM_CP_NO_RAW },
 548     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 549       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 550       .type = ARM_CP_NO_RAW },
 551     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 552       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 553       .type = ARM_CP_NO_RAW },
 554     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 555       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 556       .type = ARM_CP_NO_RAW },
 557     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 558       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 559     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 560       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 561     REGINFO_SENTINEL
 562 };
 563
 564 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 565                         uint64_t value)
 566 {
 567     uint32_t mask = 0;
 568
 569     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 570     if (!arm_feature(env, ARM_FEATURE_V8)) {
 571         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 572          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 573          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 574          */
 575         if (arm_feature(env, ARM_FEATURE_VFP)) {
 576             /* VFP coprocessor: cp10 & cp11 [23:20] */
 577             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 578
 579             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 580                 /* ASEDIS [31] bit is RAO/WI */
 581                 value |= (1 << 31);
 582             }
 583
 584             /* VFPv3 and upwards with NEON implement 32 double precision
 585              * registers (D0-D31).
 586              */
 587             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 588                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 589                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 590                 value |= (1 << 30);
 591             }
 592         }
 593         value &= mask;
 594     }
 595     env->cp15.cpacr_el1 = value;
 596 }
 597
 598 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 599 {
 600     if (arm_feature(env, ARM_FEATURE_V8)) {
 601         /* Check if CPACR accesses are to be trapped to EL2 */
 602         if (arm_current_el(env) == 1 &&
 603             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 604             return CP_ACCESS_TRAP_EL2;
 605         /* Check if CPACR accesses are to be trapped to EL3 */
 606         } else if (arm_current_el(env) < 3 &&
 607                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 608             return CP_ACCESS_TRAP_EL3;
 609         }
 610     }
 611
 612     return CP_ACCESS_OK;
 613 }
 614
 615 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 616 {
 617     /* Check if CPTR accesses are set to trap to EL3 */
 618     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 619         return CP_ACCESS_TRAP_EL3;
 620     }
 621
 622     return CP_ACCESS_OK;
 623 }
 624
 625 static const ARMCPRegInfo v6_cp_reginfo[] = {
 626     /* prefetch by MVA in v6, NOP in v7 */
 627     { .name = "MVA_prefetch",
 628       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 629       .access = PL1_W, .type = ARM_CP_NOP },
 630     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 631       .access = PL0_W, .type = ARM_CP_NOP },
 632     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 633       .access = PL0_W, .type = ARM_CP_NOP },
 634     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 635       .access = PL0_W, .type = ARM_CP_NOP },
 636     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 637       .access = PL1_RW,
 638       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 639                              offsetof(CPUARMState, cp15.ifar_ns) },
 640       .resetvalue = 0, },
 641     /* Watchpoint Fault Address Register : should actually only be present
 642      * for 1136, 1176, 11MPCore.
 643      */
 644     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 645       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 646     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 647       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 648       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 649       .resetvalue = 0, .writefn = cpacr_write },
 650     REGINFO_SENTINEL
 651 };
 652
 653 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 654 {
 655     /* Performance monitor registers user accessibility is controlled
 656      * by PMUSERENR.
 657      */
 658     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 659         return CP_ACCESS_TRAP;
 660     }
 661     return CP_ACCESS_OK;
 662 }
 663
 664 #ifndef CONFIG_USER_ONLY
 665
 666 static inline bool arm_ccnt_enabled(CPUARMState *env)
 667 {
 668     /* This does not support checking PMCCFILTR_EL0 register */
 669
 670     if (!(env->cp15.c9_pmcr & PMCRE)) {
 671         return false;
 672     }
 673
 674     return true;
 675 }
 676
 677 void pmccntr_sync(CPUARMState *env)
 678 {
 679     uint64_t temp_ticks;
 680
 681     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 682                           get_ticks_per_sec(), 1000000);
 683
 684     if (env->cp15.c9_pmcr & PMCRD) {
 685         /* Increment once every 64 processor clock cycles */
 686         temp_ticks /= 64;
 687     }
 688
 689     if (arm_ccnt_enabled(env)) {
 690         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 691     }
 692 }
 693
 694 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 695                        uint64_t value)
 696 {
 697     pmccntr_sync(env);
 698
 699     if (value & PMCRC) {
 700         /* The counter has been reset */
 701         env->cp15.c15_ccnt = 0;
 702     }
 703
 704     /* only the DP, X, D and E bits are writable */
 705     env->cp15.c9_pmcr &= ~0x39;
 706     env->cp15.c9_pmcr |= (value & 0x39);
 707
 708     pmccntr_sync(env);
 709 }
 710
 711 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 712 {
 713     uint64_t total_ticks;
 714
 715     if (!arm_ccnt_enabled(env)) {
 716         /* Counter is disabled, do not change value */
 717         return env->cp15.c15_ccnt;
 718     }
 719
 720     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 721                            get_ticks_per_sec(), 1000000);
 722
 723     if (env->cp15.c9_pmcr & PMCRD) {
 724         /* Increment once every 64 processor clock cycles */
 725         total_ticks /= 64;
 726     }
 727     return total_ticks - env->cp15.c15_ccnt;
 728 }
 729
 730 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 731                         uint64_t value)
 732 {
 733     uint64_t total_ticks;
 734
 735     if (!arm_ccnt_enabled(env)) {
 736         /* Counter is disabled, set the absolute value */
 737         env->cp15.c15_ccnt = value;
 738         return;
 739     }
 740
 741     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 742                            get_ticks_per_sec(), 1000000);
 743
 744     if (env->cp15.c9_pmcr & PMCRD) {
 745         /* Increment once every 64 processor clock cycles */
 746         total_ticks /= 64;
 747     }
 748     env->cp15.c15_ccnt = total_ticks - value;
 749 }
 750
 751 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 752                             uint64_t value)
 753 {
 754     uint64_t cur_val = pmccntr_read(env, NULL);
 755
 756     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 757 }
 758
 759 #else /* CONFIG_USER_ONLY */
 760
 761 void pmccntr_sync(CPUARMState *env)
 762 {
 763 }
 764
 765 #endif
 766
 767 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 768                             uint64_t value)
 769 {
 770     pmccntr_sync(env);
 771     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 772     pmccntr_sync(env);
 773 }
 774
 775 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 776                             uint64_t value)
 777 {
 778     value &= (1 << 31);
 779     env->cp15.c9_pmcnten |= value;
 780 }
 781
 782 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 783                              uint64_t value)
 784 {
 785     value &= (1 << 31);
 786     env->cp15.c9_pmcnten &= ~value;
 787 }
 788
 789 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 790                          uint64_t value)
 791 {
 792     env->cp15.c9_pmovsr &= ~value;
 793 }
 794
 795 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 796                              uint64_t value)
 797 {
 798     env->cp15.c9_pmxevtyper = value & 0xff;
 799 }
 800
 801 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 802                             uint64_t value)
 803 {
 804     env->cp15.c9_pmuserenr = value & 1;
 805 }
 806
 807 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 808                              uint64_t value)
 809 {
 810     /* We have no event counters so only the C bit can be changed */
 811     value &= (1 << 31);
 812     env->cp15.c9_pminten |= value;
 813 }
 814
 815 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 816                              uint64_t value)
 817 {
 818     value &= (1 << 31);
 819     env->cp15.c9_pminten &= ~value;
 820 }
 821
 822 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 823                        uint64_t value)
 824 {
 825     /* Note that even though the AArch64 view of this register has bits
 826      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 827      * architectural requirements for bits which are RES0 only in some
 828      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 829      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 830      */
 831     raw_write(env, ri, value & ~0x1FULL);
 832 }
 833
 834 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 835 {
 836     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 837      * For bits that vary between AArch32/64, code needs to check the
 838      * current execution mode before directly using the feature bit.
 839      */
 840     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 841
 842     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 843         valid_mask &= ~SCR_HCE;
 844
 845         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 846          * supported if EL2 exists. The bit is UNK/SBZP when
 847          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 848          * when EL2 is unavailable.
 849          * On ARMv8, this bit is always available.
 850          */
 851         if (arm_feature(env, ARM_FEATURE_V7) &&
 852             !arm_feature(env, ARM_FEATURE_V8)) {
 853             valid_mask &= ~SCR_SMD;
 854         }
 855     }
 856
 857     /* Clear all-context RES0 bits.  */
 858     value &= valid_mask;
 859     raw_write(env, ri, value);
 860 }
 861
 862 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 863 {
 864     ARMCPU *cpu = arm_env_get_cpu(env);
 865
 866     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 867      * bank
 868      */
 869     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 870                                         ri->secure & ARM_CP_SECSTATE_S);
 871
 872     return cpu->ccsidr[index];
 873 }
 874
 875 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 876                          uint64_t value)
 877 {
 878     raw_write(env, ri, value & 0xf);
 879 }
 880
 881 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 882 {
 883     CPUState *cs = ENV_GET_CPU(env);
 884     uint64_t ret = 0;
 885
 886     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 887         ret |= CPSR_I;
 888     }
 889     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 890         ret |= CPSR_F;
 891     }
 892     /* External aborts are not possible in QEMU so A bit is always clear */
 893     return ret;
 894 }
 895
 896 static const ARMCPRegInfo v7_cp_reginfo[] = {
 897     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 898     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 899       .access = PL1_W, .type = ARM_CP_NOP },
 900     /* Performance monitors are implementation defined in v7,
 901      * but with an ARM recommended set of registers, which we
 902      * follow (although we don't actually implement any counters)
 903      *
 904      * Performance registers fall into three categories:
 905      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 906      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 907      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 908      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 909      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 910      */
 911     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 912       .access = PL0_RW, .type = ARM_CP_ALIAS,
 913       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 914       .writefn = pmcntenset_write,
 915       .accessfn = pmreg_access,
 916       .raw_writefn = raw_write },
 917     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 918       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 919       .access = PL0_RW, .accessfn = pmreg_access,
 920       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 921       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 922     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 923       .access = PL0_RW,
 924       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 925       .accessfn = pmreg_access,
 926       .writefn = pmcntenclr_write,
 927       .type = ARM_CP_ALIAS },
 928     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 929       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 930       .access = PL0_RW, .accessfn = pmreg_access,
 931       .type = ARM_CP_ALIAS,
 932       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 933       .writefn = pmcntenclr_write },
 934     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 935       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 936       .accessfn = pmreg_access,
 937       .writefn = pmovsr_write,
 938       .raw_writefn = raw_write },
 939     /* Unimplemented so WI. */
 940     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 941       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 942     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 943      * We choose to RAZ/WI.
 944      */
 945     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 946       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 947       .accessfn = pmreg_access },
 948 #ifndef CONFIG_USER_ONLY
 949     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 950       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 951       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 952       .accessfn = pmreg_access },
 953     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 954       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 955       .access = PL0_RW, .accessfn = pmreg_access,
 956       .type = ARM_CP_IO,
 957       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 958 #endif
 959     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 960       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 961       .writefn = pmccfiltr_write,
 962       .access = PL0_RW, .accessfn = pmreg_access,
 963       .type = ARM_CP_IO,
 964       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 965       .resetvalue = 0, },
 966     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 967       .access = PL0_RW,
 968       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 969       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 970       .raw_writefn = raw_write },
 971     /* Unimplemented, RAZ/WI. */
 972     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 973       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 974       .accessfn = pmreg_access },
 975     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 976       .access = PL0_R | PL1_RW,
 977       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 978       .resetvalue = 0,
 979       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 980     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 981       .access = PL1_RW,
 982       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 983       .resetvalue = 0,
 984       .writefn = pmintenset_write, .raw_writefn = raw_write },
 985     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 986       .access = PL1_RW, .type = ARM_CP_ALIAS,
 987       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 988       .writefn = pmintenclr_write, },
 989     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 990       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 991       .access = PL1_RW, .writefn = vbar_write,
 992       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
 993                              offsetof(CPUARMState, cp15.vbar_ns) },
 994       .resetvalue = 0 },
 995     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 996       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 997       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
 998     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 999       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1000       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1001       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1002                              offsetof(CPUARMState, cp15.csselr_ns) } },
1003     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1004      * just RAZ for all cores:
1005      */
1006     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1007       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1008       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1009     /* Auxiliary fault status registers: these also are IMPDEF, and we
1010      * choose to RAZ/WI for all cores.
1011      */
1012     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1013       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1014       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1015     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1016       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1017       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1018     /* MAIR can just read-as-written because we don't implement caches
1019      * and so don't need to care about memory attributes.
1020      */
1021     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1022       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1023       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1024       .resetvalue = 0 },
1025     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1026       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1027       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1028       .resetvalue = 0 },
1029     /* For non-long-descriptor page tables these are PRRR and NMRR;
1030      * regardless they still act as reads-as-written for QEMU.
1031      */
1032      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1033       * allows them to assign the correct fieldoffset based on the endianness
1034       * handled in the field definitions.
1035       */
1036     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1037       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1038       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1039                              offsetof(CPUARMState, cp15.mair0_ns) },
1040       .resetfn = arm_cp_reset_ignore },
1041     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1042       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1043       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1044                              offsetof(CPUARMState, cp15.mair1_ns) },
1045       .resetfn = arm_cp_reset_ignore },
1046     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1047       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1048       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1049     /* 32 bit ITLB invalidates */
1050     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1051       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1052     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1053       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1054     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1055       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1056     /* 32 bit DTLB invalidates */
1057     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1058       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1059     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1060       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1061     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1062       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1063     /* 32 bit TLB invalidates */
1064     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1065       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1066     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1067       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1068     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1069       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1070     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1071       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1072     REGINFO_SENTINEL
1073 };
1074
1075 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1076     /* 32 bit TLB invalidates, Inner Shareable */
1077     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1078       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1079     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1080       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1081     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1082       .type = ARM_CP_NO_RAW, .access = PL1_W,
1083       .writefn = tlbiasid_is_write },
1084     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1085       .type = ARM_CP_NO_RAW, .access = PL1_W,
1086       .writefn = tlbimvaa_is_write },
1087     REGINFO_SENTINEL
1088 };
1089
1090 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1091                         uint64_t value)
1092 {
1093     value &= 1;
1094     env->teecr = value;
1095 }
1096
1097 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1098 {
1099     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1100         return CP_ACCESS_TRAP;
1101     }
1102     return CP_ACCESS_OK;
1103 }
1104
1105 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1106     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1107       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1108       .resetvalue = 0,
1109       .writefn = teecr_write },
1110     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1111       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1112       .accessfn = teehbr_access, .resetvalue = 0 },
1113     REGINFO_SENTINEL
1114 };
1115
1116 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1117     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1118       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1119       .access = PL0_RW,
1120       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1121     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1122       .access = PL0_RW,
1123       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1124                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1125       .resetfn = arm_cp_reset_ignore },
1126     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1127       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1128       .access = PL0_R|PL1_W,
1129       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1130       .resetvalue = 0},
1131     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1132       .access = PL0_R|PL1_W,
1133       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1134                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1135       .resetfn = arm_cp_reset_ignore },
1136     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1137       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1138       .access = PL1_RW,
1139       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1140     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1141       .access = PL1_RW,
1142       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1143                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1144       .resetvalue = 0 },
1145     REGINFO_SENTINEL
1146 };
1147
1148 #ifndef CONFIG_USER_ONLY
1149
1150 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1151 {
1152     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1153     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1154         return CP_ACCESS_TRAP;
1155     }
1156     return CP_ACCESS_OK;
1157 }
1158
1159 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1160 {
1161     unsigned int cur_el = arm_current_el(env);
1162     bool secure = arm_is_secure(env);
1163
1164     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1165     if (cur_el == 0 &&
1166         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1167         return CP_ACCESS_TRAP;
1168     }
1169
1170     if (arm_feature(env, ARM_FEATURE_EL2) &&
1171         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1172         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1173         return CP_ACCESS_TRAP_EL2;
1174     }
1175     return CP_ACCESS_OK;
1176 }
1177
1178 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1179 {
1180     unsigned int cur_el = arm_current_el(env);
1181     bool secure = arm_is_secure(env);
1182
1183     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1184      * EL0[PV]TEN is zero.
1185      */
1186     if (cur_el == 0 &&
1187         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1188         return CP_ACCESS_TRAP;
1189     }
1190
1191     if (arm_feature(env, ARM_FEATURE_EL2) &&
1192         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1193         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1194         return CP_ACCESS_TRAP_EL2;
1195     }
1196     return CP_ACCESS_OK;
1197 }
1198
1199 static CPAccessResult gt_pct_access(CPUARMState *env,
1200                                          const ARMCPRegInfo *ri)
1201 {
1202     return gt_counter_access(env, GTIMER_PHYS);
1203 }
1204
1205 static CPAccessResult gt_vct_access(CPUARMState *env,
1206                                          const ARMCPRegInfo *ri)
1207 {
1208     return gt_counter_access(env, GTIMER_VIRT);
1209 }
1210
1211 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1212 {
1213     return gt_timer_access(env, GTIMER_PHYS);
1214 }
1215
1216 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1217 {
1218     return gt_timer_access(env, GTIMER_VIRT);
1219 }
1220
1221 static CPAccessResult gt_stimer_access(CPUARMState *env,
1222                                        const ARMCPRegInfo *ri)
1223 {
1224     /* The AArch64 register view of the secure physical timer is
1225      * always accessible from EL3, and configurably accessible from
1226      * Secure EL1.
1227      */
1228     switch (arm_current_el(env)) {
1229     case 1:
1230         if (!arm_is_secure(env)) {
1231             return CP_ACCESS_TRAP;
1232         }
1233         if (!(env->cp15.scr_el3 & SCR_ST)) {
1234             return CP_ACCESS_TRAP_EL3;
1235         }
1236         return CP_ACCESS_OK;
1237     case 0:
1238     case 2:
1239         return CP_ACCESS_TRAP;
1240     case 3:
1241         return CP_ACCESS_OK;
1242     default:
1243         g_assert_not_reached();
1244     }
1245 }
1246
1247 static uint64_t gt_get_countervalue(CPUARMState *env)
1248 {
1249     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1250 }
1251
1252 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1253 {
1254     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1255
1256     if (gt->ctl & 1) {
1257         /* Timer enabled: calculate and set current ISTATUS, irq, and
1258          * reset timer to when ISTATUS next has to change
1259          */
1260         uint64_t offset = timeridx == GTIMER_VIRT ?
1261                                       cpu->env.cp15.cntvoff_el2 : 0;
1262         uint64_t count = gt_get_countervalue(&cpu->env);
1263         /* Note that this must be unsigned 64 bit arithmetic: */
1264         int istatus = count - offset >= gt->cval;
1265         uint64_t nexttick;
1266
1267         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1268         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1269                      (istatus && !(gt->ctl & 2)));
1270         if (istatus) {
1271             /* Next transition is when count rolls back over to zero */
1272             nexttick = UINT64_MAX;
1273         } else {
1274             /* Next transition is when we hit cval */
1275             nexttick = gt->cval + offset;
1276         }
1277         /* Note that the desired next expiry time might be beyond the
1278          * signed-64-bit range of a QEMUTimer -- in this case we just
1279          * set the timer for as far in the future as possible. When the
1280          * timer expires we will reset the timer for any remaining period.
1281          */
1282         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1283             nexttick = INT64_MAX / GTIMER_SCALE;
1284         }
1285         timer_mod(cpu->gt_timer[timeridx], nexttick);
1286     } else {
1287         /* Timer disabled: ISTATUS and timer output always clear */
1288         gt->ctl &= ~4;
1289         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1290         timer_del(cpu->gt_timer[timeridx]);
1291     }
1292 }
1293
1294 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1295                            int timeridx)
1296 {
1297     ARMCPU *cpu = arm_env_get_cpu(env);
1298
1299     timer_del(cpu->gt_timer[timeridx]);
1300 }
1301
1302 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1303 {
1304     return gt_get_countervalue(env);
1305 }
1306
1307 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1308 {
1309     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1310 }
1311
1312 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1313                           int timeridx,
1314                           uint64_t value)
1315 {
1316     env->cp15.c14_timer[timeridx].cval = value;
1317     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1318 }
1319
1320 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1321                              int timeridx)
1322 {
1323     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1324
1325     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1326                       (gt_get_countervalue(env) - offset));
1327 }
1328
1329 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1330                           int timeridx,
1331                           uint64_t value)
1332 {
1333     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1334
1335     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1336                                          sextract64(value, 0, 32);
1337     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1338 }
1339
1340 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1341                          int timeridx,
1342                          uint64_t value)
1343 {
1344     ARMCPU *cpu = arm_env_get_cpu(env);
1345     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1346
1347     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1348     if ((oldval ^ value) & 1) {
1349         /* Enable toggled */
1350         gt_recalc_timer(cpu, timeridx);
1351     } else if ((oldval ^ value) & 2) {
1352         /* IMASK toggled: don't need to recalculate,
1353          * just set the interrupt line based on ISTATUS
1354          */
1355         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1356                      (oldval & 4) && !(value & 2));
1357     }
1358 }
1359
1360 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1361 {
1362     gt_timer_reset(env, ri, GTIMER_PHYS);
1363 }
1364
1365 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1366                                uint64_t value)
1367 {
1368     gt_cval_write(env, ri, GTIMER_PHYS, value);
1369 }
1370
1371 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1372 {
1373     return gt_tval_read(env, ri, GTIMER_PHYS);
1374 }
1375
1376 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1377                                uint64_t value)
1378 {
1379     gt_tval_write(env, ri, GTIMER_PHYS, value);
1380 }
1381
1382 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1383                               uint64_t value)
1384 {
1385     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1386 }
1387
1388 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1389 {
1390     gt_timer_reset(env, ri, GTIMER_VIRT);
1391 }
1392
1393 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1394                                uint64_t value)
1395 {
1396     gt_cval_write(env, ri, GTIMER_VIRT, value);
1397 }
1398
1399 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1400 {
1401     return gt_tval_read(env, ri, GTIMER_VIRT);
1402 }
1403
1404 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1405                                uint64_t value)
1406 {
1407     gt_tval_write(env, ri, GTIMER_VIRT, value);
1408 }
1409
1410 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1411                               uint64_t value)
1412 {
1413     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1414 }
1415
1416 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1417                               uint64_t value)
1418 {
1419     ARMCPU *cpu = arm_env_get_cpu(env);
1420
1421     raw_write(env, ri, value);
1422     gt_recalc_timer(cpu, GTIMER_VIRT);
1423 }
1424
1425 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1426 {
1427     gt_timer_reset(env, ri, GTIMER_HYP);
1428 }
1429
1430 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1431                               uint64_t value)
1432 {
1433     gt_cval_write(env, ri, GTIMER_HYP, value);
1434 }
1435
1436 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1437 {
1438     return gt_tval_read(env, ri, GTIMER_HYP);
1439 }
1440
1441 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1442                               uint64_t value)
1443 {
1444     gt_tval_write(env, ri, GTIMER_HYP, value);
1445 }
1446
1447 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1448                               uint64_t value)
1449 {
1450     gt_ctl_write(env, ri, GTIMER_HYP, value);
1451 }
1452
1453 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1454 {
1455     gt_timer_reset(env, ri, GTIMER_SEC);
1456 }
1457
1458 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1459                               uint64_t value)
1460 {
1461     gt_cval_write(env, ri, GTIMER_SEC, value);
1462 }
1463
1464 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1465 {
1466     return gt_tval_read(env, ri, GTIMER_SEC);
1467 }
1468
1469 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1470                               uint64_t value)
1471 {
1472     gt_tval_write(env, ri, GTIMER_SEC, value);
1473 }
1474
1475 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1476                               uint64_t value)
1477 {
1478     gt_ctl_write(env, ri, GTIMER_SEC, value);
1479 }
1480
1481 void arm_gt_ptimer_cb(void *opaque)
1482 {
1483     ARMCPU *cpu = opaque;
1484
1485     gt_recalc_timer(cpu, GTIMER_PHYS);
1486 }
1487
1488 void arm_gt_vtimer_cb(void *opaque)
1489 {
1490     ARMCPU *cpu = opaque;
1491
1492     gt_recalc_timer(cpu, GTIMER_VIRT);
1493 }
1494
1495 void arm_gt_htimer_cb(void *opaque)
1496 {
1497     ARMCPU *cpu = opaque;
1498
1499     gt_recalc_timer(cpu, GTIMER_HYP);
1500 }
1501
1502 void arm_gt_stimer_cb(void *opaque)
1503 {
1504     ARMCPU *cpu = opaque;
1505
1506     gt_recalc_timer(cpu, GTIMER_SEC);
1507 }
1508
1509 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1510     /* Note that CNTFRQ is purely reads-as-written for the benefit
1511      * of software; writing it doesn't actually change the timer frequency.
1512      * Our reset value matches the fixed frequency we implement the timer at.
1513      */
1514     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1515       .type = ARM_CP_ALIAS,
1516       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1517       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1518     },
1519     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1520       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1521       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1522       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1523       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1524     },
1525     /* overall control: mostly access permissions */
1526     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1527       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1528       .access = PL1_RW,
1529       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1530       .resetvalue = 0,
1531     },
1532     /* per-timer control */
1533     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1534       .secure = ARM_CP_SECSTATE_NS,
1535       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1536       .accessfn = gt_ptimer_access,
1537       .fieldoffset = offsetoflow32(CPUARMState,
1538                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1539       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1540     },
1541     { .name = "CNTP_CTL(S)",
1542       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1543       .secure = ARM_CP_SECSTATE_S,
1544       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1545       .accessfn = gt_ptimer_access,
1546       .fieldoffset = offsetoflow32(CPUARMState,
1547                                    cp15.c14_timer[GTIMER_SEC].ctl),
1548       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1549     },
1550     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1551       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1552       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1553       .accessfn = gt_ptimer_access,
1554       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1555       .resetvalue = 0,
1556       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1557     },
1558     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1559       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1560       .accessfn = gt_vtimer_access,
1561       .fieldoffset = offsetoflow32(CPUARMState,
1562                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1563       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1564     },
1565     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1566       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1567       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1568       .accessfn = gt_vtimer_access,
1569       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1570       .resetvalue = 0,
1571       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1572     },
1573     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1574     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1575       .secure = ARM_CP_SECSTATE_NS,
1576       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1577       .accessfn = gt_ptimer_access,
1578       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1579     },
1580     { .name = "CNTP_TVAL(S)",
1581       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1582       .secure = ARM_CP_SECSTATE_S,
1583       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1584       .accessfn = gt_ptimer_access,
1585       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1586     },
1587     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1588       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1589       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1590       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1591       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1592     },
1593     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1594       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1595       .accessfn = gt_vtimer_access,
1596       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1597     },
1598     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1599       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1600       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1601       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1602       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1603     },
1604     /* The counter itself */
1605     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1606       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1607       .accessfn = gt_pct_access,
1608       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1609     },
1610     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1611       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1612       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1613       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1614     },
1615     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1616       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1617       .accessfn = gt_vct_access,
1618       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1619     },
1620     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1621       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1622       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1623       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1624     },
1625     /* Comparison value, indicating when the timer goes off */
1626     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1627       .secure = ARM_CP_SECSTATE_NS,
1628       .access = PL1_RW | PL0_R,
1629       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1630       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1631       .accessfn = gt_ptimer_access,
1632       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1633     },
1634     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1635       .secure = ARM_CP_SECSTATE_S,
1636       .access = PL1_RW | PL0_R,
1637       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1638       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1639       .accessfn = gt_ptimer_access,
1640       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1641     },
1642     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1643       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1644       .access = PL1_RW | PL0_R,
1645       .type = ARM_CP_IO,
1646       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1647       .resetvalue = 0, .accessfn = gt_ptimer_access,
1648       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1649     },
1650     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1651       .access = PL1_RW | PL0_R,
1652       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1653       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1654       .accessfn = gt_vtimer_access,
1655       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1656     },
1657     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1658       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1659       .access = PL1_RW | PL0_R,
1660       .type = ARM_CP_IO,
1661       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1662       .resetvalue = 0, .accessfn = gt_vtimer_access,
1663       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1664     },
1665     /* Secure timer -- this is actually restricted to only EL3
1666      * and configurably Secure-EL1 via the accessfn.
1667      */
1668     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1669       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1670       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1671       .accessfn = gt_stimer_access,
1672       .readfn = gt_sec_tval_read,
1673       .writefn = gt_sec_tval_write,
1674       .resetfn = gt_sec_timer_reset,
1675     },
1676     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1677       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1678       .type = ARM_CP_IO, .access = PL1_RW,
1679       .accessfn = gt_stimer_access,
1680       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1681       .resetvalue = 0,
1682       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1683     },
1684     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1685       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1686       .type = ARM_CP_IO, .access = PL1_RW,
1687       .accessfn = gt_stimer_access,
1688       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1689       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1690     },
1691     REGINFO_SENTINEL
1692 };
1693
1694 #else
1695 /* In user-mode none of the generic timer registers are accessible,
1696  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1697  * so instead just don't register any of them.
1698  */
1699 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1700     REGINFO_SENTINEL
1701 };
1702
1703 #endif
1704
1705 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1706 {
1707     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1708         raw_write(env, ri, value);
1709     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1710         raw_write(env, ri, value & 0xfffff6ff);
1711     } else {
1712         raw_write(env, ri, value & 0xfffff1ff);
1713     }
1714 }
1715
1716 #ifndef CONFIG_USER_ONLY
1717 /* get_phys_addr() isn't present for user-mode-only targets */
1718
1719 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1720 {
1721     if (ri->opc2 & 4) {
1722         /* The ATS12NSO* operations must trap to EL3 if executed in
1723          * Secure EL1 (which can only happen if EL3 is AArch64).
1724          * They are simply UNDEF if executed from NS EL1.
1725          * They function normally from EL2 or EL3.
1726          */
1727         if (arm_current_el(env) == 1) {
1728             if (arm_is_secure_below_el3(env)) {
1729                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1730             }
1731             return CP_ACCESS_TRAP_UNCATEGORIZED;
1732         }
1733     }
1734     return CP_ACCESS_OK;
1735 }
1736
1737 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1738                              int access_type, ARMMMUIdx mmu_idx)
1739 {
1740     hwaddr phys_addr;
1741     target_ulong page_size;
1742     int prot;
1743     uint32_t fsr;
1744     bool ret;
1745     uint64_t par64;
1746     MemTxAttrs attrs = {};
1747
1748     ret = get_phys_addr(env, value, access_type, mmu_idx,
1749                         &phys_addr, &attrs, &prot, &page_size, &fsr);
1750     if (extended_addresses_enabled(env)) {
1751         /* fsr is a DFSR/IFSR value for the long descriptor
1752          * translation table format, but with WnR always clear.
1753          * Convert it to a 64-bit PAR.
1754          */
1755         par64 = (1 << 11); /* LPAE bit always set */
1756         if (!ret) {
1757             par64 |= phys_addr & ~0xfffULL;
1758             if (!attrs.secure) {
1759                 par64 |= (1 << 9); /* NS */
1760             }
1761             /* We don't set the ATTR or SH fields in the PAR. */
1762         } else {
1763             par64 |= 1; /* F */
1764             par64 |= (fsr & 0x3f) << 1; /* FS */
1765             /* Note that S2WLK and FSTAGE are always zero, because we don't
1766              * implement virtualization and therefore there can't be a stage 2
1767              * fault.
1768              */
1769         }
1770     } else {
1771         /* fsr is a DFSR/IFSR value for the short descriptor
1772          * translation table format (with WnR always clear).
1773          * Convert it to a 32-bit PAR.
1774          */
1775         if (!ret) {
1776             /* We do not set any attribute bits in the PAR */
1777             if (page_size == (1 << 24)
1778                 && arm_feature(env, ARM_FEATURE_V7)) {
1779                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1780             } else {
1781                 par64 = phys_addr & 0xfffff000;
1782             }
1783             if (!attrs.secure) {
1784                 par64 |= (1 << 9); /* NS */
1785             }
1786         } else {
1787             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1788                     ((fsr & 0xf) << 1) | 1;
1789         }
1790     }
1791     return par64;
1792 }
1793
1794 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1795 {
1796     int access_type = ri->opc2 & 1;
1797     uint64_t par64;
1798     ARMMMUIdx mmu_idx;
1799     int el = arm_current_el(env);
1800     bool secure = arm_is_secure_below_el3(env);
1801
1802     switch (ri->opc2 & 6) {
1803     case 0:
1804         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1805         switch (el) {
1806         case 3:
1807             mmu_idx = ARMMMUIdx_S1E3;
1808             break;
1809         case 2:
1810             mmu_idx = ARMMMUIdx_S1NSE1;
1811             break;
1812         case 1:
1813             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1814             break;
1815         default:
1816             g_assert_not_reached();
1817         }
1818         break;
1819     case 2:
1820         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1821         switch (el) {
1822         case 3:
1823             mmu_idx = ARMMMUIdx_S1SE0;
1824             break;
1825         case 2:
1826             mmu_idx = ARMMMUIdx_S1NSE0;
1827             break;
1828         case 1:
1829             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1830             break;
1831         default:
1832             g_assert_not_reached();
1833         }
1834         break;
1835     case 4:
1836         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1837         mmu_idx = ARMMMUIdx_S12NSE1;
1838         break;
1839     case 6:
1840         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1841         mmu_idx = ARMMMUIdx_S12NSE0;
1842         break;
1843     default:
1844         g_assert_not_reached();
1845     }
1846
1847     par64 = do_ats_write(env, value, access_type, mmu_idx);
1848
1849     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1850 }
1851
1852 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1853                         uint64_t value)
1854 {
1855     int access_type = ri->opc2 & 1;
1856     uint64_t par64;
1857
1858     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1859
1860     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1861 }
1862
1863 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
1864 {
1865     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1866         return CP_ACCESS_TRAP;
1867     }
1868     return CP_ACCESS_OK;
1869 }
1870
1871 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1872                         uint64_t value)
1873 {
1874     int access_type = ri->opc2 & 1;
1875     ARMMMUIdx mmu_idx;
1876     int secure = arm_is_secure_below_el3(env);
1877
1878     switch (ri->opc2 & 6) {
1879     case 0:
1880         switch (ri->opc1) {
1881         case 0: /* AT S1E1R, AT S1E1W */
1882             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1883             break;
1884         case 4: /* AT S1E2R, AT S1E2W */
1885             mmu_idx = ARMMMUIdx_S1E2;
1886             break;
1887         case 6: /* AT S1E3R, AT S1E3W */
1888             mmu_idx = ARMMMUIdx_S1E3;
1889             break;
1890         default:
1891             g_assert_not_reached();
1892         }
1893         break;
1894     case 2: /* AT S1E0R, AT S1E0W */
1895         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1896         break;
1897     case 4: /* AT S12E1R, AT S12E1W */
1898         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1899         break;
1900     case 6: /* AT S12E0R, AT S12E0W */
1901         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1902         break;
1903     default:
1904         g_assert_not_reached();
1905     }
1906
1907     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1908 }
1909 #endif
1910
1911 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1912     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1913       .access = PL1_RW, .resetvalue = 0,
1914       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1915                              offsetoflow32(CPUARMState, cp15.par_ns) },
1916       .writefn = par_write },
1917 #ifndef CONFIG_USER_ONLY
1918     /* This underdecoding is safe because the reginfo is NO_RAW. */
1919     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1920       .access = PL1_W, .accessfn = ats_access,
1921       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1922 #endif
1923     REGINFO_SENTINEL
1924 };
1925
1926 /* Return basic MPU access permission bits.  */
1927 static uint32_t simple_mpu_ap_bits(uint32_t val)
1928 {
1929     uint32_t ret;
1930     uint32_t mask;
1931     int i;
1932     ret = 0;
1933     mask = 3;
1934     for (i = 0; i < 16; i += 2) {
1935         ret |= (val >> i) & mask;
1936         mask <<= 2;
1937     }
1938     return ret;
1939 }
1940
1941 /* Pad basic MPU access permission bits to extended format.  */
1942 static uint32_t extended_mpu_ap_bits(uint32_t val)
1943 {
1944     uint32_t ret;
1945     uint32_t mask;
1946     int i;
1947     ret = 0;
1948     mask = 3;
1949     for (i = 0; i < 16; i += 2) {
1950         ret |= (val & mask) << i;
1951         mask <<= 2;
1952     }
1953     return ret;
1954 }
1955
1956 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1957                                  uint64_t value)
1958 {
1959     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1960 }
1961
1962 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1963 {
1964     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1965 }
1966
1967 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1968                                  uint64_t value)
1969 {
1970     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1971 }
1972
1973 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1974 {
1975     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1976 }
1977
1978 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
1979 {
1980     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
1981
1982     if (!u32p) {
1983         return 0;
1984     }
1985
1986     u32p += env->cp15.c6_rgnr;
1987     return *u32p;
1988 }
1989
1990 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
1991                          uint64_t value)
1992 {
1993     ARMCPU *cpu = arm_env_get_cpu(env);
1994     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
1995
1996     if (!u32p) {
1997         return;
1998     }
1999
2000     u32p += env->cp15.c6_rgnr;
2001     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2002     *u32p = value;
2003 }
2004
2005 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2006 {
2007     ARMCPU *cpu = arm_env_get_cpu(env);
2008     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2009
2010     if (!u32p) {
2011         return;
2012     }
2013
2014     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2015 }
2016
2017 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2018                               uint64_t value)
2019 {
2020     ARMCPU *cpu = arm_env_get_cpu(env);
2021     uint32_t nrgs = cpu->pmsav7_dregion;
2022
2023     if (value >= nrgs) {
2024         qemu_log_mask(LOG_GUEST_ERROR,
2025                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2026                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2027         return;
2028     }
2029
2030     raw_write(env, ri, value);
2031 }
2032
2033 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2034     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2035       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2036       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2037       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2038     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2039       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2040       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2041       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2042     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2043       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2044       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2045       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2046     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2047       .access = PL1_RW,
2048       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2049       .writefn = pmsav7_rgnr_write },
2050     REGINFO_SENTINEL
2051 };
2052
2053 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2054     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2055       .access = PL1_RW, .type = ARM_CP_ALIAS,
2056       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2057       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2058     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2059       .access = PL1_RW, .type = ARM_CP_ALIAS,
2060       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2061       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2062     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2063       .access = PL1_RW,
2064       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2065       .resetvalue = 0, },
2066     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2067       .access = PL1_RW,
2068       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2069       .resetvalue = 0, },
2070     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2071       .access = PL1_RW,
2072       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2073     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2074       .access = PL1_RW,
2075       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2076     /* Protection region base and size registers */
2077     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2078       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2079       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2080     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2081       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2082       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2083     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2084       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2085       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2086     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2087       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2088       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2089     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2090       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2091       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2092     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2093       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2094       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2095     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2096       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2097       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2098     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2099       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2100       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2101     REGINFO_SENTINEL
2102 };
2103
2104 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2105                                  uint64_t value)
2106 {
2107     TCR *tcr = raw_ptr(env, ri);
2108     int maskshift = extract32(value, 0, 3);
2109
2110     if (!arm_feature(env, ARM_FEATURE_V8)) {
2111         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2112             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2113              * using Long-desciptor translation table format */
2114             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2115         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2116             /* In an implementation that includes the Security Extensions
2117              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2118              * Short-descriptor translation table format.
2119              */
2120             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2121         } else {
2122             value &= TTBCR_N;
2123         }
2124     }
2125
2126     /* Update the masks corresponding to the the TCR bank being written
2127      * Note that we always calculate mask and base_mask, but
2128      * they are only used for short-descriptor tables (ie if EAE is 0);
2129      * for long-descriptor tables the TCR fields are used differently
2130      * and the mask and base_mask values are meaningless.
2131      */
2132     tcr->raw_tcr = value;
2133     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2134     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2135 }
2136
2137 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2138                              uint64_t value)
2139 {
2140     ARMCPU *cpu = arm_env_get_cpu(env);
2141
2142     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2143         /* With LPAE the TTBCR could result in a change of ASID
2144          * via the TTBCR.A1 bit, so do a TLB flush.
2145          */
2146         tlb_flush(CPU(cpu), 1);
2147     }
2148     vmsa_ttbcr_raw_write(env, ri, value);
2149 }
2150
2151 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2152 {
2153     TCR *tcr = raw_ptr(env, ri);
2154
2155     /* Reset both the TCR as well as the masks corresponding to the bank of
2156      * the TCR being reset.
2157      */
2158     tcr->raw_tcr = 0;
2159     tcr->mask = 0;
2160     tcr->base_mask = 0xffffc000u;
2161 }
2162
2163 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2164                                uint64_t value)
2165 {
2166     ARMCPU *cpu = arm_env_get_cpu(env);
2167     TCR *tcr = raw_ptr(env, ri);
2168
2169     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2170     tlb_flush(CPU(cpu), 1);
2171     tcr->raw_tcr = value;
2172 }
2173
2174 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2175                             uint64_t value)
2176 {
2177     /* 64 bit accesses to the TTBRs can change the ASID and so we
2178      * must flush the TLB.
2179      */
2180     if (cpreg_field_is_64bit(ri)) {
2181         ARMCPU *cpu = arm_env_get_cpu(env);
2182
2183         tlb_flush(CPU(cpu), 1);
2184     }
2185     raw_write(env, ri, value);
2186 }
2187
2188 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2189     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2190       .access = PL1_RW, .type = ARM_CP_ALIAS,
2191       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2192                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2193     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2194       .access = PL1_RW, .resetvalue = 0,
2195       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2196                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2197     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2198       .access = PL1_RW, .resetvalue = 0,
2199       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2200                              offsetof(CPUARMState, cp15.dfar_ns) } },
2201     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2202       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2203       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2204       .resetvalue = 0, },
2205     REGINFO_SENTINEL
2206 };
2207
2208 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2209     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2210       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2211       .access = PL1_RW,
2212       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2213     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2214       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2215       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2216       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2217                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2218     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2219       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2220       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2221       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2222                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2223     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2224       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2225       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2226       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2227       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2228     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2229       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2230       .raw_writefn = vmsa_ttbcr_raw_write,
2231       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2232                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2233     REGINFO_SENTINEL
2234 };
2235
2236 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2237                                 uint64_t value)
2238 {
2239     env->cp15.c15_ticonfig = value & 0xe7;
2240     /* The OS_TYPE bit in this register changes the reported CPUID! */
2241     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2242         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2243 }
2244
2245 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2246                                 uint64_t value)
2247 {
2248     env->cp15.c15_threadid = value & 0xffff;
2249 }
2250
2251 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2252                            uint64_t value)
2253 {
2254     /* Wait-for-interrupt (deprecated) */
2255     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2256 }
2257
2258 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2259                                   uint64_t value)
2260 {
2261     /* On OMAP there are registers indicating the max/min index of dcache lines
2262      * containing a dirty line; cache flush operations have to reset these.
2263      */
2264     env->cp15.c15_i_max = 0x000;
2265     env->cp15.c15_i_min = 0xff0;
2266 }
2267
2268 static const ARMCPRegInfo omap_cp_reginfo[] = {
2269     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2270       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2271       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2272       .resetvalue = 0, },
2273     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2274       .access = PL1_RW, .type = ARM_CP_NOP },
2275     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2276       .access = PL1_RW,
2277       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2278       .writefn = omap_ticonfig_write },
2279     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2280       .access = PL1_RW,
2281       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2282     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2283       .access = PL1_RW, .resetvalue = 0xff0,
2284       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2285     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2286       .access = PL1_RW,
2287       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2288       .writefn = omap_threadid_write },
2289     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2290       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2291       .type = ARM_CP_NO_RAW,
2292       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2293     /* TODO: Peripheral port remap register:
2294      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2295      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2296      * when MMU is off.
2297      */
2298     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2299       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2300       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2301       .writefn = omap_cachemaint_write },
2302     { .name = "C9", .cp = 15, .crn = 9,
2303       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2304       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2305     REGINFO_SENTINEL
2306 };
2307
2308 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2309                               uint64_t value)
2310 {
2311     env->cp15.c15_cpar = value & 0x3fff;
2312 }
2313
2314 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2315     { .name = "XSCALE_CPAR",
2316       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2317       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2318       .writefn = xscale_cpar_write, },
2319     { .name = "XSCALE_AUXCR",
2320       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2321       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2322       .resetvalue = 0, },
2323     /* XScale specific cache-lockdown: since we have no cache we NOP these
2324      * and hope the guest does not really rely on cache behaviour.
2325      */
2326     { .name = "XSCALE_LOCK_ICACHE_LINE",
2327       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2328       .access = PL1_W, .type = ARM_CP_NOP },
2329     { .name = "XSCALE_UNLOCK_ICACHE",
2330       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2331       .access = PL1_W, .type = ARM_CP_NOP },
2332     { .name = "XSCALE_DCACHE_LOCK",
2333       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2334       .access = PL1_RW, .type = ARM_CP_NOP },
2335     { .name = "XSCALE_UNLOCK_DCACHE",
2336       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2337       .access = PL1_W, .type = ARM_CP_NOP },
2338     REGINFO_SENTINEL
2339 };
2340
2341 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2342     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2343      * implementation of this implementation-defined space.
2344      * Ideally this should eventually disappear in favour of actually
2345      * implementing the correct behaviour for all cores.
2346      */
2347     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2348       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2349       .access = PL1_RW,
2350       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2351       .resetvalue = 0 },
2352     REGINFO_SENTINEL
2353 };
2354
2355 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2356     /* Cache status: RAZ because we have no cache so it's always clean */
2357     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2358       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2359       .resetvalue = 0 },
2360     REGINFO_SENTINEL
2361 };
2362
2363 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2364     /* We never have a a block transfer operation in progress */
2365     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2366       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2367       .resetvalue = 0 },
2368     /* The cache ops themselves: these all NOP for QEMU */
2369     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2370       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2371     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2372       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2373     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2374       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2375     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2376       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2377     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2378       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2379     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2380       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2381     REGINFO_SENTINEL
2382 };
2383
2384 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2385     /* The cache test-and-clean instructions always return (1 << 30)
2386      * to indicate that there are no dirty cache lines.
2387      */
2388     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2389       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2390       .resetvalue = (1 << 30) },
2391     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2392       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2393       .resetvalue = (1 << 30) },
2394     REGINFO_SENTINEL
2395 };
2396
2397 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2398     /* Ignore ReadBuffer accesses */
2399     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2400       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2401       .access = PL1_RW, .resetvalue = 0,
2402       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2403     REGINFO_SENTINEL
2404 };
2405
2406 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2407 {
2408     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2409     uint64_t mpidr = cpu->mp_affinity;
2410
2411     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2412         mpidr |= (1U << 31);
2413         /* Cores which are uniprocessor (non-coherent)
2414          * but still implement the MP extensions set
2415          * bit 30. (For instance, Cortex-R5).
2416          */
2417         if (cpu->mp_is_up) {
2418             mpidr |= (1u << 30);
2419         }
2420     }
2421     return mpidr;
2422 }
2423
2424 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2425     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2426       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2427       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2428     REGINFO_SENTINEL
2429 };
2430
2431 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2432     /* NOP AMAIR0/1 */
2433     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2434       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2435       .access = PL1_RW, .type = ARM_CP_CONST,
2436       .resetvalue = 0 },
2437     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2438     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2439       .access = PL1_RW, .type = ARM_CP_CONST,
2440       .resetvalue = 0 },
2441     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2442       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2443       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2444                              offsetof(CPUARMState, cp15.par_ns)} },
2445     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2446       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2447       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2448                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2449       .writefn = vmsa_ttbr_write, },
2450     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2451       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2452       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2453                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2454       .writefn = vmsa_ttbr_write, },
2455     REGINFO_SENTINEL
2456 };
2457
2458 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2459 {
2460     return vfp_get_fpcr(env);
2461 }
2462
2463 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2464                             uint64_t value)
2465 {
2466     vfp_set_fpcr(env, value);
2467 }
2468
2469 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2470 {
2471     return vfp_get_fpsr(env);
2472 }
2473
2474 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2475                             uint64_t value)
2476 {
2477     vfp_set_fpsr(env, value);
2478 }
2479
2480 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2481 {
2482     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2483         return CP_ACCESS_TRAP;
2484     }
2485     return CP_ACCESS_OK;
2486 }
2487
2488 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2489                             uint64_t value)
2490 {
2491     env->daif = value & PSTATE_DAIF;
2492 }
2493
2494 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2495                                           const ARMCPRegInfo *ri)
2496 {
2497     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2498      * SCTLR_EL1.UCI is set.
2499      */
2500     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2501         return CP_ACCESS_TRAP;
2502     }
2503     return CP_ACCESS_OK;
2504 }
2505
2506 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2507  * Page D4-1736 (DDI0487A.b)
2508  */
2509
2510 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2511                                     uint64_t value)
2512 {
2513     ARMCPU *cpu = arm_env_get_cpu(env);
2514     CPUState *cs = CPU(cpu);
2515
2516     if (arm_is_secure_below_el3(env)) {
2517         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2518     } else {
2519         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2520     }
2521 }
2522
2523 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2524                                       uint64_t value)
2525 {
2526     bool sec = arm_is_secure_below_el3(env);
2527     CPUState *other_cs;
2528
2529     CPU_FOREACH(other_cs) {
2530         if (sec) {
2531             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2532         } else {
2533             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2534                                 ARMMMUIdx_S12NSE0, -1);
2535         }
2536     }
2537 }
2538
2539 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2540                                   uint64_t value)
2541 {
2542     /* Note that the 'ALL' scope must invalidate both stage 1 and
2543      * stage 2 translations, whereas most other scopes only invalidate
2544      * stage 1 translations.
2545      */
2546     ARMCPU *cpu = arm_env_get_cpu(env);
2547     CPUState *cs = CPU(cpu);
2548
2549     if (arm_is_secure_below_el3(env)) {
2550         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2551     } else {
2552         if (arm_feature(env, ARM_FEATURE_EL2)) {
2553             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2554                                 ARMMMUIdx_S2NS, -1);
2555         } else {
2556             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2557         }
2558     }
2559 }
2560
2561 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2562                                   uint64_t value)
2563 {
2564     ARMCPU *cpu = arm_env_get_cpu(env);
2565     CPUState *cs = CPU(cpu);
2566
2567     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2568 }
2569
2570 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2571                                   uint64_t value)
2572 {
2573     ARMCPU *cpu = arm_env_get_cpu(env);
2574     CPUState *cs = CPU(cpu);
2575
2576     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2577 }
2578
2579 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2580                                     uint64_t value)
2581 {
2582     /* Note that the 'ALL' scope must invalidate both stage 1 and
2583      * stage 2 translations, whereas most other scopes only invalidate
2584      * stage 1 translations.
2585      */
2586     bool sec = arm_is_secure_below_el3(env);
2587     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2588     CPUState *other_cs;
2589
2590     CPU_FOREACH(other_cs) {
2591         if (sec) {
2592             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2593         } else if (has_el2) {
2594             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2595                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2596         } else {
2597             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2598                                 ARMMMUIdx_S12NSE0, -1);
2599         }
2600     }
2601 }
2602
2603 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2604                                     uint64_t value)
2605 {
2606     CPUState *other_cs;
2607
2608     CPU_FOREACH(other_cs) {
2609         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2610     }
2611 }
2612
2613 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2614                                     uint64_t value)
2615 {
2616     CPUState *other_cs;
2617
2618     CPU_FOREACH(other_cs) {
2619         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2620     }
2621 }
2622
2623 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2624                                  uint64_t value)
2625 {
2626     /* Invalidate by VA, EL1&0 (AArch64 version).
2627      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2628      * since we don't support flush-for-specific-ASID-only or
2629      * flush-last-level-only.
2630      */
2631     ARMCPU *cpu = arm_env_get_cpu(env);
2632     CPUState *cs = CPU(cpu);
2633     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2634
2635     if (arm_is_secure_below_el3(env)) {
2636         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2637                                  ARMMMUIdx_S1SE0, -1);
2638     } else {
2639         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2640                                  ARMMMUIdx_S12NSE0, -1);
2641     }
2642 }
2643
2644 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2645                                  uint64_t value)
2646 {
2647     /* Invalidate by VA, EL2
2648      * Currently handles both VAE2 and VALE2, since we don't support
2649      * flush-last-level-only.
2650      */
2651     ARMCPU *cpu = arm_env_get_cpu(env);
2652     CPUState *cs = CPU(cpu);
2653     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2654
2655     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2656 }
2657
2658 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2659                                  uint64_t value)
2660 {
2661     /* Invalidate by VA, EL3
2662      * Currently handles both VAE3 and VALE3, since we don't support
2663      * flush-last-level-only.
2664      */
2665     ARMCPU *cpu = arm_env_get_cpu(env);
2666     CPUState *cs = CPU(cpu);
2667     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2668
2669     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2670 }
2671
2672 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2673                                    uint64_t value)
2674 {
2675     bool sec = arm_is_secure_below_el3(env);
2676     CPUState *other_cs;
2677     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2678
2679     CPU_FOREACH(other_cs) {
2680         if (sec) {
2681             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2682                                      ARMMMUIdx_S1SE0, -1);
2683         } else {
2684             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2685                                      ARMMMUIdx_S12NSE0, -1);
2686         }
2687     }
2688 }
2689
2690 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2691                                    uint64_t value)
2692 {
2693     CPUState *other_cs;
2694     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2695
2696     CPU_FOREACH(other_cs) {
2697         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2698     }
2699 }
2700
2701 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2702                                    uint64_t value)
2703 {
2704     CPUState *other_cs;
2705     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2706
2707     CPU_FOREACH(other_cs) {
2708         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2709     }
2710 }
2711
2712 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2713                                     uint64_t value)
2714 {
2715     /* Invalidate by IPA. This has to invalidate any structures that
2716      * contain only stage 2 translation information, but does not need
2717      * to apply to structures that contain combined stage 1 and stage 2
2718      * translation information.
2719      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2720      */
2721     ARMCPU *cpu = arm_env_get_cpu(env);
2722     CPUState *cs = CPU(cpu);
2723     uint64_t pageaddr;
2724
2725     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2726         return;
2727     }
2728
2729     pageaddr = sextract64(value << 12, 0, 48);
2730
2731     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2732 }
2733
2734 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2735                                       uint64_t value)
2736 {
2737     CPUState *other_cs;
2738     uint64_t pageaddr;
2739
2740     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2741         return;
2742     }
2743
2744     pageaddr = sextract64(value << 12, 0, 48);
2745
2746     CPU_FOREACH(other_cs) {
2747         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2748     }
2749 }
2750
2751 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2752 {
2753     /* We don't implement EL2, so the only control on DC ZVA is the
2754      * bit in the SCTLR which can prohibit access for EL0.
2755      */
2756     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2757         return CP_ACCESS_TRAP;
2758     }
2759     return CP_ACCESS_OK;
2760 }
2761
2762 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2763 {
2764     ARMCPU *cpu = arm_env_get_cpu(env);
2765     int dzp_bit = 1 << 4;
2766
2767     /* DZP indicates whether DC ZVA access is allowed */
2768     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2769         dzp_bit = 0;
2770     }
2771     return cpu->dcz_blocksize | dzp_bit;
2772 }
2773
2774 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2775 {
2776     if (!(env->pstate & PSTATE_SP)) {
2777         /* Access to SP_EL0 is undefined if it's being used as
2778          * the stack pointer.
2779          */
2780         return CP_ACCESS_TRAP_UNCATEGORIZED;
2781     }
2782     return CP_ACCESS_OK;
2783 }
2784
2785 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2786 {
2787     return env->pstate & PSTATE_SP;
2788 }
2789
2790 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2791 {
2792     update_spsel(env, val);
2793 }
2794
2795 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2796                         uint64_t value)
2797 {
2798     ARMCPU *cpu = arm_env_get_cpu(env);
2799
2800     if (raw_read(env, ri) == value) {
2801         /* Skip the TLB flush if nothing actually changed; Linux likes
2802          * to do a lot of pointless SCTLR writes.
2803          */
2804         return;
2805     }
2806
2807     raw_write(env, ri, value);
2808     /* ??? Lots of these bits are not implemented.  */
2809     /* This may enable/disable the MMU, so do a TLB flush.  */
2810     tlb_flush(CPU(cpu), 1);
2811 }
2812
2813 static const ARMCPRegInfo v8_cp_reginfo[] = {
2814     /* Minimal set of EL0-visible registers. This will need to be expanded
2815      * significantly for system emulation of AArch64 CPUs.
2816      */
2817     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2818       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2819       .access = PL0_RW, .type = ARM_CP_NZCV },
2820     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2821       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2822       .type = ARM_CP_NO_RAW,
2823       .access = PL0_RW, .accessfn = aa64_daif_access,
2824       .fieldoffset = offsetof(CPUARMState, daif),
2825       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2826     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2827       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2828       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2829     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2830       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2831       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2832     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2833       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2834       .access = PL0_R, .type = ARM_CP_NO_RAW,
2835       .readfn = aa64_dczid_read },
2836     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2837       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2838       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2839 #ifndef CONFIG_USER_ONLY
2840       /* Avoid overhead of an access check that always passes in user-mode */
2841       .accessfn = aa64_zva_access,
2842 #endif
2843     },
2844     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2845       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2846       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2847     /* Cache ops: all NOPs since we don't emulate caches */
2848     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2849       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2850       .access = PL1_W, .type = ARM_CP_NOP },
2851     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2852       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2853       .access = PL1_W, .type = ARM_CP_NOP },
2854     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2855       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2856       .access = PL0_W, .type = ARM_CP_NOP,
2857       .accessfn = aa64_cacheop_access },
2858     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2859       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2860       .access = PL1_W, .type = ARM_CP_NOP },
2861     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2862       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2863       .access = PL1_W, .type = ARM_CP_NOP },
2864     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2865       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2866       .access = PL0_W, .type = ARM_CP_NOP,
2867       .accessfn = aa64_cacheop_access },
2868     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2869       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2870       .access = PL1_W, .type = ARM_CP_NOP },
2871     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2872       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2873       .access = PL0_W, .type = ARM_CP_NOP,
2874       .accessfn = aa64_cacheop_access },
2875     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2876       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2877       .access = PL0_W, .type = ARM_CP_NOP,
2878       .accessfn = aa64_cacheop_access },
2879     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2880       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2881       .access = PL1_W, .type = ARM_CP_NOP },
2882     /* TLBI operations */
2883     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2884       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2885       .access = PL1_W, .type = ARM_CP_NO_RAW,
2886       .writefn = tlbi_aa64_vmalle1is_write },
2887     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2888       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2889       .access = PL1_W, .type = ARM_CP_NO_RAW,
2890       .writefn = tlbi_aa64_vae1is_write },
2891     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2892       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2893       .access = PL1_W, .type = ARM_CP_NO_RAW,
2894       .writefn = tlbi_aa64_vmalle1is_write },
2895     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2896       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2897       .access = PL1_W, .type = ARM_CP_NO_RAW,
2898       .writefn = tlbi_aa64_vae1is_write },
2899     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2900       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2901       .access = PL1_W, .type = ARM_CP_NO_RAW,
2902       .writefn = tlbi_aa64_vae1is_write },
2903     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2904       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2905       .access = PL1_W, .type = ARM_CP_NO_RAW,
2906       .writefn = tlbi_aa64_vae1is_write },
2907     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2908       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2909       .access = PL1_W, .type = ARM_CP_NO_RAW,
2910       .writefn = tlbi_aa64_vmalle1_write },
2911     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2912       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2913       .access = PL1_W, .type = ARM_CP_NO_RAW,
2914       .writefn = tlbi_aa64_vae1_write },
2915     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2916       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2917       .access = PL1_W, .type = ARM_CP_NO_RAW,
2918       .writefn = tlbi_aa64_vmalle1_write },
2919     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2920       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2921       .access = PL1_W, .type = ARM_CP_NO_RAW,
2922       .writefn = tlbi_aa64_vae1_write },
2923     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2924       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2925       .access = PL1_W, .type = ARM_CP_NO_RAW,
2926       .writefn = tlbi_aa64_vae1_write },
2927     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2928       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2929       .access = PL1_W, .type = ARM_CP_NO_RAW,
2930       .writefn = tlbi_aa64_vae1_write },
2931     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
2932       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
2933       .access = PL2_W, .type = ARM_CP_NO_RAW,
2934       .writefn = tlbi_aa64_ipas2e1is_write },
2935     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
2936       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
2937       .access = PL2_W, .type = ARM_CP_NO_RAW,
2938       .writefn = tlbi_aa64_ipas2e1is_write },
2939     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
2940       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
2941       .access = PL2_W, .type = ARM_CP_NO_RAW,
2942       .writefn = tlbi_aa64_alle1is_write },
2943     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
2944       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
2945       .access = PL2_W, .type = ARM_CP_NO_RAW,
2946       .writefn = tlbi_aa64_alle1is_write },
2947     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
2948       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
2949       .access = PL2_W, .type = ARM_CP_NO_RAW,
2950       .writefn = tlbi_aa64_ipas2e1_write },
2951     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
2952       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
2953       .access = PL2_W, .type = ARM_CP_NO_RAW,
2954       .writefn = tlbi_aa64_ipas2e1_write },
2955     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
2956       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
2957       .access = PL2_W, .type = ARM_CP_NO_RAW,
2958       .writefn = tlbi_aa64_alle1_write },
2959     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
2960       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
2961       .access = PL2_W, .type = ARM_CP_NO_RAW,
2962       .writefn = tlbi_aa64_alle1is_write },
2963 #ifndef CONFIG_USER_ONLY
2964     /* 64 bit address translation operations */
2965     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2966       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2967       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2968     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2969       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2970       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2971     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2972       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2973       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2974     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2975       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2976       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2977     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
2978       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
2979       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2980     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
2981       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
2982       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2983     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
2984       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
2985       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2986     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
2987       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
2988       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2989     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
2990     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
2991       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
2992       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2993     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
2994       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
2995       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2996     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
2997       .type = ARM_CP_ALIAS,
2998       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
2999       .access = PL1_RW, .resetvalue = 0,
3000       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3001       .writefn = par_write },
3002 #endif
3003     /* TLB invalidate last level of translation table walk */
3004     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3005       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3006     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3007       .type = ARM_CP_NO_RAW, .access = PL1_W,
3008       .writefn = tlbimvaa_is_write },
3009     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3010       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3011     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3012       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3013     /* 32 bit cache operations */
3014     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3015       .type = ARM_CP_NOP, .access = PL1_W },
3016     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3017       .type = ARM_CP_NOP, .access = PL1_W },
3018     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3019       .type = ARM_CP_NOP, .access = PL1_W },
3020     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3021       .type = ARM_CP_NOP, .access = PL1_W },
3022     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3023       .type = ARM_CP_NOP, .access = PL1_W },
3024     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3025       .type = ARM_CP_NOP, .access = PL1_W },
3026     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3027       .type = ARM_CP_NOP, .access = PL1_W },
3028     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3029       .type = ARM_CP_NOP, .access = PL1_W },
3030     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3031       .type = ARM_CP_NOP, .access = PL1_W },
3032     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3033       .type = ARM_CP_NOP, .access = PL1_W },
3034     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3035       .type = ARM_CP_NOP, .access = PL1_W },
3036     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3037       .type = ARM_CP_NOP, .access = PL1_W },
3038     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3039       .type = ARM_CP_NOP, .access = PL1_W },
3040     /* MMU Domain access control / MPU write buffer control */
3041     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3042       .access = PL1_RW, .resetvalue = 0,
3043       .writefn = dacr_write, .raw_writefn = raw_write,
3044       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3045                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3046     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3047       .type = ARM_CP_ALIAS,
3048       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3049       .access = PL1_RW,
3050       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3051     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3052       .type = ARM_CP_ALIAS,
3053       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3054       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
3055     /* We rely on the access checks not allowing the guest to write to the
3056      * state field when SPSel indicates that it's being used as the stack
3057      * pointer.
3058      */
3059     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3060       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3061       .access = PL1_RW, .accessfn = sp_el0_access,
3062       .type = ARM_CP_ALIAS,
3063       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3064     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3065       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3066       .access = PL2_RW, .type = ARM_CP_ALIAS,
3067       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3068     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3069       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3070       .type = ARM_CP_NO_RAW,
3071       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3072     REGINFO_SENTINEL
3073 };
3074
3075 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3076 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3077     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3078       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3079       .access = PL2_RW,
3080       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3081     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3082       .type = ARM_CP_NO_RAW,
3083       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3084       .access = PL2_RW,
3085       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3086     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3087       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3088       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3089     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3090       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3091       .access = PL2_RW, .type = ARM_CP_CONST,
3092       .resetvalue = 0 },
3093     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3094       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3095       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3096     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3097       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3098       .access = PL2_RW, .type = ARM_CP_CONST,
3099       .resetvalue = 0 },
3100     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3101       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3102       .access = PL2_RW, .type = ARM_CP_CONST,
3103       .resetvalue = 0 },
3104     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3105       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3106       .access = PL2_RW, .type = ARM_CP_CONST,
3107       .resetvalue = 0 },
3108     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3109       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3110       .access = PL2_RW, .type = ARM_CP_CONST,
3111       .resetvalue = 0 },
3112     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3113       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3114       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3115     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3116       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3117       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3118     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3119       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3120       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3121     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3122       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3123       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3124     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3125       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3126       .resetvalue = 0 },
3127     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3128       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3129       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3130     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3131       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3132       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3133     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3134       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3135       .resetvalue = 0 },
3136     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3137       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3138       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3139     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3140       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3141       .resetvalue = 0 },
3142     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3143       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3144       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3145     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3146       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3147       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3148     REGINFO_SENTINEL
3149 };
3150
3151 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3152 {
3153     ARMCPU *cpu = arm_env_get_cpu(env);
3154     uint64_t valid_mask = HCR_MASK;
3155
3156     if (arm_feature(env, ARM_FEATURE_EL3)) {
3157         valid_mask &= ~HCR_HCD;
3158     } else {
3159         valid_mask &= ~HCR_TSC;
3160     }
3161
3162     /* Clear RES0 bits.  */
3163     value &= valid_mask;
3164
3165     /* These bits change the MMU setup:
3166      * HCR_VM enables stage 2 translation
3167      * HCR_PTW forbids certain page-table setups
3168      * HCR_DC Disables stage1 and enables stage2 translation
3169      */
3170     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3171         tlb_flush(CPU(cpu), 1);
3172     }
3173     raw_write(env, ri, value);
3174 }
3175
3176 static const ARMCPRegInfo el2_cp_reginfo[] = {
3177     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3178       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3179       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3180       .writefn = hcr_write },
3181     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3182       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3183       .access = PL2_RW, .resetvalue = 0,
3184       .writefn = dacr_write, .raw_writefn = raw_write,
3185       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3186     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3187       .type = ARM_CP_ALIAS,
3188       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3189       .access = PL2_RW,
3190       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3191     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3192       .type = ARM_CP_ALIAS,
3193       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3194       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3195     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3196       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3197       .access = PL2_RW, .resetvalue = 0,
3198       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3199     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3200       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3201       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3202     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3203       .type = ARM_CP_ALIAS,
3204       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3205       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
3206     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3207       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3208       .access = PL2_RW, .writefn = vbar_write,
3209       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3210       .resetvalue = 0 },
3211     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3212       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3213       .access = PL3_RW, .type = ARM_CP_ALIAS,
3214       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3215     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3216       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3217       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3218       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3219     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3220       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3221       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3222       .resetvalue = 0 },
3223     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3224       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3225       .access = PL2_RW, .type = ARM_CP_ALIAS,
3226       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3227     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3228       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3229       .access = PL2_RW, .type = ARM_CP_CONST,
3230       .resetvalue = 0 },
3231     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3232     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3233       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3234       .access = PL2_RW, .type = ARM_CP_CONST,
3235       .resetvalue = 0 },
3236     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3237       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3238       .access = PL2_RW, .type = ARM_CP_CONST,
3239       .resetvalue = 0 },
3240     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3241       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3242       .access = PL2_RW, .type = ARM_CP_CONST,
3243       .resetvalue = 0 },
3244     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3245       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3246       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3247       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3248       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3249     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3250       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3251       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3252       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3253     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3254       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3255       .access = PL2_RW, .resetvalue = 0,
3256       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3257     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3258       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3259       .access = PL2_RW, .resetvalue = 0,
3260       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3261     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3262       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3263       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3264     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3265       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3266       .type = ARM_CP_NO_RAW, .access = PL2_W,
3267       .writefn = tlbi_aa64_alle2_write },
3268     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3269       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3270       .type = ARM_CP_NO_RAW, .access = PL2_W,
3271       .writefn = tlbi_aa64_vae2_write },
3272     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3273       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3274       .access = PL2_W, .type = ARM_CP_NO_RAW,
3275       .writefn = tlbi_aa64_vae2_write },
3276     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3277       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3278       .access = PL2_W, .type = ARM_CP_NO_RAW,
3279       .writefn = tlbi_aa64_alle2is_write },
3280     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3281       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3282       .type = ARM_CP_NO_RAW, .access = PL2_W,
3283       .writefn = tlbi_aa64_vae2is_write },
3284     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3285       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3286       .access = PL2_W, .type = ARM_CP_NO_RAW,
3287       .writefn = tlbi_aa64_vae2is_write },
3288 #ifndef CONFIG_USER_ONLY
3289     /* Unlike the other EL2-related AT operations, these must
3290      * UNDEF from EL3 if EL2 is not implemented, which is why we
3291      * define them here rather than with the rest of the AT ops.
3292      */
3293     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3294       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3295       .access = PL2_W, .accessfn = at_s1e2_access,
3296       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3297     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3298       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3299       .access = PL2_W, .accessfn = at_s1e2_access,
3300       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3301     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3302      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3303      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3304      * to behave as if SCR.NS was 1.
3305      */
3306     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3307       .access = PL2_W,
3308       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3309     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3310       .access = PL2_W,
3311       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3312     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3313       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3314       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3315        * reset values as IMPDEF. We choose to reset to 3 to comply with
3316        * both ARMv7 and ARMv8.
3317        */
3318       .access = PL2_RW, .resetvalue = 3,
3319       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3320     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3321       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3322       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3323       .writefn = gt_cntvoff_write,
3324       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3325     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3326       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3327       .writefn = gt_cntvoff_write,
3328       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3329     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3330       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3331       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3332       .type = ARM_CP_IO, .access = PL2_RW,
3333       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3334     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3335       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3336       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3337       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3338     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3339       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3340       .type = ARM_CP_IO, .access = PL2_RW,
3341       .resetfn = gt_hyp_timer_reset,
3342       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3343     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3344       .type = ARM_CP_IO,
3345       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3346       .access = PL2_RW,
3347       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3348       .resetvalue = 0,
3349       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3350 #endif
3351     REGINFO_SENTINEL
3352 };
3353
3354 static const ARMCPRegInfo el3_cp_reginfo[] = {
3355     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3356       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3357       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3358       .resetvalue = 0, .writefn = scr_write },
3359     { .name = "SCR",  .type = ARM_CP_ALIAS,
3360       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3361       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3362       .writefn = scr_write },
3363     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3364       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3365       .access = PL3_RW, .resetvalue = 0,
3366       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3367     { .name = "SDER",
3368       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3369       .access = PL3_RW, .resetvalue = 0,
3370       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3371       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3372     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
3373       .access = PL3_W | PL1_R, .resetvalue = 0,
3374       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
3375     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3376       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
3377       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3378     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3379       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3380       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3381       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3382       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3383     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3384       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3385       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3386       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3387     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3388       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3389       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3390       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3391       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3392     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3393       .type = ARM_CP_ALIAS,
3394       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3395       .access = PL3_RW,
3396       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3397     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3398       .type = ARM_CP_ALIAS,
3399       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3400       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3401     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3402       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3403       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3404     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3405       .type = ARM_CP_ALIAS,
3406       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3407       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
3408     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3409       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3410       .access = PL3_RW, .writefn = vbar_write,
3411       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3412       .resetvalue = 0 },
3413     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3414       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3415       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3416       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3417     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3418       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3419       .access = PL3_RW, .resetvalue = 0,
3420       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3421     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3422       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3423       .access = PL3_RW, .type = ARM_CP_CONST,
3424       .resetvalue = 0 },
3425     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3426       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3427       .access = PL3_RW, .type = ARM_CP_CONST,
3428       .resetvalue = 0 },
3429     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3430       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3431       .access = PL3_RW, .type = ARM_CP_CONST,
3432       .resetvalue = 0 },
3433     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3434       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3435       .access = PL3_W, .type = ARM_CP_NO_RAW,
3436       .writefn = tlbi_aa64_alle3is_write },
3437     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3438       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3439       .access = PL3_W, .type = ARM_CP_NO_RAW,
3440       .writefn = tlbi_aa64_vae3is_write },
3441     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3442       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3443       .access = PL3_W, .type = ARM_CP_NO_RAW,
3444       .writefn = tlbi_aa64_vae3is_write },
3445     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3446       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3447       .access = PL3_W, .type = ARM_CP_NO_RAW,
3448       .writefn = tlbi_aa64_alle3_write },
3449     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3450       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3451       .access = PL3_W, .type = ARM_CP_NO_RAW,
3452       .writefn = tlbi_aa64_vae3_write },
3453     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3454       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3455       .access = PL3_W, .type = ARM_CP_NO_RAW,
3456       .writefn = tlbi_aa64_vae3_write },
3457     REGINFO_SENTINEL
3458 };
3459
3460 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
3461 {
3462     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3463      * but the AArch32 CTR has its own reginfo struct)
3464      */
3465     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3466         return CP_ACCESS_TRAP;
3467     }
3468     return CP_ACCESS_OK;
3469 }
3470
3471 static const ARMCPRegInfo debug_cp_reginfo[] = {
3472     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3473      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3474      * unlike DBGDRAR it is never accessible from EL0.
3475      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3476      * accessor.
3477      */
3478     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3479       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3480     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3481       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3482       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3483     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3484       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3485     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3486     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3487       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3488       .access = PL1_RW,
3489       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3490       .resetvalue = 0 },
3491     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3492      * We don't implement the configurable EL0 access.
3493      */
3494     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3495       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3496       .type = ARM_CP_ALIAS,
3497       .access = PL1_R,
3498       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3499     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
3500     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3501       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3502       .access = PL1_W, .type = ARM_CP_NOP },
3503     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3504     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3505       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3506       .access = PL1_RW, .type = ARM_CP_NOP },
3507     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3508      * implement vector catch debug events yet.
3509      */
3510     { .name = "DBGVCR",
3511       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3512       .access = PL1_RW, .type = ARM_CP_NOP },
3513     REGINFO_SENTINEL
3514 };
3515
3516 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3517     /* 64 bit access versions of the (dummy) debug registers */
3518     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3519       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3520     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3521       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3522     REGINFO_SENTINEL
3523 };
3524
3525 void hw_watchpoint_update(ARMCPU *cpu, int n)
3526 {
3527     CPUARMState *env = &cpu->env;
3528     vaddr len = 0;
3529     vaddr wvr = env->cp15.dbgwvr[n];
3530     uint64_t wcr = env->cp15.dbgwcr[n];
3531     int mask;
3532     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3533
3534     if (env->cpu_watchpoint[n]) {
3535         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3536         env->cpu_watchpoint[n] = NULL;
3537     }
3538
3539     if (!extract64(wcr, 0, 1)) {
3540         /* E bit clear : watchpoint disabled */
3541         return;
3542     }
3543
3544     switch (extract64(wcr, 3, 2)) {
3545     case 0:
3546         /* LSC 00 is reserved and must behave as if the wp is disabled */
3547         return;
3548     case 1:
3549         flags |= BP_MEM_READ;
3550         break;
3551     case 2:
3552         flags |= BP_MEM_WRITE;
3553         break;
3554     case 3:
3555         flags |= BP_MEM_ACCESS;
3556         break;
3557     }
3558
3559     /* Attempts to use both MASK and BAS fields simultaneously are
3560      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3561      * thus generating a watchpoint for every byte in the masked region.
3562      */
3563     mask = extract64(wcr, 24, 4);
3564     if (mask == 1 || mask == 2) {
3565         /* Reserved values of MASK; we must act as if the mask value was
3566          * some non-reserved value, or as if the watchpoint were disabled.
3567          * We choose the latter.
3568          */
3569         return;
3570     } else if (mask) {
3571         /* Watchpoint covers an aligned area up to 2GB in size */
3572         len = 1ULL << mask;
3573         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3574          * whether the watchpoint fires when the unmasked bits match; we opt
3575          * to generate the exceptions.
3576          */
3577         wvr &= ~(len - 1);
3578     } else {
3579         /* Watchpoint covers bytes defined by the byte address select bits */
3580         int bas = extract64(wcr, 5, 8);
3581         int basstart;
3582
3583         if (bas == 0) {
3584             /* This must act as if the watchpoint is disabled */
3585             return;
3586         }
3587
3588         if (extract64(wvr, 2, 1)) {
3589             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3590              * ignored, and BAS[3:0] define which bytes to watch.
3591              */
3592             bas &= 0xf;
3593         }
3594         /* The BAS bits are supposed to be programmed to indicate a contiguous
3595          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3596          * we fire for each byte in the word/doubleword addressed by the WVR.
3597          * We choose to ignore any non-zero bits after the first range of 1s.
3598          */
3599         basstart = ctz32(bas);
3600         len = cto32(bas >> basstart);
3601         wvr += basstart;
3602     }
3603
3604     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3605                           &env->cpu_watchpoint[n]);
3606 }
3607
3608 void hw_watchpoint_update_all(ARMCPU *cpu)
3609 {
3610     int i;
3611     CPUARMState *env = &cpu->env;
3612
3613     /* Completely clear out existing QEMU watchpoints and our array, to
3614      * avoid possible stale entries following migration load.
3615      */
3616     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3617     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3618
3619     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3620         hw_watchpoint_update(cpu, i);
3621     }
3622 }
3623
3624 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3625                          uint64_t value)
3626 {
3627     ARMCPU *cpu = arm_env_get_cpu(env);
3628     int i = ri->crm;
3629
3630     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3631      * register reads and behaves as if values written are sign extended.
3632      * Bits [1:0] are RES0.
3633      */
3634     value = sextract64(value, 0, 49) & ~3ULL;
3635
3636     raw_write(env, ri, value);
3637     hw_watchpoint_update(cpu, i);
3638 }
3639
3640 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3641                          uint64_t value)
3642 {
3643     ARMCPU *cpu = arm_env_get_cpu(env);
3644     int i = ri->crm;
3645
3646     raw_write(env, ri, value);
3647     hw_watchpoint_update(cpu, i);
3648 }
3649
3650 void hw_breakpoint_update(ARMCPU *cpu, int n)
3651 {
3652     CPUARMState *env = &cpu->env;
3653     uint64_t bvr = env->cp15.dbgbvr[n];
3654     uint64_t bcr = env->cp15.dbgbcr[n];
3655     vaddr addr;
3656     int bt;
3657     int flags = BP_CPU;
3658
3659     if (env->cpu_breakpoint[n]) {
3660         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3661         env->cpu_breakpoint[n] = NULL;
3662     }
3663
3664     if (!extract64(bcr, 0, 1)) {
3665         /* E bit clear : watchpoint disabled */
3666         return;
3667     }
3668
3669     bt = extract64(bcr, 20, 4);
3670
3671     switch (bt) {
3672     case 4: /* unlinked address mismatch (reserved if AArch64) */
3673     case 5: /* linked address mismatch (reserved if AArch64) */
3674         qemu_log_mask(LOG_UNIMP,
3675                       "arm: address mismatch breakpoint types not implemented");
3676         return;
3677     case 0: /* unlinked address match */
3678     case 1: /* linked address match */
3679     {
3680         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3681          * we behave as if the register was sign extended. Bits [1:0] are
3682          * RES0. The BAS field is used to allow setting breakpoints on 16
3683          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3684          * a bp will fire if the addresses covered by the bp and the addresses
3685          * covered by the insn overlap but the insn doesn't start at the
3686          * start of the bp address range. We choose to require the insn and
3687          * the bp to have the same address. The constraints on writing to
3688          * BAS enforced in dbgbcr_write mean we have only four cases:
3689          *  0b0000  => no breakpoint
3690          *  0b0011  => breakpoint on addr
3691          *  0b1100  => breakpoint on addr + 2
3692          *  0b1111  => breakpoint on addr
3693          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3694          */
3695         int bas = extract64(bcr, 5, 4);
3696         addr = sextract64(bvr, 0, 49) & ~3ULL;
3697         if (bas == 0) {
3698             return;
3699         }
3700         if (bas == 0xc) {
3701             addr += 2;
3702         }
3703         break;
3704     }
3705     case 2: /* unlinked context ID match */
3706     case 8: /* unlinked VMID match (reserved if no EL2) */
3707     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3708         qemu_log_mask(LOG_UNIMP,
3709                       "arm: unlinked context breakpoint types not implemented");
3710         return;
3711     case 9: /* linked VMID match (reserved if no EL2) */
3712     case 11: /* linked context ID and VMID match (reserved if no EL2) */
3713     case 3: /* linked context ID match */
3714     default:
3715         /* We must generate no events for Linked context matches (unless
3716          * they are linked to by some other bp/wp, which is handled in
3717          * updates for the linking bp/wp). We choose to also generate no events
3718          * for reserved values.
3719          */
3720         return;
3721     }
3722
3723     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3724 }
3725
3726 void hw_breakpoint_update_all(ARMCPU *cpu)
3727 {
3728     int i;
3729     CPUARMState *env = &cpu->env;
3730
3731     /* Completely clear out existing QEMU breakpoints and our array, to
3732      * avoid possible stale entries following migration load.
3733      */
3734     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3735     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3736
3737     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3738         hw_breakpoint_update(cpu, i);
3739     }
3740 }
3741
3742 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3743                          uint64_t value)
3744 {
3745     ARMCPU *cpu = arm_env_get_cpu(env);
3746     int i = ri->crm;
3747
3748     raw_write(env, ri, value);
3749     hw_breakpoint_update(cpu, i);
3750 }
3751
3752 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3753                          uint64_t value)
3754 {
3755     ARMCPU *cpu = arm_env_get_cpu(env);
3756     int i = ri->crm;
3757
3758     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3759      * copy of BAS[0].
3760      */
3761     value = deposit64(value, 6, 1, extract64(value, 5, 1));
3762     value = deposit64(value, 8, 1, extract64(value, 7, 1));
3763
3764     raw_write(env, ri, value);
3765     hw_breakpoint_update(cpu, i);
3766 }
3767
3768 static void define_debug_regs(ARMCPU *cpu)
3769 {
3770     /* Define v7 and v8 architectural debug registers.
3771      * These are just dummy implementations for now.
3772      */
3773     int i;
3774     int wrps, brps, ctx_cmps;
3775     ARMCPRegInfo dbgdidr = {
3776         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3777         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3778     };
3779
3780     /* Note that all these register fields hold "number of Xs minus 1". */
3781     brps = extract32(cpu->dbgdidr, 24, 4);
3782     wrps = extract32(cpu->dbgdidr, 28, 4);
3783     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3784
3785     assert(ctx_cmps <= brps);
3786
3787     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3788      * of the debug registers such as number of breakpoints;
3789      * check that if they both exist then they agree.
3790      */
3791     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3792         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3793         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3794         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3795     }
3796
3797     define_one_arm_cp_reg(cpu, &dbgdidr);
3798     define_arm_cp_regs(cpu, debug_cp_reginfo);
3799
3800     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3801         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3802     }
3803
3804     for (i = 0; i < brps + 1; i++) {
3805         ARMCPRegInfo dbgregs[] = {
3806             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3807               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3808               .access = PL1_RW,
3809               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3810               .writefn = dbgbvr_write, .raw_writefn = raw_write
3811             },
3812             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3813               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3814               .access = PL1_RW,
3815               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3816               .writefn = dbgbcr_write, .raw_writefn = raw_write
3817             },
3818             REGINFO_SENTINEL
3819         };
3820         define_arm_cp_regs(cpu, dbgregs);
3821     }
3822
3823     for (i = 0; i < wrps + 1; i++) {
3824         ARMCPRegInfo dbgregs[] = {
3825             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
3826               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
3827               .access = PL1_RW,
3828               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
3829               .writefn = dbgwvr_write, .raw_writefn = raw_write
3830             },
3831             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
3832               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
3833               .access = PL1_RW,
3834               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
3835               .writefn = dbgwcr_write, .raw_writefn = raw_write
3836             },
3837             REGINFO_SENTINEL
3838         };
3839         define_arm_cp_regs(cpu, dbgregs);
3840     }
3841 }
3842
3843 void register_cp_regs_for_features(ARMCPU *cpu)
3844 {
3845     /* Register all the coprocessor registers based on feature bits */
3846     CPUARMState *env = &cpu->env;
3847     if (arm_feature(env, ARM_FEATURE_M)) {
3848         /* M profile has no coprocessor registers */
3849         return;
3850     }
3851
3852     define_arm_cp_regs(cpu, cp_reginfo);
3853     if (!arm_feature(env, ARM_FEATURE_V8)) {
3854         /* Must go early as it is full of wildcards that may be
3855          * overridden by later definitions.
3856          */
3857         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
3858     }
3859
3860     if (arm_feature(env, ARM_FEATURE_V6)) {
3861         /* The ID registers all have impdef reset values */
3862         ARMCPRegInfo v6_idregs[] = {
3863             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
3864               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3865               .access = PL1_R, .type = ARM_CP_CONST,
3866               .resetvalue = cpu->id_pfr0 },
3867             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
3868               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
3869               .access = PL1_R, .type = ARM_CP_CONST,
3870               .resetvalue = cpu->id_pfr1 },
3871             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
3872               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
3873               .access = PL1_R, .type = ARM_CP_CONST,
3874               .resetvalue = cpu->id_dfr0 },
3875             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
3876               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
3877               .access = PL1_R, .type = ARM_CP_CONST,
3878               .resetvalue = cpu->id_afr0 },
3879             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
3880               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
3881               .access = PL1_R, .type = ARM_CP_CONST,
3882               .resetvalue = cpu->id_mmfr0 },
3883             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
3884               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
3885               .access = PL1_R, .type = ARM_CP_CONST,
3886               .resetvalue = cpu->id_mmfr1 },
3887             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
3888               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
3889               .access = PL1_R, .type = ARM_CP_CONST,
3890               .resetvalue = cpu->id_mmfr2 },
3891             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
3892               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
3893               .access = PL1_R, .type = ARM_CP_CONST,
3894               .resetvalue = cpu->id_mmfr3 },
3895             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
3896               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
3897               .access = PL1_R, .type = ARM_CP_CONST,
3898               .resetvalue = cpu->id_isar0 },
3899             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
3900               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
3901               .access = PL1_R, .type = ARM_CP_CONST,
3902               .resetvalue = cpu->id_isar1 },
3903             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
3904               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3905               .access = PL1_R, .type = ARM_CP_CONST,
3906               .resetvalue = cpu->id_isar2 },
3907             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
3908               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
3909               .access = PL1_R, .type = ARM_CP_CONST,
3910               .resetvalue = cpu->id_isar3 },
3911             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
3912               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
3913               .access = PL1_R, .type = ARM_CP_CONST,
3914               .resetvalue = cpu->id_isar4 },
3915             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
3916               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
3917               .access = PL1_R, .type = ARM_CP_CONST,
3918               .resetvalue = cpu->id_isar5 },
3919             /* 6..7 are as yet unallocated and must RAZ */
3920             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
3921               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
3922               .resetvalue = 0 },
3923             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
3924               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
3925               .resetvalue = 0 },
3926             REGINFO_SENTINEL
3927         };
3928         define_arm_cp_regs(cpu, v6_idregs);
3929         define_arm_cp_regs(cpu, v6_cp_reginfo);
3930     } else {
3931         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
3932     }
3933     if (arm_feature(env, ARM_FEATURE_V6K)) {
3934         define_arm_cp_regs(cpu, v6k_cp_reginfo);
3935     }
3936     if (arm_feature(env, ARM_FEATURE_V7MP) &&
3937         !arm_feature(env, ARM_FEATURE_MPU)) {
3938         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
3939     }
3940     if (arm_feature(env, ARM_FEATURE_V7)) {
3941         /* v7 performance monitor control register: same implementor
3942          * field as main ID register, and we implement only the cycle
3943          * count register.
3944          */
3945 #ifndef CONFIG_USER_ONLY
3946         ARMCPRegInfo pmcr = {
3947             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
3948             .access = PL0_RW,
3949             .type = ARM_CP_IO | ARM_CP_ALIAS,
3950             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
3951             .accessfn = pmreg_access, .writefn = pmcr_write,
3952             .raw_writefn = raw_write,
3953         };
3954         ARMCPRegInfo pmcr64 = {
3955             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
3956             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
3957             .access = PL0_RW, .accessfn = pmreg_access,
3958             .type = ARM_CP_IO,
3959             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
3960             .resetvalue = cpu->midr & 0xff000000,
3961             .writefn = pmcr_write, .raw_writefn = raw_write,
3962         };
3963         define_one_arm_cp_reg(cpu, &pmcr);
3964         define_one_arm_cp_reg(cpu, &pmcr64);
3965 #endif
3966         ARMCPRegInfo clidr = {
3967             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
3968             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
3969             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
3970         };
3971         define_one_arm_cp_reg(cpu, &clidr);
3972         define_arm_cp_regs(cpu, v7_cp_reginfo);
3973         define_debug_regs(cpu);
3974     } else {
3975         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
3976     }
3977     if (arm_feature(env, ARM_FEATURE_V8)) {
3978         /* AArch64 ID registers, which all have impdef reset values */
3979         ARMCPRegInfo v8_idregs[] = {
3980             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
3981               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
3982               .access = PL1_R, .type = ARM_CP_CONST,
3983               .resetvalue = cpu->id_aa64pfr0 },
3984             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
3985               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
3986               .access = PL1_R, .type = ARM_CP_CONST,
3987               .resetvalue = cpu->id_aa64pfr1},
3988             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
3989               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
3990               .access = PL1_R, .type = ARM_CP_CONST,
3991               /* We mask out the PMUVer field, because we don't currently
3992                * implement the PMU. Not advertising it prevents the guest
3993                * from trying to use it and getting UNDEFs on registers we
3994                * don't implement.
3995                */
3996               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
3997             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
3998               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
3999               .access = PL1_R, .type = ARM_CP_CONST,
4000               .resetvalue = cpu->id_aa64dfr1 },
4001             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4002               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4003               .access = PL1_R, .type = ARM_CP_CONST,
4004               .resetvalue = cpu->id_aa64afr0 },
4005             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4006               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4007               .access = PL1_R, .type = ARM_CP_CONST,
4008               .resetvalue = cpu->id_aa64afr1 },
4009             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4010               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4011               .access = PL1_R, .type = ARM_CP_CONST,
4012               .resetvalue = cpu->id_aa64isar0 },
4013             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4014               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4015               .access = PL1_R, .type = ARM_CP_CONST,
4016               .resetvalue = cpu->id_aa64isar1 },
4017             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4018               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4019               .access = PL1_R, .type = ARM_CP_CONST,
4020               .resetvalue = cpu->id_aa64mmfr0 },
4021             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4022               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4023               .access = PL1_R, .type = ARM_CP_CONST,
4024               .resetvalue = cpu->id_aa64mmfr1 },
4025             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4026               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4027               .access = PL1_R, .type = ARM_CP_CONST,
4028               .resetvalue = cpu->mvfr0 },
4029             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4030               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4031               .access = PL1_R, .type = ARM_CP_CONST,
4032               .resetvalue = cpu->mvfr1 },
4033             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4034               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4035               .access = PL1_R, .type = ARM_CP_CONST,
4036               .resetvalue = cpu->mvfr2 },
4037             REGINFO_SENTINEL
4038         };
4039         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4040         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4041             !arm_feature(env, ARM_FEATURE_EL2)) {
4042             ARMCPRegInfo rvbar = {
4043                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4044                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4045                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4046             };
4047             define_one_arm_cp_reg(cpu, &rvbar);
4048         }
4049         define_arm_cp_regs(cpu, v8_idregs);
4050         define_arm_cp_regs(cpu, v8_cp_reginfo);
4051     }
4052     if (arm_feature(env, ARM_FEATURE_EL2)) {
4053         define_arm_cp_regs(cpu, el2_cp_reginfo);
4054         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4055         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4056             ARMCPRegInfo rvbar = {
4057                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4058                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4059                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4060             };
4061             define_one_arm_cp_reg(cpu, &rvbar);
4062         }
4063     } else {
4064         /* If EL2 is missing but higher ELs are enabled, we need to
4065          * register the no_el2 reginfos.
4066          */
4067         if (arm_feature(env, ARM_FEATURE_EL3)) {
4068             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4069         }
4070     }
4071     if (arm_feature(env, ARM_FEATURE_EL3)) {
4072         define_arm_cp_regs(cpu, el3_cp_reginfo);
4073         ARMCPRegInfo rvbar = {
4074             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4075             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4076             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4077         };
4078         define_one_arm_cp_reg(cpu, &rvbar);
4079     }
4080     if (arm_feature(env, ARM_FEATURE_MPU)) {
4081         if (arm_feature(env, ARM_FEATURE_V6)) {
4082             /* PMSAv6 not implemented */
4083             assert(arm_feature(env, ARM_FEATURE_V7));
4084             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4085             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4086         } else {
4087             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4088         }
4089     } else {
4090         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4091         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4092     }
4093     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4094         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4095     }
4096     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4097         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4098     }
4099     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4100         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4101     }
4102     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4103         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4104     }
4105     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4106         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4107     }
4108     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4109         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4110     }
4111     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4112         define_arm_cp_regs(cpu, omap_cp_reginfo);
4113     }
4114     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4115         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4116     }
4117     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4118         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4119     }
4120     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4121         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4122     }
4123     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4124         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4125     }
4126     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4127      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4128      * be read-only (ie write causes UNDEF exception).
4129      */
4130     {
4131         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4132             /* Pre-v8 MIDR space.
4133              * Note that the MIDR isn't a simple constant register because
4134              * of the TI925 behaviour where writes to another register can
4135              * cause the MIDR value to change.
4136              *
4137              * Unimplemented registers in the c15 0 0 0 space default to
4138              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4139              * and friends override accordingly.
4140              */
4141             { .name = "MIDR",
4142               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4143               .access = PL1_R, .resetvalue = cpu->midr,
4144               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4145               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4146               .type = ARM_CP_OVERRIDE },
4147             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4148             { .name = "DUMMY",
4149               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4150               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4151             { .name = "DUMMY",
4152               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4153               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4154             { .name = "DUMMY",
4155               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4156               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4157             { .name = "DUMMY",
4158               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4159               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4160             { .name = "DUMMY",
4161               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4162               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4163             REGINFO_SENTINEL
4164         };
4165         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4166             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4167               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4168               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
4169             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4170             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4171               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4172               .access = PL1_R, .resetvalue = cpu->midr },
4173             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4174               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4175               .access = PL1_R, .resetvalue = cpu->midr },
4176             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4177               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4178               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4179             REGINFO_SENTINEL
4180         };
4181         ARMCPRegInfo id_cp_reginfo[] = {
4182             /* These are common to v8 and pre-v8 */
4183             { .name = "CTR",
4184               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4185               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4186             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4187               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4188               .access = PL0_R, .accessfn = ctr_el0_access,
4189               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4190             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4191             { .name = "TCMTR",
4192               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4193               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4194             REGINFO_SENTINEL
4195         };
4196         /* TLBTR is specific to VMSA */
4197         ARMCPRegInfo id_tlbtr_reginfo = {
4198               .name = "TLBTR",
4199               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4200               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4201         };
4202         /* MPUIR is specific to PMSA V6+ */
4203         ARMCPRegInfo id_mpuir_reginfo = {
4204               .name = "MPUIR",
4205               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4206               .access = PL1_R, .type = ARM_CP_CONST,
4207               .resetvalue = cpu->pmsav7_dregion << 8
4208         };
4209         ARMCPRegInfo crn0_wi_reginfo = {
4210             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4211             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4212             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4213         };
4214         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4215             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4216             ARMCPRegInfo *r;
4217             /* Register the blanket "writes ignored" value first to cover the
4218              * whole space. Then update the specific ID registers to allow write
4219              * access, so that they ignore writes rather than causing them to
4220              * UNDEF.
4221              */
4222             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4223             for (r = id_pre_v8_midr_cp_reginfo;
4224                  r->type != ARM_CP_SENTINEL; r++) {
4225                 r->access = PL1_RW;
4226             }
4227             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4228                 r->access = PL1_RW;
4229             }
4230             id_tlbtr_reginfo.access = PL1_RW;
4231             id_tlbtr_reginfo.access = PL1_RW;
4232         }
4233         if (arm_feature(env, ARM_FEATURE_V8)) {
4234             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4235         } else {
4236             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4237         }
4238         define_arm_cp_regs(cpu, id_cp_reginfo);
4239         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4240             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4241         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4242             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4243         }
4244     }
4245
4246     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4247         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4248     }
4249
4250     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4251         ARMCPRegInfo auxcr_reginfo[] = {
4252             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4253               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4254               .access = PL1_RW, .type = ARM_CP_CONST,
4255               .resetvalue = cpu->reset_auxcr },
4256             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4257               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4258               .access = PL2_RW, .type = ARM_CP_CONST,
4259               .resetvalue = 0 },
4260             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4261               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4262               .access = PL3_RW, .type = ARM_CP_CONST,
4263               .resetvalue = 0 },
4264             REGINFO_SENTINEL
4265         };
4266         define_arm_cp_regs(cpu, auxcr_reginfo);
4267     }
4268
4269     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4270         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4271             /* 32 bit view is [31:18] 0...0 [43:32]. */
4272             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4273                 | extract64(cpu->reset_cbar, 32, 12);
4274             ARMCPRegInfo cbar_reginfo[] = {
4275                 { .name = "CBAR",
4276                   .type = ARM_CP_CONST,
4277                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4278                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4279                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4280                   .type = ARM_CP_CONST,
4281                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4282                   .access = PL1_R, .resetvalue = cbar32 },
4283                 REGINFO_SENTINEL
4284             };
4285             /* We don't implement a r/w 64 bit CBAR currently */
4286             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4287             define_arm_cp_regs(cpu, cbar_reginfo);
4288         } else {
4289             ARMCPRegInfo cbar = {
4290                 .name = "CBAR",
4291                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4292                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4293                 .fieldoffset = offsetof(CPUARMState,
4294                                         cp15.c15_config_base_address)
4295             };
4296             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4297                 cbar.access = PL1_R;
4298                 cbar.fieldoffset = 0;
4299                 cbar.type = ARM_CP_CONST;
4300             }
4301             define_one_arm_cp_reg(cpu, &cbar);
4302         }
4303     }
4304
4305     /* Generic registers whose values depend on the implementation */
4306     {
4307         ARMCPRegInfo sctlr = {
4308             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4309             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4310             .access = PL1_RW,
4311             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4312                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4313             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4314             .raw_writefn = raw_write,
4315         };
4316         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4317             /* Normally we would always end the TB on an SCTLR write, but Linux
4318              * arch/arm/mach-pxa/sleep.S expects two instructions following
4319              * an MMU enable to execute from cache.  Imitate this behaviour.
4320              */
4321             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4322         }
4323         define_one_arm_cp_reg(cpu, &sctlr);
4324     }
4325 }
4326
4327 ARMCPU *cpu_arm_init(const char *cpu_model)
4328 {
4329     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4330 }
4331
4332 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4333 {
4334     CPUState *cs = CPU(cpu);
4335     CPUARMState *env = &cpu->env;
4336
4337     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4338         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4339                                  aarch64_fpu_gdb_set_reg,
4340                                  34, "aarch64-fpu.xml", 0);
4341     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4342         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4343                                  51, "arm-neon.xml", 0);
4344     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4345         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4346                                  35, "arm-vfp3.xml", 0);
4347     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4348         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4349                                  19, "arm-vfp.xml", 0);
4350     }
4351 }
4352
4353 /* Sort alphabetically by type name, except for "any". */
4354 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4355 {
4356     ObjectClass *class_a = (ObjectClass *)a;
4357     ObjectClass *class_b = (ObjectClass *)b;
4358     const char *name_a, *name_b;
4359
4360     name_a = object_class_get_name(class_a);
4361     name_b = object_class_get_name(class_b);
4362     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4363         return 1;
4364     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4365         return -1;
4366     } else {
4367         return strcmp(name_a, name_b);
4368     }
4369 }
4370
4371 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4372 {
4373     ObjectClass *oc = data;
4374     CPUListState *s = user_data;
4375     const char *typename;
4376     char *name;
4377
4378     typename = object_class_get_name(oc);
4379     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4380     (*s->cpu_fprintf)(s->file, "  %s\n",
4381                       name);
4382     g_free(name);
4383 }
4384
4385 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4386 {
4387     CPUListState s = {
4388         .file = f,
4389         .cpu_fprintf = cpu_fprintf,
4390     };
4391     GSList *list;
4392
4393     list = object_class_get_list(TYPE_ARM_CPU, false);
4394     list = g_slist_sort(list, arm_cpu_list_compare);
4395     (*cpu_fprintf)(f, "Available CPUs:\n");
4396     g_slist_foreach(list, arm_cpu_list_entry, &s);
4397     g_slist_free(list);
4398 #ifdef CONFIG_KVM
4399     /* The 'host' CPU type is dynamically registered only if KVM is
4400      * enabled, so we have to special-case it here:
4401      */
4402     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
4403 #endif
4404 }
4405
4406 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4407 {
4408     ObjectClass *oc = data;
4409     CpuDefinitionInfoList **cpu_list = user_data;
4410     CpuDefinitionInfoList *entry;
4411     CpuDefinitionInfo *info;
4412     const char *typename;
4413
4414     typename = object_class_get_name(oc);
4415     info = g_malloc0(sizeof(*info));
4416     info->name = g_strndup(typename,
4417                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
4418
4419     entry = g_malloc0(sizeof(*entry));
4420     entry->value = info;
4421     entry->next = *cpu_list;
4422     *cpu_list = entry;
4423 }
4424
4425 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4426 {
4427     CpuDefinitionInfoList *cpu_list = NULL;
4428     GSList *list;
4429
4430     list = object_class_get_list(TYPE_ARM_CPU, false);
4431     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4432     g_slist_free(list);
4433
4434     return cpu_list;
4435 }
4436
4437 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4438                                    void *opaque, int state, int secstate,
4439                                    int crm, int opc1, int opc2)
4440 {
4441     /* Private utility function for define_one_arm_cp_reg_with_opaque():
4442      * add a single reginfo struct to the hash table.
4443      */
4444     uint32_t *key = g_new(uint32_t, 1);
4445     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4446     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4447     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4448
4449     /* Reset the secure state to the specific incoming state.  This is
4450      * necessary as the register may have been defined with both states.
4451      */
4452     r2->secure = secstate;
4453
4454     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4455         /* Register is banked (using both entries in array).
4456          * Overwriting fieldoffset as the array is only used to define
4457          * banked registers but later only fieldoffset is used.
4458          */
4459         r2->fieldoffset = r->bank_fieldoffsets[ns];
4460     }
4461
4462     if (state == ARM_CP_STATE_AA32) {
4463         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4464             /* If the register is banked then we don't need to migrate or
4465              * reset the 32-bit instance in certain cases:
4466              *
4467              * 1) If the register has both 32-bit and 64-bit instances then we
4468              *    can count on the 64-bit instance taking care of the
4469              *    non-secure bank.
4470              * 2) If ARMv8 is enabled then we can count on a 64-bit version
4471              *    taking care of the secure bank.  This requires that separate
4472              *    32 and 64-bit definitions are provided.
4473              */
4474             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4475                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4476                 r2->type |= ARM_CP_ALIAS;
4477             }
4478         } else if ((secstate != r->secure) && !ns) {
4479             /* The register is not banked so we only want to allow migration of
4480              * the non-secure instance.
4481              */
4482             r2->type |= ARM_CP_ALIAS;
4483         }
4484
4485         if (r->state == ARM_CP_STATE_BOTH) {
4486             /* We assume it is a cp15 register if the .cp field is left unset.
4487              */
4488             if (r2->cp == 0) {
4489                 r2->cp = 15;
4490             }
4491
4492 #ifdef HOST_WORDS_BIGENDIAN
4493             if (r2->fieldoffset) {
4494                 r2->fieldoffset += sizeof(uint32_t);
4495             }
4496 #endif
4497         }
4498     }
4499     if (state == ARM_CP_STATE_AA64) {
4500         /* To allow abbreviation of ARMCPRegInfo
4501          * definitions, we treat cp == 0 as equivalent to
4502          * the value for "standard guest-visible sysreg".
4503          * STATE_BOTH definitions are also always "standard
4504          * sysreg" in their AArch64 view (the .cp value may
4505          * be non-zero for the benefit of the AArch32 view).
4506          */
4507         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4508             r2->cp = CP_REG_ARM64_SYSREG_CP;
4509         }
4510         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4511                                   r2->opc0, opc1, opc2);
4512     } else {
4513         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4514     }
4515     if (opaque) {
4516         r2->opaque = opaque;
4517     }
4518     /* reginfo passed to helpers is correct for the actual access,
4519      * and is never ARM_CP_STATE_BOTH:
4520      */
4521     r2->state = state;
4522     /* Make sure reginfo passed to helpers for wildcarded regs
4523      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4524      */
4525     r2->crm = crm;
4526     r2->opc1 = opc1;
4527     r2->opc2 = opc2;
4528     /* By convention, for wildcarded registers only the first
4529      * entry is used for migration; the others are marked as
4530      * ALIAS so we don't try to transfer the register
4531      * multiple times. Special registers (ie NOP/WFI) are
4532      * never migratable and not even raw-accessible.
4533      */
4534     if ((r->type & ARM_CP_SPECIAL)) {
4535         r2->type |= ARM_CP_NO_RAW;
4536     }
4537     if (((r->crm == CP_ANY) && crm != 0) ||
4538         ((r->opc1 == CP_ANY) && opc1 != 0) ||
4539         ((r->opc2 == CP_ANY) && opc2 != 0)) {
4540         r2->type |= ARM_CP_ALIAS;
4541     }
4542
4543     /* Check that raw accesses are either forbidden or handled. Note that
4544      * we can't assert this earlier because the setup of fieldoffset for
4545      * banked registers has to be done first.
4546      */
4547     if (!(r2->type & ARM_CP_NO_RAW)) {
4548         assert(!raw_accessors_invalid(r2));
4549     }
4550
4551     /* Overriding of an existing definition must be explicitly
4552      * requested.
4553      */
4554     if (!(r->type & ARM_CP_OVERRIDE)) {
4555         ARMCPRegInfo *oldreg;
4556         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4557         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4558             fprintf(stderr, "Register redefined: cp=%d %d bit "
4559                     "crn=%d crm=%d opc1=%d opc2=%d, "
4560                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4561                     r2->crn, r2->crm, r2->opc1, r2->opc2,
4562                     oldreg->name, r2->name);
4563             g_assert_not_reached();
4564         }
4565     }
4566     g_hash_table_insert(cpu->cp_regs, key, r2);
4567 }
4568
4569
4570 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4571                                        const ARMCPRegInfo *r, void *opaque)
4572 {
4573     /* Define implementations of coprocessor registers.
4574      * We store these in a hashtable because typically
4575      * there are less than 150 registers in a space which
4576      * is 16*16*16*8*8 = 262144 in size.
4577      * Wildcarding is supported for the crm, opc1 and opc2 fields.
4578      * If a register is defined twice then the second definition is
4579      * used, so this can be used to define some generic registers and
4580      * then override them with implementation specific variations.
4581      * At least one of the original and the second definition should
4582      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4583      * against accidental use.
4584      *
4585      * The state field defines whether the register is to be
4586      * visible in the AArch32 or AArch64 execution state. If the
4587      * state is set to ARM_CP_STATE_BOTH then we synthesise a
4588      * reginfo structure for the AArch32 view, which sees the lower
4589      * 32 bits of the 64 bit register.
4590      *
4591      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4592      * be wildcarded. AArch64 registers are always considered to be 64
4593      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4594      * the register, if any.
4595      */
4596     int crm, opc1, opc2, state;
4597     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4598     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4599     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4600     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4601     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4602     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4603     /* 64 bit registers have only CRm and Opc1 fields */
4604     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4605     /* op0 only exists in the AArch64 encodings */
4606     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4607     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4608     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4609     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4610      * encodes a minimum access level for the register. We roll this
4611      * runtime check into our general permission check code, so check
4612      * here that the reginfo's specified permissions are strict enough
4613      * to encompass the generic architectural permission check.
4614      */
4615     if (r->state != ARM_CP_STATE_AA32) {
4616         int mask = 0;
4617         switch (r->opc1) {
4618         case 0: case 1: case 2:
4619             /* min_EL EL1 */
4620             mask = PL1_RW;
4621             break;
4622         case 3:
4623             /* min_EL EL0 */
4624             mask = PL0_RW;
4625             break;
4626         case 4:
4627             /* min_EL EL2 */
4628             mask = PL2_RW;
4629             break;
4630         case 5:
4631             /* unallocated encoding, so not possible */
4632             assert(false);
4633             break;
4634         case 6:
4635             /* min_EL EL3 */
4636             mask = PL3_RW;
4637             break;
4638         case 7:
4639             /* min_EL EL1, secure mode only (we don't check the latter) */
4640             mask = PL1_RW;
4641             break;
4642         default:
4643             /* broken reginfo with out-of-range opc1 */
4644             assert(false);
4645             break;
4646         }
4647         /* assert our permissions are not too lax (stricter is fine) */
4648         assert((r->access & ~mask) == 0);
4649     }
4650
4651     /* Check that the register definition has enough info to handle
4652      * reads and writes if they are permitted.
4653      */
4654     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4655         if (r->access & PL3_R) {
4656             assert((r->fieldoffset ||
4657                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4658                    r->readfn);
4659         }
4660         if (r->access & PL3_W) {
4661             assert((r->fieldoffset ||
4662                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4663                    r->writefn);
4664         }
4665     }
4666     /* Bad type field probably means missing sentinel at end of reg list */
4667     assert(cptype_valid(r->type));
4668     for (crm = crmmin; crm <= crmmax; crm++) {
4669         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
4670             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
4671                 for (state = ARM_CP_STATE_AA32;
4672                      state <= ARM_CP_STATE_AA64; state++) {
4673                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
4674                         continue;
4675                     }
4676                     if (state == ARM_CP_STATE_AA32) {
4677                         /* Under AArch32 CP registers can be common
4678                          * (same for secure and non-secure world) or banked.
4679                          */
4680                         switch (r->secure) {
4681                         case ARM_CP_SECSTATE_S:
4682                         case ARM_CP_SECSTATE_NS:
4683                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4684                                                    r->secure, crm, opc1, opc2);
4685                             break;
4686                         default:
4687                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4688                                                    ARM_CP_SECSTATE_S,
4689                                                    crm, opc1, opc2);
4690                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4691                                                    ARM_CP_SECSTATE_NS,
4692                                                    crm, opc1, opc2);
4693                             break;
4694                         }
4695                     } else {
4696                         /* AArch64 registers get mapped to non-secure instance
4697                          * of AArch32 */
4698                         add_cpreg_to_hashtable(cpu, r, opaque, state,
4699                                                ARM_CP_SECSTATE_NS,
4700                                                crm, opc1, opc2);
4701                     }
4702                 }
4703             }
4704         }
4705     }
4706 }
4707
4708 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
4709                                     const ARMCPRegInfo *regs, void *opaque)
4710 {
4711     /* Define a whole list of registers */
4712     const ARMCPRegInfo *r;
4713     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
4714         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
4715     }
4716 }
4717
4718 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4719 {
4720     return g_hash_table_lookup(cpregs, &encoded_cp);
4721 }
4722
4723 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
4724                          uint64_t value)
4725 {
4726     /* Helper coprocessor write function for write-ignore registers */
4727 }
4728
4729 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4730 {
4731     /* Helper coprocessor write function for read-as-zero registers */
4732     return 0;
4733 }
4734
4735 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
4736 {
4737     /* Helper coprocessor reset function for do-nothing-on-reset registers */
4738 }
4739
4740 static int bad_mode_switch(CPUARMState *env, int mode)
4741 {
4742     /* Return true if it is not valid for us to switch to
4743      * this CPU mode (ie all the UNPREDICTABLE cases in
4744      * the ARM ARM CPSRWriteByInstr pseudocode).
4745      */
4746     switch (mode) {
4747     case ARM_CPU_MODE_USR:
4748     case ARM_CPU_MODE_SYS:
4749     case ARM_CPU_MODE_SVC:
4750     case ARM_CPU_MODE_ABT:
4751     case ARM_CPU_MODE_UND:
4752     case ARM_CPU_MODE_IRQ:
4753     case ARM_CPU_MODE_FIQ:
4754         return 0;
4755     case ARM_CPU_MODE_MON:
4756         return !arm_is_secure(env);
4757     default:
4758         return 1;
4759     }
4760 }
4761
4762 uint32_t cpsr_read(CPUARMState *env)
4763 {
4764     int ZF;
4765     ZF = (env->ZF == 0);
4766     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
4767         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
4768         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
4769         | ((env->condexec_bits & 0xfc) << 8)
4770         | (env->GE << 16) | (env->daif & CPSR_AIF);
4771 }
4772
4773 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
4774 {
4775     uint32_t changed_daif;
4776
4777     if (mask & CPSR_NZCV) {
4778         env->ZF = (~val) & CPSR_Z;
4779         env->NF = val;
4780         env->CF = (val >> 29) & 1;
4781         env->VF = (val << 3) & 0x80000000;
4782     }
4783     if (mask & CPSR_Q)
4784         env->QF = ((val & CPSR_Q) != 0);
4785     if (mask & CPSR_T)
4786         env->thumb = ((val & CPSR_T) != 0);
4787     if (mask & CPSR_IT_0_1) {
4788         env->condexec_bits &= ~3;
4789         env->condexec_bits |= (val >> 25) & 3;
4790     }
4791     if (mask & CPSR_IT_2_7) {
4792         env->condexec_bits &= 3;
4793         env->condexec_bits |= (val >> 8) & 0xfc;
4794     }
4795     if (mask & CPSR_GE) {
4796         env->GE = (val >> 16) & 0xf;
4797     }
4798
4799     /* In a V7 implementation that includes the security extensions but does
4800      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
4801      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
4802      * bits respectively.
4803      *
4804      * In a V8 implementation, it is permitted for privileged software to
4805      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
4806      */
4807     if (!arm_feature(env, ARM_FEATURE_V8) &&
4808         arm_feature(env, ARM_FEATURE_EL3) &&
4809         !arm_feature(env, ARM_FEATURE_EL2) &&
4810         !arm_is_secure(env)) {
4811
4812         changed_daif = (env->daif ^ val) & mask;
4813
4814         if (changed_daif & CPSR_A) {
4815             /* Check to see if we are allowed to change the masking of async
4816              * abort exceptions from a non-secure state.
4817              */
4818             if (!(env->cp15.scr_el3 & SCR_AW)) {
4819                 qemu_log_mask(LOG_GUEST_ERROR,
4820                               "Ignoring attempt to switch CPSR_A flag from "
4821                               "non-secure world with SCR.AW bit clear\n");
4822                 mask &= ~CPSR_A;
4823             }
4824         }
4825
4826         if (changed_daif & CPSR_F) {
4827             /* Check to see if we are allowed to change the masking of FIQ
4828              * exceptions from a non-secure state.
4829              */
4830             if (!(env->cp15.scr_el3 & SCR_FW)) {
4831                 qemu_log_mask(LOG_GUEST_ERROR,
4832                               "Ignoring attempt to switch CPSR_F flag from "
4833                               "non-secure world with SCR.FW bit clear\n");
4834                 mask &= ~CPSR_F;
4835             }
4836
4837             /* Check whether non-maskable FIQ (NMFI) support is enabled.
4838              * If this bit is set software is not allowed to mask
4839              * FIQs, but is allowed to set CPSR_F to 0.
4840              */
4841             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
4842                 (val & CPSR_F)) {
4843                 qemu_log_mask(LOG_GUEST_ERROR,
4844                               "Ignoring attempt to enable CPSR_F flag "
4845                               "(non-maskable FIQ [NMFI] support enabled)\n");
4846                 mask &= ~CPSR_F;
4847             }
4848         }
4849     }
4850
4851     env->daif &= ~(CPSR_AIF & mask);
4852     env->daif |= val & CPSR_AIF & mask;
4853
4854     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
4855         if (bad_mode_switch(env, val & CPSR_M)) {
4856             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4857              * We choose to ignore the attempt and leave the CPSR M field
4858              * untouched.
4859              */
4860             mask &= ~CPSR_M;
4861         } else {
4862             switch_mode(env, val & CPSR_M);
4863         }
4864     }
4865     mask &= ~CACHED_CPSR_BITS;
4866     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
4867 }
4868
4869 /* Sign/zero extend */
4870 uint32_t HELPER(sxtb16)(uint32_t x)
4871 {
4872     uint32_t res;
4873     res = (uint16_t)(int8_t)x;
4874     res |= (uint32_t)(int8_t)(x >> 16) << 16;
4875     return res;
4876 }
4877
4878 uint32_t HELPER(uxtb16)(uint32_t x)
4879 {
4880     uint32_t res;
4881     res = (uint16_t)(uint8_t)x;
4882     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
4883     return res;
4884 }
4885
4886 uint32_t HELPER(clz)(uint32_t x)
4887 {
4888     return clz32(x);
4889 }
4890
4891 int32_t HELPER(sdiv)(int32_t num, int32_t den)
4892 {
4893     if (den == 0)
4894       return 0;
4895     if (num == INT_MIN && den == -1)
4896       return INT_MIN;
4897     return num / den;
4898 }
4899
4900 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
4901 {
4902     if (den == 0)
4903       return 0;
4904     return num / den;
4905 }
4906
4907 uint32_t HELPER(rbit)(uint32_t x)
4908 {
4909     x =  ((x & 0xff000000) >> 24)
4910        | ((x & 0x00ff0000) >> 8)
4911        | ((x & 0x0000ff00) << 8)
4912        | ((x & 0x000000ff) << 24);
4913     x =  ((x & 0xf0f0f0f0) >> 4)
4914        | ((x & 0x0f0f0f0f) << 4);
4915     x =  ((x & 0x88888888) >> 3)
4916        | ((x & 0x44444444) >> 1)
4917        | ((x & 0x22222222) << 1)
4918        | ((x & 0x11111111) << 3);
4919     return x;
4920 }
4921
4922 #if defined(CONFIG_USER_ONLY)
4923
4924 /* These should probably raise undefined insn exceptions.  */
4925 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4926 {
4927     ARMCPU *cpu = arm_env_get_cpu(env);
4928
4929     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
4930 }
4931
4932 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4933 {
4934     ARMCPU *cpu = arm_env_get_cpu(env);
4935
4936     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
4937     return 0;
4938 }
4939
4940 void switch_mode(CPUARMState *env, int mode)
4941 {
4942     ARMCPU *cpu = arm_env_get_cpu(env);
4943
4944     if (mode != ARM_CPU_MODE_USR) {
4945         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
4946     }
4947 }
4948
4949 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4950 {
4951     ARMCPU *cpu = arm_env_get_cpu(env);
4952
4953     cpu_abort(CPU(cpu), "banked r13 write\n");
4954 }
4955
4956 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4957 {
4958     ARMCPU *cpu = arm_env_get_cpu(env);
4959
4960     cpu_abort(CPU(cpu), "banked r13 read\n");
4961     return 0;
4962 }
4963
4964 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4965                                  uint32_t cur_el, bool secure)
4966 {
4967     return 1;
4968 }
4969
4970 void aarch64_sync_64_to_32(CPUARMState *env)
4971 {
4972     g_assert_not_reached();
4973 }
4974
4975 #else
4976
4977 /* Map CPU modes onto saved register banks.  */
4978 int bank_number(int mode)
4979 {
4980     switch (mode) {
4981     case ARM_CPU_MODE_USR:
4982     case ARM_CPU_MODE_SYS:
4983         return 0;
4984     case ARM_CPU_MODE_SVC:
4985         return 1;
4986     case ARM_CPU_MODE_ABT:
4987         return 2;
4988     case ARM_CPU_MODE_UND:
4989         return 3;
4990     case ARM_CPU_MODE_IRQ:
4991         return 4;
4992     case ARM_CPU_MODE_FIQ:
4993         return 5;
4994     case ARM_CPU_MODE_HYP:
4995         return 6;
4996     case ARM_CPU_MODE_MON:
4997         return 7;
4998     }
4999     g_assert_not_reached();
5000 }
5001
5002 void switch_mode(CPUARMState *env, int mode)
5003 {
5004     int old_mode;
5005     int i;
5006
5007     old_mode = env->uncached_cpsr & CPSR_M;
5008     if (mode == old_mode)
5009         return;
5010
5011     if (old_mode == ARM_CPU_MODE_FIQ) {
5012         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5013         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5014     } else if (mode == ARM_CPU_MODE_FIQ) {
5015         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5016         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5017     }
5018
5019     i = bank_number(old_mode);
5020     env->banked_r13[i] = env->regs[13];
5021     env->banked_r14[i] = env->regs[14];
5022     env->banked_spsr[i] = env->spsr;
5023
5024     i = bank_number(mode);
5025     env->regs[13] = env->banked_r13[i];
5026     env->regs[14] = env->banked_r14[i];
5027     env->spsr = env->banked_spsr[i];
5028 }
5029
5030 /* Physical Interrupt Target EL Lookup Table
5031  *
5032  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5033  *
5034  * The below multi-dimensional table is used for looking up the target
5035  * exception level given numerous condition criteria.  Specifically, the
5036  * target EL is based on SCR and HCR routing controls as well as the
5037  * currently executing EL and secure state.
5038  *
5039  *    Dimensions:
5040  *    target_el_table[2][2][2][2][2][4]
5041  *                    |  |  |  |  |  +--- Current EL
5042  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5043  *                    |  |  |  +--------- HCR mask override
5044  *                    |  |  +------------ SCR exec state control
5045  *                    |  +--------------- SCR mask override
5046  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5047  *
5048  *    The table values are as such:
5049  *    0-3 = EL0-EL3
5050  *     -1 = Cannot occur
5051  *
5052  * The ARM ARM target EL table includes entries indicating that an "exception
5053  * is not taken".  The two cases where this is applicable are:
5054  *    1) An exception is taken from EL3 but the SCR does not have the exception
5055  *    routed to EL3.
5056  *    2) An exception is taken from EL2 but the HCR does not have the exception
5057  *    routed to EL2.
5058  * In these two cases, the below table contain a target of EL1.  This value is
5059  * returned as it is expected that the consumer of the table data will check
5060  * for "target EL >= current EL" to ensure the exception is not taken.
5061  *
5062  *            SCR     HCR
5063  *         64  EA     AMO                 From
5064  *        BIT IRQ     IMO      Non-secure         Secure
5065  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5066  */
5067 const int8_t target_el_table[2][2][2][2][2][4] = {
5068     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5069        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5070       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5071        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5072      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5073        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5074       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5075        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5076     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5077        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5078       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5079        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5080      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5081        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5082       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5083        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5084 };
5085
5086 /*
5087  * Determine the target EL for physical exceptions
5088  */
5089 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5090                                  uint32_t cur_el, bool secure)
5091 {
5092     CPUARMState *env = cs->env_ptr;
5093     int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5094     int scr;
5095     int hcr;
5096     int target_el;
5097     int is64 = arm_el_is_aa64(env, 3);
5098
5099     switch (excp_idx) {
5100     case EXCP_IRQ:
5101         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5102         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5103         break;
5104     case EXCP_FIQ:
5105         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5106         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5107         break;
5108     default:
5109         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5110         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5111         break;
5112     };
5113
5114     /* If HCR.TGE is set then HCR is treated as being 1 */
5115     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5116
5117     /* Perform a table-lookup for the target EL given the current state */
5118     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5119
5120     assert(target_el > 0);
5121
5122     return target_el;
5123 }
5124
5125 static void v7m_push(CPUARMState *env, uint32_t val)
5126 {
5127     CPUState *cs = CPU(arm_env_get_cpu(env));
5128
5129     env->regs[13] -= 4;
5130     stl_phys(cs->as, env->regs[13], val);
5131 }
5132
5133 static uint32_t v7m_pop(CPUARMState *env)
5134 {
5135     CPUState *cs = CPU(arm_env_get_cpu(env));
5136     uint32_t val;
5137
5138     val = ldl_phys(cs->as, env->regs[13]);
5139     env->regs[13] += 4;
5140     return val;
5141 }
5142
5143 /* Switch to V7M main or process stack pointer.  */
5144 static void switch_v7m_sp(CPUARMState *env, int process)
5145 {
5146     uint32_t tmp;
5147     if (env->v7m.current_sp != process) {
5148         tmp = env->v7m.other_sp;
5149         env->v7m.other_sp = env->regs[13];
5150         env->regs[13] = tmp;
5151         env->v7m.current_sp = process;
5152     }
5153 }
5154
5155 static void do_v7m_exception_exit(CPUARMState *env)
5156 {
5157     uint32_t type;
5158     uint32_t xpsr;
5159
5160     type = env->regs[15];
5161     if (env->v7m.exception != 0)
5162         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5163
5164     /* Switch to the target stack.  */
5165     switch_v7m_sp(env, (type & 4) != 0);
5166     /* Pop registers.  */
5167     env->regs[0] = v7m_pop(env);
5168     env->regs[1] = v7m_pop(env);
5169     env->regs[2] = v7m_pop(env);
5170     env->regs[3] = v7m_pop(env);
5171     env->regs[12] = v7m_pop(env);
5172     env->regs[14] = v7m_pop(env);
5173     env->regs[15] = v7m_pop(env);
5174     if (env->regs[15] & 1) {
5175         qemu_log_mask(LOG_GUEST_ERROR,
5176                       "M profile return from interrupt with misaligned "
5177                       "PC is UNPREDICTABLE\n");
5178         /* Actual hardware seems to ignore the lsbit, and there are several
5179          * RTOSes out there which incorrectly assume the r15 in the stack
5180          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5181          */
5182         env->regs[15] &= ~1U;
5183     }
5184     xpsr = v7m_pop(env);
5185     xpsr_write(env, xpsr, 0xfffffdff);
5186     /* Undo stack alignment.  */
5187     if (xpsr & 0x200)
5188         env->regs[13] |= 4;
5189     /* ??? The exception return type specifies Thread/Handler mode.  However
5190        this is also implied by the xPSR value. Not sure what to do
5191        if there is a mismatch.  */
5192     /* ??? Likewise for mismatches between the CONTROL register and the stack
5193        pointer.  */
5194 }
5195
5196 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5197 {
5198     ARMCPU *cpu = ARM_CPU(cs);
5199     CPUARMState *env = &cpu->env;
5200     uint32_t xpsr = xpsr_read(env);
5201     uint32_t lr;
5202     uint32_t addr;
5203
5204     arm_log_exception(cs->exception_index);
5205
5206     lr = 0xfffffff1;
5207     if (env->v7m.current_sp)
5208         lr |= 4;
5209     if (env->v7m.exception == 0)
5210         lr |= 8;
5211
5212     /* For exceptions we just mark as pending on the NVIC, and let that
5213        handle it.  */
5214     /* TODO: Need to escalate if the current priority is higher than the
5215        one we're raising.  */
5216     switch (cs->exception_index) {
5217     case EXCP_UDEF:
5218         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5219         return;
5220     case EXCP_SWI:
5221         /* The PC already points to the next instruction.  */
5222         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5223         return;
5224     case EXCP_PREFETCH_ABORT:
5225     case EXCP_DATA_ABORT:
5226         /* TODO: if we implemented the MPU registers, this is where we
5227          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5228          */
5229         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5230         return;
5231     case EXCP_BKPT:
5232         if (semihosting_enabled()) {
5233             int nr;
5234             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5235             if (nr == 0xab) {
5236                 env->regs[15] += 2;
5237                 qemu_log_mask(CPU_LOG_INT,
5238                               "...handling as semihosting call 0x%x\n",
5239                               env->regs[0]);
5240                 env->regs[0] = do_arm_semihosting(env);
5241                 return;
5242             }
5243         }
5244         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5245         return;
5246     case EXCP_IRQ:
5247         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5248         break;
5249     case EXCP_EXCEPTION_EXIT:
5250         do_v7m_exception_exit(env);
5251         return;
5252     default:
5253         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5254         return; /* Never happens.  Keep compiler happy.  */
5255     }
5256
5257     /* Align stack pointer.  */
5258     /* ??? Should only do this if Configuration Control Register
5259        STACKALIGN bit is set.  */
5260     if (env->regs[13] & 4) {
5261         env->regs[13] -= 4;
5262         xpsr |= 0x200;
5263     }
5264     /* Switch to the handler mode.  */
5265     v7m_push(env, xpsr);
5266     v7m_push(env, env->regs[15]);
5267     v7m_push(env, env->regs[14]);
5268     v7m_push(env, env->regs[12]);
5269     v7m_push(env, env->regs[3]);
5270     v7m_push(env, env->regs[2]);
5271     v7m_push(env, env->regs[1]);
5272     v7m_push(env, env->regs[0]);
5273     switch_v7m_sp(env, 0);
5274     /* Clear IT bits */
5275     env->condexec_bits = 0;
5276     env->regs[14] = lr;
5277     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5278     env->regs[15] = addr & 0xfffffffe;
5279     env->thumb = addr & 1;
5280 }
5281
5282 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5283  * register set.  This is necessary when switching between AArch32 and AArch64
5284  * execution state.
5285  */
5286 void aarch64_sync_32_to_64(CPUARMState *env)
5287 {
5288     int i;
5289     uint32_t mode = env->uncached_cpsr & CPSR_M;
5290
5291     /* We can blanket copy R[0:7] to X[0:7] */
5292     for (i = 0; i < 8; i++) {
5293         env->xregs[i] = env->regs[i];
5294     }
5295
5296     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5297      * Otherwise, they come from the banked user regs.
5298      */
5299     if (mode == ARM_CPU_MODE_FIQ) {
5300         for (i = 8; i < 13; i++) {
5301             env->xregs[i] = env->usr_regs[i - 8];
5302         }
5303     } else {
5304         for (i = 8; i < 13; i++) {
5305             env->xregs[i] = env->regs[i];
5306         }
5307     }
5308
5309     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5310      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5311      * from the mode banked register.
5312      */
5313     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5314         env->xregs[13] = env->regs[13];
5315         env->xregs[14] = env->regs[14];
5316     } else {
5317         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5318         /* HYP is an exception in that it is copied from r14 */
5319         if (mode == ARM_CPU_MODE_HYP) {
5320             env->xregs[14] = env->regs[14];
5321         } else {
5322             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5323         }
5324     }
5325
5326     if (mode == ARM_CPU_MODE_HYP) {
5327         env->xregs[15] = env->regs[13];
5328     } else {
5329         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5330     }
5331
5332     if (mode == ARM_CPU_MODE_IRQ) {
5333         env->xregs[16] = env->regs[14];
5334         env->xregs[17] = env->regs[13];
5335     } else {
5336         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5337         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5338     }
5339
5340     if (mode == ARM_CPU_MODE_SVC) {
5341         env->xregs[18] = env->regs[14];
5342         env->xregs[19] = env->regs[13];
5343     } else {
5344         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5345         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5346     }
5347
5348     if (mode == ARM_CPU_MODE_ABT) {
5349         env->xregs[20] = env->regs[14];
5350         env->xregs[21] = env->regs[13];
5351     } else {
5352         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5353         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5354     }
5355
5356     if (mode == ARM_CPU_MODE_UND) {
5357         env->xregs[22] = env->regs[14];
5358         env->xregs[23] = env->regs[13];
5359     } else {
5360         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5361         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5362     }
5363
5364     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5365      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5366      * FIQ bank for r8-r14.
5367      */
5368     if (mode == ARM_CPU_MODE_FIQ) {
5369         for (i = 24; i < 31; i++) {
5370             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5371         }
5372     } else {
5373         for (i = 24; i < 29; i++) {
5374             env->xregs[i] = env->fiq_regs[i - 24];
5375         }
5376         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5377         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5378     }
5379
5380     env->pc = env->regs[15];
5381 }
5382
5383 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5384  * register set.  This is necessary when switching between AArch32 and AArch64
5385  * execution state.
5386  */
5387 void aarch64_sync_64_to_32(CPUARMState *env)
5388 {
5389     int i;
5390     uint32_t mode = env->uncached_cpsr & CPSR_M;
5391
5392     /* We can blanket copy X[0:7] to R[0:7] */
5393     for (i = 0; i < 8; i++) {
5394         env->regs[i] = env->xregs[i];
5395     }
5396
5397     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5398      * Otherwise, we copy x8-x12 into the banked user regs.
5399      */
5400     if (mode == ARM_CPU_MODE_FIQ) {
5401         for (i = 8; i < 13; i++) {
5402             env->usr_regs[i - 8] = env->xregs[i];
5403         }
5404     } else {
5405         for (i = 8; i < 13; i++) {
5406             env->regs[i] = env->xregs[i];
5407         }
5408     }
5409
5410     /* Registers r13 & r14 depend on the current mode.
5411      * If we are in a given mode, we copy the corresponding x registers to r13
5412      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
5413      * for the mode.
5414      */
5415     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5416         env->regs[13] = env->xregs[13];
5417         env->regs[14] = env->xregs[14];
5418     } else {
5419         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5420
5421         /* HYP is an exception in that it does not have its own banked r14 but
5422          * shares the USR r14
5423          */
5424         if (mode == ARM_CPU_MODE_HYP) {
5425             env->regs[14] = env->xregs[14];
5426         } else {
5427             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5428         }
5429     }
5430
5431     if (mode == ARM_CPU_MODE_HYP) {
5432         env->regs[13] = env->xregs[15];
5433     } else {
5434         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5435     }
5436
5437     if (mode == ARM_CPU_MODE_IRQ) {
5438         env->regs[14] = env->xregs[16];
5439         env->regs[13] = env->xregs[17];
5440     } else {
5441         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5442         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5443     }
5444
5445     if (mode == ARM_CPU_MODE_SVC) {
5446         env->regs[14] = env->xregs[18];
5447         env->regs[13] = env->xregs[19];
5448     } else {
5449         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5450         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5451     }
5452
5453     if (mode == ARM_CPU_MODE_ABT) {
5454         env->regs[14] = env->xregs[20];
5455         env->regs[13] = env->xregs[21];
5456     } else {
5457         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5458         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5459     }
5460
5461     if (mode == ARM_CPU_MODE_UND) {
5462         env->regs[14] = env->xregs[22];
5463         env->regs[13] = env->xregs[23];
5464     } else {
5465         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5466         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5467     }
5468
5469     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5470      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
5471      * FIQ bank for r8-r14.
5472      */
5473     if (mode == ARM_CPU_MODE_FIQ) {
5474         for (i = 24; i < 31; i++) {
5475             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
5476         }
5477     } else {
5478         for (i = 24; i < 29; i++) {
5479             env->fiq_regs[i - 24] = env->xregs[i];
5480         }
5481         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5482         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5483     }
5484
5485     env->regs[15] = env->pc;
5486 }
5487
5488 /* Handle a CPU exception.  */
5489 void arm_cpu_do_interrupt(CPUState *cs)
5490 {
5491     ARMCPU *cpu = ARM_CPU(cs);
5492     CPUARMState *env = &cpu->env;
5493     uint32_t addr;
5494     uint32_t mask;
5495     int new_mode;
5496     uint32_t offset;
5497     uint32_t moe;
5498
5499     assert(!IS_M(env));
5500
5501     arm_log_exception(cs->exception_index);
5502
5503     if (arm_is_psci_call(cpu, cs->exception_index)) {
5504         arm_handle_psci_call(cpu);
5505         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
5506         return;
5507     }
5508
5509     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5510     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5511     case EC_BREAKPOINT:
5512     case EC_BREAKPOINT_SAME_EL:
5513         moe = 1;
5514         break;
5515     case EC_WATCHPOINT:
5516     case EC_WATCHPOINT_SAME_EL:
5517         moe = 10;
5518         break;
5519     case EC_AA32_BKPT:
5520         moe = 3;
5521         break;
5522     case EC_VECTORCATCH:
5523         moe = 5;
5524         break;
5525     default:
5526         moe = 0;
5527         break;
5528     }
5529
5530     if (moe) {
5531         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5532     }
5533
5534     /* TODO: Vectored interrupt controller.  */
5535     switch (cs->exception_index) {
5536     case EXCP_UDEF:
5537         new_mode = ARM_CPU_MODE_UND;
5538         addr = 0x04;
5539         mask = CPSR_I;
5540         if (env->thumb)
5541             offset = 2;
5542         else
5543             offset = 4;
5544         break;
5545     case EXCP_SWI:
5546         if (semihosting_enabled()) {
5547             /* Check for semihosting interrupt.  */
5548             if (env->thumb) {
5549                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
5550                     & 0xff;
5551             } else {
5552                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
5553                     & 0xffffff;
5554             }
5555             /* Only intercept calls from privileged modes, to provide some
5556                semblance of security.  */
5557             if (((mask == 0x123456 && !env->thumb)
5558                     || (mask == 0xab && env->thumb))
5559                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5560                 qemu_log_mask(CPU_LOG_INT,
5561                               "...handling as semihosting call 0x%x\n",
5562                               env->regs[0]);
5563                 env->regs[0] = do_arm_semihosting(env);
5564                 return;
5565             }
5566         }
5567         new_mode = ARM_CPU_MODE_SVC;
5568         addr = 0x08;
5569         mask = CPSR_I;
5570         /* The PC already points to the next instruction.  */
5571         offset = 0;
5572         break;
5573     case EXCP_BKPT:
5574         /* See if this is a semihosting syscall.  */
5575         if (env->thumb && semihosting_enabled()) {
5576             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5577             if (mask == 0xab
5578                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5579                 env->regs[15] += 2;
5580                 qemu_log_mask(CPU_LOG_INT,
5581                               "...handling as semihosting call 0x%x\n",
5582                               env->regs[0]);
5583                 env->regs[0] = do_arm_semihosting(env);
5584                 return;
5585             }
5586         }
5587         env->exception.fsr = 2;
5588         /* Fall through to prefetch abort.  */
5589     case EXCP_PREFETCH_ABORT:
5590         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5591         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5592         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5593                       env->exception.fsr, (uint32_t)env->exception.vaddress);
5594         new_mode = ARM_CPU_MODE_ABT;
5595         addr = 0x0c;
5596         mask = CPSR_A | CPSR_I;
5597         offset = 4;
5598         break;
5599     case EXCP_DATA_ABORT:
5600         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5601         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5602         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5603                       env->exception.fsr,
5604                       (uint32_t)env->exception.vaddress);
5605         new_mode = ARM_CPU_MODE_ABT;
5606         addr = 0x10;
5607         mask = CPSR_A | CPSR_I;
5608         offset = 8;
5609         break;
5610     case EXCP_IRQ:
5611         new_mode = ARM_CPU_MODE_IRQ;
5612         addr = 0x18;
5613         /* Disable IRQ and imprecise data aborts.  */
5614         mask = CPSR_A | CPSR_I;
5615         offset = 4;
5616         if (env->cp15.scr_el3 & SCR_IRQ) {
5617             /* IRQ routed to monitor mode */
5618             new_mode = ARM_CPU_MODE_MON;
5619             mask |= CPSR_F;
5620         }
5621         break;
5622     case EXCP_FIQ:
5623         new_mode = ARM_CPU_MODE_FIQ;
5624         addr = 0x1c;
5625         /* Disable FIQ, IRQ and imprecise data aborts.  */
5626         mask = CPSR_A | CPSR_I | CPSR_F;
5627         if (env->cp15.scr_el3 & SCR_FIQ) {
5628             /* FIQ routed to monitor mode */
5629             new_mode = ARM_CPU_MODE_MON;
5630         }
5631         offset = 4;
5632         break;
5633     case EXCP_SMC:
5634         new_mode = ARM_CPU_MODE_MON;
5635         addr = 0x08;
5636         mask = CPSR_A | CPSR_I | CPSR_F;
5637         offset = 0;
5638         break;
5639     default:
5640         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5641         return; /* Never happens.  Keep compiler happy.  */
5642     }
5643
5644     if (new_mode == ARM_CPU_MODE_MON) {
5645         addr += env->cp15.mvbar;
5646     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5647         /* High vectors. When enabled, base address cannot be remapped. */
5648         addr += 0xffff0000;
5649     } else {
5650         /* ARM v7 architectures provide a vector base address register to remap
5651          * the interrupt vector table.
5652          * This register is only followed in non-monitor mode, and is banked.
5653          * Note: only bits 31:5 are valid.
5654          */
5655         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5656     }
5657
5658     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5659         env->cp15.scr_el3 &= ~SCR_NS;
5660     }
5661
5662     switch_mode (env, new_mode);
5663     /* For exceptions taken to AArch32 we must clear the SS bit in both
5664      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5665      */
5666     env->uncached_cpsr &= ~PSTATE_SS;
5667     env->spsr = cpsr_read(env);
5668     /* Clear IT bits.  */
5669     env->condexec_bits = 0;
5670     /* Switch to the new mode, and to the correct instruction set.  */
5671     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5672     env->daif |= mask;
5673     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5674      * and we should just guard the thumb mode on V4 */
5675     if (arm_feature(env, ARM_FEATURE_V4T)) {
5676         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5677     }
5678     env->regs[14] = env->regs[15] + offset;
5679     env->regs[15] = addr;
5680     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
5681 }
5682
5683
5684 /* Return the exception level which controls this address translation regime */
5685 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
5686 {
5687     switch (mmu_idx) {
5688     case ARMMMUIdx_S2NS:
5689     case ARMMMUIdx_S1E2:
5690         return 2;
5691     case ARMMMUIdx_S1E3:
5692         return 3;
5693     case ARMMMUIdx_S1SE0:
5694         return arm_el_is_aa64(env, 3) ? 1 : 3;
5695     case ARMMMUIdx_S1SE1:
5696     case ARMMMUIdx_S1NSE0:
5697     case ARMMMUIdx_S1NSE1:
5698         return 1;
5699     default:
5700         g_assert_not_reached();
5701     }
5702 }
5703
5704 /* Return true if this address translation regime is secure */
5705 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
5706 {
5707     switch (mmu_idx) {
5708     case ARMMMUIdx_S12NSE0:
5709     case ARMMMUIdx_S12NSE1:
5710     case ARMMMUIdx_S1NSE0:
5711     case ARMMMUIdx_S1NSE1:
5712     case ARMMMUIdx_S1E2:
5713     case ARMMMUIdx_S2NS:
5714         return false;
5715     case ARMMMUIdx_S1E3:
5716     case ARMMMUIdx_S1SE0:
5717     case ARMMMUIdx_S1SE1:
5718         return true;
5719     default:
5720         g_assert_not_reached();
5721     }
5722 }
5723
5724 /* Return the SCTLR value which controls this address translation regime */
5725 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
5726 {
5727     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
5728 }
5729
5730 /* Return true if the specified stage of address translation is disabled */
5731 static inline bool regime_translation_disabled(CPUARMState *env,
5732                                                ARMMMUIdx mmu_idx)
5733 {
5734     if (mmu_idx == ARMMMUIdx_S2NS) {
5735         return (env->cp15.hcr_el2 & HCR_VM) == 0;
5736     }
5737     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
5738 }
5739
5740 /* Return the TCR controlling this translation regime */
5741 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
5742 {
5743     if (mmu_idx == ARMMMUIdx_S2NS) {
5744         /* TODO: return VTCR_EL2 */
5745         g_assert_not_reached();
5746     }
5747     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
5748 }
5749
5750 /* Return the TTBR associated with this translation regime */
5751 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
5752                                    int ttbrn)
5753 {
5754     if (mmu_idx == ARMMMUIdx_S2NS) {
5755         /* TODO: return VTTBR_EL2 */
5756         g_assert_not_reached();
5757     }
5758     if (ttbrn == 0) {
5759         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
5760     } else {
5761         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
5762     }
5763 }
5764
5765 /* Return true if the translation regime is using LPAE format page tables */
5766 static inline bool regime_using_lpae_format(CPUARMState *env,
5767                                             ARMMMUIdx mmu_idx)
5768 {
5769     int el = regime_el(env, mmu_idx);
5770     if (el == 2 || arm_el_is_aa64(env, el)) {
5771         return true;
5772     }
5773     if (arm_feature(env, ARM_FEATURE_LPAE)
5774         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
5775         return true;
5776     }
5777     return false;
5778 }
5779
5780 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
5781 {
5782     switch (mmu_idx) {
5783     case ARMMMUIdx_S1SE0:
5784     case ARMMMUIdx_S1NSE0:
5785         return true;
5786     default:
5787         return false;
5788     case ARMMMUIdx_S12NSE0:
5789     case ARMMMUIdx_S12NSE1:
5790         g_assert_not_reached();
5791     }
5792 }
5793
5794 /* Translate section/page access permissions to page
5795  * R/W protection flags
5796  *
5797  * @env:         CPUARMState
5798  * @mmu_idx:     MMU index indicating required translation regime
5799  * @ap:          The 3-bit access permissions (AP[2:0])
5800  * @domain_prot: The 2-bit domain access permissions
5801  */
5802 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
5803                                 int ap, int domain_prot)
5804 {
5805     bool is_user = regime_is_user(env, mmu_idx);
5806
5807     if (domain_prot == 3) {
5808         return PAGE_READ | PAGE_WRITE;
5809     }
5810
5811     switch (ap) {
5812     case 0:
5813         if (arm_feature(env, ARM_FEATURE_V7)) {
5814             return 0;
5815         }
5816         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
5817         case SCTLR_S:
5818             return is_user ? 0 : PAGE_READ;
5819         case SCTLR_R:
5820             return PAGE_READ;
5821         default:
5822             return 0;
5823         }
5824     case 1:
5825         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5826     case 2:
5827         if (is_user) {
5828             return PAGE_READ;
5829         } else {
5830             return PAGE_READ | PAGE_WRITE;
5831         }
5832     case 3:
5833         return PAGE_READ | PAGE_WRITE;
5834     case 4: /* Reserved.  */
5835         return 0;
5836     case 5:
5837         return is_user ? 0 : PAGE_READ;
5838     case 6:
5839         return PAGE_READ;
5840     case 7:
5841         if (!arm_feature(env, ARM_FEATURE_V6K)) {
5842             return 0;
5843         }
5844         return PAGE_READ;
5845     default:
5846         g_assert_not_reached();
5847     }
5848 }
5849
5850 /* Translate section/page access permissions to page
5851  * R/W protection flags.
5852  *
5853  * @ap:      The 2-bit simple AP (AP[2:1])
5854  * @is_user: TRUE if accessing from PL0
5855  */
5856 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
5857 {
5858     switch (ap) {
5859     case 0:
5860         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5861     case 1:
5862         return PAGE_READ | PAGE_WRITE;
5863     case 2:
5864         return is_user ? 0 : PAGE_READ;
5865     case 3:
5866         return PAGE_READ;
5867     default:
5868         g_assert_not_reached();
5869     }
5870 }
5871
5872 static inline int
5873 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
5874 {
5875     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
5876 }
5877
5878 /* Translate section/page access permissions to protection flags
5879  *
5880  * @env:     CPUARMState
5881  * @mmu_idx: MMU index indicating required translation regime
5882  * @is_aa64: TRUE if AArch64
5883  * @ap:      The 2-bit simple AP (AP[2:1])
5884  * @ns:      NS (non-secure) bit
5885  * @xn:      XN (execute-never) bit
5886  * @pxn:     PXN (privileged execute-never) bit
5887  */
5888 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
5889                       int ap, int ns, int xn, int pxn)
5890 {
5891     bool is_user = regime_is_user(env, mmu_idx);
5892     int prot_rw, user_rw;
5893     bool have_wxn;
5894     int wxn = 0;
5895
5896     assert(mmu_idx != ARMMMUIdx_S2NS);
5897
5898     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
5899     if (is_user) {
5900         prot_rw = user_rw;
5901     } else {
5902         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
5903     }
5904
5905     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
5906         return prot_rw;
5907     }
5908
5909     /* TODO have_wxn should be replaced with
5910      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
5911      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
5912      * compatible processors have EL2, which is required for [U]WXN.
5913      */
5914     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
5915
5916     if (have_wxn) {
5917         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
5918     }
5919
5920     if (is_aa64) {
5921         switch (regime_el(env, mmu_idx)) {
5922         case 1:
5923             if (!is_user) {
5924                 xn = pxn || (user_rw & PAGE_WRITE);
5925             }
5926             break;
5927         case 2:
5928         case 3:
5929             break;
5930         }
5931     } else if (arm_feature(env, ARM_FEATURE_V7)) {
5932         switch (regime_el(env, mmu_idx)) {
5933         case 1:
5934         case 3:
5935             if (is_user) {
5936                 xn = xn || !(user_rw & PAGE_READ);
5937             } else {
5938                 int uwxn = 0;
5939                 if (have_wxn) {
5940                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
5941                 }
5942                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
5943                      (uwxn && (user_rw & PAGE_WRITE));
5944             }
5945             break;
5946         case 2:
5947             break;
5948         }
5949     } else {
5950         xn = wxn = 0;
5951     }
5952
5953     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
5954         return prot_rw;
5955     }
5956     return prot_rw | PAGE_EXEC;
5957 }
5958
5959 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
5960                                      uint32_t *table, uint32_t address)
5961 {
5962     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
5963     TCR *tcr = regime_tcr(env, mmu_idx);
5964
5965     if (address & tcr->mask) {
5966         if (tcr->raw_tcr & TTBCR_PD1) {
5967             /* Translation table walk disabled for TTBR1 */
5968             return false;
5969         }
5970         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
5971     } else {
5972         if (tcr->raw_tcr & TTBCR_PD0) {
5973             /* Translation table walk disabled for TTBR0 */
5974             return false;
5975         }
5976         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
5977     }
5978     *table |= (address >> 18) & 0x3ffc;
5979     return true;
5980 }
5981
5982 /* All loads done in the course of a page table walk go through here.
5983  * TODO: rather than ignoring errors from physical memory reads (which
5984  * are external aborts in ARM terminology) we should propagate this
5985  * error out so that we can turn it into a Data Abort if this walk
5986  * was being done for a CPU load/store or an address translation instruction
5987  * (but not if it was for a debug access).
5988  */
5989 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5990 {
5991     MemTxAttrs attrs = {};
5992
5993     attrs.secure = is_secure;
5994     return address_space_ldl(cs->as, addr, attrs, NULL);
5995 }
5996
5997 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5998 {
5999     MemTxAttrs attrs = {};
6000
6001     attrs.secure = is_secure;
6002     return address_space_ldq(cs->as, addr, attrs, NULL);
6003 }
6004
6005 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6006                              int access_type, ARMMMUIdx mmu_idx,
6007                              hwaddr *phys_ptr, int *prot,
6008                              target_ulong *page_size, uint32_t *fsr)
6009 {
6010     CPUState *cs = CPU(arm_env_get_cpu(env));
6011     int code;
6012     uint32_t table;
6013     uint32_t desc;
6014     int type;
6015     int ap;
6016     int domain = 0;
6017     int domain_prot;
6018     hwaddr phys_addr;
6019     uint32_t dacr;
6020
6021     /* Pagetable walk.  */
6022     /* Lookup l1 descriptor.  */
6023     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6024         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6025         code = 5;
6026         goto do_fault;
6027     }
6028     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6029     type = (desc & 3);
6030     domain = (desc >> 5) & 0x0f;
6031     if (regime_el(env, mmu_idx) == 1) {
6032         dacr = env->cp15.dacr_ns;
6033     } else {
6034         dacr = env->cp15.dacr_s;
6035     }
6036     domain_prot = (dacr >> (domain * 2)) & 3;
6037     if (type == 0) {
6038         /* Section translation fault.  */
6039         code = 5;
6040         goto do_fault;
6041     }
6042     if (domain_prot == 0 || domain_prot == 2) {
6043         if (type == 2)
6044             code = 9; /* Section domain fault.  */
6045         else
6046             code = 11; /* Page domain fault.  */
6047         goto do_fault;
6048     }
6049     if (type == 2) {
6050         /* 1Mb section.  */
6051         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6052         ap = (desc >> 10) & 3;
6053         code = 13;
6054         *page_size = 1024 * 1024;
6055     } else {
6056         /* Lookup l2 entry.  */
6057         if (type == 1) {
6058             /* Coarse pagetable.  */
6059             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6060         } else {
6061             /* Fine pagetable.  */
6062             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6063         }
6064         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6065         switch (desc & 3) {
6066         case 0: /* Page translation fault.  */
6067             code = 7;
6068             goto do_fault;
6069         case 1: /* 64k page.  */
6070             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6071             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6072             *page_size = 0x10000;
6073             break;
6074         case 2: /* 4k page.  */
6075             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6076             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6077             *page_size = 0x1000;
6078             break;
6079         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6080             if (type == 1) {
6081                 /* ARMv6/XScale extended small page format */
6082                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6083                     || arm_feature(env, ARM_FEATURE_V6)) {
6084                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6085                     *page_size = 0x1000;
6086                 } else {
6087                     /* UNPREDICTABLE in ARMv5; we choose to take a
6088                      * page translation fault.
6089                      */
6090                     code = 7;
6091                     goto do_fault;
6092                 }
6093             } else {
6094                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6095                 *page_size = 0x400;
6096             }
6097             ap = (desc >> 4) & 3;
6098             break;
6099         default:
6100             /* Never happens, but compiler isn't smart enough to tell.  */
6101             abort();
6102         }
6103         code = 15;
6104     }
6105     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6106     *prot |= *prot ? PAGE_EXEC : 0;
6107     if (!(*prot & (1 << access_type))) {
6108         /* Access permission fault.  */
6109         goto do_fault;
6110     }
6111     *phys_ptr = phys_addr;
6112     return false;
6113 do_fault:
6114     *fsr = code | (domain << 4);
6115     return true;
6116 }
6117
6118 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6119                              int access_type, ARMMMUIdx mmu_idx,
6120                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6121                              target_ulong *page_size, uint32_t *fsr)
6122 {
6123     CPUState *cs = CPU(arm_env_get_cpu(env));
6124     int code;
6125     uint32_t table;
6126     uint32_t desc;
6127     uint32_t xn;
6128     uint32_t pxn = 0;
6129     int type;
6130     int ap;
6131     int domain = 0;
6132     int domain_prot;
6133     hwaddr phys_addr;
6134     uint32_t dacr;
6135     bool ns;
6136
6137     /* Pagetable walk.  */
6138     /* Lookup l1 descriptor.  */
6139     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6140         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6141         code = 5;
6142         goto do_fault;
6143     }
6144     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6145     type = (desc & 3);
6146     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6147         /* Section translation fault, or attempt to use the encoding
6148          * which is Reserved on implementations without PXN.
6149          */
6150         code = 5;
6151         goto do_fault;
6152     }
6153     if ((type == 1) || !(desc & (1 << 18))) {
6154         /* Page or Section.  */
6155         domain = (desc >> 5) & 0x0f;
6156     }
6157     if (regime_el(env, mmu_idx) == 1) {
6158         dacr = env->cp15.dacr_ns;
6159     } else {
6160         dacr = env->cp15.dacr_s;
6161     }
6162     domain_prot = (dacr >> (domain * 2)) & 3;
6163     if (domain_prot == 0 || domain_prot == 2) {
6164         if (type != 1) {
6165             code = 9; /* Section domain fault.  */
6166         } else {
6167             code = 11; /* Page domain fault.  */
6168         }
6169         goto do_fault;
6170     }
6171     if (type != 1) {
6172         if (desc & (1 << 18)) {
6173             /* Supersection.  */
6174             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6175             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6176             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6177             *page_size = 0x1000000;
6178         } else {
6179             /* Section.  */
6180             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6181             *page_size = 0x100000;
6182         }
6183         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6184         xn = desc & (1 << 4);
6185         pxn = desc & 1;
6186         code = 13;
6187         ns = extract32(desc, 19, 1);
6188     } else {
6189         if (arm_feature(env, ARM_FEATURE_PXN)) {
6190             pxn = (desc >> 2) & 1;
6191         }
6192         ns = extract32(desc, 3, 1);
6193         /* Lookup l2 entry.  */
6194         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6195         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6196         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6197         switch (desc & 3) {
6198         case 0: /* Page translation fault.  */
6199             code = 7;
6200             goto do_fault;
6201         case 1: /* 64k page.  */
6202             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6203             xn = desc & (1 << 15);
6204             *page_size = 0x10000;
6205             break;
6206         case 2: case 3: /* 4k page.  */
6207             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6208             xn = desc & 1;
6209             *page_size = 0x1000;
6210             break;
6211         default:
6212             /* Never happens, but compiler isn't smart enough to tell.  */
6213             abort();
6214         }
6215         code = 15;
6216     }
6217     if (domain_prot == 3) {
6218         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6219     } else {
6220         if (pxn && !regime_is_user(env, mmu_idx)) {
6221             xn = 1;
6222         }
6223         if (xn && access_type == 2)
6224             goto do_fault;
6225
6226         if (arm_feature(env, ARM_FEATURE_V6K) &&
6227                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6228             /* The simplified model uses AP[0] as an access control bit.  */
6229             if ((ap & 1) == 0) {
6230                 /* Access flag fault.  */
6231                 code = (code == 15) ? 6 : 3;
6232                 goto do_fault;
6233             }
6234             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6235         } else {
6236             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6237         }
6238         if (*prot && !xn) {
6239             *prot |= PAGE_EXEC;
6240         }
6241         if (!(*prot & (1 << access_type))) {
6242             /* Access permission fault.  */
6243             goto do_fault;
6244         }
6245     }
6246     if (ns) {
6247         /* The NS bit will (as required by the architecture) have no effect if
6248          * the CPU doesn't support TZ or this is a non-secure translation
6249          * regime, because the attribute will already be non-secure.
6250          */
6251         attrs->secure = false;
6252     }
6253     *phys_ptr = phys_addr;
6254     return false;
6255 do_fault:
6256     *fsr = code | (domain << 4);
6257     return true;
6258 }
6259
6260 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6261  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6262  */
6263 typedef enum {
6264     translation_fault = 1,
6265     access_fault = 2,
6266     permission_fault = 3,
6267 } MMUFaultType;
6268
6269 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6270                                int access_type, ARMMMUIdx mmu_idx,
6271                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6272                                target_ulong *page_size_ptr, uint32_t *fsr)
6273 {
6274     CPUState *cs = CPU(arm_env_get_cpu(env));
6275     /* Read an LPAE long-descriptor translation table. */
6276     MMUFaultType fault_type = translation_fault;
6277     uint32_t level = 1;
6278     uint32_t epd;
6279     int32_t tsz;
6280     uint32_t tg;
6281     uint64_t ttbr;
6282     int ttbr_select;
6283     hwaddr descaddr, descmask;
6284     uint32_t tableattrs;
6285     target_ulong page_size;
6286     uint32_t attrs;
6287     int32_t granule_sz = 9;
6288     int32_t va_size = 32;
6289     int32_t tbi = 0;
6290     TCR *tcr = regime_tcr(env, mmu_idx);
6291     int ap, ns, xn, pxn;
6292     uint32_t el = regime_el(env, mmu_idx);
6293     bool ttbr1_valid = true;
6294
6295     /* TODO:
6296      * This code does not handle the different format TCR for VTCR_EL2.
6297      * This code also does not support shareability levels.
6298      * Attribute and permission bit handling should also be checked when adding
6299      * support for those page table walks.
6300      */
6301     if (arm_el_is_aa64(env, el)) {
6302         va_size = 64;
6303         if (el > 1) {
6304             tbi = extract64(tcr->raw_tcr, 20, 1);
6305         } else {
6306             if (extract64(address, 55, 1)) {
6307                 tbi = extract64(tcr->raw_tcr, 38, 1);
6308             } else {
6309                 tbi = extract64(tcr->raw_tcr, 37, 1);
6310             }
6311         }
6312         tbi *= 8;
6313
6314         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6315          * invalid.
6316          */
6317         if (el > 1) {
6318             ttbr1_valid = false;
6319         }
6320     } else {
6321         /* There is no TTBR1 for EL2 */
6322         if (el == 2) {
6323             ttbr1_valid = false;
6324         }
6325     }
6326
6327     /* Determine whether this address is in the region controlled by
6328      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6329      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6330      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6331      */
6332     uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
6333     if (va_size == 64) {
6334         t0sz = MIN(t0sz, 39);
6335         t0sz = MAX(t0sz, 16);
6336     }
6337     uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
6338     if (va_size == 64) {
6339         t1sz = MIN(t1sz, 39);
6340         t1sz = MAX(t1sz, 16);
6341     }
6342     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
6343         /* there is a ttbr0 region and we are in it (high bits all zero) */
6344         ttbr_select = 0;
6345     } else if (ttbr1_valid && t1sz &&
6346                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
6347         /* there is a ttbr1 region and we are in it (high bits all one) */
6348         ttbr_select = 1;
6349     } else if (!t0sz) {
6350         /* ttbr0 region is "everything not in the ttbr1 region" */
6351         ttbr_select = 0;
6352     } else if (!t1sz && ttbr1_valid) {
6353         /* ttbr1 region is "everything not in the ttbr0 region" */
6354         ttbr_select = 1;
6355     } else {
6356         /* in the gap between the two regions, this is a Translation fault */
6357         fault_type = translation_fault;
6358         goto do_fault;
6359     }
6360
6361     /* Note that QEMU ignores shareability and cacheability attributes,
6362      * so we don't need to do anything with the SH, ORGN, IRGN fields
6363      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
6364      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6365      * implement any ASID-like capability so we can ignore it (instead
6366      * we will always flush the TLB any time the ASID is changed).
6367      */
6368     if (ttbr_select == 0) {
6369         ttbr = regime_ttbr(env, mmu_idx, 0);
6370         epd = extract32(tcr->raw_tcr, 7, 1);
6371         tsz = t0sz;
6372
6373         tg = extract32(tcr->raw_tcr, 14, 2);
6374         if (tg == 1) { /* 64KB pages */
6375             granule_sz = 13;
6376         }
6377         if (tg == 2) { /* 16KB pages */
6378             granule_sz = 11;
6379         }
6380     } else {
6381         /* We should only be here if TTBR1 is valid */
6382         assert(ttbr1_valid);
6383
6384         ttbr = regime_ttbr(env, mmu_idx, 1);
6385         epd = extract32(tcr->raw_tcr, 23, 1);
6386         tsz = t1sz;
6387
6388         tg = extract32(tcr->raw_tcr, 30, 2);
6389         if (tg == 3)  { /* 64KB pages */
6390             granule_sz = 13;
6391         }
6392         if (tg == 1) { /* 16KB pages */
6393             granule_sz = 11;
6394         }
6395     }
6396
6397     /* Here we should have set up all the parameters for the translation:
6398      * va_size, ttbr, epd, tsz, granule_sz, tbi
6399      */
6400
6401     if (epd) {
6402         /* Translation table walk disabled => Translation fault on TLB miss
6403          * Note: This is always 0 on 64-bit EL2 and EL3.
6404          */
6405         goto do_fault;
6406     }
6407
6408     /* The starting level depends on the virtual address size (which can be
6409      * up to 48 bits) and the translation granule size. It indicates the number
6410      * of strides (granule_sz bits at a time) needed to consume the bits
6411      * of the input address. In the pseudocode this is:
6412      *  level = 4 - RoundUp((inputsize - grainsize) / stride)
6413      * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
6414      * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
6415      * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6416      *     = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
6417      *     = 4 - (va_size - tsz - 4) / granule_sz;
6418      */
6419     level = 4 - (va_size - tsz - 4) / granule_sz;
6420
6421     /* Clear the vaddr bits which aren't part of the within-region address,
6422      * so that we don't have to special case things when calculating the
6423      * first descriptor address.
6424      */
6425     if (tsz) {
6426         address &= (1ULL << (va_size - tsz)) - 1;
6427     }
6428
6429     descmask = (1ULL << (granule_sz + 3)) - 1;
6430
6431     /* Now we can extract the actual base address from the TTBR */
6432     descaddr = extract64(ttbr, 0, 48);
6433     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
6434
6435     /* Secure accesses start with the page table in secure memory and
6436      * can be downgraded to non-secure at any step. Non-secure accesses
6437      * remain non-secure. We implement this by just ORing in the NSTable/NS
6438      * bits at each step.
6439      */
6440     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
6441     for (;;) {
6442         uint64_t descriptor;
6443         bool nstable;
6444
6445         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
6446         descaddr &= ~7ULL;
6447         nstable = extract32(tableattrs, 4, 1);
6448         descriptor = arm_ldq_ptw(cs, descaddr, !nstable);
6449         if (!(descriptor & 1) ||
6450             (!(descriptor & 2) && (level == 3))) {
6451             /* Invalid, or the Reserved level 3 encoding */
6452             goto do_fault;
6453         }
6454         descaddr = descriptor & 0xfffffff000ULL;
6455
6456         if ((descriptor & 2) && (level < 3)) {
6457             /* Table entry. The top five bits are attributes which  may
6458              * propagate down through lower levels of the table (and
6459              * which are all arranged so that 0 means "no effect", so
6460              * we can gather them up by ORing in the bits at each level).
6461              */
6462             tableattrs |= extract64(descriptor, 59, 5);
6463             level++;
6464             continue;
6465         }
6466         /* Block entry at level 1 or 2, or page entry at level 3.
6467          * These are basically the same thing, although the number
6468          * of bits we pull in from the vaddr varies.
6469          */
6470         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
6471         descaddr |= (address & (page_size - 1));
6472         /* Extract attributes from the descriptor and merge with table attrs */
6473         attrs = extract64(descriptor, 2, 10)
6474             | (extract64(descriptor, 52, 12) << 10);
6475         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
6476         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
6477         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
6478          * means "force PL1 access only", which means forcing AP[1] to 0.
6479          */
6480         if (extract32(tableattrs, 2, 1)) {
6481             attrs &= ~(1 << 4);
6482         }
6483         attrs |= nstable << 3; /* NS */
6484         break;
6485     }
6486     /* Here descaddr is the final physical address, and attributes
6487      * are all in attrs.
6488      */
6489     fault_type = access_fault;
6490     if ((attrs & (1 << 8)) == 0) {
6491         /* Access flag */
6492         goto do_fault;
6493     }
6494
6495     ap = extract32(attrs, 4, 2);
6496     ns = extract32(attrs, 3, 1);
6497     xn = extract32(attrs, 12, 1);
6498     pxn = extract32(attrs, 11, 1);
6499
6500     *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
6501
6502     fault_type = permission_fault;
6503     if (!(*prot & (1 << access_type))) {
6504         goto do_fault;
6505     }
6506
6507     if (ns) {
6508         /* The NS bit will (as required by the architecture) have no effect if
6509          * the CPU doesn't support TZ or this is a non-secure translation
6510          * regime, because the attribute will already be non-secure.
6511          */
6512         txattrs->secure = false;
6513     }
6514     *phys_ptr = descaddr;
6515     *page_size_ptr = page_size;
6516     return false;
6517
6518 do_fault:
6519     /* Long-descriptor format IFSR/DFSR value */
6520     *fsr = (1 << 9) | (fault_type << 2) | level;
6521     return true;
6522 }
6523
6524 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
6525                                                 ARMMMUIdx mmu_idx,
6526                                                 int32_t address, int *prot)
6527 {
6528     *prot = PAGE_READ | PAGE_WRITE;
6529     switch (address) {
6530     case 0xF0000000 ... 0xFFFFFFFF:
6531         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
6532             *prot |= PAGE_EXEC;
6533         }
6534         break;
6535     case 0x00000000 ... 0x7FFFFFFF:
6536         *prot |= PAGE_EXEC;
6537         break;
6538     }
6539
6540 }
6541
6542 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
6543                                  int access_type, ARMMMUIdx mmu_idx,
6544                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
6545 {
6546     ARMCPU *cpu = arm_env_get_cpu(env);
6547     int n;
6548     bool is_user = regime_is_user(env, mmu_idx);
6549
6550     *phys_ptr = address;
6551     *prot = 0;
6552
6553     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
6554         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
6555     } else { /* MPU enabled */
6556         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
6557             /* region search */
6558             uint32_t base = env->pmsav7.drbar[n];
6559             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
6560             uint32_t rmask;
6561             bool srdis = false;
6562
6563             if (!(env->pmsav7.drsr[n] & 0x1)) {
6564                 continue;
6565             }
6566
6567             if (!rsize) {
6568                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
6569                 continue;
6570             }
6571             rsize++;
6572             rmask = (1ull << rsize) - 1;
6573
6574             if (base & rmask) {
6575                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
6576                               "to DRSR region size, mask = %" PRIx32,
6577                               base, rmask);
6578                 continue;
6579             }
6580
6581             if (address < base || address > base + rmask) {
6582                 continue;
6583             }
6584
6585             /* Region matched */
6586
6587             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
6588                 int i, snd;
6589                 uint32_t srdis_mask;
6590
6591                 rsize -= 3; /* sub region size (power of 2) */
6592                 snd = ((address - base) >> rsize) & 0x7;
6593                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
6594
6595                 srdis_mask = srdis ? 0x3 : 0x0;
6596                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
6597                     /* This will check in groups of 2, 4 and then 8, whether
6598                      * the subregion bits are consistent. rsize is incremented
6599                      * back up to give the region size, considering consistent
6600                      * adjacent subregions as one region. Stop testing if rsize
6601                      * is already big enough for an entire QEMU page.
6602                      */
6603                     int snd_rounded = snd & ~(i - 1);
6604                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
6605                                                      snd_rounded + 8, i);
6606                     if (srdis_mask ^ srdis_multi) {
6607                         break;
6608                     }
6609                     srdis_mask = (srdis_mask << i) | srdis_mask;
6610                     rsize++;
6611                 }
6612             }
6613             if (rsize < TARGET_PAGE_BITS) {
6614                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
6615                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
6616                               rsize, TARGET_PAGE_BITS);
6617                 continue;
6618             }
6619             if (srdis) {
6620                 continue;
6621             }
6622             break;
6623         }
6624
6625         if (n == -1) { /* no hits */
6626             if (cpu->pmsav7_dregion &&
6627                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
6628                 /* background fault */
6629                 *fsr = 0;
6630                 return true;
6631             }
6632             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
6633         } else { /* a MPU hit! */
6634             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
6635
6636             if (is_user) { /* User mode AP bit decoding */
6637                 switch (ap) {
6638                 case 0:
6639                 case 1:
6640                 case 5:
6641                     break; /* no access */
6642                 case 3:
6643                     *prot |= PAGE_WRITE;
6644                     /* fall through */
6645                 case 2:
6646                 case 6:
6647                     *prot |= PAGE_READ | PAGE_EXEC;
6648                     break;
6649                 default:
6650                     qemu_log_mask(LOG_GUEST_ERROR,
6651                                   "Bad value for AP bits in DRACR %"
6652                                   PRIx32 "\n", ap);
6653                 }
6654             } else { /* Priv. mode AP bits decoding */
6655                 switch (ap) {
6656                 case 0:
6657                     break; /* no access */
6658                 case 1:
6659                 case 2:
6660                 case 3:
6661                     *prot |= PAGE_WRITE;
6662                     /* fall through */
6663                 case 5:
6664                 case 6:
6665                     *prot |= PAGE_READ | PAGE_EXEC;
6666                     break;
6667                 default:
6668                     qemu_log_mask(LOG_GUEST_ERROR,
6669                                   "Bad value for AP bits in DRACR %"
6670                                   PRIx32 "\n", ap);
6671                 }
6672             }
6673
6674             /* execute never */
6675             if (env->pmsav7.dracr[n] & (1 << 12)) {
6676                 *prot &= ~PAGE_EXEC;
6677             }
6678         }
6679     }
6680
6681     *fsr = 0x00d; /* Permission fault */
6682     return !(*prot & (1 << access_type));
6683 }
6684
6685 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
6686                                  int access_type, ARMMMUIdx mmu_idx,
6687                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
6688 {
6689     int n;
6690     uint32_t mask;
6691     uint32_t base;
6692     bool is_user = regime_is_user(env, mmu_idx);
6693
6694     *phys_ptr = address;
6695     for (n = 7; n >= 0; n--) {
6696         base = env->cp15.c6_region[n];
6697         if ((base & 1) == 0) {
6698             continue;
6699         }
6700         mask = 1 << ((base >> 1) & 0x1f);
6701         /* Keep this shift separate from the above to avoid an
6702            (undefined) << 32.  */
6703         mask = (mask << 1) - 1;
6704         if (((base ^ address) & ~mask) == 0) {
6705             break;
6706         }
6707     }
6708     if (n < 0) {
6709         *fsr = 2;
6710         return true;
6711     }
6712
6713     if (access_type == 2) {
6714         mask = env->cp15.pmsav5_insn_ap;
6715     } else {
6716         mask = env->cp15.pmsav5_data_ap;
6717     }
6718     mask = (mask >> (n * 4)) & 0xf;
6719     switch (mask) {
6720     case 0:
6721         *fsr = 1;
6722         return true;
6723     case 1:
6724         if (is_user) {
6725             *fsr = 1;
6726             return true;
6727         }
6728         *prot = PAGE_READ | PAGE_WRITE;
6729         break;
6730     case 2:
6731         *prot = PAGE_READ;
6732         if (!is_user) {
6733             *prot |= PAGE_WRITE;
6734         }
6735         break;
6736     case 3:
6737         *prot = PAGE_READ | PAGE_WRITE;
6738         break;
6739     case 5:
6740         if (is_user) {
6741             *fsr = 1;
6742             return true;
6743         }
6744         *prot = PAGE_READ;
6745         break;
6746     case 6:
6747         *prot = PAGE_READ;
6748         break;
6749     default:
6750         /* Bad permission.  */
6751         *fsr = 1;
6752         return true;
6753     }
6754     *prot |= PAGE_EXEC;
6755     return false;
6756 }
6757
6758 /* get_phys_addr - get the physical address for this virtual address
6759  *
6760  * Find the physical address corresponding to the given virtual address,
6761  * by doing a translation table walk on MMU based systems or using the
6762  * MPU state on MPU based systems.
6763  *
6764  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
6765  * prot and page_size may not be filled in, and the populated fsr value provides
6766  * information on why the translation aborted, in the format of a
6767  * DFSR/IFSR fault register, with the following caveats:
6768  *  * we honour the short vs long DFSR format differences.
6769  *  * the WnR bit is never set (the caller must do this).
6770  *  * for PSMAv5 based systems we don't bother to return a full FSR format
6771  *    value.
6772  *
6773  * @env: CPUARMState
6774  * @address: virtual address to get physical address for
6775  * @access_type: 0 for read, 1 for write, 2 for execute
6776  * @mmu_idx: MMU index indicating required translation regime
6777  * @phys_ptr: set to the physical address corresponding to the virtual address
6778  * @attrs: set to the memory transaction attributes to use
6779  * @prot: set to the permissions for the page containing phys_ptr
6780  * @page_size: set to the size of the page containing phys_ptr
6781  * @fsr: set to the DFSR/IFSR value on failure
6782  */
6783 static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
6784                                  int access_type, ARMMMUIdx mmu_idx,
6785                                  hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6786                                  target_ulong *page_size, uint32_t *fsr)
6787 {
6788     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6789         /* TODO: when we support EL2 we should here call ourselves recursively
6790          * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
6791          * functions will also need changing to perform ARMMMUIdx_S2NS loads
6792          * rather than direct physical memory loads when appropriate.
6793          * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
6794          */
6795         assert(!arm_feature(env, ARM_FEATURE_EL2));
6796         mmu_idx += ARMMMUIdx_S1NSE0;
6797     }
6798
6799     /* The page table entries may downgrade secure to non-secure, but
6800      * cannot upgrade an non-secure translation regime's attributes
6801      * to secure.
6802      */
6803     attrs->secure = regime_is_secure(env, mmu_idx);
6804     attrs->user = regime_is_user(env, mmu_idx);
6805
6806     /* Fast Context Switch Extension. This doesn't exist at all in v8.
6807      * In v7 and earlier it affects all stage 1 translations.
6808      */
6809     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
6810         && !arm_feature(env, ARM_FEATURE_V8)) {
6811         if (regime_el(env, mmu_idx) == 3) {
6812             address += env->cp15.fcseidr_s;
6813         } else {
6814             address += env->cp15.fcseidr_ns;
6815         }
6816     }
6817
6818     /* pmsav7 has special handling for when MPU is disabled so call it before
6819      * the common MMU/MPU disabled check below.
6820      */
6821     if (arm_feature(env, ARM_FEATURE_MPU) &&
6822         arm_feature(env, ARM_FEATURE_V7)) {
6823         *page_size = TARGET_PAGE_SIZE;
6824         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
6825                                     phys_ptr, prot, fsr);
6826     }
6827
6828     if (regime_translation_disabled(env, mmu_idx)) {
6829         /* MMU/MPU disabled.  */
6830         *phys_ptr = address;
6831         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6832         *page_size = TARGET_PAGE_SIZE;
6833         return 0;
6834     }
6835
6836     if (arm_feature(env, ARM_FEATURE_MPU)) {
6837         /* Pre-v7 MPU */
6838         *page_size = TARGET_PAGE_SIZE;
6839         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
6840                                     phys_ptr, prot, fsr);
6841     }
6842
6843     if (regime_using_lpae_format(env, mmu_idx)) {
6844         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
6845                                   attrs, prot, page_size, fsr);
6846     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
6847         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
6848                                 attrs, prot, page_size, fsr);
6849     } else {
6850         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
6851                                 prot, page_size, fsr);
6852     }
6853 }
6854
6855 /* Walk the page table and (if the mapping exists) add the page
6856  * to the TLB. Return false on success, or true on failure. Populate
6857  * fsr with ARM DFSR/IFSR fault register format value on failure.
6858  */
6859 bool arm_tlb_fill(CPUState *cs, vaddr address,
6860                   int access_type, int mmu_idx, uint32_t *fsr)
6861 {
6862     ARMCPU *cpu = ARM_CPU(cs);
6863     CPUARMState *env = &cpu->env;
6864     hwaddr phys_addr;
6865     target_ulong page_size;
6866     int prot;
6867     int ret;
6868     MemTxAttrs attrs = {};
6869
6870     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
6871                         &attrs, &prot, &page_size, fsr);
6872     if (!ret) {
6873         /* Map a single [sub]page.  */
6874         phys_addr &= TARGET_PAGE_MASK;
6875         address &= TARGET_PAGE_MASK;
6876         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
6877                                 prot, mmu_idx, page_size);
6878         return 0;
6879     }
6880
6881     return ret;
6882 }
6883
6884 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
6885 {
6886     ARMCPU *cpu = ARM_CPU(cs);
6887     CPUARMState *env = &cpu->env;
6888     hwaddr phys_addr;
6889     target_ulong page_size;
6890     int prot;
6891     bool ret;
6892     uint32_t fsr;
6893     MemTxAttrs attrs = {};
6894
6895     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
6896                         &attrs, &prot, &page_size, &fsr);
6897
6898     if (ret) {
6899         return -1;
6900     }
6901
6902     return phys_addr;
6903 }
6904
6905 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
6906 {
6907     if ((env->uncached_cpsr & CPSR_M) == mode) {
6908         env->regs[13] = val;
6909     } else {
6910         env->banked_r13[bank_number(mode)] = val;
6911     }
6912 }
6913
6914 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
6915 {
6916     if ((env->uncached_cpsr & CPSR_M) == mode) {
6917         return env->regs[13];
6918     } else {
6919         return env->banked_r13[bank_number(mode)];
6920     }
6921 }
6922
6923 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
6924 {
6925     ARMCPU *cpu = arm_env_get_cpu(env);
6926
6927     switch (reg) {
6928     case 0: /* APSR */
6929         return xpsr_read(env) & 0xf8000000;
6930     case 1: /* IAPSR */
6931         return xpsr_read(env) & 0xf80001ff;
6932     case 2: /* EAPSR */
6933         return xpsr_read(env) & 0xff00fc00;
6934     case 3: /* xPSR */
6935         return xpsr_read(env) & 0xff00fdff;
6936     case 5: /* IPSR */
6937         return xpsr_read(env) & 0x000001ff;
6938     case 6: /* EPSR */
6939         return xpsr_read(env) & 0x0700fc00;
6940     case 7: /* IEPSR */
6941         return xpsr_read(env) & 0x0700edff;
6942     case 8: /* MSP */
6943         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
6944     case 9: /* PSP */
6945         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
6946     case 16: /* PRIMASK */
6947         return (env->daif & PSTATE_I) != 0;
6948     case 17: /* BASEPRI */
6949     case 18: /* BASEPRI_MAX */
6950         return env->v7m.basepri;
6951     case 19: /* FAULTMASK */
6952         return (env->daif & PSTATE_F) != 0;
6953     case 20: /* CONTROL */
6954         return env->v7m.control;
6955     default:
6956         /* ??? For debugging only.  */
6957         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
6958         return 0;
6959     }
6960 }
6961
6962 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
6963 {
6964     ARMCPU *cpu = arm_env_get_cpu(env);
6965
6966     switch (reg) {
6967     case 0: /* APSR */
6968         xpsr_write(env, val, 0xf8000000);
6969         break;
6970     case 1: /* IAPSR */
6971         xpsr_write(env, val, 0xf8000000);
6972         break;
6973     case 2: /* EAPSR */
6974         xpsr_write(env, val, 0xfe00fc00);
6975         break;
6976     case 3: /* xPSR */
6977         xpsr_write(env, val, 0xfe00fc00);
6978         break;
6979     case 5: /* IPSR */
6980         /* IPSR bits are readonly.  */
6981         break;
6982     case 6: /* EPSR */
6983         xpsr_write(env, val, 0x0600fc00);
6984         break;
6985     case 7: /* IEPSR */
6986         xpsr_write(env, val, 0x0600fc00);
6987         break;
6988     case 8: /* MSP */
6989         if (env->v7m.current_sp)
6990             env->v7m.other_sp = val;
6991         else
6992             env->regs[13] = val;
6993         break;
6994     case 9: /* PSP */
6995         if (env->v7m.current_sp)
6996             env->regs[13] = val;
6997         else
6998             env->v7m.other_sp = val;
6999         break;
7000     case 16: /* PRIMASK */
7001         if (val & 1) {
7002             env->daif |= PSTATE_I;
7003         } else {
7004             env->daif &= ~PSTATE_I;
7005         }
7006         break;
7007     case 17: /* BASEPRI */
7008         env->v7m.basepri = val & 0xff;
7009         break;
7010     case 18: /* BASEPRI_MAX */
7011         val &= 0xff;
7012         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
7013             env->v7m.basepri = val;
7014         break;
7015     case 19: /* FAULTMASK */
7016         if (val & 1) {
7017             env->daif |= PSTATE_F;
7018         } else {
7019             env->daif &= ~PSTATE_F;
7020         }
7021         break;
7022     case 20: /* CONTROL */
7023         env->v7m.control = val & 3;
7024         switch_v7m_sp(env, (val & 2) != 0);
7025         break;
7026     default:
7027         /* ??? For debugging only.  */
7028         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7029         return;
7030     }
7031 }
7032
7033 #endif
7034
7035 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7036 {
7037     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7038      * Note that we do not implement the (architecturally mandated)
7039      * alignment fault for attempts to use this on Device memory
7040      * (which matches the usual QEMU behaviour of not implementing either
7041      * alignment faults or any memory attribute handling).
7042      */
7043
7044     ARMCPU *cpu = arm_env_get_cpu(env);
7045     uint64_t blocklen = 4 << cpu->dcz_blocksize;
7046     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7047
7048 #ifndef CONFIG_USER_ONLY
7049     {
7050         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7051          * the block size so we might have to do more than one TLB lookup.
7052          * We know that in fact for any v8 CPU the page size is at least 4K
7053          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7054          * 1K as an artefact of legacy v5 subpage support being present in the
7055          * same QEMU executable.
7056          */
7057         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7058         void *hostaddr[maxidx];
7059         int try, i;
7060         unsigned mmu_idx = cpu_mmu_index(env);
7061         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7062
7063         for (try = 0; try < 2; try++) {
7064
7065             for (i = 0; i < maxidx; i++) {
7066                 hostaddr[i] = tlb_vaddr_to_host(env,
7067                                                 vaddr + TARGET_PAGE_SIZE * i,
7068                                                 1, mmu_idx);
7069                 if (!hostaddr[i]) {
7070                     break;
7071                 }
7072             }
7073             if (i == maxidx) {
7074                 /* If it's all in the TLB it's fair game for just writing to;
7075                  * we know we don't need to update dirty status, etc.
7076                  */
7077                 for (i = 0; i < maxidx - 1; i++) {
7078                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7079                 }
7080                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7081                 return;
7082             }
7083             /* OK, try a store and see if we can populate the tlb. This
7084              * might cause an exception if the memory isn't writable,
7085              * in which case we will longjmp out of here. We must for
7086              * this purpose use the actual register value passed to us
7087              * so that we get the fault address right.
7088              */
7089             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7090             /* Now we can populate the other TLB entries, if any */
7091             for (i = 0; i < maxidx; i++) {
7092                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7093                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7094                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7095                 }
7096             }
7097         }
7098
7099         /* Slow path (probably attempt to do this to an I/O device or
7100          * similar, or clearing of a block of code we have translations
7101          * cached for). Just do a series of byte writes as the architecture
7102          * demands. It's not worth trying to use a cpu_physical_memory_map(),
7103          * memset(), unmap() sequence here because:
7104          *  + we'd need to account for the blocksize being larger than a page
7105          *  + the direct-RAM access case is almost always going to be dealt
7106          *    with in the fastpath code above, so there's no speed benefit
7107          *  + we would have to deal with the map returning NULL because the
7108          *    bounce buffer was in use
7109          */
7110         for (i = 0; i < blocklen; i++) {
7111             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7112         }
7113     }
7114 #else
7115     memset(g2h(vaddr), 0, blocklen);
7116 #endif
7117 }
7118
7119 /* Note that signed overflow is undefined in C.  The following routines are
7120    careful to use unsigned types where modulo arithmetic is required.
7121    Failure to do so _will_ break on newer gcc.  */
7122
7123 /* Signed saturating arithmetic.  */
7124
7125 /* Perform 16-bit signed saturating addition.  */
7126 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7127 {
7128     uint16_t res;
7129
7130     res = a + b;
7131     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7132         if (a & 0x8000)
7133             res = 0x8000;
7134         else
7135             res = 0x7fff;
7136     }
7137     return res;
7138 }
7139
7140 /* Perform 8-bit signed saturating addition.  */
7141 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7142 {
7143     uint8_t res;
7144
7145     res = a + b;
7146     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7147         if (a & 0x80)
7148             res = 0x80;
7149         else
7150             res = 0x7f;
7151     }
7152     return res;
7153 }
7154
7155 /* Perform 16-bit signed saturating subtraction.  */
7156 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7157 {
7158     uint16_t res;
7159
7160     res = a - b;
7161     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7162         if (a & 0x8000)
7163             res = 0x8000;
7164         else
7165             res = 0x7fff;
7166     }
7167     return res;
7168 }
7169
7170 /* Perform 8-bit signed saturating subtraction.  */
7171 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7172 {
7173     uint8_t res;
7174
7175     res = a - b;
7176     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7177         if (a & 0x80)
7178             res = 0x80;
7179         else
7180             res = 0x7f;
7181     }
7182     return res;
7183 }
7184
7185 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7186 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7187 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
7188 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
7189 #define PFX q
7190
7191 #include "op_addsub.h"
7192
7193 /* Unsigned saturating arithmetic.  */
7194 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7195 {
7196     uint16_t res;
7197     res = a + b;
7198     if (res < a)
7199         res = 0xffff;
7200     return res;
7201 }
7202
7203 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7204 {
7205     if (a > b)
7206         return a - b;
7207     else
7208         return 0;
7209 }
7210
7211 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7212 {
7213     uint8_t res;
7214     res = a + b;
7215     if (res < a)
7216         res = 0xff;
7217     return res;
7218 }
7219
7220 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7221 {
7222     if (a > b)
7223         return a - b;
7224     else
7225         return 0;
7226 }
7227
7228 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7229 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7230 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
7231 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
7232 #define PFX uq
7233
7234 #include "op_addsub.h"
7235
7236 /* Signed modulo arithmetic.  */
7237 #define SARITH16(a, b, n, op) do { \
7238     int32_t sum; \
7239     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7240     RESULT(sum, n, 16); \
7241     if (sum >= 0) \
7242         ge |= 3 << (n * 2); \
7243     } while(0)
7244
7245 #define SARITH8(a, b, n, op) do { \
7246     int32_t sum; \
7247     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7248     RESULT(sum, n, 8); \
7249     if (sum >= 0) \
7250         ge |= 1 << n; \
7251     } while(0)
7252
7253
7254 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7255 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7256 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
7257 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
7258 #define PFX s
7259 #define ARITH_GE
7260
7261 #include "op_addsub.h"
7262
7263 /* Unsigned modulo arithmetic.  */
7264 #define ADD16(a, b, n) do { \
7265     uint32_t sum; \
7266     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7267     RESULT(sum, n, 16); \
7268     if ((sum >> 16) == 1) \
7269         ge |= 3 << (n * 2); \
7270     } while(0)
7271
7272 #define ADD8(a, b, n) do { \
7273     uint32_t sum; \
7274     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7275     RESULT(sum, n, 8); \
7276     if ((sum >> 8) == 1) \
7277         ge |= 1 << n; \
7278     } while(0)
7279
7280 #define SUB16(a, b, n) do { \
7281     uint32_t sum; \
7282     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7283     RESULT(sum, n, 16); \
7284     if ((sum >> 16) == 0) \
7285         ge |= 3 << (n * 2); \
7286     } while(0)
7287
7288 #define SUB8(a, b, n) do { \
7289     uint32_t sum; \
7290     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7291     RESULT(sum, n, 8); \
7292     if ((sum >> 8) == 0) \
7293         ge |= 1 << n; \
7294     } while(0)
7295
7296 #define PFX u
7297 #define ARITH_GE
7298
7299 #include "op_addsub.h"
7300
7301 /* Halved signed arithmetic.  */
7302 #define ADD16(a, b, n) \
7303   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7304 #define SUB16(a, b, n) \
7305   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7306 #define ADD8(a, b, n) \
7307   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7308 #define SUB8(a, b, n) \
7309   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7310 #define PFX sh
7311
7312 #include "op_addsub.h"
7313
7314 /* Halved unsigned arithmetic.  */
7315 #define ADD16(a, b, n) \
7316   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7317 #define SUB16(a, b, n) \
7318   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7319 #define ADD8(a, b, n) \
7320   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7321 #define SUB8(a, b, n) \
7322   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7323 #define PFX uh
7324
7325 #include "op_addsub.h"
7326
7327 static inline uint8_t do_usad(uint8_t a, uint8_t b)
7328 {
7329     if (a > b)
7330         return a - b;
7331     else
7332         return b - a;
7333 }
7334
7335 /* Unsigned sum of absolute byte differences.  */
7336 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
7337 {
7338     uint32_t sum;
7339     sum = do_usad(a, b);
7340     sum += do_usad(a >> 8, b >> 8);
7341     sum += do_usad(a >> 16, b >>16);
7342     sum += do_usad(a >> 24, b >> 24);
7343     return sum;
7344 }
7345
7346 /* For ARMv6 SEL instruction.  */
7347 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
7348 {
7349     uint32_t mask;
7350
7351     mask = 0;
7352     if (flags & 1)
7353         mask |= 0xff;
7354     if (flags & 2)
7355         mask |= 0xff00;
7356     if (flags & 4)
7357         mask |= 0xff0000;
7358     if (flags & 8)
7359         mask |= 0xff000000;
7360     return (a & mask) | (b & ~mask);
7361 }
7362
7363 /* VFP support.  We follow the convention used for VFP instructions:
7364    Single precision routines have a "s" suffix, double precision a
7365    "d" suffix.  */
7366
7367 /* Convert host exception flags to vfp form.  */
7368 static inline int vfp_exceptbits_from_host(int host_bits)
7369 {
7370     int target_bits = 0;
7371
7372     if (host_bits & float_flag_invalid)
7373         target_bits |= 1;
7374     if (host_bits & float_flag_divbyzero)
7375         target_bits |= 2;
7376     if (host_bits & float_flag_overflow)
7377         target_bits |= 4;
7378     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
7379         target_bits |= 8;
7380     if (host_bits & float_flag_inexact)
7381         target_bits |= 0x10;
7382     if (host_bits & float_flag_input_denormal)
7383         target_bits |= 0x80;
7384     return target_bits;
7385 }
7386
7387 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
7388 {
7389     int i;
7390     uint32_t fpscr;
7391
7392     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
7393             | (env->vfp.vec_len << 16)
7394             | (env->vfp.vec_stride << 20);
7395     i = get_float_exception_flags(&env->vfp.fp_status);
7396     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
7397     fpscr |= vfp_exceptbits_from_host(i);
7398     return fpscr;
7399 }
7400
7401 uint32_t vfp_get_fpscr(CPUARMState *env)
7402 {
7403     return HELPER(vfp_get_fpscr)(env);
7404 }
7405
7406 /* Convert vfp exception flags to target form.  */
7407 static inline int vfp_exceptbits_to_host(int target_bits)
7408 {
7409     int host_bits = 0;
7410
7411     if (target_bits & 1)
7412         host_bits |= float_flag_invalid;
7413     if (target_bits & 2)
7414         host_bits |= float_flag_divbyzero;
7415     if (target_bits & 4)
7416         host_bits |= float_flag_overflow;
7417     if (target_bits & 8)
7418         host_bits |= float_flag_underflow;
7419     if (target_bits & 0x10)
7420         host_bits |= float_flag_inexact;
7421     if (target_bits & 0x80)
7422         host_bits |= float_flag_input_denormal;
7423     return host_bits;
7424 }
7425
7426 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
7427 {
7428     int i;
7429     uint32_t changed;
7430
7431     changed = env->vfp.xregs[ARM_VFP_FPSCR];
7432     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
7433     env->vfp.vec_len = (val >> 16) & 7;
7434     env->vfp.vec_stride = (val >> 20) & 3;
7435
7436     changed ^= val;
7437     if (changed & (3 << 22)) {
7438         i = (val >> 22) & 3;
7439         switch (i) {
7440         case FPROUNDING_TIEEVEN:
7441             i = float_round_nearest_even;
7442             break;
7443         case FPROUNDING_POSINF:
7444             i = float_round_up;
7445             break;
7446         case FPROUNDING_NEGINF:
7447             i = float_round_down;
7448             break;
7449         case FPROUNDING_ZERO:
7450             i = float_round_to_zero;
7451             break;
7452         }
7453         set_float_rounding_mode(i, &env->vfp.fp_status);
7454     }
7455     if (changed & (1 << 24)) {
7456         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7457         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7458     }
7459     if (changed & (1 << 25))
7460         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
7461
7462     i = vfp_exceptbits_to_host(val);
7463     set_float_exception_flags(i, &env->vfp.fp_status);
7464     set_float_exception_flags(0, &env->vfp.standard_fp_status);
7465 }
7466
7467 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
7468 {
7469     HELPER(vfp_set_fpscr)(env, val);
7470 }
7471
7472 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
7473
7474 #define VFP_BINOP(name) \
7475 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
7476 { \
7477     float_status *fpst = fpstp; \
7478     return float32_ ## name(a, b, fpst); \
7479 } \
7480 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
7481 { \
7482     float_status *fpst = fpstp; \
7483     return float64_ ## name(a, b, fpst); \
7484 }
7485 VFP_BINOP(add)
7486 VFP_BINOP(sub)
7487 VFP_BINOP(mul)
7488 VFP_BINOP(div)
7489 VFP_BINOP(min)
7490 VFP_BINOP(max)
7491 VFP_BINOP(minnum)
7492 VFP_BINOP(maxnum)
7493 #undef VFP_BINOP
7494
7495 float32 VFP_HELPER(neg, s)(float32 a)
7496 {
7497     return float32_chs(a);
7498 }
7499
7500 float64 VFP_HELPER(neg, d)(float64 a)
7501 {
7502     return float64_chs(a);
7503 }
7504
7505 float32 VFP_HELPER(abs, s)(float32 a)
7506 {
7507     return float32_abs(a);
7508 }
7509
7510 float64 VFP_HELPER(abs, d)(float64 a)
7511 {
7512     return float64_abs(a);
7513 }
7514
7515 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
7516 {
7517     return float32_sqrt(a, &env->vfp.fp_status);
7518 }
7519
7520 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
7521 {
7522     return float64_sqrt(a, &env->vfp.fp_status);
7523 }
7524
7525 /* XXX: check quiet/signaling case */
7526 #define DO_VFP_cmp(p, type) \
7527 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
7528 { \
7529     uint32_t flags; \
7530     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
7531     case 0: flags = 0x6; break; \
7532     case -1: flags = 0x8; break; \
7533     case 1: flags = 0x2; break; \
7534     default: case 2: flags = 0x3; break; \
7535     } \
7536     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7537         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7538 } \
7539 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
7540 { \
7541     uint32_t flags; \
7542     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
7543     case 0: flags = 0x6; break; \
7544     case -1: flags = 0x8; break; \
7545     case 1: flags = 0x2; break; \
7546     default: case 2: flags = 0x3; break; \
7547     } \
7548     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7549         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7550 }
7551 DO_VFP_cmp(s, float32)
7552 DO_VFP_cmp(d, float64)
7553 #undef DO_VFP_cmp
7554
7555 /* Integer to float and float to integer conversions */
7556
7557 #define CONV_ITOF(name, fsz, sign) \
7558     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
7559 { \
7560     float_status *fpst = fpstp; \
7561     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
7562 }
7563
7564 #define CONV_FTOI(name, fsz, sign, round) \
7565 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
7566 { \
7567     float_status *fpst = fpstp; \
7568     if (float##fsz##_is_any_nan(x)) { \
7569         float_raise(float_flag_invalid, fpst); \
7570         return 0; \
7571     } \
7572     return float##fsz##_to_##sign##int32##round(x, fpst); \
7573 }
7574
7575 #define FLOAT_CONVS(name, p, fsz, sign) \
7576 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
7577 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
7578 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
7579
7580 FLOAT_CONVS(si, s, 32, )
7581 FLOAT_CONVS(si, d, 64, )
7582 FLOAT_CONVS(ui, s, 32, u)
7583 FLOAT_CONVS(ui, d, 64, u)
7584
7585 #undef CONV_ITOF
7586 #undef CONV_FTOI
7587 #undef FLOAT_CONVS
7588
7589 /* floating point conversion */
7590 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
7591 {
7592     float64 r = float32_to_float64(x, &env->vfp.fp_status);
7593     /* ARM requires that S<->D conversion of any kind of NaN generates
7594      * a quiet NaN by forcing the most significant frac bit to 1.
7595      */
7596     return float64_maybe_silence_nan(r);
7597 }
7598
7599 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
7600 {
7601     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
7602     /* ARM requires that S<->D conversion of any kind of NaN generates
7603      * a quiet NaN by forcing the most significant frac bit to 1.
7604      */
7605     return float32_maybe_silence_nan(r);
7606 }
7607
7608 /* VFP3 fixed point conversion.  */
7609 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
7610 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
7611                                      void *fpstp) \
7612 { \
7613     float_status *fpst = fpstp; \
7614     float##fsz tmp; \
7615     tmp = itype##_to_##float##fsz(x, fpst); \
7616     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
7617 }
7618
7619 /* Notice that we want only input-denormal exception flags from the
7620  * scalbn operation: the other possible flags (overflow+inexact if
7621  * we overflow to infinity, output-denormal) aren't correct for the
7622  * complete scale-and-convert operation.
7623  */
7624 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
7625 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
7626                                              uint32_t shift, \
7627                                              void *fpstp) \
7628 { \
7629     float_status *fpst = fpstp; \
7630     int old_exc_flags = get_float_exception_flags(fpst); \
7631     float##fsz tmp; \
7632     if (float##fsz##_is_any_nan(x)) { \
7633         float_raise(float_flag_invalid, fpst); \
7634         return 0; \
7635     } \
7636     tmp = float##fsz##_scalbn(x, shift, fpst); \
7637     old_exc_flags |= get_float_exception_flags(fpst) \
7638         & float_flag_input_denormal; \
7639     set_float_exception_flags(old_exc_flags, fpst); \
7640     return float##fsz##_to_##itype##round(tmp, fpst); \
7641 }
7642
7643 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
7644 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
7645 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
7646 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
7647
7648 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
7649 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
7650 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
7651
7652 VFP_CONV_FIX(sh, d, 64, 64, int16)
7653 VFP_CONV_FIX(sl, d, 64, 64, int32)
7654 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
7655 VFP_CONV_FIX(uh, d, 64, 64, uint16)
7656 VFP_CONV_FIX(ul, d, 64, 64, uint32)
7657 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
7658 VFP_CONV_FIX(sh, s, 32, 32, int16)
7659 VFP_CONV_FIX(sl, s, 32, 32, int32)
7660 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
7661 VFP_CONV_FIX(uh, s, 32, 32, uint16)
7662 VFP_CONV_FIX(ul, s, 32, 32, uint32)
7663 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
7664 #undef VFP_CONV_FIX
7665 #undef VFP_CONV_FIX_FLOAT
7666 #undef VFP_CONV_FLOAT_FIX_ROUND
7667
7668 /* Set the current fp rounding mode and return the old one.
7669  * The argument is a softfloat float_round_ value.
7670  */
7671 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
7672 {
7673     float_status *fp_status = &env->vfp.fp_status;
7674
7675     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
7676     set_float_rounding_mode(rmode, fp_status);
7677
7678     return prev_rmode;
7679 }
7680
7681 /* Set the current fp rounding mode in the standard fp status and return
7682  * the old one. This is for NEON instructions that need to change the
7683  * rounding mode but wish to use the standard FPSCR values for everything
7684  * else. Always set the rounding mode back to the correct value after
7685  * modifying it.
7686  * The argument is a softfloat float_round_ value.
7687  */
7688 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
7689 {
7690     float_status *fp_status = &env->vfp.standard_fp_status;
7691
7692     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
7693     set_float_rounding_mode(rmode, fp_status);
7694
7695     return prev_rmode;
7696 }
7697
7698 /* Half precision conversions.  */
7699 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
7700 {
7701     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7702     float32 r = float16_to_float32(make_float16(a), ieee, s);
7703     if (ieee) {
7704         return float32_maybe_silence_nan(r);
7705     }
7706     return r;
7707 }
7708
7709 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
7710 {
7711     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7712     float16 r = float32_to_float16(a, ieee, s);
7713     if (ieee) {
7714         r = float16_maybe_silence_nan(r);
7715     }
7716     return float16_val(r);
7717 }
7718
7719 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
7720 {
7721     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
7722 }
7723
7724 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
7725 {
7726     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
7727 }
7728
7729 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
7730 {
7731     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
7732 }
7733
7734 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
7735 {
7736     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
7737 }
7738
7739 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
7740 {
7741     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7742     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
7743     if (ieee) {
7744         return float64_maybe_silence_nan(r);
7745     }
7746     return r;
7747 }
7748
7749 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
7750 {
7751     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7752     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
7753     if (ieee) {
7754         r = float16_maybe_silence_nan(r);
7755     }
7756     return float16_val(r);
7757 }
7758
7759 #define float32_two make_float32(0x40000000)
7760 #define float32_three make_float32(0x40400000)
7761 #define float32_one_point_five make_float32(0x3fc00000)
7762
7763 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
7764 {
7765     float_status *s = &env->vfp.standard_fp_status;
7766     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
7767         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
7768         if (!(float32_is_zero(a) || float32_is_zero(b))) {
7769             float_raise(float_flag_input_denormal, s);
7770         }
7771         return float32_two;
7772     }
7773     return float32_sub(float32_two, float32_mul(a, b, s), s);
7774 }
7775
7776 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
7777 {
7778     float_status *s = &env->vfp.standard_fp_status;
7779     float32 product;
7780     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
7781         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
7782         if (!(float32_is_zero(a) || float32_is_zero(b))) {
7783             float_raise(float_flag_input_denormal, s);
7784         }
7785         return float32_one_point_five;
7786     }
7787     product = float32_mul(a, b, s);
7788     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
7789 }
7790
7791 /* NEON helpers.  */
7792
7793 /* Constants 256 and 512 are used in some helpers; we avoid relying on
7794  * int->float conversions at run-time.  */
7795 #define float64_256 make_float64(0x4070000000000000LL)
7796 #define float64_512 make_float64(0x4080000000000000LL)
7797 #define float32_maxnorm make_float32(0x7f7fffff)
7798 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
7799
7800 /* Reciprocal functions
7801  *
7802  * The algorithm that must be used to calculate the estimate
7803  * is specified by the ARM ARM, see FPRecipEstimate()
7804  */
7805
7806 static float64 recip_estimate(float64 a, float_status *real_fp_status)
7807 {
7808     /* These calculations mustn't set any fp exception flags,
7809      * so we use a local copy of the fp_status.
7810      */
7811     float_status dummy_status = *real_fp_status;
7812     float_status *s = &dummy_status;
7813     /* q = (int)(a * 512.0) */
7814     float64 q = float64_mul(float64_512, a, s);
7815     int64_t q_int = float64_to_int64_round_to_zero(q, s);
7816
7817     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
7818     q = int64_to_float64(q_int, s);
7819     q = float64_add(q, float64_half, s);
7820     q = float64_div(q, float64_512, s);
7821     q = float64_div(float64_one, q, s);
7822
7823     /* s = (int)(256.0 * r + 0.5) */
7824     q = float64_mul(q, float64_256, s);
7825     q = float64_add(q, float64_half, s);
7826     q_int = float64_to_int64_round_to_zero(q, s);
7827
7828     /* return (double)s / 256.0 */
7829     return float64_div(int64_to_float64(q_int, s), float64_256, s);
7830 }
7831
7832 /* Common wrapper to call recip_estimate */
7833 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
7834 {
7835     uint64_t val64 = float64_val(num);
7836     uint64_t frac = extract64(val64, 0, 52);
7837     int64_t exp = extract64(val64, 52, 11);
7838     uint64_t sbit;
7839     float64 scaled, estimate;
7840
7841     /* Generate the scaled number for the estimate function */
7842     if (exp == 0) {
7843         if (extract64(frac, 51, 1) == 0) {
7844             exp = -1;
7845             frac = extract64(frac, 0, 50) << 2;
7846         } else {
7847             frac = extract64(frac, 0, 51) << 1;
7848         }
7849     }
7850
7851     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
7852     scaled = make_float64((0x3feULL << 52)
7853                           | extract64(frac, 44, 8) << 44);
7854
7855     estimate = recip_estimate(scaled, fpst);
7856
7857     /* Build new result */
7858     val64 = float64_val(estimate);
7859     sbit = 0x8000000000000000ULL & val64;
7860     exp = off - exp;
7861     frac = extract64(val64, 0, 52);
7862
7863     if (exp == 0) {
7864         frac = 1ULL << 51 | extract64(frac, 1, 51);
7865     } else if (exp == -1) {
7866         frac = 1ULL << 50 | extract64(frac, 2, 50);
7867         exp = 0;
7868     }
7869
7870     return make_float64(sbit | (exp << 52) | frac);
7871 }
7872
7873 static bool round_to_inf(float_status *fpst, bool sign_bit)
7874 {
7875     switch (fpst->float_rounding_mode) {
7876     case float_round_nearest_even: /* Round to Nearest */
7877         return true;
7878     case float_round_up: /* Round to +Inf */
7879         return !sign_bit;
7880     case float_round_down: /* Round to -Inf */
7881         return sign_bit;
7882     case float_round_to_zero: /* Round to Zero */
7883         return false;
7884     }
7885
7886     g_assert_not_reached();
7887 }
7888
7889 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
7890 {
7891     float_status *fpst = fpstp;
7892     float32 f32 = float32_squash_input_denormal(input, fpst);
7893     uint32_t f32_val = float32_val(f32);
7894     uint32_t f32_sbit = 0x80000000ULL & f32_val;
7895     int32_t f32_exp = extract32(f32_val, 23, 8);
7896     uint32_t f32_frac = extract32(f32_val, 0, 23);
7897     float64 f64, r64;
7898     uint64_t r64_val;
7899     int64_t r64_exp;
7900     uint64_t r64_frac;
7901
7902     if (float32_is_any_nan(f32)) {
7903         float32 nan = f32;
7904         if (float32_is_signaling_nan(f32)) {
7905             float_raise(float_flag_invalid, fpst);
7906             nan = float32_maybe_silence_nan(f32);
7907         }
7908         if (fpst->default_nan_mode) {
7909             nan =  float32_default_nan;
7910         }
7911         return nan;
7912     } else if (float32_is_infinity(f32)) {
7913         return float32_set_sign(float32_zero, float32_is_neg(f32));
7914     } else if (float32_is_zero(f32)) {
7915         float_raise(float_flag_divbyzero, fpst);
7916         return float32_set_sign(float32_infinity, float32_is_neg(f32));
7917     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
7918         /* Abs(value) < 2.0^-128 */
7919         float_raise(float_flag_overflow | float_flag_inexact, fpst);
7920         if (round_to_inf(fpst, f32_sbit)) {
7921             return float32_set_sign(float32_infinity, float32_is_neg(f32));
7922         } else {
7923             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
7924         }
7925     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
7926         float_raise(float_flag_underflow, fpst);
7927         return float32_set_sign(float32_zero, float32_is_neg(f32));
7928     }
7929
7930
7931     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
7932     r64 = call_recip_estimate(f64, 253, fpst);
7933     r64_val = float64_val(r64);
7934     r64_exp = extract64(r64_val, 52, 11);
7935     r64_frac = extract64(r64_val, 0, 52);
7936
7937     /* result = sign : result_exp<7:0> : fraction<51:29>; */
7938     return make_float32(f32_sbit |
7939                         (r64_exp & 0xff) << 23 |
7940                         extract64(r64_frac, 29, 24));
7941 }
7942
7943 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
7944 {
7945     float_status *fpst = fpstp;
7946     float64 f64 = float64_squash_input_denormal(input, fpst);
7947     uint64_t f64_val = float64_val(f64);
7948     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
7949     int64_t f64_exp = extract64(f64_val, 52, 11);
7950     float64 r64;
7951     uint64_t r64_val;
7952     int64_t r64_exp;
7953     uint64_t r64_frac;
7954
7955     /* Deal with any special cases */
7956     if (float64_is_any_nan(f64)) {
7957         float64 nan = f64;
7958         if (float64_is_signaling_nan(f64)) {
7959             float_raise(float_flag_invalid, fpst);
7960             nan = float64_maybe_silence_nan(f64);
7961         }
7962         if (fpst->default_nan_mode) {
7963             nan =  float64_default_nan;
7964         }
7965         return nan;
7966     } else if (float64_is_infinity(f64)) {
7967         return float64_set_sign(float64_zero, float64_is_neg(f64));
7968     } else if (float64_is_zero(f64)) {
7969         float_raise(float_flag_divbyzero, fpst);
7970         return float64_set_sign(float64_infinity, float64_is_neg(f64));
7971     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
7972         /* Abs(value) < 2.0^-1024 */
7973         float_raise(float_flag_overflow | float_flag_inexact, fpst);
7974         if (round_to_inf(fpst, f64_sbit)) {
7975             return float64_set_sign(float64_infinity, float64_is_neg(f64));
7976         } else {
7977             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
7978         }
7979     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
7980         float_raise(float_flag_underflow, fpst);
7981         return float64_set_sign(float64_zero, float64_is_neg(f64));
7982     }
7983
7984     r64 = call_recip_estimate(f64, 2045, fpst);
7985     r64_val = float64_val(r64);
7986     r64_exp = extract64(r64_val, 52, 11);
7987     r64_frac = extract64(r64_val, 0, 52);
7988
7989     /* result = sign : result_exp<10:0> : fraction<51:0> */
7990     return make_float64(f64_sbit |
7991                         ((r64_exp & 0x7ff) << 52) |
7992                         r64_frac);
7993 }
7994
7995 /* The algorithm that must be used to calculate the estimate
7996  * is specified by the ARM ARM.
7997  */
7998 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
7999 {
8000     /* These calculations mustn't set any fp exception flags,
8001      * so we use a local copy of the fp_status.
8002      */
8003     float_status dummy_status = *real_fp_status;
8004     float_status *s = &dummy_status;
8005     float64 q;
8006     int64_t q_int;
8007
8008     if (float64_lt(a, float64_half, s)) {
8009         /* range 0.25 <= a < 0.5 */
8010
8011         /* a in units of 1/512 rounded down */
8012         /* q0 = (int)(a * 512.0);  */
8013         q = float64_mul(float64_512, a, s);
8014         q_int = float64_to_int64_round_to_zero(q, s);
8015
8016         /* reciprocal root r */
8017         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
8018         q = int64_to_float64(q_int, s);
8019         q = float64_add(q, float64_half, s);
8020         q = float64_div(q, float64_512, s);
8021         q = float64_sqrt(q, s);
8022         q = float64_div(float64_one, q, s);
8023     } else {
8024         /* range 0.5 <= a < 1.0 */
8025
8026         /* a in units of 1/256 rounded down */
8027         /* q1 = (int)(a * 256.0); */
8028         q = float64_mul(float64_256, a, s);
8029         int64_t q_int = float64_to_int64_round_to_zero(q, s);
8030
8031         /* reciprocal root r */
8032         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8033         q = int64_to_float64(q_int, s);
8034         q = float64_add(q, float64_half, s);
8035         q = float64_div(q, float64_256, s);
8036         q = float64_sqrt(q, s);
8037         q = float64_div(float64_one, q, s);
8038     }
8039     /* r in units of 1/256 rounded to nearest */
8040     /* s = (int)(256.0 * r + 0.5); */
8041
8042     q = float64_mul(q, float64_256,s );
8043     q = float64_add(q, float64_half, s);
8044     q_int = float64_to_int64_round_to_zero(q, s);
8045
8046     /* return (double)s / 256.0;*/
8047     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8048 }
8049
8050 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8051 {
8052     float_status *s = fpstp;
8053     float32 f32 = float32_squash_input_denormal(input, s);
8054     uint32_t val = float32_val(f32);
8055     uint32_t f32_sbit = 0x80000000 & val;
8056     int32_t f32_exp = extract32(val, 23, 8);
8057     uint32_t f32_frac = extract32(val, 0, 23);
8058     uint64_t f64_frac;
8059     uint64_t val64;
8060     int result_exp;
8061     float64 f64;
8062
8063     if (float32_is_any_nan(f32)) {
8064         float32 nan = f32;
8065         if (float32_is_signaling_nan(f32)) {
8066             float_raise(float_flag_invalid, s);
8067             nan = float32_maybe_silence_nan(f32);
8068         }
8069         if (s->default_nan_mode) {
8070             nan =  float32_default_nan;
8071         }
8072         return nan;
8073     } else if (float32_is_zero(f32)) {
8074         float_raise(float_flag_divbyzero, s);
8075         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8076     } else if (float32_is_neg(f32)) {
8077         float_raise(float_flag_invalid, s);
8078         return float32_default_nan;
8079     } else if (float32_is_infinity(f32)) {
8080         return float32_zero;
8081     }
8082
8083     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8084      * preserving the parity of the exponent.  */
8085
8086     f64_frac = ((uint64_t) f32_frac) << 29;
8087     if (f32_exp == 0) {
8088         while (extract64(f64_frac, 51, 1) == 0) {
8089             f64_frac = f64_frac << 1;
8090             f32_exp = f32_exp-1;
8091         }
8092         f64_frac = extract64(f64_frac, 0, 51) << 1;
8093     }
8094
8095     if (extract64(f32_exp, 0, 1) == 0) {
8096         f64 = make_float64(((uint64_t) f32_sbit) << 32
8097                            | (0x3feULL << 52)
8098                            | f64_frac);
8099     } else {
8100         f64 = make_float64(((uint64_t) f32_sbit) << 32
8101                            | (0x3fdULL << 52)
8102                            | f64_frac);
8103     }
8104
8105     result_exp = (380 - f32_exp) / 2;
8106
8107     f64 = recip_sqrt_estimate(f64, s);
8108
8109     val64 = float64_val(f64);
8110
8111     val = ((result_exp & 0xff) << 23)
8112         | ((val64 >> 29)  & 0x7fffff);
8113     return make_float32(val);
8114 }
8115
8116 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8117 {
8118     float_status *s = fpstp;
8119     float64 f64 = float64_squash_input_denormal(input, s);
8120     uint64_t val = float64_val(f64);
8121     uint64_t f64_sbit = 0x8000000000000000ULL & val;
8122     int64_t f64_exp = extract64(val, 52, 11);
8123     uint64_t f64_frac = extract64(val, 0, 52);
8124     int64_t result_exp;
8125     uint64_t result_frac;
8126
8127     if (float64_is_any_nan(f64)) {
8128         float64 nan = f64;
8129         if (float64_is_signaling_nan(f64)) {
8130             float_raise(float_flag_invalid, s);
8131             nan = float64_maybe_silence_nan(f64);
8132         }
8133         if (s->default_nan_mode) {
8134             nan =  float64_default_nan;
8135         }
8136         return nan;
8137     } else if (float64_is_zero(f64)) {
8138         float_raise(float_flag_divbyzero, s);
8139         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8140     } else if (float64_is_neg(f64)) {
8141         float_raise(float_flag_invalid, s);
8142         return float64_default_nan;
8143     } else if (float64_is_infinity(f64)) {
8144         return float64_zero;
8145     }
8146
8147     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8148      * preserving the parity of the exponent.  */
8149
8150     if (f64_exp == 0) {
8151         while (extract64(f64_frac, 51, 1) == 0) {
8152             f64_frac = f64_frac << 1;
8153             f64_exp = f64_exp - 1;
8154         }
8155         f64_frac = extract64(f64_frac, 0, 51) << 1;
8156     }
8157
8158     if (extract64(f64_exp, 0, 1) == 0) {
8159         f64 = make_float64(f64_sbit
8160                            | (0x3feULL << 52)
8161                            | f64_frac);
8162     } else {
8163         f64 = make_float64(f64_sbit
8164                            | (0x3fdULL << 52)
8165                            | f64_frac);
8166     }
8167
8168     result_exp = (3068 - f64_exp) / 2;
8169
8170     f64 = recip_sqrt_estimate(f64, s);
8171
8172     result_frac = extract64(float64_val(f64), 0, 52);
8173
8174     return make_float64(f64_sbit |
8175                         ((result_exp & 0x7ff) << 52) |
8176                         result_frac);
8177 }
8178
8179 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8180 {
8181     float_status *s = fpstp;
8182     float64 f64;
8183
8184     if ((a & 0x80000000) == 0) {
8185         return 0xffffffff;
8186     }
8187
8188     f64 = make_float64((0x3feULL << 52)
8189                        | ((int64_t)(a & 0x7fffffff) << 21));
8190
8191     f64 = recip_estimate(f64, s);
8192
8193     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8194 }
8195
8196 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8197 {
8198     float_status *fpst = fpstp;
8199     float64 f64;
8200
8201     if ((a & 0xc0000000) == 0) {
8202         return 0xffffffff;
8203     }
8204
8205     if (a & 0x80000000) {
8206         f64 = make_float64((0x3feULL << 52)
8207                            | ((uint64_t)(a & 0x7fffffff) << 21));
8208     } else { /* bits 31-30 == '01' */
8209         f64 = make_float64((0x3fdULL << 52)
8210                            | ((uint64_t)(a & 0x3fffffff) << 22));
8211     }
8212
8213     f64 = recip_sqrt_estimate(f64, fpst);
8214
8215     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8216 }
8217
8218 /* VFPv4 fused multiply-accumulate */
8219 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8220 {
8221     float_status *fpst = fpstp;
8222     return float32_muladd(a, b, c, 0, fpst);
8223 }
8224
8225 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
8226 {
8227     float_status *fpst = fpstp;
8228     return float64_muladd(a, b, c, 0, fpst);
8229 }
8230
8231 /* ARMv8 round to integral */
8232 float32 HELPER(rints_exact)(float32 x, void *fp_status)
8233 {
8234     return float32_round_to_int(x, fp_status);
8235 }
8236
8237 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
8238 {
8239     return float64_round_to_int(x, fp_status);
8240 }
8241
8242 float32 HELPER(rints)(float32 x, void *fp_status)
8243 {
8244     int old_flags = get_float_exception_flags(fp_status), new_flags;
8245     float32 ret;
8246
8247     ret = float32_round_to_int(x, fp_status);
8248
8249     /* Suppress any inexact exceptions the conversion produced */
8250     if (!(old_flags & float_flag_inexact)) {
8251         new_flags = get_float_exception_flags(fp_status);
8252         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8253     }
8254
8255     return ret;
8256 }
8257
8258 float64 HELPER(rintd)(float64 x, void *fp_status)
8259 {
8260     int old_flags = get_float_exception_flags(fp_status), new_flags;
8261     float64 ret;
8262
8263     ret = float64_round_to_int(x, fp_status);
8264
8265     new_flags = get_float_exception_flags(fp_status);
8266
8267     /* Suppress any inexact exceptions the conversion produced */
8268     if (!(old_flags & float_flag_inexact)) {
8269         new_flags = get_float_exception_flags(fp_status);
8270         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8271     }
8272
8273     return ret;
8274 }
8275
8276 /* Convert ARM rounding mode to softfloat */
8277 int arm_rmode_to_sf(int rmode)
8278 {
8279     switch (rmode) {
8280     case FPROUNDING_TIEAWAY:
8281         rmode = float_round_ties_away;
8282         break;
8283     case FPROUNDING_ODD:
8284         /* FIXME: add support for TIEAWAY and ODD */
8285         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
8286                       rmode);
8287     case FPROUNDING_TIEEVEN:
8288     default:
8289         rmode = float_round_nearest_even;
8290         break;
8291     case FPROUNDING_POSINF:
8292         rmode = float_round_up;
8293         break;
8294     case FPROUNDING_NEGINF:
8295         rmode = float_round_down;
8296         break;
8297     case FPROUNDING_ZERO:
8298         rmode = float_round_to_zero;
8299         break;
8300     }
8301     return rmode;
8302 }
8303
8304 /* CRC helpers.
8305  * The upper bytes of val (above the number specified by 'bytes') must have
8306  * been zeroed out by the caller.
8307  */
8308 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
8309 {
8310     uint8_t buf[4];
8311
8312     stl_le_p(buf, val);
8313
8314     /* zlib crc32 converts the accumulator and output to one's complement.  */
8315     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
8316 }
8317
8318 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
8319 {
8320     uint8_t buf[4];
8321
8322     stl_le_p(buf, val);
8323
8324     /* Linux crc32c converts the output to one's complement.  */
8325     return crc32c(acc, buf, bytes) ^ 0xffffffff;
8326 }